JP2009003955A - Delay clock generator and delay time measurement instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay clock generator which generates a delay clock with high level of accuracy. <P>SOLUTION: A reference clock is input in a posterior border matching part and a phase control part. A ring oscillator oscillates a shift clock with the same cycle as that of the reference clock. The posterior border matching part matches a posterior border of the shift clock to a posterior border of the reference clock. The shift clock whose posterior border is matched is supplied to a pulse insertion part. The phase control part receives the reference clock and generates a phase control signal for determining to which cycle among a plurality of cycles of the shift clock the insertion pulse is inserted. The pulse insertion part inserts the insertion pulse to the cycle of the shift clock determined by the phase control signal. A delay phase lock part generates the delay clock by delaying a phase of the shift clock oscillated in the ring oscillator to a phase of the reference clock based on the reference clock and the shift clock to which the insertion pulse is inserted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a delay clock generation apparatus that generates a delay clock, and more particularly to a delay clock generation apparatus incorporated in a delay signal generation apparatus in a semiconductor test apparatus that tests a semiconductor device.

  In recent years, development of semiconductor devices that operate at high speed has been actively promoted. Accordingly, very strict control of the operation timing is required for a semiconductor test apparatus for testing a high-speed device. In particular, the timing for inputting the test pattern to the device under test needs to be accurately delayed with respect to the reference clock according to the input characteristics of the device under test.

  FIG. 1 is a block diagram showing a delay line 176 for generating a delay designation signal having a predetermined delay time in a semiconductor test apparatus. The delay line 176 includes delay elements 180, 184, 188, 192, selectors 182, 186, 190, 194, and a linearized memory 196. In the delay line 176, a clock is input from the input end, and a delay designation signal delayed by a predetermined time is output from the output end.

  The linearize memory 196 stores data of combinations of delay elements that generate a predetermined delay amount (delay time) at a predetermined address. The selectors 182, 186, 190, and 194 select either the clock that has passed through each delay element 180, 184, 188, or 192 based on the data sent from the linearize memory 196, Output. For example, when a delay element in the preceding stage of each selector is used to generate a predetermined delay time, “0” is set to the corresponding bit of the linearize memory 196, and when not used, the bit is set to the bit. “1” is set.

  The delay elements 180, 184, 188, and 192 provided in the delay line 176 are each designed to have a delay amount of several picoseconds to several tens of picoseconds or hundreds of picoseconds. Therefore, for example, in order to generate seven types of delay times of 10, 20... 70 picoseconds, theoretically, three types of delay elements having delay amounts of 10, 20, 40 picoseconds are used. You can combine them.

  However, in reality, an error may occur between the delay time actually provided by the delay element and the designed delay time due to variations in the quality of the delay element, temperature conditions when the delay element is used, and the like. . In order to eliminate this error, it is necessary to actually obtain an optimum combination of delay elements that generate a predetermined delay time by measurement.

  FIG. 2 is a block diagram showing a conventional configuration for measuring the output signal of the waveform shaper 12 delayed from the signal generated by the pattern generator 10 in the semiconductor test apparatus. In this measurement, the pattern generator 10 supplies the reference clock 34 to the timing generator 14 and supplies the measurement signal 32 for measuring the delay time to the waveform shaper 12. The timing generator 14 has a plurality of delay lines 176 shown in FIG. 1, and generates a delay designation signal 36 obtained by delaying the reference clock 34 by a predetermined time based on a combination of arbitrarily selected delay elements. . The delay designation signal 36 is given to the waveform shaper 12, and the waveform shaper 12 delays the measurement signal 32 based on the delay designation signal 36 and outputs a delay measurement signal 38 to the oscilloscope 16. The oscilloscope 16 observes the delay time generated by any combination of delay elements. The combination data of the delay elements at this time is stored at a predetermined address in the linearize memory 196 (see FIG. 1).

  Conventionally, as shown in FIG. 2, the delay time generated by each combination of delay elements is observed with an oscilloscope 16, and correspondence data between the combination of delay elements and the delay time is stored in a linearization memory 196. It was. When actually testing a semiconductor device, a delay element that generates a desired delay time is selected based on data stored in the linearized memory 196 in accordance with the input characteristics of the semiconductor device.

  According to the conventional delay time measurement method, since the oscilloscope 16 is used, the waveform output from the waveform shaper 12 can be measured only one pin at a time. When measuring a delay time on the order of several picoseconds or several tens of picoseconds, the resolution of the oscilloscope 16 cannot measure a sufficiently accurate delay time. Accordingly, an object of the present invention is to provide a delay time measuring method and a delay time measuring apparatus capable of accurately measuring the delay times of a plurality of delay lines in parallel.

  As a delay time measuring method for measuring an accurate delay time of a delay line, the present invention uses a delay clock having a predetermined delay time with respect to the reference clock 34 to generate a predetermined delay time. It is an object to provide a method for determining the combination of the above. Conventionally, since it has been difficult to generate a delay clock having an accurate delay time, it has been difficult to accurately measure the delay time caused by the combination of delay elements using the delay clock. Therefore, an object of the present invention is to provide a delay clock generation device capable of generating a delay clock having an accurate delay time.

  Therefore, an object of the present invention is to provide a delay clock generation device, a delay time measurement method, and a delay time measurement device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above-described problem, the first aspect of the present invention provides a delay clock generation device that generates a delay clock obtained by delaying a reference clock by a predetermined time. The delay clock generator includes an oscillator that oscillates a shift clock having the same cycle as the reference clock, and an insertion in which at least one of a leading edge and a trailing edge is inserted into a reference shift clock synchronized with a leading edge or a trailing edge of the shift clock. A pulse insertion unit that generates a pulse and inserts it into the reference shift clock; a reference reference clock that is synchronized with the reference clock and has the same cycle as the reference shift clock; and the reference shift clock into which the insertion pulse is inserted And a delay phase lock unit that delays the phase of the shift clock oscillated in the oscillator with respect to the phase of the reference clock, and generates the delayed clock by delaying the reference clock by the predetermined time. It is characterized by that. According to this delay clock generation device, it is possible to easily generate a delay clock having an accurate delay time with respect to the reference clock.

  In one aspect of the first aspect, the delay clock generation device generates a phase difference between a synchronous shift clock synchronized with the shift clock and a synchronous reference clock synchronized with the reference clock and having the same cycle as the synchronous shift clock. Based on this, a phase comparison unit that outputs the reference standard clock and the reference shift clock may be further included.

  In another aspect of the first aspect, the phase comparison unit can output the reference reference clock and the reference shift clock with trailing edges combined based on the synchronization reference clock and the synchronization shift clock.

  In still another aspect of the first aspect, the pulse insertion unit may insert the insertion pulse between a trailing edge of the reference shift clock and a leading edge of the next reference shift clock.

  In still another aspect of the first aspect, the pulse insertion unit can insert the insertion pulse into the reference shift clock in synchronization with the reference clock.

  In still another aspect of the first aspect, the delay clock generation device divides the reference clock and outputs the synchronization reference clock, and the same period as the synchronization reference clock. And a synchronous shift clock generator that divides the shift clock and outputs the synchronous shift clock.

  In still another aspect of the first aspect, the delay clock generation device further includes a phase control unit that generates a phase control signal that determines in which cycle of the plurality of cycles of the reference shift clock the insertion pulse is to be inserted. The pulse insertion unit can insert the insertion pulse in a cycle of the reference shift clock determined by the phase control signal.

  In still another aspect of the first aspect, the delay phase lock unit includes the shift clock of the shift clock oscillated in the oscillator based on the number of insertions of the insertion pulse inserted in a plurality of cycles of the reference shift clock. It is possible to delay the phase.

  In still another aspect of the first aspect, the delay phase lock unit is an average value obtained by subtracting the potential of the pulse train of the reference shift clock into which the insertion pulse has been inserted from the potential of the pulse train of the synchronization reference clock. And a pulse width adjustment unit that adjusts the pulse width of the reference shift clock into which the insertion pulse is inserted so that the average value of the subtraction results in the subtraction circuit is 0. Also good.

  In still another aspect of the first aspect, the oscillator is a ring oscillator whose oscillation frequency changes according to a power supply voltage, and the pulse width adjustment unit is based on the average value of the subtraction results in the subtraction circuit. By adjusting the power supply voltage of the ring oscillator, it is possible to adjust the pulse width of the reference shift clock in which the insertion pulse is inserted.

  In still another aspect of the first aspect, the ring oscillator is configured on a single chip together with a plurality of electronic circuits, and the delay clock generation device is adjusted based on the average value of the subtraction results. You may further provide the power supply voltage supply part which supplies a power supply voltage also to these electronic circuits.

  In still another aspect of the first embodiment, the oscillator is a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, and the pulse width adjustment unit sets the average value of the subtraction results in the subtraction circuit. The pulse width of the reference shift clock into which the insertion pulse has been inserted can be adjusted by adjusting the control voltage of the voltage controlled oscillator based on the above.

  In still another aspect of the first aspect, the phase control unit generates the phase control signal so that the insertion pulse is inserted in a time-series manner in a plurality of cycles of the reference shift clock. it can.

  In still another aspect of the first aspect, the phase control unit stores an M-bit (M is a natural number) counter that increases an output value based on the synchronization reference clock, and an insertion number of the insertion pulse. , (M + 1) -bit pulse insertion setting register, a plurality of change point detection units for detecting the change point of the bit of the counter, and (M−n + 1) (n is a natural number) th bit of the pulse insertion setting register A plurality of AND circuits that take a logical product of the corresponding register values and the output value of the change point detection unit corresponding to the nth bit of the counter, and the phase control unit includes the AND circuit A cycle for inserting the insertion pulse can be determined based on a logical product.

  In order to solve the above problem, the second embodiment of the present invention provides a delay time measuring method for measuring a delay time in a delay line. In this delay time measuring method, the delay line has an input end and an output end of a reference clock, and the output end is operated by a delay clock having a predetermined delay time with respect to the reference clock. Assuming that the delay time measuring method is connected to an input, a delay time setting step for setting a constant delay time in the delay line, and the constant delay time is set in the delay time setting step. A reference clock supply stage for supplying the reference clock to the input terminal of the delay line; a delay clock supply stage for supplying a synchronous delay clock synchronized with the delay clock to the clock input of the flip-flop; and an output from the flip-flop. Averaged output logic values, and based on the average value of the output logic values Characterized by comprising a delay time measuring step of measuring the delay time of the delay line. With this delay time measurement method, the delay times of a plurality of delay lines can be accurately measured simultaneously.

  In one aspect of the second embodiment, the delay time measurement step includes the step of measuring the delay time of the delay line to be a predetermined delay time of the delay clock when the average value of the output logic values is approximately 0.5. May be determined to be approximately equal to.

  In order to solve the above-described problem, a third embodiment of the present invention is a delay time measuring apparatus for measuring a delay time in a delay line, and generates a delay clock having a predetermined delay time with respect to a reference clock. A delay clock generating means for performing the reference clock supply means for supplying the reference clock to the delay line, an edge of a delay pulse obtained by delaying the reference clock in the delay line, and a synchronous delay clock synchronized with the delay clock. Timing comparison means for comparing edge timings and outputting the comparison result as a logical value “0” or “1”; and averaging means for generating an average value obtained by averaging the comparison results output from the timing comparison means Measuring means for measuring a delay time in the delay line based on the average value generated by the averaging means. A delay time measuring apparatus comprising: a stage. With this delay time measuring device, the delay times of a plurality of delay lines can be accurately measured simultaneously.

  In one aspect of the third aspect, the timing comparison means may include a flip-flop having a data input to which the delay pulse is input and a clock input to which the synchronous delay clock is input.

  In another aspect of the third mode, the measuring means may determine that the delay time of the delay line is approximately equal to the predetermined delay time of the delay clock when the average value is approximately 0.5. Also good.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 3 is a block diagram of a semiconductor test apparatus for testing the device under test 22. The semiconductor test apparatus includes a pattern generator 10, a delay signal generator 24, a device insertion unit 18, and a comparator 20. The delay signal generation device 24 includes a waveform shaper 12 and a timing generator 14. During the test, the device under test 22 is inserted into the device insertion unit 18.

  The pattern generator 10 generates an input pattern 33 and a reference clock 34 to be input to the device under test 22 and supplies them to the delay signal generator 24. Specifically, the input pattern 33 is supplied to the waveform shaper 12 and the reference clock 34 is supplied to the timing generator 14. The timing generator 14 includes a delay clock generation unit (not shown) and a delay line (not shown). In the linearization memory 196 of the delay line 176 (see FIG. 1), data relating to combinations of delay elements that generate a predetermined delay time is stored in advance. In the present invention, this data is obtained based on a delay clock having a predetermined delay time generated by the delay clock generator.

  A delay designation signal 36 obtained by delaying the reference clock 34 by a predetermined time is supplied to the waveform shaper 12. The waveform shaper 12 delays the timing of inputting the input pattern 33 to the device under test 22 based on the delay designation signal 36, and supplies the delayed signal 39, which is a delayed input pattern, to the device insertion unit 18. In this embodiment, the delay clock generator and the delay line are incorporated in the timing generator 14. However, in another embodiment, the delay clock generator and the delay line may be incorporated in the waveform shaper 12. . The delay signal generation device 24 can output a delay signal 39 obtained by delaying the input pattern 33 for a predetermined time according to the input characteristics of the device under test 22 as a whole.

  The device under test 22 receives the delay signal 39 via the device plug-in unit 18 and outputs an output signal 40 to the comparator 20 based on the received delay signal 39. For example, if the device under test 22 is a memory device, the data stored based on the delay signal 39 is output as the output signal 40. If the device under test 22 is a computing device, the data is calculated based on the delay signal 39. The calculated result is output as an output signal 40. The pattern generator 10 outputs an expected value pattern 42 expected as an output response to the normal device under test 22 to the comparator 20. The comparator 20 determines whether the device under test 22 is good or bad by detecting whether or not the output signal 40 and the expected value pattern 42 match.

  FIG. 4 is a block diagram showing a delay clock generation apparatus according to an embodiment of the present invention, which generates a delay clock obtained by delaying a reference clock by a predetermined time. This delay clock generator is incorporated in the delay signal generator 24 shown in FIG. 3, and is used to obtain data to be stored in the linearized memory 196 in the delay line before testing the device under test 22. Is possible. The delay clock generation device includes a ring oscillator 50, a phase comparison unit 52, a pulse insertion unit 54, a phase control unit 56, and a delay phase lock unit 58. The delay phase lock unit 58 includes a subtraction circuit 60 and a pulse width adjustment unit. 62.

  The reference clock 34 is input to the phase comparison unit 52 and the phase control unit 56. The ring oscillator 50 can oscillate a shift clock 70 having the same cycle as that of the reference clock 34. The phase comparison unit 52 compares the phases of the reference clock 34 and the shift clock 70, and outputs the reference reference clock 35 and the reference shift clock 72 based on the phase difference between the reference clock 34 and the shift clock 70, respectively. The reference reference clock 35 is synchronized with the reference clock 34 and has the same period as the reference shift clock 72. At least one of the leading edge and the trailing edge of the reference shift clock 72 is synchronized with the leading edge or the trailing edge of the shift clock 70. The reference shift clock 72 is supplied to the pulse insertion unit 54.

  The phase control unit 56 receives the reference clock 34 and generates a phase control signal 74 that determines in which cycle of the plurality of cycles of the reference shift clock 72 the insertion pulse is to be inserted. It is desirable that the phase control unit 56 generates the phase control signal 74 so that the insertion pulse is diffused and inserted in a time series in a plurality of cycles of the reference shift clock 72. The pulse insertion unit 54 can generate an insertion pulse to be inserted into the reference shift clock 72 and insert the insertion pulse into the cycle of the reference shift clock 72 determined by the phase control signal 74. This insertion pulse is inserted between the trailing edge of the reference shift clock 72 and the leading edge of the next reference shift clock 72.

  The delay phase lock unit 58 delays the phase of the shift clock 70 oscillated in the ring oscillator 50 with respect to the phase of the reference clock 34 based on the reference standard clock 35 and the reference shift clock 76 into which the insertion pulse is inserted. Thus, the ring oscillator 50 is caused to generate a delay clock 82 obtained by delaying the reference clock 34 by a predetermined time. Specifically, the delay phase lock unit 58 shifts the shift clock 70 oscillated in the ring oscillator 50 based on the number of insertion pulses inserted in a plurality of cycles of the reference shift clock 72 and the pulse width of the insertion pulses. Can be delayed in phase. As a configuration for this purpose, in this embodiment, the delay phase lock unit 58 includes a subtraction circuit 60 and a pulse width adjustment unit 62. The subtracting circuit 60 can output a subtraction result 78 obtained by subtracting the potential of the pulse train of the reference shift clock 76 into which the insertion pulse has been inserted from the potential of the pulse train of the reference clock 34 and averaging it.

  If the averaged subtraction result 78 is 0, it is indicated that the shift clock 70 oscillated by the ring oscillator 50 is the delay clock 82 delayed by a predetermined time with respect to the reference clock 34, while the subtraction result 78 is 0. Otherwise, it is indicated that the shift clock 70 does not yet have a predetermined delay time with respect to the reference clock 34. The pulse width adjustment unit 62 adjusts the oscillation frequency of the ring oscillator 50 so that the subtraction result of the subtraction circuit 60 becomes zero. That is, the pulse width adjustment unit 62 adjusts the pulse width of the reference shift clock 76 until the subtraction result 78 of the subtraction circuit 60 becomes 0 by adjusting the oscillation frequency of the ring oscillator 50. When the ring oscillator 50 changes the oscillation frequency according to the power supply voltage, the pulse width adjustment unit 62 outputs a voltage adjustment signal 80 for adjusting the power supply voltage of the ring oscillator 50 based on the subtraction result 78 of the subtraction circuit 60. It is also possible to adjust the oscillation frequency of the ring oscillator 50 and adjust the pulse width of the reference shift clock 76.

  In this embodiment, the ring oscillator 50 is shown as an oscillator. However, in another embodiment, the oscillator may be a voltage-controlled oscillator whose oscillation frequency changes according to the control voltage. At this time, the pulse width adjustment unit 62 adjusts the control voltage of the voltage controlled oscillator based on the average value of the subtraction result 78 in the subtraction circuit 60, thereby reducing the pulse width of the reference shift clock 76 into which the insertion pulse is inserted. You may adjust.

  As described above, in the delay clock generator shown in FIG. 4, when the subtraction result 78 of the subtraction circuit 60 becomes 0, that is, the sum of the pulse width lengths of the reference clock 34 in a predetermined cycle and the pulse When the sum of the pulse width lengths of the inserted reference shift clock 76 becomes equal, the ring oscillator 50 oscillates a delay clock 82 having a predetermined delay time. By locking the state of each component at this time, the ring oscillator 50 can continue to oscillate the delay clock 82 having a predetermined delay time.

  FIG. 5 is a circuit configuration diagram illustrating an example of a delay clock generation apparatus according to an embodiment of the present invention that generates a delay clock obtained by delaying a reference clock by a predetermined time, and the block diagram in FIG. 4 is illustrated in a circuit form. In FIG. 5, the configuration given the same reference numeral as that in FIG. 4 realizes the same or similar function and operation as the corresponding configuration in FIG. 4. 5 includes a ring oscillator 50, a phase comparison unit 52, a pulse insertion unit 54, a phase control unit 56, a delay phase lock unit 58, a power supply voltage unit 90, a synchronization reference clock generation unit 92, a synchronization shift. A clock generation unit 94, an OR gate 124, and drivers 162 and 164 are provided.

  The synchronization reference clock generation unit 92 outputs a synchronization reference clock 140 synchronized with the reference clock 34 based on the input reference clock 34. Similarly, the synchronous shift clock generation unit 94 outputs a synchronous shift clock 142 synchronized with the shift clock 70 based on the shift clock 70. The synchronization reference clock 140 and the synchronization shift clock 142 have the same period. In the present embodiment, the synchronization reference clock generation unit 92 and the synchronization shift clock generation unit 94 are both 8 frequency dividers that divide the input signal by 1/8. However, the synchronization reference clock generation unit 92 and the synchronization shift clock generation unit 94 are not limited to an 8-divider, but a 1/4 divider that divides by 1/4, a 2 divider that divides by 1/2, and 1 For example, a frequency divider that divides the frequency by 1 may be used. The 1 frequency divider may be a buffer. Here, the synchronous shift clock generation unit 94 is provided to widen the portion of the logical value “0” of the reference shift clock 146 into which the insertion pulse 150 is inserted later. Therefore, if it is possible to insert the insertion pulse 150 into the portion of the logical value “0” of the original shift clock 70, the synchronous shift clock generation unit 94 may be a simple buffer, and may not be provided. Also good.

  The power supply voltage unit 90 supplies a power supply voltage to the ring oscillator 50 and drives the ring oscillator 50. The phase comparison unit 52 includes FFs (flip flops) 96 and 98, and the pulse insertion unit 54 includes two FFs (flip flops) 116 and 118, an AND gate 120, and an OR gate 122. Here, the ring oscillator 50 may be configured on a single chip together with a plurality of electronic circuits such as the phase comparison unit 52 and the pulse insertion unit 54.

  The phase control unit 56 includes a pulse insertion setting register 100, a counter 102, a plurality of change point detection units 104, a plurality of AND gates 110, an OR gate 112, and an FF (flip flop) 114. The counter 102 is an M-bit counter (M is a natural number). In this embodiment, the counter 102 is a 12-bit counter from the least significant bit COUNT0 to the most significant bit COUNT11. On the other hand, the pulse insertion setting register 100 is an (M + 1) -bit register that stores the number of insertion pulses to be inserted in the pulse insertion unit 54. In this embodiment, from the least significant bit REG0 to the most significant bit REG12. It is a 13-bit register.

  The change point detection unit 104 includes an FF (flip-flop) 106 and an AND gate 108 and can detect a change point of the bit of the counter 102. In this example, the change point detection unit 104 is provided in the bits from COUNT1 to COUNT11 of the counter 102. The AND gate 110 calculates a register value corresponding to the (M−n + 1) (n is a natural number) th bit of the pulse insertion register 100 and an output value of the change point detection unit 104 corresponding to the nth bit of the counter 102. Logical AND. That is, in the illustrated configuration, REG0 and COUNT11, REG1 and COUNT10, REG2 and COUNT9, REG3 and COUNT8, REG4 and COUNT7, REG5 and COUNT6, REG6 and COUNT5, REG7 and COUNT4, REG8 and COUNT3, REG9 and COUNT2, And COUNT1 and REG11 and COUNT0 bits are associated with each other. The OR gate 112 calculates the logical sum of the output values of the plurality of AND gates 110 and the bits of the REG 12. The output of the OR gate 112 is supplied to the FF 114, and the FF 114 supplies the pulse insertion unit 54 with a phase control signal 74 that determines the timing for inserting the insertion pulse.

  The delay phase lock unit 58 includes a subtraction circuit 60 and a pulse width adjustment unit 62, and the subtraction circuit 60 includes a subtraction unit 130 and a filter 132. The subtractor 130 performs a subtraction operation on two inputs, and the filter 132 supplies a voltage value obtained by averaging the subtraction results to the pulse width adjuster 62. The pulse width adjustment unit 62 adjusts the phase of the shift clock 70 by adjusting the power supply voltage of the power supply voltage unit 90.

  The operation of each component that generates the delay clock 82 will be described below.

  The reference clock 34 of 266 MHz is divided by 1/8 by the synchronization reference clock generator 92, and the synchronization reference clock 140 that is synchronized with the reference clock 34 and divided by 1/8 is input to the clock input of the FF 96. On the other hand, the ring oscillator 50 that changes the oscillation frequency according to the power supply voltage oscillates the shift clock 70 having the same cycle as that of the reference clock 34 based on the power supply voltage supplied from the power supply voltage unit 90. The shift clock 70 is frequency-divided by 1/8 by the synchronous shift clock generation unit 94, and the synchronous shift clock 142 that is synchronized with the shift clock 70 and frequency-divided by 1/8 is input to the clock input of the FF 98. The synchronization reference clock 140 and the synchronization shift clock 142 have the same period.

  In this embodiment, each of the reference clock 34 and the shift clock 70 is divided by 1/8 by the synchronous reference clock generators 92 and 94, but in other embodiments, it is divided by other division ratios. May be rounded or may not be divided. In this embodiment, “synchronous reference clock” means a clock whose leading edge is synchronized with the leading edge of the reference clock 34, and “synchronous shift clock” means that the leading edge is synchronized with the leading edge of the shift clock 70. Means clock. For example, in another embodiment in which the synchronization reference clock generation units 92 and 94 are not provided, the synchronization reference clock 140 may be the reference clock 34 itself, and the synchronization shift clock 142 is the shift clock 70 itself. May be.

  An inverted synchronization reference clock 141 obtained by inverting the synchronization reference clock 140 is input to R (reset) inputs of the FF 96 and FF 98. The FF 96 and the FF 98 are reset by the leading edge of the inverted synchronization reference clock 141 (that is, at the timing of the trailing edge of the synchronization reference clock 140). Therefore, the trailing edges of the synchronization shift clock 142 and the synchronization reference clock 140 are matched. In this way, the phase comparison unit 52 outputs the reference standard clock 144 and the reference shift clock 146 whose trailing edges are aligned based on the phase difference between the synchronous shift clock 142 and the synchronous reference clock 140. Specifically, the FF 96 outputs the reference standard clock 144, and the FF 98 outputs the reference shift clock 146 whose pulse width is shortened according to the phase difference between the synchronization reference clock 140 and the synchronization shift clock 142. In this example, the synchronization reference clock 140 and the reference reference clock 144 are the same pulse train.

  The pulse insertion setting register 100 stores the number of insertion pulses to be inserted by the pulse insertion unit 54. That is, the pulse insertion setting register 100 stores in advance how many insertion pulses are inserted into the reference shift clock 146 of 4096 cycles (12 bits). As will be described later, the delay time of the delay clock 82 with respect to the reference clock 34 is determined by the number of inserted pulses stored in the pulse insertion setting register 100.

  The counter 102 is a 12-bit counter and increases the output value based on the synchronization reference clock 140 divided by 1/8. The outputs from COUNT1 to COUNT11 are supplied to change point detection units 104 provided in each of them (in FIG. 5, only the change point detection unit 104 provided for COUNT11 is shown). In this example, the change point detection unit 104 is not provided at the subsequent stage of the output of COUNT0, but may be provided in another example.

  The change point detection unit 104 can detect a bit change point of the counter 102. As described above, the change point detection unit 104 is provided in the subsequent stage of COUNT1 to COUNT11. As an example, the operation of the change point detection unit 104 provided in the subsequent stage of COUNT11 will be described.

  The output of COUNT11 is input to the data input of FF106. A synchronous reference clock 140 divided by 1/8 is input to the clock input of the FF 106. The output of the FF 106 is inverted and input to one input terminal of the AND gate 108. The output of COUNT11 is input to the other input terminal of the AND gate. Therefore, when the output of the COUNT 11 changes from the logical value “0” to the logical value “1” based on the synchronization reference clock 140, the AND gate 108 outputs the logical value “1”. The change point detector 104 provided at the subsequent stage of COUNT1 to COUNT10 performs the same operation as described above.

  In the configuration of the phase control unit 56 shown in the figure, the change point detection unit 104 is not provided after the COUNT0. This is because the change point detection unit 104 detects only the change point at which the output value of the bit of the counter 102 is switched, so that the change occurs with respect to COUNT0 in which logical values “0” and “1” appear alternately as outputs. This is because it is not necessary to provide the point detector as a configuration. Therefore, it can be said that the change point detection unit is already provided in the subsequent stage of COUNT0. However, similarly to COUNT1 to COUNT11, the change point detection unit 104 may be provided as a physical configuration in the subsequent stage of COUNT0.

  If the pulse insertion unit 54 collectively inserts insertion pulses into a plurality of cycles (4096 cycles (12 bits in this embodiment)), a low-frequency ripple may occur in the power supply. Therefore, it is desirable that the insertion pulse is inserted in a time-series manner during a plurality of cycles of the reference shift clock 146.

  In order to spread and insert the insertion pulse in a plurality of cycles of the reference shift clock 146 in a time series, the AND gate 110 in the phase control unit 56 uses (M−n + 1) (n Is a logical product of the register value corresponding to the nth bit and the output value of the change point detector 104 corresponding to the nth bit of the counter 102. That is, the output of REG (12-n) (n: 1 ≦ n ≦ 12) of the pulse insertion setting register 100 is input to one input of each AND gate 110, and the COUNT of the counter 102 is input to the other input. The output of the change point detection unit 104 corresponding to (n-1) or the output of COUNT0 is input. If the output of REG (12-n) and the output of the change point detection unit 104 corresponding to COUNT (n-1) or the output of COUNT0 take a logical value “1”, each AND gate 110 outputs a logical value. Outputs “1”. The output of the AND gate 110 is input to the OR gate 112. The output of the bit of REG12 is input to the OR gate 112. In this embodiment, when the insertion pulse is inserted 4096 times (# 1000000000000) in 4096 cycles, the register value of REG12 becomes “1”. The OR gate 112 calculates the logical sum of the outputs of all the AND gates 110 and the register value of the REG 12, and outputs the logical sum to the data input of the FF 114 in the subsequent stage. The timing for inserting the insertion pulse determined by this configuration will be described in detail with reference to FIG.

  The synchronous reference clock 140 divided by 1/8 is input to the clock input of the FF 114. Further, an inverted synchronization reference clock 141 obtained by inverting the synchronization reference clock 140 is input to the R (reset) input of the FF 114. Based on the outputs of the synchronization reference clock 140, the inverted synchronization reference clock 141, and the OR gate 112, the FF 114 outputs to the pulse insertion unit 54 a phase control signal 74 that determines the cycle of the reference shift clock 146 into which the insertion pulse is inserted.

  The phase control signal 74 is input to the data input of the FF 116, and the data output from the FF 116 is input to the data input of the FF 118. The 266 MHz reference clock 34 is input to the clock inputs of the FF 116 and FF 118, and both the FF 116 and FF 118 are operated by the reference clock 34. Data output from the FF 118 is input to one input terminal of the AND gate 120. The inverted phase control signal 74 is input to the other input terminal of the AND gate 120.

  The AND gate 120 calculates the logical product of the inverted phase control signal 74 and the output data of the FF 118 and outputs an insertion pulse 150. Since the pulse insertion unit 54 has the above configuration, the insertion pulse 150 can be inserted between the trailing edge of the reference shift clock 146 and the next leading edge of the shift clock. Specifically, the AND gate 122 rises at the timing of the trailing edge of the reference shift clock 146 and outputs the insertion pulse 150 that maintains the logical value “1” for two periods of the 266 MHz reference clock 34 and falls thereafter. .

  The OR gate 122 calculates the logical sum of the reference shift clock 146 and the insertion pulse 150 and inserts the insertion pulse 150 into the reference shift clock 146. The OR gate 122 outputs the reference shift clock 152 into which the insertion pulse 150 is inserted to the driver 164. The driver 164 outputs the reference shift clock 152 to the subtraction unit 130 in a differential manner. Similarly, the reference standard clock 144 is supplied to the OR gate 124, and the OR gate 124 outputs the reference standard clock 148 to the driver 162. Here, the reference standard clock 144 and the reference standard clock 148 are the same pulse train.

  The subtracting unit 130 subtracts the potential of the pulse train of the reference shift clock 152 into which the insertion pulse 150 is inserted from the potential of the pulse train of the reference standard clock 148. The subtraction result 154 after subtraction is filtered by the filter 132 and averaged. The filter 132 outputs the averaged subtraction result 78 to the pulse width adjustment unit 62. The value of the averaged subtraction result 78 is related to the phase difference between the reference clock 34 and the shift clock 70, the pulse width of the insertion pulse 150, and the number of insertions.

  A subtraction result 78 of 0 indicates that the delay clock 82 has a desired (predetermined) delay time with respect to the reference clock 34. On the other hand, if the subtraction result 78 is not 0, the delay clock 82 does not have a desired delay time, and it is necessary to adjust the pulse width of the reference shift clock 152 by changing the oscillation frequency of the ring oscillator 50. . The pulse width adjustment unit 62 generates a voltage adjustment signal 80 for adjusting the power supply voltage of the power supply voltage unit 90 based on the subtraction result 78. The power supply voltage unit 90 adjusts the power supply voltage supplied to the ring oscillator 50 based on the voltage adjustment signal 80 and adjusts the frequency of the shift clock 70. That is, the pulse width of the reference shift clock 152 can be adjusted. The delay phase lock unit 58 adjusts the power supply voltage unit 90 until the subtraction result 78 becomes 0, locks the state of each component when the subtraction result 78 becomes 0, and has a predetermined delay time. The clock 82 can be generated.

  When the ring oscillator 50 is configured on a single chip together with a plurality of electronic circuits, a power supply voltage supply unit that supplies the power supply voltage adjusted based on the average value of the subtraction results 78 to the plurality of electronic circuits ( (Not shown) is preferably provided. By supplying the adjusted power supply voltage also to other electronic circuits on the same chip, it becomes possible to compensate for the timing error due to the overall temperature drift and power supply fluctuation.

  FIG. 6 is a diagram for explaining an insertion method for inserting the insertion pulse 150 into the reference shift clock 146. 6A and 6C, for the sake of simplicity, the reference shift clock 146 pulse is not shown, and only the insertion pulse 150 pulse is shown.

  FIG. 6A shows a state in which the insertion pulse 150 is inserted together with the reference shift clock 146. FIG. 6B shows a low frequency ripple generated in the power supply by inserting the insertion pulse 150 together with the reference shift clock 146. When ripples occur in the power supply, the power supply voltage fluctuates, making it difficult to supply a stable voltage. Such a ripple is not preferable for generating a delay clock having an accurate delay time.

  FIG. 6C shows a state in which the insertion pulse 150 is diffused in time series and inserted into the reference shift clock 146. By inserting the insertion pulse 150 in a dispersed manner, the ripple shown in FIG. 6B does not occur, and a stable voltage supply can be realized. Therefore, in order to generate a delay clock having an accurate delay time, it is preferable to insert the insertion pulse 150 in a dispersed manner.

  FIG. 7 is a diagram illustrating an example of a cycle in which an insertion pulse is inserted in a plurality of cycles based on the phase control signal 74 generated by the configuration of the phase control unit 56 illustrated in FIG. In this example, in order to simplify the description, the timing for inserting an insertion pulse into a 16-cycle shift clock will be described. That is, in this example, the pulse insertion setting register 100 is a 5-bit register having the least significant bit REG0 to the most significant bit REG4, and the counter 102 is 4 having the least significant bit COUNT0 to the most significant bit COUNT3. It is a bit counter. In this case, as described with reference to FIG. 5, REG0 and COUNT3, REG1 and COUNT2, REG2 and COUNT1, and REG3 and COUNT0 are associated with each other.

  In FIG. 7, the vertical axis represents the number of insertion pulses inserted, the horizontal axis represents time series (cycle), and ◯ represents that the insertion pulse is inserted into the cycle. As shown in the figure, according to the phase control unit 56 in the present embodiment, it is possible to insert and insert the insertion pulse in time series. When insertion pulses are inserted into all 16 cycles, that is, when the number of pulse insertions is set to 16 (# 10000), “1” is stored in REG4, and the insertion pulses are always inserted into the shift clock. become. Thus, in order to insert the insertion pulse in every cycle, the number of bits of the pulse insertion setting register 100 is preferably one more than the number of bits of the counter 102.

  FIG. 8 shows a shift clock in which an insertion pulse is inserted in the cycle shown in FIG. FIG. 8A shows a 16-cycle shift clock in which three insertion pulses are inserted when the number of pulse insertions is set to three. In the figure, the insertion pulse is shown hatched with diagonal lines, and it is shown that the insertion pulse is inserted in the fourth, eighth and twelfth cycles in 16 cycles. FIG. 8B shows a 16-cycle shift clock in which seven insertion pulses are inserted when the number of pulse insertions is set to seven. At this time, insertion pulses are inserted in the second, fourth, sixth, eighth, tenth, twelfth and fourteenth cycles.

  FIG. 9 is a timing chart of each signal shown in FIG. Hereinafter, the operation of each component shown in FIG. 5 will be described in detail with reference to FIGS.

  A reference clock 34 of 266 MHz (period 3.76 ns) is input to the synchronous reference clock generation unit 92. On the other hand, the ring oscillator 50 oscillates a shift clock 70 having the same cycle as the reference clock 34. In the example shown in FIG. 9, the shift clock 70 is delayed by τ from the reference clock 34. The reference clock 34 and the shift clock 70 are input to the synchronous reference clock generation units 92 and 94, respectively, and are divided by 1/8. The period of the synchronization reference clock 140 and the synchronization shift clock 142 divided by 1/8 is 30.08 ns (half period 15.04 ns).

  The synchronization reference clock 140 and the synchronization shift clock 142 are input to the phase comparison unit 52, and the trailing edge of the synchronization shift clock 142 is aligned with the trailing edge of the synchronization reference clock 140. The reference shift clock 146 output from the phase comparison unit 52 is a pulse in which the period of the logical value “1” is shorter by τ in one cycle than the reference standard clock 144. The reference standard clock 144 is output to the driver 162 as the reference standard clock 148 via the OR gate 124, and the reference standard clock 148 is supplied from the driver 162 to the subtraction unit 130.

  The pulse insertion unit 54 generates an insertion pulse 150 based on the reference clock 34. The insertion pulse 150 is a pulse train in which the period of the logical value “1” is a length corresponding to two periods (7.52 ns) of the reference clock 34. The reference shift clock 146 and the insertion pulse 150, which are aligned at the trailing edge, are input to the OR gate 122 and ORed. The insertion pulse 150 is inserted between the trailing edge of the reference shift clock 146 and the next leading edge, and the OR gate 122 outputs the reference shift clock 152 with the insertion pulse 150 inserted to the driver 164. The reference shift clock 152 is supplied from the driver 164 to the subtraction unit 130.

  In the subtracting unit 130, the reference standard clock 148 and the reference shift clock 152 are subtracted. The subtraction unit 130 outputs the subtraction result 154 to the filter 132. The filter 132 averages the subtraction results and outputs the averaged subtraction result 78 to the pulse width adjustment unit 62. The pulse width adjustment unit 62 adjusts the power supply voltage of the power supply voltage unit 90 and adjusts the oscillation frequency of the ring oscillator 50 so that the subtraction result 78 becomes zero.

As shown in the timing chart of the subtraction result 154, the pulse width based on the phase difference between the reference clock 34 and the shift clock 70 is w1, and the pulse width of the insertion pulse is w2. Here, w1 is τ and w2 is 7.52 ns. In this example, if the number of insertion pulses is set to N, the output of the filter 132 is
(W1 × 4096 (number of cycles)) − (w2 × N (number of insertions)) (1)
Is proportional to That is, the pulse width adjustment unit 62 adjusts the oscillation frequency of the ring oscillator 50 so that the value of the expression (1) becomes 0, and as a result, the pulse width of the w1 is adjusted, so that the shift clock 70 has a desired ( A delay clock 82 is generated with a predetermined delay amount.

  In this embodiment, a case where the maximum phase difference is set by inserting the insertion pulse 150a in all the cycles (4096 cycles) of the reference shift clock 146 will be described.

  At this time, the insertion pulse 150a is inserted into the reference shift clock 146. The insertion pulse 150 a is a pulse train having a pulse in all portions of the logical value “0” of the reference shift clock 146. The reference shift clock 146 and the insertion pulse 150a are ORed in the OR gate 122, and the OR gate 122 outputs the reference shift clock 152a in which the insertion pulse 150a is inserted to the driver 164. The reference standard clock 148 and the reference shift clock 152a are subtracted by the subtracting unit 130, and the subtracting unit 130 outputs a subtraction result 154a.

  Referring to Equation (1), w2 at this time is 7.52 ns, and N is 4096. The pulse width adjustment unit 62 adjusts the oscillation frequency of the ring oscillator 50 so that the subtraction result 78 obtained by averaging the subtraction results 154a becomes zero. Later, when the subtraction unit 130 outputs a subtraction result 154a ′ that is a pulse train having a pulse width w1 of 7.52 ns, the averaged subtraction result 78 becomes zero. At this time, the ring oscillator 50 oscillates a synchronous shift clock 142a having a delay time (maximum phase difference) of 7.52 ns.

  As described above, the delay clock generation apparatus according to the present embodiment can accurately and accurately generate a delay clock having a predetermined delay time according to the number of insertion pulses inserted in a predetermined cycle (4096 cycles). Become. In this embodiment, all the insertion pulses 150 have the same pulse width. However, by adjusting the pulse width of the insertion pulse 150, it is possible to generate a delay clock having a predetermined delay time. For example, it is possible to generate a delay clock having a predetermined (desired) delay time by inserting an insertion pulse 150 having a pulse width equal to a desired delay time into every cycle of the reference shift clock 146.

  FIG. 10 is a block diagram of a delay time measuring apparatus that measures the delay time of the delay line 176 (176a to 176n). The delay time measuring apparatus includes a logic unit 172, a high accuracy unit 174, and a delay phase lock unit 58. The logic unit 172 includes a phase control unit 56, an average unit 198, and a measurement unit 200. The high precision unit 174 includes a ring oscillator 50, a synchronization reference clock generation unit 92, a synchronization shift clock generation unit 94, a phase comparison unit 52, a pulse insertion unit 54, delay lines 176a to 176n, and timing comparison units 178a to 178n. In addition, the delay phase lock unit 58 includes a subtraction circuit 60 and a pulse width adjustment unit 62. Here, the ring oscillator 50, the phase comparison unit 52, the pulse insertion unit 54, the phase control unit 56, the synchronization reference clock generation unit 92, the synchronization shift clock generation unit 94, the subtraction circuit 60, and the pulse width adjustment unit 62 are shown in FIG. The delay clock generation device described in detail in connection with 5 is formed. First, in this delay time measuring apparatus, the operation of each configuration in which the delay clock generation apparatus generates a delay clock will be briefly described.

  The reference clock 34 is input to the synchronous reference clock generation unit 92. The synchronization reference clock generation unit 92 outputs a synchronization reference clock 140 obtained by dividing the reference clock 34 by 1/8. On the other hand, the ring oscillator 50 oscillates a shift clock 70 having the same frequency as that of the reference clock 34. The shift clock 70 is input to the synchronous shift clock generation unit 94, and the synchronous shift clock generation unit 94 outputs the synchronous shift clock 142 divided by 1/8. In the phase comparison unit 52, the trailing edge of the synchronization shift clock 142 is aligned with the trailing edge of the synchronization reference clock 140 and is output from the phase comparison unit 52 as the reference shift clock 146.

  The synchronization reference clock 140 output from the synchronization reference clock generation unit 92 is supplied to the phase control unit 56, and the phase control unit 56 pulses the phase control signal 74 that determines the cycle of the reference shift clock 146 into which the insertion pulse is inserted. Output to the insertion unit 54. The pulse insertion unit 54 inserts an insertion pulse into the cycle defined by the phase control signal 74 of the reference shift clock 146, and outputs the reference shift clock 152 into which the insertion pulse has been inserted. The reference standard clock 144 and the reference shift clock 152 are sent to the subtraction circuit 60 and subtracted. The subtraction circuit 60 averages the subtraction results and supplies the averaged subtraction result 78 to the pulse width adjustment unit 62. Based on the subtraction result 78, the pulse width adjustment unit 62 outputs a voltage adjustment signal 80 for adjusting the power supply voltage of the ring oscillator 50 and adjusts the oscillation frequency of the ring oscillator 50. The ring oscillator 50 oscillates a shift clock (delay clock) 70 having an accurate delay time with respect to the reference clock 34 based on the voltage adjustment signal 80. Here, the synchronous shift clock 142 obtained by dividing the shift clock 70 by 1/8, that is, the synchronous delay clock 170 also has an accurate delay time with respect to the reference clock 34.

  Next, the connection relationship and function of each component of the delay time measuring apparatus that measures the delay times of the delay lines 176a to 176n using the delay clock generated by the delay clock generating apparatus will be described. As described with reference to FIG. 1, the plurality of delay lines 176a to 176n have a plurality of delay elements, and a desired (predetermined) delay time can be generated by combining the plurality of delay elements. it can. In this embodiment, the reference clock 34 is input to the delay lines 176a to 176n in order to measure the delay time of the delay lines 176a to 176n. The delay lines 176a to 176n have an input end and an output end of the reference clock 34, and the input end is connected to reference clock supply means (not shown). In this embodiment, the timing comparison means 178a to 178n are flip-flops operated by a synchronous delay clock 170 having an accurate predetermined delay time with respect to the reference clock 34, and output terminals of the delay lines 176a to 176n. Are respectively connected to the data inputs of the timing comparison means 178a to 178n. The outputs of the timing comparison means 178a to 178n are averaged in the averaging unit 198, and the measuring unit 200 measures the delay times of the delay lines 176a to 176n based on the average result in the averaging unit 198.

  A first embodiment of the delay time measuring method for measuring a predetermined delay time in the delay lines 176a to 176n will be described below. The delay time measuring method in the first embodiment selects a combination of delay elements in the delay lines 176a to 176n that generate an equal delay time with respect to a predetermined delay time of the delay clock generated by the delay clock generator. It is characterized by doing. Since this delay time measuring method is executed in the same procedure for each of the plurality of delay lines 176a to 176n, the delay time measuring method for one delay line 176a will be described below.

  First, a delay element is appropriately selected to set a fixed delay time in the delay line 176a. As a selection method of the delay elements, it is desirable to select the delay elements so that a desired delay time to be generated and a design delay time generated by combining the delay elements are equal. Then, the reference clock 34 is supplied to the input terminal of the delay line 176a set with a certain delay time. The reference clock 34 is output from the delay line 176a as a delay pulse 177a delayed by the selected delay element. The delay pulse 177a is input to the data input of the timing comparison means 178a. Further, the synchronous delay clock 170 is input to the clock input of the timing comparison means 178a. At this time, a shift clock (delayed clock) 70 having the same frequency as that of the reference clock 34 may be input to the clock input.

  The timing comparison means 178a compares the timing of the edge (leading edge or trailing edge) of the delay pulse 177a and the edge (leading edge or trailing edge) of the synchronous delay clock 170, and compares the comparison result with a logical value “0” or “1”. Is a flip-flop that outputs as In this embodiment, the timing comparison means 178a is a positive edge type flip-flop that operates at the leading edge of the clock. When the timing comparison means 178a receives the leading edge of the synchronous delay clock 170, it is input to the data input at that time. The data that has been read is output. The output logic value is supplied to the averaging unit 198, where the output logic value is averaged. For example, when the timing comparison means 178a receives the leading edge of the shift clock 170 100 times, outputs the logical value “1” 70 times, and outputs the logical value “0” 30 times, the averaging unit 198 averages the result. The value is 0.7. The average value generated in the average unit 198 is sent to the measurement unit 200, and the measurement unit 200 measures the delay time of the delay line 176a. In this embodiment, the measurement unit 200 determines whether or not the delay time of the delay line 176a is equal to the delay time of the synchronous delay clock 170.

  FIG. 11 is a timing chart showing the timing of the synchronous delay clock 170 and the delay pulses 177 (A), 177 (B), and 177 (C) input to the data input of the timing comparison means 178a. The leading edge of the synchronous delay clock 170 is input to the clock input of the timing comparison means 178a at time t.

  The delay pulse 177 (A) takes a logical value “1” at time t. The synchronous delay clock 170 has a frequency obtained by multiplying the frequency of the delay pulse 177 (A) by 1/8. Therefore, even at the time when the next leading edge of the synchronous delay clock 170 occurs, the delay pulse 177 (A). Takes the logical value "1". Therefore, the delay pulse 177 (A) always takes the logical value “1” when the leading edge of the synchronous delay clock 170 occurs, and the output of the timing comparison means 178a always takes the logical value “1”. At this time, the average value of the logical values averaged by the averaging unit 198 shown in FIG. 10 is “1”.

  The delay pulse 177 (B) takes a logical value “0” at time t. As described with respect to the delay pulse 177 (A), the delay pulse 177 (B) takes a logical value “0” even at the time when the next leading edge of the synchronous delay clock 170 occurs. Therefore, when the leading edge of the synchronous delay clock 170 occurs, the delay pulse 177 (B) always takes the logical value “0”, and the output of the timing comparison means 178a always takes the logical value “0”. At this time, the average value of the logical values averaged by the averaging unit 198 is “0”.

  On the other hand, the delay pulse 177 (C) takes a logical value “0” or “1” at time t. Since the leading edge of the synchronous delay clock 170 is input to the timing comparison means 178a during the rising time from the start of the leading edge of the delay pulse 177 (C) to the end of rising, the output of the timing comparison means 178a is "1 It is undefined whether it is “or” or “0”, and it is not always “1” or “0”. Therefore, at this time, the average value of the output logical values of the timing comparison means 178a takes a value between 0 and 1. When the average value of the output logic values averaged in the averaging unit 198 takes a value between 0 and 1, the measuring unit 200 has the delay time of the synchronous delay clock 170 substantially equal to the delay time of the delay line 176a. Judge that. In order to determine the optimum combination of delay elements, it is preferable that the average value of the output logic value of the timing comparison means 178a takes a value from 0.3 to 0.7, and the average value is approximately 0.5. Is preferred. When the timing comparison unit 178a outputs the same number of logical values “1” or “0” during a predetermined period, the average value of the output logical values of the timing comparison unit 178a is 0.5, and the measurement unit 200 determines that the delay line It is determined that the delay amount of 176a is equal to the predetermined delay time of the synchronous delay clock 170. Referring to FIG. 1, data relating to the delay time of delay line 176a measured as described above is stored in linearized memory 196 and used later in the test of a semiconductor device.

  As described above, when the delay pulse 177 (A) is input to the timing comparison means 178a, the average value of the output logic value of the timing comparison means 178a is always "1", and the delay pulse 177 (B) is the timing comparison. When input to the means 178a, the average value of the output logical values of the timing comparison means 178a is always "0". An average value of “1” or “0” indicates that the delay time generated by the combination of the delay elements in the delay line 176a is not equal to the predetermined delay time of the synchronous delay clock 170. Therefore, in these cases, the delay line 176a is selected by selecting a combination of delay elements so that the average value in the timing comparison means 178a takes a value between 0 and 1 (preferably 0.5). It is possible to adjust the predetermined delay time in.

  As described with reference to FIGS. 10 and 11, when the delay clock generation device according to the present invention is used, a synchronous delay clock 170 having a very accurate delay time can be generated. Thus, a combination of delay elements having the delay time can be set appropriately. Further, according to this embodiment, it is possible to set a combination of delay elements having a predetermined delay time by parallel processing for all delay lines from the delay lines 176a to 176n. Further, according to this embodiment, it is possible to measure a delay time with very high accuracy in the delay line. As described above, according to the present invention, the delay time can be measured at a lower cost and faster than the conventional delay time measurement method in which the delay time of the delay line is measured using an oscilloscope.

  The second embodiment of the delay time measuring method for measuring a predetermined delay time in the delay lines 176a to 176n will be described below. The delay time measuring method in the second embodiment is characterized in that the delay amount of the delay line 176a is determined by matching the delay time of the synchronous delay clock 170 with the delay amount of the delay line 176a.

  First, an arbitrary delay element in the delay line 176a is selected. Then, the reference clock 34 is supplied to the input end of the delay line. The ring oscillator 50 oscillates a delay clock 70 having a predetermined delay time, and a synchronous delay clock 170 obtained by dividing the delay clock 70 by 1/8 is input to the clock input of the timing comparison means 178a. The averaging unit 198 averages the output logical values of the timing comparison means 178a.

  If the average value of the output logical value of the timing comparison means 178a is a value between “0” and “1” (preferably approximately 0.5), a delay generated by a combination of arbitrarily selected delay elements The measurement unit 200 determines that the time is equal to the delay time of the synchronous delay clock 170. On the other hand, if the average value of the output logical values is “0” or “1”, the measurement unit 200 indicates that the delay time generated by the combination of the delay elements is not equal to the delay time of the synchronous delay clock 170. Determined. At this time, the pulse width adjustment unit 62 adjusts the oscillation frequency of the ring oscillator 50 based on the average value of the output logic values in the averaging unit 198 and changes the delay time of the delay clock 70. The delay time of the delay clock 70 is adjusted until the average value of the output logical values of the timing comparison means 178a takes a value between “0” and “1”. When the average value takes a value between “0” and “1”, it is determined that the delay time generated by the combination of the delay elements is equal to the delay time of the delay clock 70. Data of a combination of delay elements that generate a predetermined delay time is written to a predetermined address of the linearized memory 196 in FIG. 1 for each delay line 176.

  According to the present invention, in the semiconductor test apparatus, the delay line 176 can generate a desired delay timing according to the characteristics of the device under test. That is, the semiconductor test apparatus incorporating the delay clock generation apparatus and / or delay time measurement apparatus according to the present invention can test a device under test with a highly accurate delay timing. In FIG. 3, the delay specifying signal 36 is output through the delay line in the timing generator 14. However, the delay specifying signal 36 may be directly generated by the delay clock generating device according to the present invention.

  As is apparent from the above description, according to the present invention, a highly accurate delay clock can be generated, and further, the delay time of the delay line can be accurately measured. As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements are also included in the technical scope of the present invention.

  According to the present invention, there is an effect that a highly accurate delay clock can be generated. Further, according to the present invention, for example, there is an effect that the delay time of the delay line in the semiconductor test apparatus can be accurately measured.

It is a block diagram which shows an example of the delay line 176 which delays a test pattern by predetermined delay amount in a semiconductor test device. It is a block diagram which shows the conventional structure which measures the output signal of the waveform shaper 12, delayed with respect to the signal generated by the pattern generator 10 in the semiconductor test apparatus. 1 is a block diagram of a semiconductor test apparatus that tests a device under test 22. FIG. It is a block diagram which shows the delay clock generator which is embodiment of this invention which produces | generates the delay clock which delayed the reference clock only for predetermined time. It is a circuit block diagram which shows the delay clock generator which is embodiment of this invention which produces | generates the delay clock which delayed the reference clock only for predetermined time. (A) shows a state in which insertion pulses are collectively inserted into the shift clock, (b) shows low-frequency ripple generated in the power supply by inserting the insertion pulses into the shift clock, and (c) shows The state where the insertion pulse is spread in time series and inserted into the shift clock is shown. It is a figure which shows an example of the cycle which inserts an insertion pulse in several cycles with the structure of the phase control part 56 shown by FIG. (A) shows a 16-cycle shift clock into which three insertion pulses are inserted when the number of pulse insertions is set to 3, and (b) shows 7 cycles when the number of pulse insertions is set to 7. A 16-cycle shift clock with one inserted pulse inserted is shown. 6 is a timing chart of each signal shown in FIG. 5. 4 is a block diagram of a delay time measuring device for determining a delay time of a delay line 176. FIG. It is a timing chart which shows the timing of the delay pulse 177 (A), 177 (B), and 177 (C) input into the data input of the synchronous delay clock 170 and the timing comparison means 178a.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Pattern generator, 12 ... Waveform shaper, 14 ... Timing generator, 16 ... Oscilloscope, 18 ... Device insertion part, 20 ... Comparator, 22 ... Device under test, 24 ... delayed signal generator, 32 ... measurement signal, 33 ... input pattern, 34 ... reference clock, 35 ... reference reference clock, 36 ... delay designation signal 38 ... Delay measurement signal, 39 ... Delay signal, 40 ... Output signal, 42 ... Expected value pattern, 50 ... Ring oscillator, 52 ... Phase comparator, 54 ...・ Pulse insertion unit, 56... Phase control unit, 58... Delayed phase lock unit, 60... Subtracting circuit, 62. Reference shift clock, 74 ... phase control signal, 8 ... subtraction result, 80 ... voltage adjustment signal, 82 ... delay clock, 90 ... power supply voltage section, 92, 94 ... 8 frequency divider, 96, 98 ... FF (flip-flop) 100 ... Pulse insertion setting register, 102 ... Counter, 104 ... Change point detection unit, 106 ... FF, 108 ... AND gate, 110 ... AND gate 110, 112 OR gate, 114, 116, 118 ... FF (flip-flop), 120 ... AND gate, 122,124 ... OR gate, 130 ... subtraction unit, 132 ... filter, 140 ..Synchronous reference clock, 141... Inverted synchronous reference clock, 142... Synchronous shift clock, 144... Reference reference clock, 146. Reference clock, 150 ... Insertion pulse, 152 ... Reference shift clock, 154 ... Subtraction result, 162, 164 ... Driver, 170 ... Synchronous delay clock, 172 ... Logic part, 174 ... High precision section, 176, 176a, 176n ... delay line, 177 ... delay pulse, 178a-178n ... timing comparison means, 180, 184, 188, 192 ... delay element, 182, 186, 190, 194 ... selector, 196 ... linearize memory, 198 ... average part, 200 ... measurement part

Claims (19)

A delay clock generation device that generates a delay clock obtained by delaying a reference clock by a predetermined time,
An oscillator that oscillates a shift clock having the same period as the reference clock;
A pulse insertion unit for generating an insertion pulse to be inserted into a reference shift clock in which at least one of a leading edge and a trailing edge is synchronized with a leading edge or a trailing edge of the shift clock;
The phase of the shift clock oscillated in the oscillator is based on the reference reference clock synchronized with the reference clock and having the same cycle as the reference shift clock, and the reference shift clock having the insertion pulse inserted therein. A delay clock generation apparatus comprising: a delay phase lock unit configured to generate the delay clock that is delayed with respect to a phase of the clock and delayed the reference clock by the predetermined time.   A phase for outputting the reference reference clock and the reference shift clock based on a phase difference between a synchronous shift clock synchronized with the shift clock and a synchronous reference clock synchronized with the reference clock and having the same period as the synchronous shift clock. The delay clock generation apparatus according to claim 1, further comprising a comparison unit.   3. The delayed clock generation according to claim 2, wherein the phase comparison unit outputs the reference reference clock and the reference shift clock whose trailing edges are matched based on the synchronization reference clock and the synchronization shift clock. apparatus.   4. The delayed clock generation apparatus according to claim 3, wherein the pulse insertion unit inserts the insertion pulse between a trailing edge of the reference shift clock and a leading edge of a next reference shift clock.   The delay clock generation apparatus according to claim 4, wherein the pulse insertion unit inserts the insertion pulse into the reference shift clock in synchronization with the reference clock. A synchronization reference clock generation unit that divides the reference clock and outputs the synchronization reference clock;
6. The synchronous shift clock generation unit according to claim 2, further comprising a synchronous shift clock generation unit that divides the shift clock so as to have the same period as the synchronous reference clock and outputs the synchronous shift clock. The delay clock generation device described. A phase control unit that generates a phase control signal that determines in which cycle of the plurality of cycles of the reference shift clock the insertion pulse is inserted;
The delay clock generation apparatus according to claim 1, wherein the pulse insertion unit inserts the insertion pulse into a cycle of the reference shift clock determined by the phase control signal.   The delay phase lock unit delays the phase of the shift clock oscillated in the oscillator based on the number of insertions of the insertion pulse inserted in a plurality of cycles of the reference shift clock. The delay clock generation device described in 1. The delay phase lock unit includes:
A subtraction circuit that outputs an average value of the result of subtracting the potential of the pulse train of the reference shift clock into which the insertion pulse has been inserted from the potential of the pulse train of the synchronization reference clock;
8. A pulse width adjustment unit that adjusts a pulse width of the reference shift clock into which the insertion pulse is inserted so that the average value of the subtraction results in the subtraction circuit becomes zero. 9. The delay clock generation device according to 8. The oscillator is a ring oscillator whose oscillation frequency changes according to a power supply voltage;
The pulse width adjustment unit adjusts the pulse width of the reference shift clock into which the insertion pulse is inserted by adjusting the power supply voltage of the ring oscillator based on the average value of the subtraction result in the subtraction circuit. The delay clock generation device according to claim 9. The ring oscillator is configured on a single chip with a plurality of electronic circuits,
The delay clock generation apparatus according to claim 10, further comprising a power supply voltage supply unit that supplies the power supply voltage adjusted based on the average value of the subtraction results to the plurality of electronic circuits. The oscillator is a voltage controlled oscillator in which an oscillation frequency changes according to a control voltage,
The pulse width adjustment unit adjusts the control voltage of the voltage controlled oscillator based on the average value of the subtraction result in the subtraction circuit, thereby reducing the pulse width of the reference shift clock into which the insertion pulse is inserted. The delay clock generation apparatus according to claim 9, wherein the delay clock generation apparatus adjusts the delay clock generation apparatus.   The phase control signal is generated by the phase control unit so as to diffuse and insert the insertion pulse in a plurality of cycles of the reference shift clock in a time series. The delay clock generation device described in 1. The phase control unit
An M-bit (M is a natural number) counter that increases an output value based on the synchronization reference clock;
An (M + 1) -bit pulse insertion setting register for storing the number of insertion pulses;
A plurality of change point detectors for detecting change points of the counter bits;
A logical product of the register value corresponding to the (M−n + 1) (n is a natural number) th bit of the pulse insertion setting register and the output value of the change point detection unit corresponding to the nth bit of the counter is calculated. A plurality of AND circuits;
The delay clock generation device according to claim 13, wherein the phase control unit determines a cycle in which the insertion pulse is inserted based on the logical product by the AND circuit. A delay time measuring method for measuring a delay time in a delay line, wherein the delay line has an input end and an output end of a reference clock, and the output end has a predetermined delay time with respect to the reference clock. It is connected to the data input of the flip-flop that operates by the delay clock,
A delay time setting step for setting a constant delay time in the delay line;
A reference clock supply step of supplying the reference clock to the input end of the delay line set with the constant delay time in the delay time setting step;
A delay clock supply stage for supplying a synchronous delay clock synchronized with the delay clock to a clock input of the flip-flop;
Averaging output logic values output from the flip-flops;
A delay time measurement method comprising: a delay time measurement step of measuring the delay time in the delay line based on an average value of the output logic values.   The delay time measuring step includes a step of determining that the delay time of the delay line is approximately equal to a predetermined delay time of the delay clock when the average value of the output logic value is approximately 0.5. The delay time measuring method according to claim 15, wherein: A delay time measuring device for measuring a delay time in a delay line,
Delay clock generating means for generating a delay clock having a predetermined delay time with respect to the reference clock;
Reference clock supply means for supplying the reference clock to the delay line;
The timing at which the edge of the delay pulse obtained by delaying the reference clock in the delay line is compared with the timing of the edge of the synchronous delay clock synchronized with the delay clock, and the comparison result is output as a logical value “0” or “1”. A comparison means;
An averaging means for generating an average value obtained by averaging the comparison results output from the timing comparison means;
A delay time measuring apparatus comprising: a measuring unit that measures a delay time in the delay line based on the average value generated by the averaging unit.   18. The delay time measuring apparatus according to claim 17, wherein the timing comparison unit includes a flip-flop having a data input to which the delay pulse is input and a clock input to which the synchronous delay clock is input.   The measurement means according to claim 17 or 18, wherein when the average value is approximately 0.5, the delay time of the delay line is approximately equal to the predetermined delay time of the delay clock. The delay time measuring apparatus described.

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