JPH09214317A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by quickening turn-on of an output stage transistor (TR) in a level shift circuit and setting a rapidly increasing current to be supplied at state transition to be an optimum value. SOLUTION: The level shift circuit 40 has a signal voltage level conversion circuit 30' whose node N2 is not connected to a gate G of an output stage MOSFET 5 and an output buffer circuit 50 charging/discharging a gate capacitance C5 of a flip-flop FF rapidly based on a node voltage Vg of the M0SFET5 and an inverting input signal VIN. As soon as the input signal VIN descends and a MOSFET2 is closed and a MOSFET1 is open, a charging MOFET52a is closed. A rapidly increased drain current flows to the MOSFET2, but since a gate of a MOSFET5 is not connected to the node N2 , the voltage at the node N2 is rapidly dropped, a MOSFET3 is immediately closed to discharge a capacitor C. and a discharge MOSFET 54a is immediately open. Since a capacitor C, is rapidly charged through the closed MOSFET 52a and an output voltage VOUT is rapidly dropped, the MOSFET5 is quickly turned on, Th throughperiod is short and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit (level shifter) for converting an input signal having a narrow logic amplitude in the 3V range into an output signal having a wide logic amplitude in the 30V range, for example.
About.

[0002]

2. Description of the Related Art For example, a liquid crystal drive IC (liquid crystal driver)
In addition to the power transistor in the output stage, a level shift circuit for converting a low voltage level selection signal into a high voltage level liquid crystal drive voltage is built in. Conventionally, as the level shift circuit, a low power consumption type flip-flop circuit configuration, in which CMOSs are connected in two stages and feedback is applied, has been a basic type as shown in FIG. That is,
The level shift circuit 10 shown in FIG.
V (= Vss) to 3V (= Vdd)) power supply with narrow logic amplitude (3V = Vdd-Vss) from logic input signal V _IN to 3 in reverse phase
A CMOS inverter I for generating a V system inverted signal V _IN ^*
NV1 and the first N-channel MOSFET (first switch MOS) 1 for pulling down which is opened and closed by the logic input signal V _IN , and the first N-channel MOSFET 1 which is inverted by the inverted signal V _IN ^* are exclusively opened and closed. Second pull-down N-channel MOSFET (second switch MO
S) 2 and, for example, 30 V (0 V (Vss) to 30 V (Vcc))
The first N-channel MOSFET 1 and the totem pole connection (serial connection) are connected between the high-voltage power supplies, and the first P-channel MOSFET 3 that is closed by closing the second N-channel MOSFET 2 and 30 V (0 V ( Vss) ~ 30V
(Vcc)) A second N-channel MOSFET 2 between the power supplies
And totem pole connection, the first N-channel type M
The second P-channel MOSFET 4 is closed by closing the OSFET 1.

Here, the first P-channel MOSFET
3 and the second P-channel MOSFET 4 are drains
A flip-flop (bistable circuit) FF in which nodes (storage nodes) N ₁ and N ₂ are cross-connected to their gates is configured. The wide logic amplitude output signal V _out of the level shift circuit 10 is now taken from the drain node N ₂ and its inverted output signal V _out ^* appears at the drain node N ₁ .

In the level shift circuit 10 having such a basic structure, when the logic input signal V _IN rises from the low level 0V (= Vss) having a narrow logic amplitude to the high level 3V (= Vdd), the first N channel The type MOSFET 1 is closed, and since the inverted signal V _IN ^* of the opposite phase falls to 0 V (= Vss), the second N-channel type MOSFET 3 is opened reversely. By closing the first N-channel MOSFET 2, the drain node N ₁ of the flip-flop FF is closed.
0V (= Vss) is sent to the gate and the voltage is determined as a low level with a wide logic amplitude.
Although the voltage of the drain node N ₂ floats and becomes indefinite due to the opening of the node 3, it becomes the second voltage due to the definite voltage of 0 V at the node N ₁ .
Since the P-channel MOSFET 4 is closed, the drain node N ₂ is directly connected to a high level voltage of 30V with a wide logic amplitude.
Set to (= Vcc). As a result, the first P-channel MOSFET 3 is opened. Therefore, the P-channel type MO of the output stage whose gate is connected to the drain node N ₂
SFET5 opens.

On the contrary, the logic input signal V _IN is high level 3V.
When the voltage drops from (= Vdd) to a low level 0V (= Vss), the first N-channel MOSFET 1 is opened and the second N-channel MOSFET 3 is closed. 0V (= Vss) is sent to the drain node N ₂ of the flip-flop FF and the voltage is determined as a low level with a wide logic amplitude, and the voltage of the drain node N ₁ floats and becomes indefinite, but the node N _Since the first N-channel MOSFET 3 is closed by the definite voltage 0V of ₂ , the drain node N ₁ is directly connected to the high level voltage 30 of wide logic amplitude.
Set to V (= Vcc). As a result, the second P-channel MOSFET 4 is opened. Therefore, the P-channel MOSFET 5 in the output stage is closed.

As described above, in the level shift circuit 10,
Low level 0V (Vss) to high level 3V (Vdd) Narrow logic amplitude logic input signal V _IN step waveform of low level 0V (Vss) to high level 30V (Vcc) wide logic amplitude logic output signal A step waveform of V _OUT is obtained.

The level shift circuit 10 described above includes a pre-stage circuit (not shown) for producing the logic input signal V _IN and an M stage of the output stage.
Together with the OSFET 5, it is monolithic as a semiconductor integrated circuit (IC). For this reason, it is desirable that all gate insulating films of MOSFETs in one chip be formed to have the same thickness in view of cost merit by reducing the manufacturing process. However, the potentials of the drain nodes (storage nodes) N ₁ and N ₂ of the flip-flop FF in the level shift circuit 10 described above are set to the switch MOS1,
Since it is set to 0V (Vss) alternately by opening and closing 2,
A first P-channel type MOSFET 3 and a second P-channel type MOSFET 4 constituting a flip-flop FF.
Since the source-drain voltage is high (about 30 V) in the MOSFET 5 of the output stage and the output stage, it is necessary to use a high breakdown voltage transistor in which an offset gate type low concentration drain region is formed. High voltage (approx.
30V) is applied, so MO for the purpose of improving the gate breakdown voltage.
There is no choice but to form the gate insulating film of the SFETs 3, 4, 5 to be thicker than the gate insulating film of the MOSFETs of other low voltage system control circuits.

MOSFETs 3, 4 and output transistor 5
In order to keep the gate-source, gate-drain, and gate-subslate breakdown voltages of 3 V within 3 V, a level shift circuit 20 shown in FIG. 8 is proposed. That is, the level shift circuit 20 is the same as the level shift circuit 10 shown in FIG. 7, except that the first P-channel type MOSFET 3 and the second P-channel type MOSF which form the flip-flop FF.
Constant voltage diode D ₁ of the diode for clamper gates of ET4, a structure connected to a 30 V (Vcc) high-voltage power supply via a D _2.

If the Zener voltage V _Z of these constant voltage diodes D ₁ and D ₂ is about 3 V, the first N-channel type M
Even when the OSFET 1 is closed, the drain node N ₁ is Vcc-V _Z = due to the voltage clamp of the constant voltage diode D _2.
The second P-channel type MOSF that does not drop below 27V
ET4 gate-source, gate-drain, gate-
The voltage between subslates is within 3V. Similarly,
Even when the second N-channel MOSFET 2 is closed, the drain node N ₂ does not fall below about 27 V due to the voltage clamp of the constant voltage diode D ₁ , and the gate-source, gate of the first P-channel MOSFET 3 -Drain,
The voltage between the gate and the substrate is within 3V. Further, the gate-source and gate-subslate voltages of the MOSFET 5 in the output stage are also within 3V. Flip
Not only the MOSFETs 3 and 4 of the flop FF but also the gate withstand voltage of the output stage MOSFET 5 can be 3V. The source-drain voltage of MOSFETs 3 and 4 is also 3
Fits within V. Since the source-drain voltage of the switch MOS1 and MOSFET2 and the MOSFET 5 of the output stage is 3 V or more, a high withstand voltage MOSFET such as an offset gate structure having a low concentration drain region (the element symbol is circled). Is used).

By the way, the level shift circuit 1 shown in FIG.
At 0, in the stable (steady-state) state of the flip-flop FF, the leakage current of the switches MOS1 and 2 (P-channel type M
Except for the saturation currents of the OSFETs 3 and 4, current consumption does not occur in principle, and only a minute through current flows through the two-stage series circuit during the transition process of the flip-flop. Therefore, the power consumption is low. On the other hand, in the level shift circuit 20 shown in FIG. 8, in the process of closing the first switch MOS1,
The current to be passed through the first switch MOS1 is the first P-channel MOSFET 3 closed in the immediately preceding stable state.
Is a breakdown current (write current that sets the storage node N ₁ to a low level) enough to generate a Zener voltage V _Z in the diode D ₂ above the saturation current flowing in the second switch MOS2. The second switch MO
The current that should flow in S2 is the second current that was closed in the last stable state.
Of the P-channel MOSFET 5 in the output stage, and a breakdown current (write current that makes the storage node N ₂ low level) enough to generate the Zener voltage V _Z in the diode D ₁ above the saturation current flowing in the P-channel MOSFET 5 of FIG. It is equal to or more than the sum of the charging current for charging the inter-gate capacity (gate capacity) C ₅ . And the first switch MO
After S1 shifts to a stable state that is a closed state, the first
The current to be passed through the switch MOS1 of the second switch MOS1 may be a minute current (holding current) sufficient for the diode D ₂ to hold the Zener voltage V _{Z, and} after the second switch MOS2 shifts to another stable state which is a closed state. , Its second switch M
The current to be passed through OS2 may be a minute current (holding current) sufficient for the diode D ₁ to hold the Zener voltage V _Z.

However, in the circuit configuration of FIG.
Even after the switch MOS1 of the first switch MOS1 reaches the stable state of the flip-flop FF in the closed state, the first switch MOS
The same current value as that at the time of the state transition still continues to flow in 1 and after the second switch MOS2 reaches another stable state of the flip-flop FF which is in the closed state,
Since the same current value as that at the time of the state transition continues to flow as it is in the switch MOS2, there is a problem that the power consumption is large.

Therefore, the present applicant proposes a level shift circuit 30 including the drain current variable circuits 32 and 34 shown in FIG. This level shift circuit 30 is shown in FIG.
In the level shift circuit 20 shown in FIG. 1, the series source resistances R ₁₁ and R ₁₂ that form a source follower circuit (constant current circuit) together with the first N-channel MOSFET 1 operating in the non-saturation region, and one of the source resistances R N-channel MOSFET 6 for switching source resistance value that shorts ₁₂
Then, at the time point t ₁ when the logic input signal V _IN rises, the switching time pulse P1 having the predetermined pulse width ΔT ₁ is applied to the MOSFET 6
The one-shot circuit (monostable multivibrator) 7 applied to the gate, the second N-channel type MOSFET2 series source resistor R ₂₁ and constituting a source follower circuit (constant current circuit) together with R acting in a non-saturation region ₂₂ and
A source resistance value switching N-channel MOSFET 8 for short-circuiting one of the source resistances R ₂₂ and a logic input signal V
At the time t ₂ when _IN falls, the predetermined pulse width ΔT ₂ (= ΔT
_It has a one-shot circuit 9 for applying the switching timing pulse P2 of ₁ ) to the gate of the MOSFET 8.

The first N-channel MOSFET 1, the source resistances R ₁₁ and R ₁₂ , the source resistance value switching N-channel MOSFET 6 and the one-shot circuit 7 constitute a first drain current variable circuit 32. The N-channel MOSFET 2, the source resistances R ₂₁ , R ₂₂ , the source resistance value switching N-channel MOSFET 8 and the one-shot circuit 9 constitute a second drain current variable circuit 34.

A flip-up that raises the logic input signal V _IN
At the time point t ₁ of the state transition process of the flop FF, the MOSFET 6 is maintained in the closed state for the ΔT ₁ period due to the generation of the switching timing pulse P1, so that the source resistance of the first N-channel MOSFET 1 is only the resistance R ₁₁ . Therefore, the drain current I _D1 flowing through the first N-channel MOSFET 1 rapidly increases, but when the ΔT ₁ period elapses, M
Since the OSFET 6 is opened and the resistor R ₁₂ is connected in series with the resistor R ₁₁ , the drain current I _D1 flowing through the first N-channel MOSFET 1 sharply decreases and returns to a minute current. At the time t of another state transition process when the logic input signal V _IN rises.
_{In 2} , the MOSF is generated by the generation of the switching time-limited pulse P2.
Since the ET8 is maintained in the closed state for the ΔT ₂ period, the source resistance of the second N-channel MOSFET 2 is the resistance R.
_{Since there} are only ₂₁ , the second N-channel MOSFET 2
Although the drain current I _D2 flowing through the IC rapidly increases, when the ΔT ₂ period elapses, the MOSFET 8 is opened and the resistor R ₂₂ is connected in series with the resistor R _21.
The drain current I _D2 flowing through ET2 suddenly decreases and returns to a minute current. Thus, the first and second N-channel MOSFs are
The drain currents I _D1 and I _D2 of ET become a sudden increase drain current I _{MAX in} the transition process of the flip-flop FF, and in the stable state, the power saving drain current (quiescent mode current) I _MIN.
Therefore, it contributes to realization of reliable state transition and reduction of power consumption.

[0015]

By the way, when the level shift circuit 30 shown in FIG. 9 is viewed as a dynamic circuit,
Drain nodes N ₁ and N _{2 of the} flip-flop FF
Power P-channel MOSFET in the output stage
In the configuration in which ₅ is connected, it can be seen that a large-capacity source-gate capacitance C ₅ is connected to one node. Timing symmetry is necessarily broken.

That is, as shown in FIG. 9, when the gate of the P-channel type MOSFET 5 in the output stage is connected to the drain node N ₂ , the first N-channel type M is obtained at time t ₁ .
When the OSFET1 is closed, the second N-channel type MO
When SFET2 is opened, the second P-channel type MOSF
ET4 but is adapted to close, the second P-channel type MOSFET4 source - are built into the chip as a relatively large device for rapidly discharging the gate capacitance C _5. Therefore, since the second P-channel type MOSFET 4 is a larger element than the first P-channel type MOSFET 3, the source-gate capacitance C ₄ which cannot be ignored is inevitably parasitic.

As a result, when the second N-channel type MOSFET 2 is closed and the first N-channel type MOSFET 1 is opened at the time t ₂ when the logic input signal V _IN falls, the source-gate capacitance is initially set. Since the voltage of the drain node N ₁ is hard to rise because of C ₄ , and the second P-channel MOSFET 4 is still closed, the sudden increase in drain current I flowing through the second N-channel MOSFET 2 at the time of state transition. Almost all of _MAX penetrates as a reactive current through the second P-channel MOSFET 4 and is difficult to flow through the constant voltage diode D _1, and the second N-channel MOSF having a relatively large element size is used.
Due to the low on-resistance of ET2, the first P-channel MO
Lowering of the gate voltage of SFET3 (voltage drain node N ₂₎ is delayed. Therefore, MO with a time lag
SFET3 Although Vcc voltage is supplied to the node N ₂ and closed the source - because of the discharge time of the gate capacitance C _4, immediately when the second gate voltage of the P-channel type MOSFET4 not rise, Second P-channel MOSFET 4
Will be opened after the closing of the second N-channel MOSFET 2.

Here, as shown in FIG. 10, the logic input signal V _IN falls and the second N-channel MOSFET 2
The second P-channel type MOSFE from the time t ₂ when the
Rapid increase in drain current I _MAX until time t ₂₁ when T4 opens
Flows as a reactive current Q1. Similarly, the logic input signal V _IN rises and the first N-channel MOSFET
1 from the time t ₁ when the first P-channel type MOSF is closed.
The rapid increase drain current I _MAX flows as the reactive current q1 even during the period until the time point t ₁₁ when the ET3 is opened, but since the gate capacitance of the first P-channel MOSFET 3 can be ignored,
Period up to time t ₁ ~ time t ₁₁ is considerably shorter than the period until time point t ₂ ~ time t _21, also considerably smaller than the reactive current q1 also reactive current Q1.

The second P-channel type MOSF
Becomes the open time t ₂₁ of ET4, second N during state transition
Sudden increase in drain current I flowing in the channel type MOSFET 2
_Since all of _MAX effectively flows through the constant voltage diode D ₁ , the voltage V _{OUT at} the drain node N ₂ drops from the power supply voltage Vcc by the Zener voltage V _Z, and the source-gate capacitance C _{5 is} charged for the first time. Be started.

The charging of the source-gate capacitance C ₅ (charge amount Q2) is a short-circuit discharge due to the closing of the second P-channel MOSFET 4 for a moment, whereas the large capacitance C ₅ and the second N-channel are charged. Since the charging is performed with a relatively large time constant corresponding to the product of the resistance of the source follower circuit including the MOSFET ₂ , the voltage of the drain node N ₂ , that is, the output signal V _OUT is gradually decreased in an exponential function waveform. As a result, the turn-on time T _ON of the P-channel MOSFET 5 in the output stage becomes long, an imbalance with the turn-off time T _OFF occurs, and the P-channel MOSFET 5 in the output stage becomes unbalanced.
Has poor switching characteristics.

In order to eliminate such an imbalance between the turn-on time T _ON and the turn-off time T _OFF , the time t
_In order to rapidly charge the source-gate capacitance C ₅ from ₂₁ , the sudden increase in drain current I _MAX flowing through the second N-channel MOSFET 2 at the time of state transition is further increased. It is conceivable to make the area larger than that of the first N-channel MOSFET 1 to increase the current capacity. This leads to an increase in chip size and raises the cost of the semiconductor integrated circuit, but in addition to this, the following operational difficulties can be pointed out.

As described above, the second N-channel type M
Even if the current capacity of the OSFET 2 itself is increased to perform rapid charging, after all, after all, the second P-channel MOSFET
Since charging of the gate capacitance C ₅ is started only after waiting for the opening time t _{21 of} 4, the turn-on time is inevitably longer than the turn-off time for the charging period t _{21 to} t ₂₃ , and the switching speed is Is bad.

Before that, the second P-channel MO
A source-gate capacitance C ₄ parasitic on the SFET ₄ causes a time lag before the second P-channel MOSFET 4 is opened. Therefore, the turn-on time is longer than the turn-off time, and an imbalance occurs. Has become.

Output-stage P-channel MOSFET 5
In order to rapidly charge the source-gate capacitance C ₅ of the second N-channel type M as shown in FIG.
A further large increase in drain current I _MAX ′ in OSFET2
Even if (> I _MAX ) is flown, the abrupt increase in drain current I _MAX ′ is from the closing time of the second N-channel MOSFET 2 (the rising time of the logic input signal V _IN ) t ₂ to the second P-channel. period opened up to the time t ₂₁ type MOSFET 4, since that must be previously pre-flow as a larger through-current of the two-stage series circuit (reactive current) Q1 ', rather ineffective current increases and power consumption increases I will end up.

Therefore, there is a trade-off between improving the switching speed by shortening the turn-on time and reducing the reactive current at the time of state transition.

Further, since it is a time-switching type current value variable circuit, the time limit for switching from the sudden increase drain current I _MAX to the power saving drain current I _MIN (time t _11, time t ₂₃ ).
Is uniformly time-dependent on the pulse widths ΔT ₁ and ΔT ₂ of the switching time-limited pulse P2 by the one-shot circuits 7 and 9. If the pulse width is too short, the drain current I _MIN decreases before the voltage at the nodes N _{1 and} N ₂ rises or falls sufficiently, resulting in a further delay in rise or fall, resulting in a transition time (turn-on time). , Turn-off time) becomes longer. If the pulse width is too long, the rapid increase in drain current I _MAX continues to flow unnecessarily even after the voltages at the nodes N _{1 and} N ₂ have risen or falled sufficiently, thus increasing power consumption. However, in reality, in consideration of variations in element characteristics and temperature characteristics, the pulse width ΔT
_{Since 1} and ΔT ₂ have to be set longer, the power consumption at the time of state transition becomes large.

Therefore, in view of the above problems, the first aspect of the present invention
It is an object of the present invention to provide a level shift circuit capable of improving the switching speed of the output stage transistor.

A second object of the present invention is to provide a level shift circuit capable of suppressing the sudden increase current value to be flown at the time of state transition to a necessary minimum and thereby reducing power consumption.

Further, a third object of the present invention is to provide a level shift circuit capable of suppressing the supply period of the sudden increase current to be flown at the time of state transition to a necessary minimum and thereby reducing power consumption.

[0030]

In order to solve the first problem described above, the means taken by the present invention is to provide an output buffer circuit for rapidly charging / discharging the parasitic capacitance in the control terminal of the output stage transistor. Is. That is, the level shift circuit according to the present invention includes a first first-conductivity-type transistor whose opening and closing is controlled by a logic input having a narrow logic amplitude by a low-voltage power supply, and a first input by an inverting input having a phase opposite to the logic input. First
The conductivity type transistor is connected to the second first conductivity type transistor whose opening / closing is controlled exclusively, and the first first type between the high voltage power source.
A second first-conductivity type transistor connected between the first-conductivity-type transistor in series and being closed and controlled by closing the second first-conductivity-type transistor and the high-voltage power supply. Connected in series to the transistor,
A second second conductivity type transistor whose closing is controlled by closing the conductivity type transistor.
In a signal voltage level conversion circuit in which the second conductivity type transistor constitutes a flip-flop via the first and second storage nodes, and the discharge transistor is controlled to open / close based on the voltage of any one of the storage nodes. Have
A capacitance discharge circuit that discharges the capacitance parasitic on the control terminal of the output stage second conductivity type transistor, and a capacitance discharge circuit that has a charging transistor that is controlled to open and close based on the logic input or the inverting input, and charges the capacitance. And is added.

Here, it is preferable that diode clampers are connected between the first and second storage nodes and the high-voltage power supply.

In order to solve the second problem, a rapid increase in current is caused to flow through the first and second first conductivity type transistors and the charging transistor during a transition period of the level change of the logic input, and then a low current is applied. Each of them is provided with a current variable circuit for lowering the voltage.

As such a current variable circuit, a time-switching type current variable circuit that switches the sudden increase current to a low current after a predetermined uniform period from the time when the level of the logic input changes can be used.

In order to solve the third problem, as the current variable circuit, the end of the level change of the output voltage appearing at the control terminal of the output stage second conductivity type transistor is detected and the rapid increase current is reduced to a low current. It is a level detection switching type current variable circuit for switching.

In a level shift circuit having a level detection switching type current variable circuit, an output stage first conductivity type transistor forming a complementary drive system of an output terminal together with the output stage second conductivity type transistor, and the level detection circuit. A closing timing circuit for inhibiting simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor by using the output level detection signal of the switching type current variable circuit can be provided.

[Operation] In addition to the first and second second-conductivity-type transistors that form the flip-flop, a discharge transistor whose opening and closing is controlled based on the voltage of one of the storage nodes is provided. Since the storage node is also not connected to the control terminal of the output stage second conductivity type transistor, the discharge transistor is quickly opened without being affected by the parasitic capacitance of the control terminal. Therefore, the current due to the charging transistor does not easily flow as a through current, and the parasitic capacitance of the control terminal can be charged rapidly. Therefore, the switching speed of the output stage second conductivity type transistor can be increased. Also, since the shoot-through current is reduced,
Power consumption can be reduced.

Further, in the structure in which the diode clampers are respectively connected between the first and second storage nodes and the high voltage power supply, the breakdown voltage of the elements such as the transistors forming the flip-flop is reduced. be able to.

Further, in the structure provided with the current variable circuit, the state transition of the flip-flop is accelerated by the sudden increase in current, which contributes to the improvement of the switching speed. At the same time, the opening operation of the discharge transistor is accelerated,
The period of the through current via this is shortened, and the power consumption is further reduced.

In particular, according to the configuration using the level detection switching type current variable circuit as the current variable circuit, the rapid current increase period can be always made to flow for the optimum time without the rapid current increase period being too long or too short. Therefore, speeding up of state transition operation and low power consumption can be achieved at the same time.

In a semiconductor integrated circuit having an output-stage first-conductivity-type transistor which constitutes a complementary driving system for an output terminal together with an output-stage second-conductivity-type transistor, the output level detection signal of the level-detection switching type current variable circuit is used. If a configuration is provided in which a closing timing circuit that prohibits simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor is adopted, before the output stage second conductivity type transistor is opened, Even if the closing control signal of the output stage first conductivity type transistor is generated, the output stage first conductivity type transistor is not closed until the output stage second conductivity type transistor is actually opened by the closing timing circuit. Therefore, it is possible to eliminate the shoot-through current in the output stage and achieve a significant reduction in power consumption.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

[0042]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 1 is a circuit diagram showing an output stage transistor together with a level shift circuit according to Embodiment 1 of the present invention.

The level shift circuit 40 of this embodiment converts the signal voltage level without connecting the drain node N ₂ of the level shift circuit 30 shown in FIG. 9 to the gate G of the power P-channel MOSFET 5 in the output stage. Circuit 30 '
And an output buffer for rapidly charging and discharging the gate capacitance C ₅ of the power P-channel type MOSFET 5 at the output stage based on the node voltage V _g of the flip-flop FF of the signal voltage level conversion circuit 30 'and the inverted input signal V _IN ^*. Circuit 50.

The signal voltage level conversion circuit 30 'generates a reverse phase 3V system inversion signal V _IN ^* from a logic input signal V _{IN having} a narrow logic amplitude (3 V = Vdd-Vss) by a 3 V power supply.
A first high breakdown voltage N-channel MOSFET whose switching is controlled by a MOS inverter INV1 and a logic input signal V _IN
1 and the inverted signal V _IN ^{* for} the first N-channel MOS
The first high-voltage N-channel MOSFET 2 whose opening / closing is controlled exclusively with the FET 1 and the first high-voltage between the 30V (Vcc) power supply
A first P-channel type MOSFET 3 which is configured to form a two-stage series circuit together with the N-channel type MOSFET 1 and is controlled to be closed by closing the second N-channel type MOSFET 2.
Second N-channel MOSFET between 30V (Vcc) power supplies
2 and a two-stage series circuit to form a first N-channel type M
The second P-channel type MOSFET 5 is controlled to be closed by closing the OSFET 1. The first P-channel type MOSFET 3 and the second P-channel type MOSFET 3 are provided.
5 is a flip-flop FF formed by a feedback loop via drain nodes (storage nodes) N ₁ and N _2.
Is composed.

Then, the first P-channel MOSFET
The gates (drain nodes N ₁ and N ₂ ) of the third P-channel MOSFET 4 and the second P-channel MOSFET 4 are connected to the Vcc power supply via constant voltage diodes D ₁ and D ₂ for diode clampers.

Further, the signal voltage level conversion circuit 3 of this example
0'also has drain current variable circuits 32 and 34.
The first drain current variable circuit 32 includes series source resistors R ₁₁ and R ₁₂ that form a source follower circuit (constant current circuit) together with the first N-channel MOSFET 1 that operates in a non-saturation region, and one of the sources. A source resistance value switching N-channel MOSFET 6 for short-circuiting the resistor R _12.
Then, at the time point t ₁ when the logic input signal V _IN rises, the switching time pulse P1 having the predetermined pulse width ΔT ₁ is applied to the MOSFET 6
It has a one-shot circuit (monostable multivibrator) 7 applied to the gate of the. The second drain current variable circuit 34 also has series source resistors R ₂₁ and R ₂₂ that form a source follower circuit (constant current circuit) together with the second N-channel MOSFET 2 that operates in the non-saturation region, and one of them. A source resistance value switching N-channel type MOSFET 8 for short-circuiting the source resistance R ₂₂ and a logic input signal V _IN
Predetermined pulse width [Delta] T ₂ (= delta at time t ₂ which falls
It has a one-shot circuit 9 for applying a switching timed pulse P2 of T ₁ ) to the gate of the MOSFET 8.

The output buffer circuit 50 includes a gate capacitance charging circuit 52 for rapidly charging the gate capacitance C ₅ of the power P-channel MOSFET 5 at the output stage when one state transition of the flip-flop FF and the flip-flop FF. The power P-channel type MO of the output stage at the time of the other state transition
It has a gate capacitance discharge circuit 54 for rapidly discharging the gate capacitance C _{5 of the} SFET ₅ .

The gate capacitance charging circuit 52 has a gate capacitance C ₅
Is a charge pump that lowers the voltage of the gate G from the V _cc voltage (source voltage) by extracting the electric charge from the gate G and supplying it to the ground (Vss). The second high breakdown voltage N channel is generated by the inverting input signal V _IN ^* . High voltage N-channel MOSFET for charging which is controlled to open and close in synchronization with the MOSFET 2
52a and a series of source resistances R ₃₁ and R that form a source follower circuit (constant current circuit) together with a charging high breakdown voltage N-channel MOSFET 52a that operates in a non-saturation region.
₃₂ and a source resistance value switching N-channel MOSFET 52b for short-circuiting one of the source resistances R ₃₂ , and the MOSFET 52b receives the timed pulse P2 from the one-shot circuit 9 at its gate and is controlled to open / close.

The gate capacitance discharging circuit 54 has a gate capacitance C.
Connect to both ends (between source and drain) of ₅ ,
Discharge P-channel MOSFET 54a of a relatively large element controlled to open / close by the node voltage V _g of the node N _1.
And a constant voltage diode D ₃ for a diode clamper connected between the gate of the MOSFET 54a and the Vcc power supply.

First, as shown in FIG. 2, the logic input signal V _IN having a narrow logic amplitude (0 to 3 V) rises at time t ₁ ,
When the first N-channel type MOSFET 1 is closed and the second N-channel type MOSFET 2 is opened, the rapid increase current I is caused by the timed pulse P1 of the drain current variable circuit 32.
_{Since MAX} flows through the first N-channel MOSFET 1, the node voltage V _g suddenly drops from Vcc by the Zener voltage V _Z of the constant voltage diode D ₂ , so that the second P-channel MOSFET 4 and the discharging MOSFET 54a are closed. .

By the way, in this example, the second P-channel type M
OSFET4 is power P-channel type MOSFE of output stage
Since it is not necessary to rapidly discharge the gate capacitance C _{5 of} T5,
It is formed as a small-scale element. On the other hand, the discharging P-channel MOSFET 54a is formed as a large-scale element because it rapidly discharges the gate capacitance C ₅ , and the parasitic gate capacitance C ₆ cannot be ignored, but here the current value of the sudden increase current I _MAX is pulsed. By increasing the width narrowly, the node voltage V _g can be rapidly decreased. Then, by closing the second P-channel MOSFET 4 and the discharging P-channel MOSFET 54a, the node N
The voltage of ₂ becomes the high level Vcc, which causes the first P-channel MOSFET 3 to open. The opening time of the first P-channel MOSFET 3 substantially corresponds to the time t ₁₁ when the drain current of the first N-channel MOSFET 1 returns to the saving current I _MIN by the drain current variable circuit 32. After that, most of the saving current I _MIN is used to maintain the Zener voltage V _Z of the constant voltage diode D ₂ .

The node voltage V _g is greater than Vcc and the zener voltage V is
At the time when _{Z is} lowered, a discharge P-channel type MOSF
Since the ET 54a is also closed, the gate capacitance C ₅ of the power P-channel MOSFET 5 in the output stage is instantaneously discharged. As a result, the power P-channel MOSFET 5 in the output stage is sharply turned off.

Next, at the time t ₂ when the logic input signal V _IN falls, the second N-channel MOSFET 2 is closed and the first N-channel MOSFET 1 is opened. At the same time, the charging MOSFET 52a is closed. To do. Therefore, on the one hand, the second N-channel MOSFE
Due to the closing of T2, the drain current I _MAX increases rapidly,
Since the gate G of the power MOSFET 5 in the output stage is not connected to the node N ₂ and the gate capacitance C ₅ need not be charged, the voltage of the node N ₂ drops rapidly, and the first P-channel MOSFET 3 is immediately connected. Closed to gate capacitance C
₆ is discharged, and the discharging MOSFET 54a is quickly opened. On the other hand, the power P-channel MOSFET 5 at the output stage is closed by closing the charging MOSFET 52a.
Since the electric charge extracted from the gate capacitance C ₅ of the above flows as the drain current I _D3 , the gate capacitance C ₅ is quickly charged. As a result, the output voltage V _OUT drops, and the power P-channel MOSFET 5 in the output stage sharply turns on.

By the way, the energization time [Delta] T ₂ flowing a surge drain current I _MAX to the N-channel type MOSFET2 is substantially possible in a short time as compared with the energizing time [Delta] T ₁ to flow a surge drain current I _MAX to the N-channel type MOSFET 1. The node N ₁ has a second P-channel type MOSF which is a small-scale element.
While the ET4 is connected to the discharging MOSFET 54a of the large-scale element, only the first P-channel type MOSFET 3 of the small-scale element is connected to the node N ₂ and the first P-channel type MOSFET 3 is connected. This is because the gate capacitance of can be ignored. Therefore, the charge amount q2 in FIG.
Is an extremely small amount. When a further increased drain current I _MAX ′ is supplied to the N-channel MOSFET 2, the charging time can be further shortened, and the closing time t _{21 of} the first P-channel MOSFET 3 can be extended, and the discharge MO can be extended.
The opening time of the SFET 54a can be advanced. On the other hand, the drain current I _D3 flowing through the charging MOSFET 52a closed at the time point t ₂₁ slightly flows as a through current in the initial stage, but as described above, it is directly discharged.
Since the FET 54a is opened, the conduction time of the through current is t
The period is about _{2 to} t ₂₁ , which can be set to an extremely short time, so that electric power consumption can be suppressed like q3. It is possible to shorten the conduction period of this through current by increasing the drain current I _D3 and increasing the drain current I _{D3.
Although the} power consumption does not change so much even if it is _MAX , it is effective in accelerating the charging time of the gate capacitance C ₅ . As a result, the second N-channel MOSFET 2 and the charging MOSFE
The power P-channel type MOSFE of the output stage while reducing the power consumption by reducing the reactive current in T52a
The turn-on time T _{ON of} T5 can be shortened and balanced with the turn-off time T _OFF . This leads to an improvement in switching speed.

By the drain current variable circuit 34, the drain current I _D3 is designed to decrease rapidly when the conduction time ΔT ₂ of the sudden increase drain current I _MAX has passed, but the gate G has a constant voltage diode for a voltage clamper. Since they are not connected, it is desirable that the value of the drain current I _D3 is as small as possible, and the source resistance R ₃₂ has a high resistance. FIG.
In the circuit arrangement of, but when the start to flow surge drain current I _MAX of the charging MOSFET52a has become rapidly drain current I time t ₁ to start the flow of _MAX the MOSFET 2, a dedicated one-shot circuit and a delay element or the like The time point t ₁ may be slightly delayed. Charge MOSFET 5
The through current of 2a can be further suppressed, and the electric power consumption indicated by q3 in FIG. 2 can be substantially eliminated.

[Embodiment 2] FIG. 3 is a circuit diagram showing an output stage transistor together with a level shift circuit according to Embodiment 2 of the present invention.

The level shift circuit 40 'of this example comprises a signal voltage level conversion circuit 30' and a simplified output buffer circuit 50 '. The gate capacitance charging circuit 52 'of the output buffer circuit 50' is controlled to open / close in synchronization with the second high breakdown voltage N-channel MOSFET 2 by the inverted input signal V _IN ^*, and has a charging high breakdown voltage N-channel MOSFET 52.
a, and a series source resistances R ₂₁ ′ and R ₂₂ ′ of a signal voltage level conversion circuit 30 ′ that constitutes a source follower circuit (constant current circuit) together with a charging high breakdown voltage N-channel MOSFET 52 a that operates in a non-saturation region, It has a source resistance value switching N-channel MOSFET 8 for short-circuiting one of the source resistances R ₂₂ ′ and a one-shot circuit 9. The source resistors R ₂₁ ′ and R ₂₂ ′, the source resistance value switching N-channel MOSFET 8 and the one-shot circuit 9 are all the second N of the signal voltage level conversion circuit 30 ′.
The channel type MOSFET 2 is also used. The gate capacitance discharge circuit 54 ', both ends of the gate capacitance C ₅ - connected to (source-drain), drain node N ₁ of the node voltage V _g by opening and closing controlled by relatively discharging P-channel of larger elements Type MOSFET 54a only, and does not include the constant voltage diode D ₃ for the diode clamper shown in FIG. Source resistance R ₂₁ ′ and R
By optimizing the value of ₂₂ ′, the sudden increase drain current I _MAX and the power saving current I _MIN that should flow in the second N-channel MOSFET 2 as well as the high breakdown voltage N-channel MM for charging.
It is possible to set the respective values of the sudden increase drain current and the minimum current that should flow in the OSFET 52a.

Even if the constant voltage diode D ₃ is not provided,
Since a constant voltage diode D ₂ is provided in parallel with this, the gate voltage of the discharging P-channel MOSFET 54a can be clamped.

[Third Embodiment] FIG. 4 is a circuit diagram showing a level shift circuit according to a third embodiment of the present invention and an output stage transistor thereof.

The level shift circuit 60 of the present example has output voltage level change detection circuits 62 and 64 in place of the one-shot circuits 7 and 9 of the drain current variable circuits 32 and 34 in the level shift circuit 40 'shown in FIG. , A constant current source type current mirror circuit 66 of a constant current circuit which causes constant currents I ₁ and I ₂ to flow therethrough. This 2 constant current source type current mirror circuit 66 includes a gate-drain connection P-channel type MOSFET 66b for flowing a drain current from a Vcc power source by a current source 66a, and a gate connected to this gate to supply a constant current I ₁ from the Vcc power source. It has a first mirror P-channel MOSFET 66c for flowing and a second mirror P-channel MOSFET 66d for connecting a gate to the gate of the MOSFET 66b and flowing a constant current I ₂ from the Vcc power source.

Further, the first output signal level change detection circuit 62 is closed by the falling change of the voltage of the first node N ₁ and outputs a constant current I ₁ as a drain current. Withstand voltage P-channel MOSFET
62a and current / voltage conversion resistor r for flowing the constant current I _1
1 and a CMOS inverter INV2 which receives the voltage drop of the resistor r ₁ and generates a gate signal S1. Further, the second output signal level change detection circuit 64
Is closed by the falling change of the gate voltage (output voltage V _OUT ) of the power MOSFET 5 in the output stage, and the constant current I
₂ , a high breakdown voltage P-channel MOSFET 64a for detecting an output voltage fall, which flows ₂ as a drain current, a current-voltage conversion resistor r ₂ which flows its constant current I ₂ , and its resistance r _2.
CM that generates the gate signal S2 by inputting the voltage drop of
It has an OS inverter INV3.

First, as shown in FIG. 5, immediately before the time t ₁ when the logic input signal V _IN having a narrow logic amplitude rises, the voltage V _g of the node N ₁ is the high voltage Vcc (30 V) and the output Although the voltage V _OUT is Vss (0V), one P-channel MOSFET 62a is in the open state and the other P-channel MOSFET 64a.
Is in a closed state. Therefore, since no voltage drop occurs in one of the voltage conversion resistors r ₁ , the CMOS inverter IN
The output S1 of V2 is at a high level of 3 V, and the N-channel MOSFET 6 is in the closed state, but the voltage conversion resistance r ₂ on the other side has a voltage drop due to the constant current I _2. The output S2 of the inverter INV3 is 0
Low level of V, N-channel MOSFET
8, 52b are in the open state.

Here, at time t ₁ , the logic input signal V _IN having a narrow logic amplitude rises, and the first N-channel type MOSFE
Second T-channel MOSFET with T1 closed
When 2 is opened, the N-channel MOSFET 6 of the drain current variable circuit 32 'is already in the closed state, so that the rapid increase current I _MAX flows as the drain current I _{D1 and} the voltage V _g of the node N ₁ is lowered. As it starts, the output voltage V _OUT begins to rise. During the rising transition period of the output voltage V _OUT , the voltage V _{g of the} node N ₁ which is the inverted output thereof.
The falling change of is monitored and the voltage V _g becomes (Vcc
-V _Z ), the P-channel MO
Closed at t ₁₂ SFET62a detects this, the gate voltage S1 is a low level (0V) and a voltage drop occurs in the current-voltage conversion resistor r _1, N-channel type MO
The SFET 6 is opened, whereby the drain current I _D1 is switched to the power saving drain current I _MIN . Therefore, the voltage V
_g is Tachiagariru output voltage V _OUT contrary to the falls, or because this rising of the output voltage V _OUT ceases the supply of surge current I _MAX at t _12, which was completed in reality, the supply time is too short, Since it is optimized without being too long, both the turn-off time T _OFF and the power consumption can be reduced.

When the output voltage V _OUT rises at time t ₁₂ , the P-channel MOSFET 64a is opened and the constant current I ₂ stops flowing, so that the current-voltage conversion resistor r ₂
Disappears and the gate signal S2 rises. As a result, the N-channel type M of the drain current variable circuit 34 'is
The OSFET 8 and the N-channel MOSFET 52b of the gate capacitance charging circuit 52 are closed.

Next, at the time t ₂ when the logic input signal V _IN falls, the second N-channel type MOSFET 2 is closed and the first N-channel type MOSFET 1 is opened. At the same time, the charging MOSFET 52a is closed. To do. Here, the N channel type MO of the drain current variable circuit 34 'is
Since the SFET 8 and the N-channel MOSFET 52b of the gate capacitance charging circuit 52 are already closed, the second N-channel MOSFET 2 has a sudden increase in drain current I.
_MAX flows, the voltage V ₂ of the node N ₂ drops rapidly, and the first
The P-channel MOSFET 3 is immediately closed, the gate capacitance C ₆ is discharged, and the discharging MOSFET 54a is quickly opened. On the other hand, the charging MOSFET 52a
A rapid increase in drain current I _MAX flows through the gate, the gate capacitance C ₅ of the power P-channel MOSFET ₅ is rapidly charged, and the output voltage V _OUT falls. During this falling transition period of the output voltage V _OUT , the falling change is monitored by the P-channel MOSFET 64a, and the output voltage V _{OUT is changed.}
When it falls to a value close to the voltage Vss, the P-channel MO
When the SFET 64a detects this and closes at time t ₂₄ , a voltage drop occurs in the current-voltage conversion resistor r ₂ and the gate voltage S2 falls to a low level (0V), so that the N-channel MOSFETs 8, 52b are turned on. The drain currents I _D2 and I _D3 are switched to the power saving drain current I _MIN . Therefore, the supply of the sudden increase drain current I _MAX is stopped at the time t ₂₄ when the fall of the output voltage V _OUT is actually completed, so that the supply time is not too short or too long, and is optimized. As described above, since the level detection switching type current variable circuit is used in this example, the turn-on time T _ON
Both reduction of power consumption and reduction of power consumption can be achieved.

Since V _g has already risen during the transitional period when the output voltage V _OUT falls at time t ₂₄ , the P-channel MOSFET 62a is opened and the constant current I ₁ stops flowing, so current-voltage conversion is performed. The voltage drop across the resistor r ₁ disappears and the gate signal S1 rises. As a result, the N-channel MOSFET 6 of the drain current variable circuit 32 'is
N-channel MOSFET 6 is closed.

In this example, the MOSFETs 8 and 52b are opened in synchronization with the fall of the gate signal S2, and the drain currents I _D2 and I _D3 are simultaneously switched from the sudden increase drain current I _MAX to the power saving drain current I _MIN . However, if the switching time of the drain current I _D2 is advanced to the rising time of the gate voltage, the power consumption can be reduced.

[Embodiment 4] FIG. 6 is a circuit diagram showing the output stage transistors of the level shift circuit according to Embodiment 3 of the present invention.

In this example, the output stage of the level shift circuit 60 is a power high withstand voltage N-channel type MO of the output stage forming a two-stage series circuit with the power P-channel type MOSFET 5.
The SFET 15 is provided, and the driving high withstand voltage P-channel MO is connected to the output terminal 5b connected to the common drain D.
The gate G of the SFET 25 is connected. The high breakdown voltage P-channel MOSFET 25 for driving has a gate breakdown voltage of 30 V or higher, and drives an inductance load L of an inverter circuit, for example. The gate of the N-channel MOSFET 15 as a complementary transistor of the P-channel MOSFET 5 is driven by the output signal CT of the closing timing circuit 70.
The closing timing circuit 70 includes a NAND gate 70a having two inputs, a logic input signal V _IN having a narrow logic amplitude and an output S2 of the CMOS inverter INV3, and a NAND gate 70.
an inverter 70b that inverts the output of a and amplifies the power.

In this example, the driving high-voltage large-current-capacity MOSFET 25 is switched by the complementary gate driving method of the P-channel MOSFET 5 and the N-channel MOSFET 15. When a logic input signal V _IN is applied via a buffer circuit to drive the gate of the N-channel MOSFET 15, switching control of the N-channel MOSFET 15 is possible, but P-channel MOSFET
Since the output voltage V _OUT for driving the gate of No. 5 is formed via the level shift circuit 60, a phase delay is inevitably generated with respect to the logic input signal V _IN . If the phase delay is large, the complementary P-channel type M that should be opened and closed exclusively
Since the simultaneous closing period is mixed in the OSFET 5 and the N-channel MOSFET 15, a through current having a high current value is generated, resulting in large power consumption. To reduce this, N
It is possible to take measures to provide a delay circuit in the transmission system of the logic input signal V _IN on the channel MOSFET 15 side. However, since the delay amount of the delay circuit is determined only by the expected amount, in reality, the simultaneous closing period is mixed due to manufacturing variations of the semiconductor element, and a through current that cannot be ignored is generated.

However, in this example, when the logic input signal V _IN is at a low level as shown in FIG. 6, as described above, the sudden increase of the drain current I of the gate capacitance charging circuit 52.
_The output voltage V _OUT immediately drops due to _MIN , and the P-channel MOSFET 5 turns on. Since the output voltage V _OUT is at a low level in the closed state of the P-channel MOSFET 5, the output S2 of the CMOS inverter INV3 of the output voltage level change detection circuit 64 is also at a low level. As long as the output S2 is at the low level, the NAND gate 70 will be able to operate even if the logic input signal V _IN quickly becomes the high level.
The output of a remains high level, and N-channel MOS
The FET 15 is not closed. Output S2 goes high,
When the P-channel MOSFET 5 is turned off, the N-channel MOSFET 15 is closed for the first time. Therefore,
When the P-channel MOSFET 5 is turned off and N
The simultaneous closing time does not occur when the channel type MOSFET 15 is turned on, and the through current can be eliminated.
When the N-channel MOSFET 15 is turned off and the P-channel MOSFET 5 is turned on, the N-channel MOSFET 15 receives the input signal V _IN.
Since the opening is directly controlled by, the opening is early, so that no through current is generated.

In each of the above embodiments, the P channel type M
A flip-flop FF is composed of OSFETs 3 and 4,
The pull-down MOSFETs 3 and 4 for writing the potentials to the recording nodes N _{1 and} N ₂ are of N-channel type. However, the conductivity type is reversed, and a flip-flop FF is formed by the N-channel MOSFETs. N _1,
The pull-up MOSFET for writing the potential to N ₂ may be a P-channel type.

In the above embodiment, the logic input V having a narrow logic amplitude is used.
The low level voltage V _ss of _IN is 0V, its high level voltage V _dd is 3V, and the low level voltage V _ss of the logic output V _OUT of wide logic amplitude is 0V, and its high level voltage V _cc is 30V. In the present invention, if the low level voltage V _ee of the logic output V _OUT having a wide logic amplitude is set, it is sufficient to satisfy the relationship of low voltage source (V _dd -V _ss ) <high voltage source (V _cc -V _ee ). In the above embodiment, V _ss = V _ee <V _dd <V _cc only. V _ee <V _cc ≤ V _ss <V _dd , V _ee <V _ss <V _cc ≤
V _dd , V _ss ≤ V _ee <V _dd ≤ V _cc , V _ss <V _dd ≤ V _ee <V
_It goes without saying that the case of _cc is also included.

[0075] Further, if set to be equal to the resistors R _11, the value of R _21, R ₃₁ the on-resistance of MOSFET6,8,52b, it is possible to omit the resistors R _11, R _21, R ₃₁ .

Further, the level shift circuit may be constructed by using bipolar transistors instead of monopolar transistors such as MOSFET (insulated gate type field effect transistor).

[0077]

As described above, in the level shift circuit according to the present invention, the control terminal of the output stage transistor is parasitic, in addition to the first and second conductivity type transistors forming the flip-flop. In order to charge and discharge the capacity, a discharge transistor whose opening and closing is controlled based on the voltage of one of the storage nodes and a charging transistor whose opening and closing is controlled by a logic input or an inverted input thereof are provided. Therefore, the following effects are obtained.

Since neither storage node is connected to the control terminal of the output stage second conductivity type transistor, the discharge transistor is quickly opened without being affected by the parasitic capacitance of the control terminal. It is difficult for the current to flow as a through current, and the parasitic capacitance of the control terminal can be rapidly charged. Therefore, the switching speed of the output stage second conductivity type transistor can be increased. Moreover, since the through current is reduced, the power consumption can be reduced.

In the configuration in which the diode clampers are respectively connected between the first and second storage nodes and the high voltage power supply, it is possible to reduce the breakdown voltage of the elements such as the transistors forming the flip-flop. it can.

In the configuration including the current variable circuit, the state transition of the flip-flop becomes faster due to the sudden increase in current, which contributes to the improvement of the switching speed. At the same time, the opening operation of the discharge transistor is accelerated,
The period of the through current via this is shortened, and the power consumption is further reduced.

In particular, according to the configuration using the level detection switching type current variable circuit as the current variable circuit, the rapid current increase period can be always made to flow for the optimum time without the rapid current increase period being too long or too short. Therefore, speeding up of state transition operation and low power consumption can be achieved at the same time.

In a semiconductor integrated circuit having an output-stage first-conductivity-type transistor that constitutes a complementary driving system for an output terminal together with an output-stage second-conductivity-type transistor, an output level detection signal of the level-detection switching type current variable circuit is used. When a configuration is provided in which a closing timing circuit for prohibiting simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor is adopted,
Until the output stage second conductivity type transistor is actually opened,
Since the output-stage first-conductivity-type transistor is not closed, it is possible to eliminate a through current in the output stage and achieve a significant reduction in power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output stage transistor of a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms at various points in the first embodiment.

FIG. 3 is a circuit diagram showing an output stage transistor of the level shift circuit according to the second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an output stage transistor of the level shift circuit according to a third embodiment of the present invention.

FIG. 5 is a timing diagram showing waveforms at various points in the third embodiment.

FIG. 6 is a circuit diagram showing an output stage transistor together with a level shift circuit according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional basic level shift circuit and its output stage transistor.

FIG. 8 is a circuit diagram showing a conventional level shift circuit including a diode clamper and an output stage transistor thereof.

9 is a circuit diagram showing an output stage transistor of the level shift circuit shown in FIG. 8 together with an improved level shift circuit.

FIG. 10 is a timing diagram showing waveforms at various parts of the circuit shown in FIG.

[Explanation of symbols]

1 ... 1st high breakdown voltage N channel type MOSFET 2 ... 2nd high breakdown voltage N channel type MOSFET 3 ... 1st high breakdown voltage P channel type MOSFET 4 ... 2nd high breakdown voltage P channel type MOSFET 5 ... Power of output stage P-channel MOSFETs 5a, 5b ... Output terminals 6, 8, 52b ... Source resistance value switching N-channel MOSFET 15 ... Output stage power N-channel MOSFET 25 ... Driving high breakdown voltage P-channel MOSFETs 30 ', 30 " ... signal voltage level conversion circuit 32 ... first drain current variable circuit 34 ... second drain current variable circuit 40, 40 ', 60 ... level shift circuit 50, 50' ... output buffer circuit 52, 52 '... gate capacitance charging Circuit 52a ... High breakdown voltage N-channel MOSFET 54, 54 'for charging ... Gate capacitance discharging circuit 54a ... High withstand voltage P-channel MOSFETs 62, 64 ... Output voltage level change detection circuit 62a ... High withstand voltage P-channel MOSFET 64a for detecting rising output voltage ... High withstand voltage P-channel MOSFET 66 ... 2 for detecting falling output voltage Constant current source type current mirror circuit 66a ... Current source 66b ... P channel MOSFET 66c ... First mirror P channel MOSFET 66d ... Second mirror P channel MOSFET 70 ... Closing timing circuit 70a ... NAND gate 70b ... Inverter P1 , P2 ... switching timed pulses r _1, r ₂ ... current-voltage conversion resistor S1, S2 ... Zener diode FF ... flip-flop of a gate signal INV1 to INV3 ... CMOS inverter _{D 1, D 2, D 3} ... diode clamper V _g ... node voltage V _IN ... narrow Sense the amplitude of the logic input signal V _IN ^* ... inverted input signal V _OUT ... wide logic logic output signal N 1 of the _amplitude, N ₂ ... flip-flop drain node (storage node) C _5, C ₆ ... gate capacitance CT ... Output signal.

Claims (6)

[Claims] 1. A first first-conductivity-type transistor whose opening and closing is controlled by a logic input having a narrow logic amplitude by a low-voltage power supply, and a first first transistor by an inverting input having a phase opposite to that of the logic input.
The conductivity type transistor is connected to the second first conductivity type transistor whose opening / closing is controlled exclusively, and the first first type between the high voltage power source.
A second first-conductivity type transistor is connected between the first-conductivity-type transistor and the high-voltage power source, and a first second-conductivity-type transistor that is closed and controlled by closing the second first-conductivity-type transistor. Connected in series to the transistor,
A second second conductivity type transistor whose closing is controlled by closing the conductivity type transistor.
In a signal voltage level conversion circuit in which the second conductivity type transistor is a flip-flop via the first and second memory nodes, and the discharge transistor is controlled to be opened or closed based on the voltage of any one of the memory nodes. Have
A capacitance discharging circuit that discharges the capacitance parasitic on the control terminal of the output stage second conductivity type transistor, and a capacitance discharging circuit that has a charging transistor that is controlled to open and close based on the logic input or the inverting input, and charges the capacitance. And a level shift circuit characterized by being added. 2. The level shift circuit according to claim 1, wherein diode clampers are connected between the first and second storage nodes and the high voltage power supply, respectively. . 3. The level shift circuit according to claim 2, wherein a sudden increase current is caused to flow through the first and second first conductivity type transistors and the charging transistor during a transition period of the level change of the logic input, A level shift circuit comprising a current variable circuit for reducing to a low current. 4. The level shift circuit according to claim 3, wherein the current variable circuit switches the sudden increase current to a low current after a predetermined uniform period from the time when the level of the logic input changes. A level shift circuit characterized by: 5. The level shift circuit according to claim 3, wherein the current variable circuit detects the end of the level change of the output voltage appearing at the control terminal of the output stage second conductivity type transistor to reduce the sudden increase current. A level shift circuit characterized by being a level detection switching type current variable circuit for switching to current. 6. The level shift circuit according to claim 5, wherein the output stage first constituting a complementary drive system of the output terminal together with the output stage second conductivity type transistor.
Closing timing circuit for prohibiting simultaneous closing of the output stage first conductivity type transistor and the output stage second conductivity type transistor by using a conductivity type transistor and an output level detection signal of the level detection switching type current value variable circuit A level shift circuit comprising: