JP2011035923A - Drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption during standby in a high-voltage drive circuit in which a low-voltage control signal is converted into a high-voltage control signal to be outputted. <P>SOLUTION: Transistors MN1-MN8 of a high voltage portion 2 are driven by control signals a1-d1 and a2-d2 from a low voltage portion 1, and a driving signal is outputted to an operating object 3. In that case, the control signals a1-d1 from the low voltage portion 1 are inputted to gates of the transistors MN1, MN3, MN5, MN7 of the high voltage portion 2 via one input terminal of each of AND gates Q1-Q4, and an ON/OFF signal of the high voltage part 2 is inputted to another input terminal of each of the AND gates Q1-Q4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a drive circuit that converts a low-voltage control signal into a high-voltage control signal and outputs the signal, and more particularly to a drive circuit that suppresses power consumption during standby.

  A semiconductor element or electronic circuit device such as a MOS transistor or a bipolar transistor that receives a power supply voltage on the high voltage side needs to be operated under a power supply voltage suitable for each application, but its control system is generally 5 V or less. Since it is incorporated in an integrated circuit device that operates with a low power supply voltage, it is difficult to control or operate an operation target that directly receives the high-voltage power supply voltage from the output of the control system. For this reason, it is necessary to interpose a drive circuit having a level shift circuit between the control system and the operation target, and this drive circuit is usually incorporated in an integrated circuit device for the control system (see, for example, Patent Document 1). ).

  FIG. 6 is a diagram showing a configuration example of the conventional drive circuit. This circuit is generally composed of a low voltage part that operates at a low power supply voltage of 5 V or less and a high voltage part that operates at a high power supply voltage of more than 10 V (for example, 300 V), and is input to the input terminal IN of the low voltage part. In accordance with the pulse signal from the control system, a drive signal is output from the output terminal OUT of the high voltage unit to the operation target.

  The high voltage unit is composed of a level shift stage, an amplification stage, and an output stage. The level shift stage is a circuit that shifts up the low-voltage control signal from the low-voltage unit to the high-voltage control signal, and the amplification stage and the output stage amplify the power required to drive the operation target, It is a circuit to output. When power for driving the operation target may be small, the amplification stage can be omitted. Further, when a large amount of power is required for driving the operation target, the number of amplification stages may be increased as appropriate.

  Also, the P-channel transistors MP1 to MP4 and the N-channel transistors MN1 to MN8 constituting the high-voltage unit increase in size as they become downstream in order to perform power amplification. Z1 to Z4 are Zener diodes used to clamp the gate-source voltage of the transistors MP1 to MP4 and the P-channel transistor MP5 to be operated. This is because a normal transistor has a gate-source breakdown voltage of about several volts, and is kept at a constant voltage lower than that. R1 to R10 are resistors.

  The low voltage part is a circuit for driving the transistors MN1 to MN8 of the high voltage part. FIG. 7 shows an example of the circuit. Q11 is an inverter, D1 and D2 are delay elements, and B1 to B4 are buffers. Control signals a1 to d1 and a2 to d2 are output from the low-pressure part.

  FIG. 8 is a diagram showing operation waveforms of the circuit of FIG. Here, operational waveforms of the amplification stage are shown. In the figure, VGp3 is the gate voltage of the transistor MP3, VDp3 is the drain voltage (output voltage) of the transistor MP3, Iloss is the current flowing through the transistor MN5, IH is the sudden increase current, and IL is the saving current. VDDH is a high-voltage power supply voltage, VDDL is a low-voltage power supply voltage, and td is a delay time by the delay elements D1 and D2 in FIG.

  The gate voltage VGp3 of the transistor MP3 rises by the clamp voltage of the Zener diode Z1 to VDDH until the control signal c1 from the low voltage section rises at time t1 and the control signal c2 falls at time t2 after the delay time td. (Although not shown, since the transistor MN3 is turned off when the control signal b1 having a phase opposite to that of the control signal c1 falls at the time t1, the drain voltage VDp3 of the transistor MP3 is equal to the clamp voltage of the Zener diode Z3. Lower than VDDH. During this time, the rapidly increasing current IH flows through the transistor MN5. Further, the gate voltage VGp3 of the transistor MP3 falls below VDDH by the clamp voltage of the Zener diode Z1 until the control signal c1 falls at the time t3 and until the control signal c2 rises at the time t4 after the delay time td (illustrated). However, since the control signal b1 having a phase opposite to that of the control signal c1 rises at time t3, the transistor MN3 is turned on, and at time t3, the transistor MN4 has already been turned on by the control signal b2 having a phase opposite to that of the control signal c2. The drain voltage VDp3 of the transistor MP3 is increased by the clamp voltage of the Zener diode Z3 and becomes VDDH.

  Here, in a normal electronic circuit device, a minimum necessary circuit is set in an operating state during standby, and other circuits are stopped, thereby reducing power consumption during standby. Some drive circuits perform similar operations. FIG. 9 shows a configuration example of such a general low-voltage drive circuit.

  This drive circuit has a configuration in which inverters of P-channel transistors P1, P2... Pn-1, Pn and N-channel transistors N1, N2,. In such a circuit, as long as the input signal H (High) and L (Low) do not change, either the P-channel transistor or the N-channel transistor in each stage is always turned off. Not. Therefore, it is possible to enter a stop state by fixing the input to H or L during standby.

  However, in the high-voltage drive circuit as shown in FIG. 6, even if the input is fixed to H or L, there is a clamp Zener diode in the high-voltage section that is in an ON state (in the above-described saving current IL). Corresponding) steady current flows.

  For example, when the input is fixed to H, the transistor MN1 is turned on, and a current flows through the Zener diode Z2, the transistor MN1, and the resistors R1 and R2. Further, the transistor MN5 is turned on, and a current flows through the Zener diode Z3, the transistor MN5, and the resistors R6 and R7. When the input is fixed to L, the transistor MN3 is turned on, and a current flows through the Zener diode Z1, the transistor MN3, and the resistors R3 and R4. Further, the transistor MN7 is turned on, and a current flows through the Zener diode Z4, the transistor MN7, and the resistors R9 and R10.

JP-A-9-214317

  In the conventional high-voltage drive circuit having the above configuration, measures are taken to reduce the power consumption during operation (the period during which the rapid increase current IH flows is limited to the delay time td). Even if the input is fixed to H or L sometimes, there is a problem that the Zener diode for clamping in the high voltage section is in an on state and a steady current flows, so that power consumption during standby cannot be reduced. is there.

  The present invention has been made in view of these points, and an object thereof is to provide a drive circuit that can reduce power consumption during standby.

  In order to solve the above-described problems, the present invention includes a low-voltage unit that outputs a low-voltage control signal, and a high-voltage unit that converts a control signal from the low-voltage unit into a high-voltage control signal. A clamp element, a first transistor, a first resistor, and a second transistor are connected in series between a high-voltage power supply voltage and a ground voltage, and a connection portion between the first resistor and the second transistor Is a drive circuit having a configuration that is grounded via a second resistor, wherein a switch element is inserted in series with the second resistor, which is a path of a steady current that flows during clamping by the clamp element, and the switch is in standby mode A drive circuit is provided wherein the device is turned off.

According to such a drive circuit, the standby current path is cut off by the switch element, so that power consumption during standby can be reduced.
In order to solve the above problems, the present invention has a low-voltage unit that outputs a low-voltage control signal, and a high-voltage unit that converts the control signal from the low-voltage unit into a high-voltage control signal, The high-voltage unit includes a clamp element, a first transistor, a first resistor, and a second transistor connected in series between a high-voltage power supply voltage and a ground voltage, and the first resistor and the second transistor A drive circuit having a configuration in which a connection portion is grounded via a second resistor, wherein the first switch element is inserted in series with the second resistor that is a path of a steady current that flows during clamping by the clamp element. In addition, the second switch element is connected to the gate of the second transistor that is turned off during standby, and the first switch element is turned off and the second switch element is turned on during standby. Drive circuit according to claim bets is provided.

  According to such a drive circuit, the standby current path is cut off by the switch element, so that power consumption during standby can be reduced.

  The drive circuit of the present invention has an advantage that power consumption during standby can be reduced because the current path during standby is cut off by the switch element.

It is a figure which shows the structure of the drive circuit based on the related technology of this invention. It is a figure which shows the structure of the drive circuit of the 1st Embodiment of this invention. It is a figure which shows the structure of the drive circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the drive circuit of the 3rd Embodiment of this invention. It is a figure which shows the structure of the drive circuit of the 4th Embodiment of this invention. It is a figure which shows the structural example of the conventional drive circuit. It is a figure which shows an example of the circuit of a low voltage | pressure part. It is a figure which shows the operation | movement waveform of the circuit of FIG. It is a figure which shows the structural example of the drive circuit for general low voltage | pressure.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same components as those of the drive circuit shown in FIG.
FIG. 1 is a diagram showing a configuration of a drive circuit according to a related technique of the present invention. The drive circuit includes a low voltage unit 1 that outputs a low voltage control signal and a high voltage unit 2 that converts the control signal from the low voltage unit 1 into a high voltage control signal. The high voltage unit 2 includes a level shift stage 2a, an amplification stage 2b, and an output stage 2c, and includes P-channel transistors MP1 to MP4 and N-channel transistors MN1 to MN8.

  In the level shift stage 2a, the transistors MN1 and MN2 are connected in series with the transistor MP1, the transistors MN3 and MN4 are connected in series with the transistor MP2, the gate of the transistor MP1 and the drain of the transistor MP2 are connected, and the gate of the transistor MP2 And the drain of the transistor MP1 are connected. In the amplification stage 2b, transistors MN5 and MN6 are connected in series with the transistor MP3, and in the output stage 2c, transistors MN7 and MN8 are connected in series with the transistor MP4.

  Zener diodes Z1 to Z4 are connected as clamp elements to the gates of the P-channel transistors MP1 to MP4 of the high voltage unit 2 and the gate of the P-channel transistor MP5 to be operated.

  The low-voltage unit 1 has the configuration shown in FIG. 7, and the control signals a1 to d1 are input to the gates of the transistors MN1, MN3, MN5, and MN7 of the high-voltage unit 2 through one input terminals of the AND gates Q1 to Q4, respectively. The other input terminals of the AND gates Q1 to Q4 receive the on / off signal of the high voltage unit 2 from the on / off terminal EN. The control signals a2 to d2 are input to the gates of the transistors MN2, MN4, MN6 and MN8 of the high voltage unit 2, respectively.

  In the drive circuit configured as described above, the control signals a1 to d1 from the low voltage unit 1 are respectively supplied to the transistors MN1, MN3, MN5, and MN7 of the high voltage unit 2 through one input terminals of the AND gates Q1 to Q4. The ON / OFF signal of the high voltage unit 2 is input to the other input terminals of the AND gates Q1 to Q4. When the on / off signal is H, the drive circuit is in an operating state, and when the on / off signal is L, the drive circuit is in a standby state.

  That is, when the on / off signal is H, the control signals a1 to d1 are input to the gates of the transistors MN1, MN3, MN5, and MN7 through the AND gates Q1 to Q4, but the on / off signal is L. Since the L signals are output from the AND gates Q1 to Q4 regardless of the values of the control signals a1 to d1, the transistors MN1, MN3, MN5, and MN7 are turned off, and the current paths of the respective stages are cut off. It is. Therefore, power consumption during standby can be reduced.

  FIG. 2 is a diagram showing the configuration of the drive circuit according to the first embodiment of the present invention. This drive circuit is a circuit whose output is H during standby, and the switch elements S1 and S2 are inserted in the path of steady current that flows during clamping by the Zener diodes Z1 to Z4, and the switch elements S1 and S2 are turned off during standby. .

  The above drive circuit assumes a case where a large amount of power is required to drive the operation target 3. When a large amount of power is required to drive the operation target 3, the sizes of the transistors MN1, MN3, MN5, and MN7 are increased, and it is necessary to increase the power for driving the gates. It is difficult to increase the power output of Q1 to Q4.

  Therefore, in the present embodiment, the gates of the transistors MN1, MN3, MN5, and MN7 are directly driven by the low-voltage unit 1 having a buffer, and switch elements S1 and S2 that operate in response to an on / off signal in series with the resistors R2 and R7. At the time of standby, a signal whose output is H in the operating state is input to the input terminal IN. In this case, the transistors MN2, MN3, MN6, and MN7 are turned off, and the transistors MN1 and MN5 are turned on. Further, by turning off the switch elements S1 and S2, the current path of each stage can be cut off.

  FIG. 3 is a diagram showing the configuration of the drive circuit according to the second embodiment of the present invention. In contrast to the first embodiment shown in FIG. 2, this drive circuit is a circuit whose output is L during standby, and is provided with switch elements S1 and S2 that operate in response to an on / off signal in series with resistors R4 and R10. During standby, a signal that outputs L in the operating state is input to the input terminal IN. In this case, the transistors MN1, MN4, MN5, MN8 are turned off and the transistors MN3, MN7 are turned on. Further, by turning off the switch elements S1 and S2, the current path of each stage can be cut off.

  FIG. 4 is a diagram showing the configuration of the drive circuit according to the third embodiment of the present invention. This drive circuit is a circuit whose output becomes H during standby, and assumes that the power supply of the low-voltage unit 1 is turned off during standby. The first switch elements S1 and S2 are inserted in the path of the steady current that flows during clamping by the Zener diodes Z1 to Z4, and the second switch element S3 is connected to the gates of the transistors MN2, MN3, MN6, and MN7 that are turned off during standby. , S4, S5 and S6 are connected. During standby, the first switch elements S1 and S2 are turned off, and the second switch elements S3, S4, S5 and S6 are turned on.

  That is, in this embodiment, in addition to the switch elements S1 and S2 provided in the first embodiment shown in FIG. 2, the switch elements S3, S4 and S5 are connected between the gates of the transistors MN2, MN3, MN6 and MN7 and the ground. , S6. When the power supply of the low voltage unit 1 is turned off, it is difficult to reliably turn off these transistors MN2, MN3, MN6, MN7. Therefore, during standby, the switch elements S1, S2 are turned off by a signal from the on / off terminal EN1, and the switch elements S3, S4, S5, S6 are turned on by a signal from the on / off terminal EN2. Thereby, the transistors MN2, MN3, MN6, and MN7 can be reliably turned off, and the current path of each stage can be cut off.

  FIG. 5 is a diagram showing the configuration of the drive circuit according to the fourth embodiment of the present invention. This drive circuit is a circuit whose output is L during standby in contrast to the third embodiment shown in FIG. 4, and in addition to the switch elements S1 and S2 provided in the second embodiment shown in FIG. Switching elements S3, S4, S5 and S6 are provided between the gates of the transistors MN1, MN4, MN5 and MN8 and the ground. During standby, the switch elements S1, S2 are turned off by a signal from the on / off terminal EN1, and the switch elements S3, S4, S5, S6 are turned on by a signal from the on / off terminal EN2. Thereby, even when the power supply of the low-voltage unit 1 is turned off, the transistors MN1, MN4, MN5, MN8 can be reliably turned off, and the current path of each stage can be cut off.

DESCRIPTION OF SYMBOLS 1 Low voltage | pressure part 2 High voltage | pressure part 2a Level shift stage 2b Amplification stage 2c Output stage 3 Operation object MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 N channel transistor MP1, MP2, MP3, MP4, MP5 Transistor Q1, Q2, Q3, Q4 AND gate S1, S2, S3, S4, S5, S6 Switch element Z1, Z2, Z3, Z4 Zener diode

Claims (2)

A low-voltage unit that outputs a low-voltage control signal;
A high-voltage unit that converts a control signal from the low-voltage unit into a high-voltage control signal,
The high-voltage unit includes a clamp element, a first transistor, a first resistor, and a second transistor connected in series between a high-voltage power supply voltage and a ground voltage, and the first resistor and the second transistor A drive circuit having a configuration in which the connection portion of the first electrode is grounded via a second resistor,
A drive circuit, wherein a switch element is inserted in series with the second resistor that is a path of a steady current that flows during clamping by the clamp element, and the switch element is turned off during standby. A low-voltage unit that outputs a low-voltage control signal;
A high-voltage unit that converts a control signal from the low-voltage unit into a high-voltage control signal,
The high-voltage unit includes a clamp element, a first transistor, a first resistor, and a second transistor connected in series between a high-voltage power supply voltage and a ground voltage, and the first resistor and the second transistor A drive circuit having a configuration in which the connection portion of the first electrode is grounded via a second resistor,
A first switch element is inserted in series with the second resistor, which is a path of a steady current that flows during clamping by the clamp element, and a second switch element is connected to the gate of the second transistor that is turned off during standby. The drive circuit, wherein the first switch element is turned off and the second switch element is turned on during standby.

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