JPH09213735A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH09213735A JPH09213735A JP8021298A JP2129896A JPH09213735A JP H09213735 A JPH09213735 A JP H09213735A JP 8021298 A JP8021298 A JP 8021298A JP 2129896 A JP2129896 A JP 2129896A JP H09213735 A JPH09213735 A JP H09213735A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip
- package base
- curing agent
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Adhesives Or Adhesive Processes (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、たとえば基板上
に半導体素子をフェイス・ダウン・ボンディング法によ
り接合するようにしてなる半導体装置およびその製造方
法に関するもので、特に高密度実装に適したＣＳＰ（Ch
ip Scale Package）などに用いられるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is bonded to a substrate by a face down bonding method, and a method for manufacturing the same, and particularly to a CSP (high-density mounting). Ch
ip Scale Package) etc.
【０００２】[0002]
【従来の技術】現在、高密度実装が可能な半導体装置と
して、半導体チップとほぼ同等のサイズを有するパッケ
ージ、いわゆるＣＳＰが注目されている。このＣＳＰと
しては、従来、フリップチップ接続方式（フェイス・ダ
ウン・ボンデイング法）を用いて製造されるものが一般
的となっていた。その製造方法について、以下に簡単に
説明する。2. Description of the Related Art At present, as a semiconductor device capable of high-density mounting, a package having a size substantially equal to that of a semiconductor chip, that is, a so-called CSP is drawing attention. Conventionally, as the CSP, a CSP manufactured by using a flip chip connection method (face down bonding method) has been generally used. The manufacturing method will be briefly described below.
【０００３】まず、ウェーハ状態のチップの金属パッド
に電界メッキにより半田バンプをそれぞれ形成した後、
ダイシングを行って各チップを切り出す。このチップが
搭載される外囲器上の、上記金属パッドと対応する位置
に半田バンプを形成する。First, solder bumps are respectively formed on the metal pads of a chip in a wafer state by electrolytic plating, and then,
Each chip is cut by dicing. Solder bumps are formed at positions corresponding to the metal pads on the package on which the chip is mounted.
【０００４】上記外囲器を、フリップチップボンダのス
テージ上にバキューム吸着により固定するとともに、上
記チップの裏面を、ホルダでバキューム吸着して保持す
る。そして、チップと外囲器との位置合わせを行って
後、外囲器上の半田バンプとチップ上の半田バンプとを
低温環境下にて仮付けする。The envelope is fixed on the stage of a flip chip bonder by vacuum suction, and the back surface of the chip is held by vacuum suction by a holder. Then, after the chip and the envelope are aligned with each other, the solder bumps on the envelope and the solder bumps on the chip are temporarily attached in a low temperature environment.
【０００５】その仮付けされた外囲器とチップとを、半
田の溶解温度に設定されたリフロー炉内に通し、両バン
プ間を本格的に接合する。しかる後、外囲器とチップと
の間の、バンプの高さ分の隙間に、樹脂を毛細管現象な
どを利用して充填する。The temporarily attached envelope and the chip are passed through a reflow furnace set to the melting temperature of the solder, and the bumps are joined together in earnest. After that, a gap corresponding to the height of the bump between the envelope and the chip is filled with resin by utilizing a capillary phenomenon or the like.
【０００６】こうして、チップサイズとほぼ同等サイズ
のＣＳＰが製造される。しかしながら、上記した従来の
製造方法においては、金属パッドと半田バンプとの接合
の信頼性の向上のために外囲器とチップとの間に樹脂を
充填するようになっているが、樹脂の充填を毛細管現象
などを利用して行うために、短時間で充填を終了するこ
とが不可能であり、生産性が非常に悪いという問題があ
った。Thus, a CSP having a size substantially equal to the chip size is manufactured. However, in the above-described conventional manufacturing method, the resin is filled between the envelope and the chip in order to improve the reliability of the bonding between the metal pad and the solder bump. Therefore, it is impossible to finish the filling in a short time, and there is a problem that the productivity is very poor.
【０００７】[0007]
【発明が解決しようとする課題】上記したように、従来
においては、外囲器と半導体チップとをフェイス・ダウ
ン接合した後に、外囲器とチップとの間に接合の信頼性
を向上させるための樹脂を充填するようになっているた
め、それに長い時間を要し、生産性が非常に悪いという
問題があった。As described above, in the prior art, in order to improve the reliability of bonding between the envelope and the chip after face-down bonding between the envelope and the semiconductor chip. Since it is designed to be filled with the above resin, it takes a long time and the productivity is very poor.
【０００８】そこで、この発明は、半導体素子と基板と
の間の隙間に樹脂を充填するための工程を不要にでき、
生産性を大幅に向上することが可能な半導体装置および
その製造方法を提供することを目的としている。Therefore, the present invention can eliminate the step of filling the resin between the semiconductor element and the substrate,
It is an object of the present invention to provide a semiconductor device and its manufacturing method capable of significantly improving productivity.
【０００９】[0009]
【課題を解決するための手段】上記の目的を達成するた
めに、この発明の半導体装置にあっては、基板上に半導
体素子をフェイス・ダウン・ボンディング法により接合
するようにしてなるものにおいて、前記半導体素子と前
記基板とを、主剤と硬化剤とを混合してなる２液性の樹
脂層を介して接着してなる構成とされている。In order to achieve the above object, in a semiconductor device of the present invention, a semiconductor element is bonded on a substrate by a face down bonding method. The semiconductor element and the substrate are bonded to each other with a two-component resin layer formed by mixing a main component and a curing agent.
【００１０】また、この発明の半導体装置の製造方法に
あっては、半導体素子の表面の、電極の形成位置を除く
部分に主剤または硬化剤のいずれか一方を塗布し、前記
半導体素子がフェイス・ダウン・ボンディング法により
接合される基板の、その表面の、電極の形成位置を除く
部分に主剤または硬化剤のいずれか他方を塗布し、前記
半導体素子上の電極と前記基板上の電極とをフェイス・
ダウンして位置合わせした後、加圧し、前記半導体素子
と前記基板との相互を、前記主剤および硬化剤を混合し
てなる２液性の樹脂層を介して接着するようになってい
る。Further, in the method of manufacturing a semiconductor device of the present invention, either the main component or the curing agent is applied to a portion of the surface of the semiconductor element excluding the position where the electrode is formed, and the semiconductor element is face-coated. Either the main component or the curing agent is applied to the surface of the substrate to be joined by the down bonding method except the position where the electrode is formed, and the electrode on the semiconductor element and the electrode on the substrate are faced.・
After down and positioning, pressure is applied to bond the semiconductor element and the substrate to each other via a two-component resin layer formed by mixing the base material and the curing agent.
【００１１】この発明は、たとえば半導体素子および基
板の表面にそれぞれ主剤または硬化剤を塗布しておき、
これら主剤および硬化剤を混合してなる２液性の樹脂層
を介して半導体素子と基板との間を接着するようにして
いる。これにより、半導体素子と基板との間の隙間をあ
らかじめ２液性の樹脂層によって埋め込むことが可能と
なるため、隙間が形成されることはなく、したがって、
樹脂を充填するための工程が不要となるものである。According to the present invention, for example, a main component or a curing agent is applied to the surfaces of a semiconductor element and a substrate, respectively,
The semiconductor element and the substrate are adhered to each other via a two-liquid resin layer formed by mixing the main component and the curing agent. As a result, the gap between the semiconductor element and the substrate can be filled with the two-liquid resin layer in advance, so that the gap is not formed.
This eliminates the need for the step of filling the resin.
【００１２】しかも、２液性の樹脂層は、主剤と硬化剤
とが混ざり合って始めて接着力を生じるものであるた
め、管理が容易であるなど、製造工程上での作業性に優
れるものである。Moreover, since the two-component resin layer produces an adhesive force only after the main component and the curing agent are mixed with each other, the management is easy and the workability in the manufacturing process is excellent. is there.
【００１３】[0013]
【発明の実施の形態】以下、この発明の実施の一形態に
ついて図面を参照して説明する。図１は、本発明の実施
の一形態にかかる、チップサイズとほぼ同等のサイズを
有してなるＣＳＰ（Chip Scale Package）の概略構成を
示すものである。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a CSP (Chip Scale Package) having a size substantially equal to a chip size according to an embodiment of the present invention.
【００１４】このＣＳＰは、半導体素子としての半導体
チップ１０を、パッケージ基台（基板）２０上に、２液
性の樹脂からなる接着層３０を介して、フェイス・ダウ
ン・ボンディング法（フリップチップ接続方式）により
接合してなる構造となっている。In this CSP, a semiconductor chip 10 as a semiconductor element is mounted on a package base (substrate) 20 through a face down bonding method (flip chip connection) via an adhesive layer 30 made of a two-component resin. It is a structure that is joined by the method).
【００１５】上記半導体チップ１０は、その表面に、た
とえばアルミニウム（Ａｌ）または銅（Ａｕ）からなる
複数の電極パッド１１が配置されている。各電極パッド
１１上には、半田や金（Ａｕ）などからなる突起電極１
２が設けられている。On the surface of the semiconductor chip 10, a plurality of electrode pads 11 made of, for example, aluminum (Al) or copper (Au) are arranged. On each electrode pad 11, a protruding electrode 1 made of solder, gold (Au), or the like is provided.
2 are provided.
【００１６】上記パッケージ基台２０は、たとえば上記
半導体チップ１０とほぼ同等のサイズを有して形成され
る、セラミックやガラス−エポキシなどからなるベース
２１の表面の、上記半導体チップ１０上の各電極パッド
１１に対応する位置に、それぞれＡｕなどからなる配線
パッド２２が設けられている。各配線パッド２２は、ス
ルーホール２３をそれぞれに介して上記ベース２１の裏
面に引き出されている。上記各スルーホール２３に対応
する、上記ベース２１の裏面には、それぞれ半田ボール
からなる電極バンプ２４が形成されている。The package base 20 is provided with electrodes on the surface of the semiconductor chip 10 on the surface of a base 21 made of, for example, ceramic or glass-epoxy, which is formed to have substantially the same size as the semiconductor chip 10. Wiring pads 22 made of Au or the like are provided at positions corresponding to the pads 11. Each wiring pad 22 is drawn out to the back surface of the base 21 through a through hole 23. Electrode bumps 24 each made of a solder ball are formed on the back surface of the base 21 corresponding to the through holes 23.
【００１７】上記接着層３０は、たとえばエポキシ系の
主剤と硬化剤とを混合して所望の接着力を得るようにし
てなり、上記半導体チップ１０とパッケージ基台２０と
の間の隙間を完全に埋め込むかたちで設けられている。The adhesive layer 30 is formed by mixing, for example, an epoxy-based main agent and a curing agent to obtain a desired adhesive force, and the gap between the semiconductor chip 10 and the package base 20 is completely removed. It is provided by embedding.
【００１８】次に、上記した構成のＣＳＰの製造方法に
ついて説明する。図２は、上記のＣＳＰの製造プロセス
を概略的に示すものである。まず、ウェーハ状態の半導
体チップ１０の各電極パッド１１上に電界メッキにより
突起電極１２をそれぞれ形成した後、ダイシングを行っ
て各チップ１０を切り出す。そして、切り出したチップ
１０の表面（ボンディング面）に、たとえば硬化剤３０
ａを塗布する（同図（ａ））。Next, a method of manufacturing the CSP having the above structure will be described. FIG. 2 schematically shows the manufacturing process of the CSP described above. First, the protruding electrodes 12 are formed by electroplating on the electrode pads 11 of the semiconductor chip 10 in a wafer state, and then the chips 10 are cut out by dicing. Then, on the surface (bonding surface) of the cut chip 10, for example, a curing agent 30
A is applied ((a) in the figure).
【００１９】上記硬化剤３０ａの塗布は、たとえば、デ
ィスペンサを用いる方法と印刷による方法のどちらでも
可能であるが、ここでは、特にディスペンサを用いた１
点ノズルによる方法を示している。The coating of the curing agent 30a can be performed by either a method using a dispenser or a method using printing. Here, in particular, a dispenser is used.
The method using a point nozzle is shown.
【００２０】一方、上記パッケージ基台２０の、上記ベ
ース２１の裏面に、上記配線パッド２２およびスルーホ
ール２３につながる電極バンプ２４をそれぞれ形成す
る。また、上記半導体チップ１０の搭載面に、たとえば
エポキシ系の主剤３０ｂを塗布する（同図（ｂ））。上
記主剤３０ｂの塗布は、たとえば、ディスペンサを用い
て行われる。On the other hand, electrode bumps 24 connected to the wiring pads 22 and through holes 23 are formed on the back surface of the base 21 of the package base 20. Further, for example, an epoxy-based base material 30b is applied to the mounting surface of the semiconductor chip 10 ((b) of the same figure). The base material 30b is applied using, for example, a dispenser.
【００２１】ここで、上記硬化剤３０ａおよび主剤３０
ｂの塗布量は、上記半導体チップ１０とパッケージ基台
２０との間の隙間、つまり、上記両パッド１１，２２の
接合部の高さ（実際には、各パッド１１，２２の高さは
無視できる程度のものであるため、上記突起電極１２の
高さ）と上記半導体チップ１０の面積とから事前に計算
される上記接着層３０の容量（体積）、並びに、上記半
導体チップ１０とパッケージ基台２０との間での接着の
強度（所望の接着力を得るための割合（比率））に応じ
て決定される。Here, the curing agent 30a and the main agent 30 are used.
The coating amount of b is the gap between the semiconductor chip 10 and the package base 20, that is, the height of the joint between the pads 11 and 22 (actually, the height of each pad 11 and 22 is ignored. Since it is as small as possible, the capacity (volume) of the adhesive layer 30 calculated in advance from the height of the protruding electrode 12) and the area of the semiconductor chip 10, and the semiconductor chip 10 and the package base. It is determined according to the strength of adhesion between 20 and 20 (ratio for obtaining a desired adhesive force).
【００２２】たとえば、上記硬化剤３０ａと主剤３０ｂ
とを１対１の割合で混合することにより所望の接着力が
得られる条件下においては、上記硬化剤３０ａおよび主
剤３０ｂの塗布量はそれぞれ上記接着層３０の体積の１
／２ずつとなる。For example, the curing agent 30a and the main agent 30b
Under the condition that a desired adhesive force is obtained by mixing and in a ratio of 1: 1, the coating amount of each of the curing agent 30a and the main agent 30b is 1 volume of the adhesive layer 30.
/ 2 each.
【００２３】さて、上記硬化剤３０ａの塗布された半導
体チップ１０は、その裏面が、フリップチップボンダの
ホルダ４０によってバキューム吸着されて保持される。
また、上記主剤３０ｂの塗布されたパッケージ基台２０
は、図示していないステージ上にバキューム吸着されて
固定される（同図（ｃ））。The back surface of the semiconductor chip 10 coated with the curing agent 30a is vacuum-held and held by the holder 40 of the flip chip bonder.
In addition, the package base 20 coated with the main agent 30b
Are vacuum-adsorbed and fixed on a stage (not shown) ((c) in the figure).
【００２４】そして、半導体チップ１０上の各電極パッ
ド１１とパッケージ基台２０の各配線パッド２２とを位
置合わせした後、上記ホルダ４０を降下させながら加圧
することにより、両パッド１１，２２間がそれぞれ突起
電極１２を介してフェイス・ダウン接合される。After the electrode pads 11 on the semiconductor chip 10 and the wiring pads 22 of the package base 20 are aligned, the holder 40 is pressed down while being pressed, so that the space between the pads 11 and 22 is reduced. Face-down bonding is performed through the protruding electrodes 12, respectively.
【００２５】その際、半導体チップ１０の表面に塗布さ
れた硬化剤３０ａとパッケージ基台２０の表面に塗布さ
れた主剤３０ｂとが徐々に混ざり合い、上記半導体チッ
プ１０とパッケージ基台２０との間の、両パッド１１，
２２の接合部を除く、上記突起電極１２の高さ分の隙間
内に充填される。At this time, the curing agent 30a applied to the surface of the semiconductor chip 10 and the main agent 30b applied to the surface of the package base 20 are gradually mixed, and the space between the semiconductor chip 10 and the package base 20 is gradually increased. , Both pads 11,
It is filled in a gap corresponding to the height of the bump electrode 12 excluding the joint portion 22.
【００２６】しかる後、その半導体チップ１０とパッケ
ージ基台２０とを、半田の溶解温度に設定されたリフロ
ー炉（図示していない）内に通すことにより、両パッド
１１，２２間が本格的に接合されるとともに、キュアに
よって硬化剤３０ａおよび主剤３０ｂが完全に硬化され
て、半導体チップ１０とパッケージ基台２０との間が接
着層３０を介して強固に接着される。Thereafter, the semiconductor chip 10 and the package base 20 are passed through a reflow furnace (not shown) set to the melting temperature of the solder, so that the space between the pads 11 and 22 is made in earnest. While being bonded, the curing agent 30a and the main agent 30b are completely cured by curing, and the semiconductor chip 10 and the package base 20 are firmly bonded via the adhesive layer 30.
【００２７】こうして、図１に示した、チップサイズと
ほぼ同等のサイズを有してなる、ＢＧＡ（Ball Grid Ar
ray ）タイプのＣＳＰが容易に完成される。なお、信頼
性の向上を図るために、半導体チップ１０の露出部をモ
ールド樹脂などによって封止してなる構成とすることも
可能である。Thus, a BGA (Ball Grid Ar) having a size almost equal to the chip size shown in FIG.
ray) type CSP is easily completed. In addition, in order to improve the reliability, the exposed portion of the semiconductor chip 10 may be sealed with a molding resin or the like.
【００２８】上記したように、半導体チップおよびパッ
ケージ基台の表面にそれぞれ主剤または硬化剤を塗布し
ておき、これら主剤および硬化剤を混合してなる２液性
の樹脂からなる接着層を介して、チップと基台との間を
接着するようにしている。これにより、フェイス・ダウ
ン接合時に、半導体チップとパッケージ基台との間にあ
らかじめ接着層を埋め込む（充填する）ことが可能とな
る。したがって、半導体チップとパッケージ基台との両
パッドの接合部を接合とほぼ同時に保護できるととも
に、半導体チップとパッケージ基台との間に隙間が形成
されることがなくなるために、接合後における、樹脂を
充填するための工程を省略できるものである。As described above, the main component or the curing agent is applied to the surfaces of the semiconductor chip and the package base, respectively, and the adhesive layer made of a two-component resin prepared by mixing the main component and the curing agent is used. , The chip and the base are bonded together. This makes it possible to embed (fill) the adhesive layer in advance between the semiconductor chip and the package base during face-down joining. Therefore, the joint between the pads of the semiconductor chip and the package base can be protected almost at the same time as the joint, and a gap is not formed between the semiconductor chip and the package base. It is possible to omit the step for filling.
【００２９】しかも、２液性の樹脂からなる接着層は、
主剤と硬化剤とが混ざり合って始めて接着力を生じるも
のであるため、管理が容易であるなど、製造工程上での
作業性に優れ、生産性の向上にとって大変に有利であ
る。Moreover, the adhesive layer made of a two-component resin is
Since the adhesive force is generated only when the main agent and the curing agent are mixed, the management is easy and the workability in the manufacturing process is excellent, which is very advantageous for improving the productivity.
【００３０】なお、上記した実施の一形態においては、
硬化剤を半導体チップの表面に塗布し、主剤をパッケー
ジ基台の表面に塗布するようにした場合について説明し
たが、これに限らず、たとえば硬化剤をパッケージ基台
の表面に塗布し、主剤を半導体チップの表面に塗布する
ようにした場合にも同様の効果が得られる。In the above embodiment,
Although the case where the curing agent is applied to the surface of the semiconductor chip and the main agent is applied to the surface of the package base has been described, the present invention is not limited to this. For example, the curing agent is applied to the surface of the package base and the main agent is applied. The same effect can be obtained when applied to the surface of the semiconductor chip.
【００３１】また、外囲器としてのパッケージ基台は、
半導体チップのサイズとほぼ同等サイズのものに限ら
ず、他のサイズのものを用いることも可能である。その
他、この発明の要旨を変えない範囲において、種々変形
実施可能なことは勿論である。Further, the package base as an envelope is
The size of the semiconductor chip is not limited to substantially the same size, and other sizes can be used. Of course, various modifications can be made without departing from the scope of the present invention.
【００３２】[0032]
【発明の効果】以上、詳述したようにこの発明によれ
ば、半導体素子と基板との間の隙間に樹脂を充填するた
めの工程を不要にでき、生産性を大幅に向上することが
可能な半導体装置およびその製造方法を提供できる。As described above in detail, according to the present invention, the process for filling the resin in the gap between the semiconductor element and the substrate can be eliminated, and the productivity can be greatly improved. A semiconductor device and a method for manufacturing the same can be provided.
【図１】この発明の実施の一形態にかかる、ＣＳＰの概
略構成を示す断面図。FIG. 1 is a sectional view showing a schematic configuration of a CSP according to an embodiment of the present invention.
【図２】同じく、ＣＳＰの製造プロセスを説明するため
に示す概略図。FIG. 2 is a schematic diagram similarly shown for explaining the manufacturing process of the CSP.
１０…半導体チップ、１１…電極パッド、１２…突起電
極、２０…パッケージ基台、２１…ベース、２２…配線
パッド、２３…スルーホール、２４…電極バンプ、３０
…接着層、３０ａ…硬化剤、３０ｂ…主剤。10 ... Semiconductor chip, 11 ... Electrode pad, 12 ... Projection electrode, 20 ... Package base, 21 ... Base, 22 ... Wiring pad, 23 ... Through hole, 24 ... Electrode bump, 30
... Adhesive layer, 30a ... Curing agent, 30b ... Main agent.
Claims (4)
・ボンディング法により接合するようにしてなる半導体
装置において、 前記半導体素子と前記基板とを、主剤と硬化剤とを混合
してなる２液性の樹脂層を介して接着してなることを特
徴とする半導体装置。1. A semiconductor device in which a semiconductor element is bonded onto a substrate by a face down bonding method, wherein the semiconductor element and the substrate are two-part liquid prepared by mixing a main agent and a curing agent. A semiconductor device characterized by being bonded via the resin layer of.
大きさを有する外囲器であることを特徴とする請求項１
に記載の半導体装置。2. The substrate is an envelope having substantially the same size as the semiconductor element.
3. The semiconductor device according to claim 1.
除く部分に主剤または硬化剤のいずれか一方を塗布し、 前記半導体素子がフェイス・ダウン・ボンディング法に
より接合される基板の、その表面の、電極の形成位置を
除く部分に主剤または硬化剤のいずれか他方を塗布し、 前記半導体素子上の電極と前記基板上の電極とをフェイ
ス・ダウンして位置合わせした後、加圧し、 前記半導体素子と前記基板との相互を、前記主剤および
硬化剤を混合してなる２液性の樹脂層を介して接着する
ようにしたことを特徴とする半導体装置の製造方法。3. A surface of a substrate to which the semiconductor element is bonded by a face-down bonding method, by coating either one of a main agent and a curing agent on a portion of the surface of the semiconductor element excluding an electrode forming position. Of the main component or the curing agent is applied to a portion excluding the position where the electrode is formed, and the electrode on the semiconductor element and the electrode on the substrate are face down aligned and then pressed, A method of manufacturing a semiconductor device, characterized in that a semiconductor element and the substrate are adhered to each other through a two-component resin layer formed by mixing the main component and a curing agent.
じ大きさを有する外囲器が用いられることを特徴とする
請求項３に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein an envelope having substantially the same size as the semiconductor element is used for the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8021298A JPH09213735A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8021298A JPH09213735A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09213735A true JPH09213735A (en) | 1997-08-15 |
Family
ID=12051247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8021298A Pending JPH09213735A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09213735A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007035897A (en) * | 2005-07-27 | 2007-02-08 | Asahi Kasei Electronics Co Ltd | Circuit adhesive sheet and fine connection structure |
-
1996
- 1996-02-07 JP JP8021298A patent/JPH09213735A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007035897A (en) * | 2005-07-27 | 2007-02-08 | Asahi Kasei Electronics Co Ltd | Circuit adhesive sheet and fine connection structure |
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