JPH09213715A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of dispersion of threshold voltage due to the use of not less than two injection conditions by forming Schottky electrodes using a plurality of metals and by forming transistors with a plurality of thresholds by using those Schottky electrodes as gate electrodes respectively. SOLUTION: Nitrogen ions are injected with an accelerating voltage of e.g. 80keV into a predetermined region on a silicon carbide substrate 13 by using a photoresist as a mask to form active layers 11a, 11b. Then nitrogen ions are injected into the source and drain regions to form heavily doped regions 14a, 14b. Then, a silicon oxide film 15 is deposited on the whole surface of the substrate, and an annealing treatment is carried out by using this oxide film 15 as a cap. Continuously, a source-drain region pattern is formed and source electrodes 16a, 16b and drain electrodes 17a, 17b are formed. Then, after a gate electrode forming parts are patterned, the oxide film 15 is etched to form a titanium gate electrode 21. Then, a gold electrode 23 is formed similarly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A metal-semiconductor contact-type field effect transistor (hereinafter referred to as MESFET) using a compound semiconductor has recently been used as a power device with high gain and high efficiency in a high frequency band for transmission of mobile communication equipment. The demand for the device is increasing. The method of manufacturing this MESFET is roughly classified into two methods, one that uses epitaxial growth for forming the active layer and the other that uses ion implantation.

7 and 8 show a conventional integrated circuit manufacturing process. Using the photoresist 72 as a mask, nitrogen ions are implanted into the GaAs substrate 73 at 80 keV to form the active layer 71 (FIG. 7A).

Again using the photoresist as a mask, nitrogen ions are implanted at 40 keV to form an active region 74.

Next, using the photoresist as a mask, nitrogen ions are implanted into the source and drain regions at 150 keV to form a source / drain n + layer (high concentration layer) (FIG. 7 (c)).

A silicon oxide film 78 is deposited on the entire surface of the substrate,
Using this film as a cap, annealing treatment is performed at 1500 ° C. for 15 minutes to activate the implanted nitrogen ions.
A source / drain region pattern is formed again using the photolithography process, nickel is vapor-deposited on the entire surface, lift-off is performed, and heat treatment is performed to form the source electrode 76 / drain electrode 77 (FIG. 7D).

Next, a pattern is formed on the gate electrode formation portion with a photoresist (FIG. 8A).

The silicon oxide film 78 is etched by reactive dry etching (hereinafter referred to as RIE) using CF4 gas to form a titanium electrode 81 (FIG. 8).
(B)).

In this way, by separately implanting ions into the active layer, an integrated circuit composed of FETs having two kinds of threshold voltages is produced.

[0010]

In the manufacturing process of such a conventional semiconductor integrated circuit, different ion implantation conditions are used when forming the active layer 71 and the active layer 74.
The problem is that the threshold voltage variations of the active layer 71 and the active layer 74 are different. That is, even if the threshold value of the active layer 71 varies toward the lower side of the set value, the active layer 74 varies toward the higher side of the set value. Therefore, the width of variation in the threshold value of this integrated circuit is considerably larger than that in the case where one active layer is formed. In a circuit (logic circuit or the like) using two kinds of threshold voltages, the logic circuit may not be formed due to the variation in the threshold voltage, resulting in a decrease in yield.

In view of the above, the present invention provides a high-performance semiconductor integrated circuit that reduces the influence of threshold voltage variations due to the use of two or more types of implantation conditions, and a manufacturing method capable of forming the semiconductor integrated circuit easily and with high yield. The purpose is to do.

[0012]

In order to solve the above problems, the present invention uses only one kind of ion implantation condition by using different combinations of the Schottky barrier heights of the semiconductor / metal interface. To realize different threshold voltages. That is, if two kinds of materials forming the gate electrode are used, an integrated circuit having different threshold values can be formed due to the difference in Schottky barrier from the active layer.

According to the manufacturing method of the present invention, FETs having different threshold voltages can be realized by forming the active layer only once. Further, compared to the conventional method, the active layer is formed only once, so that the characteristics can be stabilized.

Further, since it is almost the same as the conventional process, it can be easily introduced into the FET manufacturing process.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Specific examples will be described in detail below.

(Embodiment 1) FIGS. 1 and 2 explain a first embodiment of the present invention.

A photolithography process is used on one main surface of the silicon carbide substrate (4H-SiC) 13, and nitrogen ions are implanted into a predetermined region at an accelerating voltage of 80 keV using the photoresist 12 as a mask to activate the active layers 11a and 11b. Are formed (FIG. 1A).

Next, again using the photoresist 12a as a mask, nitrogen ions of 150 are applied to the source and drain regions.
Source / drain n + layers 14a, 14b by injection with keV
(High concentration layer) is formed (FIG. 1B).

A silicon oxide film 15 is deposited on the entire surface of the substrate,
Using this film as a cap, an annealing treatment is performed at 1500 ° C. for 15 minutes to activate the implanted material. A source / drain region pattern is formed again by using the photolithography process, nickel is entirely vapor-deposited, lift-off is performed, and heat treatment is performed to form the source electrodes 16a16b / drain electrodes 17a17b (FIG. 1C).

Next, the photoresist 12b is used to pattern the gate electrode formation portion 18 of the arbitrary first FET formation portion within the wafer surface (FIG. 1 (d)).

The silicon oxide film 15 is etched by RIE using CF4 gas to form a titanium gate electrode 21 (FIG. 2 (a)).

Next, with the photoresist, the first FET
Patterning is performed on the gate electrode formation portion 22 of the second FET formation portion other than the formation portion (FIG. 2B).

The silicon oxide film 15 is etched by RIE using CF4 gas to remove the gold gate electrode 23.
Is formed (FIG. 2C).

As described above, the FET is formed with titanium as the gate electrode in the first FET formation region, and the FET is formed with gold as the gate electrode in the second FET formation region. FETs with different materials
An integrated circuit with is formed. 4H-Si of this example
In C, the height of the Schottky barrier of the titanium electrode is 1.16 eV.
And the Schottky barrier height of the gold electrode is 1.80 eV.

In the integrated circuit thus formed, the difference between the threshold voltages of the two types of FETs is determined only by the difference in the Schottky barrier height peculiar to the material. Even if the threshold value varies greatly, the difference between the threshold voltages of the two types of FETs (logical amplitude in the logic circuit)
Does not change. Therefore, the yield of the integrated circuit can be improved without being affected by the process variation.

In the above description, the case of the MESFET in which the active layer is formed by using the ion implantation has been described, but the MESFET in which the active layer is formed by using the crystal growth is described.
In the case of, it can be implemented in the same manner.

In the present embodiment, the case where the active layer is the n-type alone has been described, but (1) a p-type layer is buried under the n-type active layer to form a depletion layer formed as a pn junction. A p-layer embedded structure that can effectively reduce the thickness of the n-type active layer by using it.
It goes without saying that the same applies to the case.

(Embodiment 2) FIGS. 3 and 4 explain a second embodiment of the present invention. This embodiment is an integrated circuit in which the threshold is different depending on whether the surface of the active layer is a silicon atomic plane or a carbon atomic plane.

Using a photolithography process on one main surface of the silicon carbide substrate 13, nitrogen ions are implanted into a predetermined region at an acceleration voltage of 80 keV to form an active layer, and then a first FET is formed. Only the active layer is opened, and the active layer 31 having the carbon atom surface on the outermost surface is formed by selective etching (FIG. 3A).

Next, the second FET other than the active layer 31
After forming a resist pattern having an opening only on the region where the silicon is formed, the active layer 32 in which the silicon atomic plane appears on the outermost surface is formed by selective etching (FIG. 3B). The surface of the second FET formation region is a silicon atomic plane,
The surface of the first FET formation region is a carbon atom plane.

Next, again using the photoresist as a mask, nitrogen ions are introduced into the source and drain regions at 150 keV.
To form a source / drain n + layer 14 (high concentration layer) (FIG. 3 (c)).

A silicon oxide film 15 is deposited on the entire surface of the substrate,
Using this film as a cap, annealing treatment is performed at 1500 ° C. for 15 minutes to activate the implanted nitrogen ions. A source / drain region pattern is formed again using the photolithography process, nickel is vapor-deposited over the entire surface, lift-off is performed, and heat treatment is performed to form the source electrode 16 / drain electrode 17 (FIG. 3D).

Next, a photoresist is used to form a pattern on the gate electrode formation portion of an arbitrary FET formation portion on the wafer surface (FIG. 4A). RIE using CF4 gas
The silicon oxide film is etched by means of the active layer 3 in which the titanium gate electrode 41 has the carbon atom surface on the outermost surface.
1 (FIG. 4B).

Next, with the photoresist, the first FET
Patterning of the gate electrode formation portion is performed in the second FET formation region other than the formation portion (FIG. 4C).

The silicon oxide film is etched by RIE using CF4 gas to form the gold gate electrode 42 on the active layer 32 where the silicon atomic plane appears on the outermost surface (FIG. 4 (d)).

By repeating the above steps, an integrated circuit having FETs having different combinations of gate electrode materials and active layers is formed. Since the surface of the SiC substrate has a silicon atomic plane and a carbon atomic plane, the difference in threshold voltage can be about 0.3V. In the integrated circuit thus formed, the difference in the threshold voltage of the FET is determined only by the difference in the height of the Schottky barrier peculiar to the material, so that there is no influence of the activation fluctuation of the FET active layer and the yield is improved. Can be achieved.

(Embodiment 3) FIGS. 5 and 6 explain a third embodiment of the present invention. In this embodiment, a silicon substrate is used, and layers having different crystal structures of crystals grown on the substrate are used to form integrated circuits having different threshold voltages.

First, silicon oxide 53 is deposited on a silicon substrate 51, an arbitrary portion of silicon oxide is removed by a photolithography process to form an opening in a first region, and an n-type silicon carbide is formed in this opening. (6H-SiC) 52
Are grown (FIG. 5 (a)).

Silicon oxide is deposited again, silicon oxide in the second region near the first region is removed, and n-type silicon carbide (4C-SiC) 54 is grown (FIG. 5B). The layer grown here is SiC having a 4C structure, which is different from the 6H structure grown in the first region. This growth can be performed by changing the growth temperature and the like, as compared with the conditions under which the 6H structure grows.

Next, the in-plane silicon oxide film 53 is etched and flattened by using the etch back method (FIG. 5).
(C)).

Next, with the resist 55, n-type silicon carbide (6
A gate region opening pattern is formed on the (H-SiC) 52 (FIG. 5D). Then, isotropic etching is performed to form an active layer of the field effect transistor in the first region (FIG. 6A).

Similarly, n-type silicon carbide (4C-S
A gate area opening pattern is formed on the iC) 54 (FIG. 6B). Next, isotropic etching is performed to form an active layer of the field effect transistor in the second region. And
A source electrode 61 and a drain electrode 62 are formed in the first region and the second region, respectively (FIG. 6C).

Finally, a gold gate electrode 63 and a titanium gate electrode 64 are formed in the first region and the second region, respectively, to complete field effect transistors having different threshold values. The difference in threshold voltage between the FET formed in the first region and the FET formed in the second region can be secured at about 1.0V.

In the figure, only one FET is formed in each of the first region and the second region, but an FET having titanium and gold as gate electrodes is formed in the first region and the second region is formed.
By forming an FET using titanium and gold as the gate electrodes in the region (1), it is possible to form a field effect transistor having four kinds of threshold voltages in total.

[0045]

As described above, according to the present invention, a plurality of threshold voltages can be easily realized by forming the active layer once and using different materials for the gate electrodes.
Further, since the difference between the plurality of threshold voltages can be determined only by selecting the gate electrode material, the yield of the integrated circuit can be improved. Furthermore, since only the same process as the conventional process is repeated, it can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a first embodiment of the present invention.

FIG. 3 is a process sectional view showing a second embodiment of the present invention.

FIG. 4 is a process sectional view showing a second embodiment of the present invention.

FIG. 5 is a process sectional view showing a third embodiment of the present invention.

FIG. 6 is a process sectional view showing a third embodiment of the present invention.

FIG. 7 is a sectional view of a conventional integrated circuit manufacturing process.

FIG. 8 is a sectional view of a conventional integrated circuit manufacturing process.

[Explanation of symbols]

 11 Active Layer 12 Photoresist 13 Silicon Carbide Substrate 14 High Concentration Region 15 Silicon Oxide Film 16 Source Electrode 17 Drain Electrode 18 First Gate Aperture 21 Titanium Gate Electrode 22 Second Gate Aperture 23 Gold Gate Electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/095

Claims (10)

[Claims] 1. A field effect transistor, comprising: forming a Schottky electrode using a plurality of metals, and forming a transistor having a plurality of threshold values by using the Schottky electrode as a gate electrode. 2. The field effect transistor according to claim 1, wherein the field effect transistor has two or more kinds of threshold voltages by using electrode materials having different Schottky barrier heights. 3. The field effect transistor according to claim 1, wherein a compound semiconductor having a large band gap is used as the substrate material. 4. The field effect transistor according to claim 1, wherein silicon carbide is used as the substrate material, and titanium and gold are used as the gate electrode material. 5. A first type of a forming element of a compound semiconductor
Forming a first gate electrode that is in Schottky contact with the first surface formed only of the atoms, and Schottky formed on the second surface formed only of the second atoms other than the first atoms. And a step of forming a contacting second gate electrode. 6. A first transistor having silicon carbide, a first gate electrode in Schottky contact with a carbon atomic plane of the silicon carbide, and a second transistor having a Schottky contact in a silicon atomic plane of the silicon carbide. Second with a gate electrode
Field effect transistor having a transistor of. 7. The field effect transistor according to claim 5, wherein the field effect transistor has at least four kinds of threshold voltage transistors. 8. The field effect transistor according to claim 6, wherein titanium and gold are used as an electrode material. 9. A compound semiconductor is used which is characterized in that selective growth is used for forming an active layer, and an active layer having two or more kinds of crystal structures is grown at an arbitrary place by changing growth conditions. Method for manufacturing field effect transistor. 10. The method for manufacturing a field effect transistor according to claim 9, wherein silicon is used for the substrate and silicon carbide is used for the active layer.