JPH09213064A - Memory write/read method and memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the system performance by allowing a controller to read data from another flash memory while writing data in an arbitrary flash memory to shorten the processing time. SOLUTION: In a flash disk system, a system is designed so that, while a controller 10 executes an operation writing data DATAW equivalent to one page with respect to a certain arbitrary flash memory (for example, FM1), the controller executes a read access with respect to another arbitrary flash memory (for example, FM0) in a period tWB by using the period tWB when the flash memory FM1 is in a busy state because of the operation writing data in the memory to read out data DATAR equivalent to one page from the flash memory. Thus, the system performance is improved by shortening the processing time.

Description

Detailed Description of the Invention

[0010]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system in which a plurality of flash memories are connected on the same bus.

[0020]

2. Description of the Related Art Generally, in a memory system using a semiconductor memory having a fixed storage capacity, a large number of semiconductor memories (chips) are connected in parallel on the same bus in order to increase the storage capacity of the entire system. Is taken. In such a memory system, while the controller (or computer) connected to the bus is accessing a certain semiconductor memory, the bus is occupied by this semiconductor memory, and other semiconductor memories are effectively isolated from the controller. Be placed in the specified state. Then, when the access to the semiconductor memory is completed, the bus is released and the other semiconductor memories can be accessed.

By the way, in recent years, a flash memory (flash EEPR) has been used as a semiconductor memory replacing a magnetic memory such as a hard disk or a floppy disk.
OM) is receiving attention. Flash memory is a non-volatile, low-power-consumption, electrically rewritable semiconductor memory, which is lightweight and small in size and has good earthquake resistance, and therefore its application to portable devices and the like is expanding.

Generally, in a computer system using a flash memory as an external storage device, the flash memory is
A dedicated controller for memory is used. A host computer (for example, a personal computer) may instruct the controller to write or read data. Upon receiving an instruction (command) from the host, the controller directly controls writing and reading of data with respect to the flash memory, and further performs memory management such as batch erasing unique to the flash memory.

[0050]

Even in the system using the flash memory as described above, in order to obtain a desired storage capacity in the entire system, a structure in which a plurality of flash memories are connected to the internal bus is adopted. There are many.

In the conventional flash memory system of this kind, there is a limitation on the internal bus as described above, that is, on the hardware that another memory cannot be accessed while the certain memory is being accessed. In accordance with the limitation of 1), the controller has been configured to execute write access to one flash memory and read access to another flash memory non-simultaneously or non-parallelly.

Therefore, when, for example, rewriting data, data of almost one block in a certain flash memory is moved to an empty block of another flash memory, one data is moved from the flash memory of the movement source. An operation is performed in which a read cycle for reading data for a page or a sector and a write cycle for writing the read data for one page to the destination flash memory are repeated (serially in time). It was
Therefore, the total number of pages to be moved is N, one read cycle is TR, and one write cycle is TW.
Then, the total time required was about N (TR + TW).

However, such a non-simultaneous or non-parallel write / read method directly follows the memory access method in the conventional general memory system in which a plurality of ROMs and RAMs are connected on the same bus. It overlooked the unique characteristics of flash memory.

That is, in the flash memory,
There is a marked difference between the time required to write data and the time required to read data. Since data writing is performed by injecting hot electrons into the memory cell (EEPROM), a long time of about 300 to 500 μs is required. On the other hand, when reading data, a predetermined voltage is applied to the gate of the memory cell to detect whether or not the memory cell conducts (that is, to detect the current).
Since this is done, a short time of about 25 μs is sufficient.

In a general flash memory, since the time required for writing is long as described above, all the terminals except the busy terminal are closed during the writing operation in the memory chip. Therefore, the control signal and data from the outside are not accepted.

The present invention has been made in view of the above-mentioned problems of the prior art and the nature of the flash memory, and provides a memory system in which a plurality of flash memories are connected on the same bus. Provide a memory writing / reading method and a memory control device for shortening processing time and improving system performance by reading data from another arbitrary flash memory while writing data to an arbitrary certain flash memory The purpose is to do.

[0120]

In order to achieve the above-mentioned object, the invention according to claim 1 of the present invention is the first flash in which a memory control device connected to a plurality of flash memories is arbitrary. .First via a common bus for memory
Of the second flash data from the second flash memory via the bus at the same time as writing the data of the first flash memory, wherein the memory control device includes the first flash memory via the bus. A first step of applying a write command, a write address and the first data to the flash memory at a predetermined timing; and the first flash memory responding to the write command at a first predetermined time. A second step of writing the first data in a storage area designated by the write address in a state where a signal from the outside is not received therein;
A third step in which the memory control device gives a read command and a read address to the second flash memory at a predetermined timing via the bus within the first predetermined time; and the second flash. The memory, in response to the read command, reads the second data from the storage area designated by the read address within a second predetermined time.
Reading the data of the second flash memory and setting the read data in the output port, and the second data set in the output port of the second flash memory by the memory control device after the second predetermined time has elapsed. Is taken in via the bus.

Further, according to the second aspect of the present invention, in response to the write command, the write address and the first data given at the predetermined timing, the external signal is not accepted within the first predetermined time. In the write mode for writing the first data to the storage address designated by the write address, and in response to the read command and the read address given at a predetermined timing, a second mode shorter than the first predetermined time. A memory connected through a common bus to a plurality of flash memories, each having a read mode for reading second data from a storage address designated by the address within a predetermined time In the control device, the write command, the write address, and the first write command are sent to the first flash memory via the bus. Write control means for supplying first data at a predetermined timing to cause the first flash memory to execute the write mode; and a first flash memory in the first predetermined time during the first predetermined time. The read command and the read address are supplied to the two flash memories via the bus at a predetermined timing, and after the second predetermined time has elapsed, the read command is output from the output port of the second flash memory. Read control means for fetching the second data via the bus.

According to a third aspect of the present invention, in the configuration of the second aspect of the invention, the read control means sets each of the flash memories individually to an output enable state. It is characterized by including a dedicated output enable control line.

According to a fourth aspect of the invention, in the configuration of the second aspect of the invention, the write control means and the read control means individually determine whether or not each of the flash memories is in a busy state. It is characterized in that it includes a dedicated busy line for each flash memory in order to make it visually recognizable.

[0160]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the configuration of a flash disk system according to an embodiment of the present invention. In this system, one controller 10 and a plurality of (n + 1
Each chip of each NAND flash memory FM0 to FMn is mounted on one card (flash disk card) 12. The card 12 is installed in the card slot of the host computer 14, and the controller 10 is connected to the host computer 14 by an interface of a predetermined standard, for example, PCMCIA-ATA or IDE interface 16. Flash memory F
M0 to FMn are memory chips having the same structure and function.

[0180] on the card 12, the controller 10, for example an internal bus FD0~7 8-bit wide, all flash memory FM0 to FMn in common the one control line FCLE, FALE, XFWP and XFWE _- and , (N + 1) control lines XFCE0 _-to XFC individually assigned to the respective flash memories FM0 to FMn
En ₋ , XFRE0 _{− to} XFREn ₋ and XFBSY0 _{− to} X
FBSYn _- and each flash memory FM0-F
It is connected to Mn.

The internal buses FD0 to FD7 are connected to the controller 10
And commands between each flash memory FM0 to FMn,
It is also used for address and data transmission. Among the common control lines, FCLE is a command latch enable control line for making the flash memories FM0 to FMn identify the command codes on the buses FD0 to FD7 as commands. FALE is an address latch enable control line for causing the flash memories FM0 to FMn to identify the address code on the buses FD0 to FD7 as an address. XFWP is a flash memory FM
This is a write protect control line for forcibly prohibiting writing from 0 to FMn. XFWE _- is the bus FD0
~ 7 Code or data on each flash memory F
This is a write enable control line to be taken into M0 to FMn.

Of the above individual control lines, XFCE
0 _- ~XFCEn _- is, each flash memory FM0 ~FM
A chip enable control line for individually or independently setting n to the chip enable state (operable state). XFRE0 _- ~XFREn _- is read (output) enable control line for outputting individually or independently read data on bus FD0 to 7-from the output port of each flash memory FM0 to FMn. Also, XF
BSY0 _-to XFBSYn _- are each flash memory FM
0 to FMn are busy lines for individually or independently notifying the controller 10 of each busy state.

FIG. 2 is a block diagram showing the functional structure of the inside of the controller 10. The controller 10 has a main body interface unit 20, a reset processing unit 22, an address conversion unit 24, a command processing unit 26, a flash table control unit 28, a flash command generation unit 30, an error control unit 32, and a flash interface unit 34. doing.

The main body interface section 20 incorporates various registers which can be written / read out directly from the host computer 14, and a bus of the host 14 has an interface of a predetermined standard such as PCMCIA-ATA or ID.
Connected by E interface.

In this host interface, in order to select each register in the main body interface section 20 from the host 14, address signals A0-10 and control signal XC are selected.
E1-2 are used. XREG is used to select the memory space and I / O space of the address map. A control signal XWE ₋ / XOE ₋ is used for writing / reading in the memory space, and a control signal X is used for writing / reading in the I / O space.
IOWR _- / XIORD _- is used. For host 14 from the main interface unit 20, an interrupt request signal XIREQ _-, the input acknowledge signal XINPACK
_- and the like can be emitted. The main body interface unit 20 also includes a circuit for decoding a command from the host 14.

The reset processing unit 22 controls the process of resetting each unit in the controller 10 in response to a reset signal from the outside, for example, XPONRST, as well as the process of initialization after reset release.

The address conversion unit 24 converts the CHS (cylinder head sector) mode logical address specified by the host 14 side into the LBA (logical block address) mode logical address in the flash disk.

The command processing section 26 controls each section in the controller 10 to execute the command from the host 14 decoded by the main body interface section 20.

The flash table control unit 28 initializes the address conversion table and the empty block table in response to a request from the reset processing unit 22, the command processing unit 26, etc., and responds to a command from the host 14. Search or update the table. The flash table control unit 28 is provided with a volatile table memory such as an SRAM, and an address conversion table and an empty block table are constructed on this memory.

The flash command generator 30 generates command codes and address signals for the flash memories FM0 to FMn in response to requests from the flash table controller 28, the command processor 26 and the like.

The error control unit 32 executes ECC (Error Checking and Correction) processing at the time of writing / reading.

The flash interface section 34 includes the common buses FD0 to FD7 and various control lines (FCLE,
Flash memory FM0 to FM via FALE, etc.
It is an input / output port for exchanging data and signals with n and has a timing control function for multiplexing commands, addresses and data on the common buses FD0 to FD7 at different timings.

In FIG. 3, each flash memory FMi (i
= 0 to n) indicates a partition format of a storage area. The entire storage area of each flash memory FMi is divided into a plurality of blocks, for example 512 blocks BL0 to BL511, and each block BLj (j = 0 to 511) has a plurality of blocks, for example 1.
It is divided into six pages or sectors PG0 to PG15. Normally, programming (writing) and reading are performed in page units, and erasing is performed in block units.

Each page PGk (k = 0 to 15) comprises a data area of a predetermined capacity, for example 512 bytes, and a redundant portion of a predetermined capacity, for example, 16 bytes. The data area is the original data storage area. The redundant part is divided into several fields, and each field shows a "translation table address" indicating the logical address currently assigned to the block BLj with a predetermined data amount (number of bytes) and the pass / fail of the block BLj. Redundant data such as "block status" is stored. If the block BLj is an empty block that is not currently accumulating any data, the redundant data has the "conversion table address".
Data is not included.

FIG. 4 shows an example of the internal structure of each flash memory FMi. Flash memory array 40
Is composed of a large number of memory cells arranged in a matrix. For example, as shown in FIG. 3, one chip flash memory FMi has 512 blocks BL0 ...
If each block BLj has 16 pages or sectors PG0 to PG15 and each page PGk has a 512-byte data area and a 16-byte redundant portion, the memory array 40 has 8192 (16 × 16). 51
2) It is composed of memory cells of row × 528 (512 + 16) columns and has a storage capacity of 32 megabytes.

The flash memory array 40 is electrically connected to the I / O buffer 46 having a storage capacity of one page (528 bytes) through the page register 42 and the gate circuit 44, and the memory array Parallel data transfer in page units is performed between the I / O buffer 40 and the I / O buffer 46. This flash
In the memory FMi, the I / O buffer 42 constitutes a substantial output port.

Commands, addresses or data on buses FD0-7 are latched in command register 50, X, Y address buffers 52, 54 and I / O buffer 46, respectively, via global buffer 48.

The command register 50 decodes the input command and then decodes it into the address buffers 52 and 54.
To address decoders 56 and 58 and I / O buffer 46. The command register 50 includes a status register that holds status information indicating a state in the memory.

X address buffer 52 has row address A
Taking in DX, the X address decoder 56 decodes this row address ADX and activates the designated (selected) row (page) in the array 40. The Y address buffer 54 fetches the column address ADY and
The address decoder 58 controls the gate circuit 44 to decode the column address ADY and transfer the data of the designated (selected) column in the array 40.

[0380] The control circuit 60, control signals FCLE from the controller _{10, FALE, FWP, XFCEi -} , X
FWE ₋ and XFREi ₋ are input and each unit in the memory is controlled in response to each control signal. The output driver 62 is I / O
The bus lines are driven when the read data set in the O buffer 46 is sent to the buses FD0 to FD7.

Next, referring to the timing chart of FIG. 5, in the flash disk system of this embodiment, the write cycle for writing one page of data to a certain flash memory (for example, FM1) is being executed. An operation for executing a read cycle for reading one page of data from another flash memory (for example, FM0) simultaneously or in parallel will be described.

[0400] The controller 10, the chip enable control signal throughout the period of the write cycle TW in the flash memory FM1 XFCE1 _- Active (L
Level) to keep the flash memory FM1 in the chip enable (operable) state.

First, the controller 10 activates the command latch enable control signal FCLE (H level) to send the data input command CMS of a predetermined code on the buses FD0 to FD7, and at the same time, the write enable control signal XFWE. _- and an active (L level). In response to the command writing operation from the controller 10, the flash memory FM1 is connected to the bus FD0 ...
The data input command CMS above is fetched and latched in its own command register 50.

Next, the controller 10 activates the address latch enable control signal FALE (H level) to write the write address ADW having a predetermined number of bits on the buses FD0 to FD7 once or plural times (in this example). Then 3
The write enable control signal XFWE _{-is set} to the active state (L level) each time. In response to the address write operation from the controller 10, the flash memory FM1 is connected to the buses FD0 to FD7.
The write address ADW above is fetched and latched in its own address buffers 52 and 54. This write address ADW specifies the page to be written in the flash memory FM1.

[0430] Next, the controller 10, command latch enable control signal FCLE and address latch enable control signal FALE _- in a state in which were respectively inactive (L level), one page onto the bus FD0 to 7- (528 bytes) write data DATAW
Is transmitted byte by byte, and the write enable control signal XFWE _{-is set} to the active state (L level) each time. Flash memory FM1, the write enable control signal XFWE _- in response to and stored in the I / O buffer 46 takes in one byte of data DATAW on bus FD0 to 7-.

Next, the controller 10 again activates the command latch enable control signal FCLE (H level) to send the program command CMP of a predetermined code to the buses FD0 to FD7, and at the same time, perform the write enable control. The signal XFWE _- is made active (L level). In response to the command write operation from the controller 10, the flash memory FM1 takes in the program command CMP on the buses FD0 to FD7 and latches it in the command register 50 to start the programming operation.

That is, the flash memory FM1 is
The program command CMP is decoded, and the I / O buffer 46 is stored in the storage area (page) in the flash memory array 40 designated by the write address ADW.
Write one page (528 bytes) of data DATAW stored in The data writing operation in this memory requires a fixed time tWB of, for example, about 300 μs. Flash memory FM1, when starting the data write operation, the busy signal XFBSY1 _- was active (L level), (until the predetermined time tWB elapses) thereafter until the data write operation is terminated holds this busy state.

Flash memory FM1 is busy signal X
When FBSY1 ₋ is activated (L level), the controller 10 responds to this by making the flash memory FM0.
, The read cycle TR is started. For this read cycle TR, the controller 10, the chip enable control signal XFCE0 _- holding the active (L level) to keep the flash memories FM0 to chip enable (operable) state.

[0470] First, the controller 10 sets the command latch enable control signal FCLE be active (H level), and at the same time sends a read command CMR predetermined code onto the bus FD0 to 7-, write enable control signal XFWE _- Is activated (L level). In response to the command writing operation from the controller 10, the flash memory FM0 is connected to the buses FD0 to FD7.
The read command CMR is fetched from above and latched in its own command register 50.

Next, the controller 10 activates the address latch enable control signal FALE (H level) to read the read address ADR of a predetermined number of bits on the buses FD0 to FD7 once or plural times (in this example). Then 3
The write enable control signal XFWE _{-is set} to the active state (L level) each time. The read address ADR designates a page as a read source in the flash memory FM0.

In response to the address write operation from the controller 10, the flash memory FM0 is transferred to the bus F
The read address ADR on D0-7 is taken in and the data read operation in the memory is started.

That is, the flash memory FM0 is
Input read command CMR and read address A
Data DATA of one page (528 bytes) is decoded from the storage area (page) in the flash memory array 40 designated by the read address ADR by decoding DR.
R is read and the read data DATAR is transferred (set) to the I / O buffer 46. Since the read operation in this memory requires a fixed time tRB of, for example, about 25 μs, the flash memory FM0 requires this processing time tRB.
During busy signal XFBSY0 _- active (L level)
To hold.

When the read operation in the flash memory FM0 is completed and the busy state is released (XFB
SY0 _- is back to H level), the controller 10 start to capture read data DATAR set in the I / O buffer 46 of the flash memory FM0. That is, the controller 10 reads (outputs)
Enable control signal XFRE0 _- by the repeating in a constant cycle (528 times) active (L level), the read data DATA for one page from the I / O buffer 46 of the flash memory FM0 (528 bytes)
R is fetched byte by byte via the buses FD0 to FD7.

During the read cycle TR for the flash memory FM0 as described above, the flash memory F
M1 is in the middle of a data write operation (busy state) in the memory and does not accept external signals. Therefore, the read cycle TR can be performed between the controller 10 and the flash memory FM0 independently of the flash memory FM1.

[0530] Other flash memory FM2
~ FMn are the respective chip enable control signals X
FCE2 _- ~XFCEn _- is because it is held in the disabled state (H level), substantially remain isolated from the bus AD0 to 7-. Therefore, the write cycle TW and the flash memory FM1 in the flash memory FM1
There is no influence on the read cycle TR in the memory FM0.

The read cycle TR in the flash memory FM0 is completed, and the flash memory FM
When the data write busy time tWB in 1 ends, the controller 10 confirms that the busy signal XFBSY1 ₋ has returned to the inactive state (H level), and the controller 10 successfully writes data (programming) in the flash memory FM1 this time. Inspect whether it has been done.

In order to check the quality of the programming result, the controller 10 activates the command latch enable control signal FCLE (H level) and outputs the status register read command CMC of a predetermined code on the buses FD0 to FD7. At the same time as the transmission, the write enable control signal XFWE _- is made active (L level).

In response to the command writing operation from the controller 10, the flash memory FM1 is connected to the bus F
It takes in the status register read command CMC from above D0-7, decodes this command CMC, and responds to this command CMC. That is, the write status bit I / O0 set in the status register in the command register 50 in the flash memory FM1 is sent to the buses FD0 to FD7 via the I / O buffer 46. The controller 10 receives the write status bit I / O0 from the memory FM1, and based on the bit contents, the current write cycle TW
It is determined whether or not the data writing (programming) has been successfully performed.

As described above, in the flash disk system of the present embodiment, the controller 10 executes the operation of writing the data DATAW for one page to any given flash memory (for example, FM1). , During the write cycle TW, the period tWB during which the flash memory FM1 is busy due to the data write operation in the memory is utilized, and during this period tWB, another flash memory (for example, FM0) is Read access to the flash memory FM
One page of data DATAR can be read from 0.

[0580] Even when writing or reading less than one page (528 bytes) at a time,
The write busy time tWB or the read busy time tRB in each memory FMi is almost the same as that for one page. The difference is that the controller 10 and each flash memory FM
The point is that the time required for serial transfer of write data or read data to and from i becomes shorter in proportion to the amount of data. The cycle of this serial transfer is, for example, 27 ns.
Since it is about 1 byte, the difference in data amount or serial transfer time does not significantly affect the entire write cycle TW or read cycle TR.

Next, the processing at the time of rewriting data in the flash disk system of this embodiment will be described with reference to FIGS. In the data rewriting process, writing of data in any one flash memory FMi and any other flash memory Fi as described above.
It is possible to perform parallel processing with the reading of data in Me.

In the flash disk system of this embodiment, immediately after the power is turned on or the reset is released, the flash table control unit 28 of the controller 10 stores all blocks BL0 to BL511 in each flash memory FM0 to FMn. The data stored in the redundant portion of the first page PG0 is read, and the address conversion table and empty block table are initialized for each flash memory FM0 to FMn based on the "conversion table address" included in the redundant data. To do.

Here, the address conversion table shows the physical address of the block in which data is currently written for each flash memory FM0 to FMn and the LBA (logical block address) mode designated by the host 14 when writing the data. It is a table that correlates with the logical address of. The empty block table is a table in which one or more empty blocks BL in which no data is currently written are registered for each flash memory FM0 to FMn. Always set a physical block address or pointer that specifies what should be used.

Now, in FIG. 6, when writing data to this flash disk system, the host 14 gives the controller 10 the logical address [AD] CHS in the CHS (cylinder head sector) mode. The logical address [AD] CHS from the host 14 is converted into a logical address [AD] LBA in the LBA (logical block address) mode by the address conversion unit 24 in the controller 10. Then, the logical address [AD] LBA in the LBA mode is sent to the flash table control unit 28 in the controller 10.

The flash table controller 28 assigns this logical address [AD] LBA to one specific block BL.
Upper address part that specifies j, that is, logical block address [AD] LBA, BLj, and lower address part that specifies one specific page PGj, that is, logical page address [AD]
It is divided into LBA and PGk. Then, the address conversion table 28A is referred to or searched for, and the physical block address << AD] LBA, BLj corresponding to this logical block address <AD
If AD> PH, BLj is registered in the table 28A, this physical block address <AD> PH, BLj is issued (output).
I do.

Since the logical block address [AD] LBA, BLj is a logical address in the LBA (logical block address) mode, this lower address portion, that is, the logical page address [AD] LBA, PGk is directly used as the page address of the physical address. Can also be used. Therefore, by combining this logical page address [AD] LBA, PGk and the physical block address <AD> PH, BLj,
A physical address <AD> PH that specifies the page to which data is to be written this time is obtained.

However, this physical address <AD>
Some data is currently written in the page PGk in the block BLj designated by PH, and new data cannot be overwritten on it because of the nature of the flash memory. New data must be written to another free block. Along with this, the other pages (PG0 to PGk-1, PG in the block BLj) are
The data stored in (k + 1 to PG15) must be completely transferred to the same empty block as the new data. Normally, the empty block existing in the adjacent flash memory is the destination (new block) of this data rewrite.
Be devoted to.

[0660] Therefore, the flash table control unit 28
Issues the physical block address <AD> PH, BLj in the flash memory FM0 specified by this data write, and at the same time searches the free block table 28B for the adjacent flash memory FM1 and Issue a physical block address <AD> PH, BLh that specifies one empty block BLh in the memory FM1. This physical block address <AD> PH, BLh and the lower address section (logical page address) [AD] LBA, PG
By composing with k, the page PGk to be rewritten in the empty block BLh of the flash memory FM1
A physical address <AD> PH 'that specifies

As described above, the block BLj in the flash memory FM0 to which the logical address designated by the host 14 has been allocated for writing the data has been determined, and the flash memory for rewriting the data has been allocated.
The empty block BLh in the memory FM0 is determined.

Next, as shown in FIG. 7, the controller 1
0 reads data one page at a time from the first page PG0 of the block BLj in the flash memory FM0 (except for the page PGk to be rewritten) and reads the read data from each empty block BLh in the flash memory FM1. Perform the data transfer operation of writing to the corresponding page. For the page PGk to be rewritten this time, the flash memory FM
The old data is not read from the corresponding page PGk of the block BLj in 0 but the write data (new data) from the host 14 is written to the corresponding page PGk of the empty block BLh in the flash memory FM1.

[0690] Such a series of data transfer and new data write operation is performed by the controller 10.
This is performed by the flash command generation unit 30 and the flash interface unit 34 under the control of the command processing unit 26. The flash interface unit 34 is sent from the host 14 with a buffer 34A for temporarily holding one page of data read from the source (old) block BLj until it is written to the destination (new) block BLh. Write data (new data)
Is stored in the new block BLh until the buffer 34B is temporarily held.

FIG. 8A shows the flash of this embodiment.
7 shows a time chart of data rewriting processing in the disk system.

First, in the flash memory FM0, a read cycle TR for reading data for one page from the first page PG0 of the block BLj is executed. This read cycle TR is in the same sequence as the read cycle TR in the flash memory FM0 shown in FIG. One page of data DATAPG0 read from the first page PG0 of the block BLj of the flash memory FM0 in this read cycle TR is once held in the buffer 34A in the flash interface section 34.

Immediately after the above-mentioned read cycle TR in the flash memory FM0 is completed, it is held in the buffer 34A (read from the first page PG0 of the block BLj of the flash memory FM0 in the previous read cycle TR). ) One page of data DATA
Write cycle T for writing PG0 to the first page PG0 of the empty block BLh in the flash memory FM1
W is started. This write cycle TW has the same sequence as the write cycle TW in the flash memory FM1 shown in FIG.

In this embodiment, this flash memory F
A read cycle TR for reading one page of data DATAPG1 from the second page PG1 of the block BLj in the flash memory FM0 in the same manner as the timing shown in FIG. 5 simultaneously or in parallel with the write cycle TW in M1. Is executed. The data DATAPG1 for one page read from the page PG1 of the block BLi in the read cycle TR is once held in the buffer 34A in the flash interface unit 34.

As a result, when the write cycle TW for writing the data DATAPG0 for one page to the first page PG0 of the empty block BLh in the flash memory FM1 is completed, the empty block BL is stored in the buffer 34A.
This means that the data DATAPG1 to be written to the next (second) page PG1 of h is prepared. Therefore, in the flash memory FM1, it is immediately held in the buffer 34A (previous read cycle T
A write cycle TW for writing one page of data DATAPG1 read from the second page PG1 of the block BLj of the flash memory FM0 to the second page PG1 of the empty block BLh can be started by R.

Then, a read cycle TR for reading one page of data DATAPG2 from the third page PG2 of the block BLi in the flash memory FM0 is executed simultaneously or in parallel with the write cycle TW in the flash memory FM1. .

Thereafter, the same operation as described above is repeated for the subsequent pages PG2, PG3, .... However, in the flash memory FM1, k of the empty block BLh
Data DATAPG for one page in the th page PGk-1
During the period in which the write cycle TW for writing k-1 is executed, the block BLj in the flash memory FM0.
The read cycle TR for reading the data DATAPGk from the (k + 1) th page PGk to be rewritten is not performed. This is because new data DATAPGk 'from the host 14 replacing the old data DATAPGk is prepared in the buffer 34B in the controller 10.

[0770] Also, the last (16th) page PG15 of the empty block BLh in the flash memory FM1
Even when the write cycle TW for writing one page of data DATAPG15 is executed in the flash memory F
In M0, since all data has already been read from all pages of the movement source, the read cycle TR is unnecessary.

After the above data rewriting processing is completed, as post-processing, all the data in the block BLj of the flash memory FM0 which is the data transfer source (old) block in this rewriting is erased all together. For this block erase, the controller 10 issues a predetermined block erase command and an address designating the block BLj at a predetermined timing to the flash memory FM.
Give to 0. Then, in response to this, the flash
A block erase operation is executed for the block BLj in the memory FM0.

Further, as post-processing associated with the above-mentioned data rewriting, the address conversion table 28A and the empty block table 2 are set in the flash table control unit 28.
8B is updated by a predetermined operation.

In updating the address conversion table 28A,
Logical block address [A
D] As a physical block address corresponding to LBA, BLj,
The physical address designating the block BLj in the flash memory FM0 is deleted from the table 28A, and the physical address designating the block BLh in the flash memory FM1 is registered in the table 28A instead.

In the empty block table 28B, the physical address indicating the block BLh in the flash memory FM1 is erased from the table 28B as an empty block that does not currently contain data, and instead the block BLj in the flash memory FM0. Is registered in the table 28B.

As described above, in the data rewriting of this embodiment, as shown in FIG. 8A, the flash memory F
During the write cycle TW in M1, the read cycle TR in the flash memory FM0 is masked simultaneously or in parallel. Therefore, the total rewrite processing time is the value (16TW) obtained by multiplying the write cycle TW by the number of repetitions (the number corresponding to the total number of pages PG0 to PG15 in one block: 16 times) and the first read cycle TR. Time (16 TW +
TR).

In this respect, if the same data rewriting processing is performed in the conventional system, as shown in FIG. 8B, the block BL of the flash memory FM0 of the movement source is shown.
Read cycle T for reading one page of data from j
R and the write cycle TW for writing the read one page of data to the empty block BLh of the destination flash memory FM1 are alternately (timely serially) repeated. However, the read cycle TR for reading one page of old data from the page PGk of the block BLj in the flash memory FM0 to be rewritten is unnecessary. Therefore, the total processing time is 16TW + 15TR.

As described above, according to this embodiment, it is possible to shorten (save) the time corresponding to about 14 TR in the data rewriting process as compared with the conventional case. This also significantly reduces the data write time seen by the host 14 and greatly improves the performance of the flash disk system.

In the above-described embodiment, the read (output) enable control line XFR is individually or independently provided between the controller 10 and each of the flash memories FM0 to FMn.
E0 _- ~XFREn _- because they provided, the controller 10
Is capable of fetching data from any flash memory FMi at any time (without depending on the states of other flash memories).

Therefore, in the above example, the read command CMR and the read address A are stored in the flash memory FM0.
After DR is supplied, even if the write busy time tWB in the flash memory FM1 ends before the read cycle TR ends in the flash memory FM0, the controller 10 writes the flash memory FM1 after the write. Flash memory FM regardless of status
The read data DATAR can be fetched from 0 via the buses FD0 to FD7. Therefore, each flash
The method of the present invention can be implemented even if the write busy time tWB in the memory FMi is relatively short or the read busy time tRB is relatively long.

However, as shown in FIG. 5, the write busy time tWB is significantly longer than the read busy time tRB in each flash memory, and the write busy time tWB is different during the write busy time twB in a certain flash memory FMi. Read cycle TR in the flash memory FMe of
Is when it can be completed reliably, the one common lead between the controller 10 and each flash memory FM0 to FMn (output) enable control line XFRE _- it is also possible to dispense with.

Further, in the above-mentioned embodiment, since the individual or independent busy lines XFBSY0 _-to- n _- are provided between the controller 10 and each of the flash memories FM0 to FMn, the controller 10 needs to write the individual flash memory. -The start and end of the busy state in the memory FMi can be immediately known. So, for example, the example above (Fig. 5)
In the controller 10, the flash memory F
While the M1 is in the write busy state (XFBSY1 _-
There While in the active state), it and a separate busy signal that the read busy time tRB is completed in the flash memories FM0 XFBSY0 _- can immediately know through, immediately the reading data from the flash memories FM0 You can start importing.

[0890] However, the controller 10, a busy signal XFBSY0 from the flash memory FM0 _- even without receiving a status register read command CMC
Is issued to the flash memory FM0 and the required status bit is read, it is possible to know the state of the memory FM0. Therefore, the controller 10
The common busy signal line XFBSY of one between each flash memory FM0 to FMn _- it is also possible to dispense with.

Also, the configuration of the flash disk system in the above embodiment, particularly the flash memory FM
The internal configuration and the internal configuration of the controller 10 are examples, and the present invention can be applied to any memory system in which a plurality of flash memories are connected to one controller or a computer via a common bus.

[0910]

As described above, according to the memory writing / reading method or the memory control device of the present invention, in the memory system in which a plurality of flash memories are connected on the same bus, the memory control device is Since the data can be read from any other flash memory while writing the data to any given flash memory, the processing time can be shortened and the system performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a flash disk system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration inside a controller in the embodiment.

FIG. 3 is a diagram showing a partition format of a storage area in a flash memory.

FIG. 4 shows an example of the internal configuration of a flash memory according to an embodiment.

FIG. 5 illustrates one flash memory with one in an embodiment.
FIG. 11 is a timing diagram showing an operation of executing a read cycle for reading one page of data from another flash memory, simultaneously or in parallel, while a write cycle for writing data for a page is being executed.

FIG. 6 is a block diagram showing a configuration and a function for performing address conversion and table search for an access for writing data from a host in the embodiment.

FIG. 7 is a diagram for explaining a data movement and a new data writing operation at the time of rewriting data in the embodiment.

FIG. 8 is a diagram showing the execution procedure (A) of the write cycle and the read cycle in the data rewriting processing of the embodiment in comparison with the execution procedure (B) of the write cycle and the read cycle in the conventional data rewriting processing.

[Explanation of symbols]

10 controller 12 flash disk card 14 host computer 20 main body interface 22 reset processing unit 24 address conversion unit 26 command processing unit 28 flash table control unit 28A address conversion table 28B empty block table 30 flash command generation unit 34 flash Interface section 34A, 34B Buffer FM0 to FMn Flash memory FD0 to 7 Internal (common) bus FCLE command latch enable control line FALE address latch enable control line XFWE _- Write enable control line XFCE0 _-to XFCEn _- Chip enable control line XFRE0 _- ~XFREn _- read (output) enable control line XFBSY0 _- ~XFBSYn _- busy line

Claims (4)

[Claims] 1. A memory controller connected to a plurality of flash memories simultaneously writes first data to any first flash memory via a common bus and at the same time any second flash. A memory write / read method for reading second data from a memory via the bus, wherein the memory control device writes a command to the first flash memory at a predetermined timing via the bus; A first step of providing a write address and the first data; and the first flash memory in response to the write command, the write in a state in which a signal from the outside is not accepted within a first predetermined time. A second step of writing the first data in a storage area specified by an address; and the memory control device within the first predetermined time. A third step of giving a read command and a read address to the second flash memory at a predetermined timing via the bus; and a second step of the second flash memory responding to the read command. A second step of reading the second data from the storage area designated by the read address within a predetermined time of 2 and setting the second data in the output port; and, after the elapse of the second predetermined time, the memory control device A fifth step of fetching the second data set in the output port of the second flash memory via the bus. 2. The write address specified in response to a write command, write address and first data given at a predetermined timing in a state where no external signal is received within a first predetermined time. In response to a write mode for writing the first data in a memory address and a read command and a read address given at a predetermined timing, the address is received within a second predetermined time at least shorter than the first predetermined time. In a memory control device connected to a plurality of flash memories each having a read mode for reading second data from a storage address designated by the above and setting it to an output port via a common bus, The write command, the write address, and the first address to the flash memory via the bus.
Write control means for causing the first flash memory to execute the write mode at a predetermined timing, and the second flash memory during the first predetermined time in the first flash memory. The read command and the read address are supplied to the flash memory via the bus at a predetermined timing, and after a lapse of the second predetermined time, the second command is output from the output port of the second flash memory. And a read control means for fetching the data of 1. through the bus. 3. The read control means includes an output enable control line dedicated to each flash memory for individually setting an output enable state of each of the flash memories. Memory controller. 4. The write control means and the read control means include a busy line dedicated to each flash memory for individually recognizing whether or not each of the flash memories is in a busy state. The memory control device according to claim 2, wherein: