JP2012198962A - Semiconductor memory and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read a memory block while writing another memory block, thereby improving access efficiency.SOLUTION: A semiconductor memory comprises a plurality of memory blocks having a plurality of memory areas which hold, for each bit, a plurality of bits of write data and the parity data of the write data. In response to a write command, the write data and the parity data are sequentially written to the memory area of a write memory block being one of the memory blocks. In response to a read command, data is read from a memory area corresponding to a data line to which the write data and the parity data are not supplied in one of the memory blocks other than a write memory block, and data that cannot be read due to write operation is reproduced. Thus, read operation can be executed in parallel with the write operation.

Description

  The present invention relates to a semiconductor memory having a plurality of memory blocks and a system in which the semiconductor memory is mounted.

  A semiconductor memory such as a flash memory stores data by changing a threshold voltage of a cell transistor of a nonvolatile memory cell by a write operation. In this type of semiconductor memory, since the write operation includes a program operation and a program verify operation, the time required for the write operation is longer than the time required for the read operation. Since the read operation cannot be executed during the write operation, the data read efficiency of the semiconductor memory is reduced by the write operation. In view of this, a semiconductor memory has been proposed in which data lines for writing and reading are connected to a plurality of memory blocks so that a reading operation can be executed during the writing operation (see, for example, Patent Documents 1 and 2). In addition, a multiplexer is provided to selectively connect the data lines of the two memory blocks to the write and read circuits, and the read operation of another memory block is executed while the write operation of one memory block is being executed. A semiconductor memory that can be used has been proposed (see, for example, Patent Document 3).

JP 2007-207425 A JP 2006-252747 A Special table 2000-509871 gazette

  However, in a semiconductor memory having a plurality of memory blocks and performing a write operation and a read operation using a common data line, one memory block is read while another memory block is being read. The access efficiency cannot be improved.

  An object of the present invention is to improve the access efficiency by executing a read operation of another memory block during a write operation of one memory block.

  In one embodiment of the present invention, a semiconductor memory includes a plurality of memory blocks including a plurality of memory areas including memory cells that hold a plurality of bits of write data and parity data of the write data for each bit, and write data and parity data. A plurality of data lines corresponding to each bit, a first write switch and a second write switch connected in series between each memory area and each data line corresponding to each data line, and each data line In response to a write command, a first read switch and a second read switch connected in series between each memory region and each data line, and write data and parity data in a write memory block that is one of the memory blocks Write data and parity data in parallel. An input data control unit for executing an input operation for sequentially supplying data to the corresponding data lines, and when the input operation is executed, the first write switch corresponding to the write memory block is turned on, and the write data and parity data are A first switch operation for sequentially turning on a second write switch corresponding to a write data line that is a data line that is sequentially supplied is executed, and in response to a read command, a read that is one of the memory blocks excluding the write memory block The first read switch corresponding to the memory block is turned on, and data is transferred from the memory area corresponding to the read data line to which the write data and parity data are not supplied to the data line in the memory area of the read memory block. Corresponds to the read data line to read A second switch operation for turning on the second read switch in parallel with the first switch operation and a switch controller that executes.

  In a semiconductor memory having a plurality of memory blocks connected to a data line common to a write operation and a read operation, a read operation of another block can be executed during the write operation of one memory block, and access efficiency can be improved.

1 illustrates an example of a semiconductor memory in one embodiment. 2 shows an example of the operation of the semiconductor memory shown in FIG. 2 shows an example of the operation of the semiconductor memory shown in FIG. 2 shows an example of the operation of the semiconductor memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. 6 shows an example of the memory core shown in FIG. 7 shows an example of the memory cell array, sector switch, read switch, write switch, and column switch shown in FIG. 6 shows an example of the amplifier shown in FIG. 6 shows an example of the address control unit shown in FIG. 6 shows an example of assignment of address signals received at the address terminals shown in FIG. 6 shows examples of the address predecoder, word decoder, and sector selection control circuit shown in FIG. An example of the row address selector and the column address selector shown in FIG. 11 is shown. An example of the sector selection control circuit shown in FIG. 11 is shown. 6 shows an example of the column control circuit shown in FIG. 6 shows an example of the input data control unit shown in FIG. An example of the shift register shown in FIG. 15 is shown. An example of the write bit selector shown in FIG. 15 is shown. 6 shows an example of command input of the semiconductor memory shown in FIG. 6 shows an example of a sequence of read operation, write operation and erase operation of the semiconductor memory shown in FIG. 8 shows an example of threshold voltage distribution of the cell transistor shown in FIG. 6 shows examples of signal line voltages in the read operation, write operation, and erase operation of the semiconductor memory shown in FIG. 6 shows an example of voltages applied to the cell transistors in the read operation, write operation and erase operation of the semiconductor memory shown in FIG. 6 shows an example of the operation of the input data control unit during the write operation of the semiconductor memory shown in FIG. 6 shows an example of a write operation of the semiconductor memory shown in FIG. 6 shows an example of the state of the memory core in the write operation of the semiconductor memory shown in FIG. 6 shows an example of the operation of the input data control unit during the erase operation of the semiconductor memory shown in FIG. 6 shows an example of the operation of the input data control unit during the erase operation of the semiconductor memory shown in FIG. 6 shows an example of the operation of the input data control unit during the erase operation of the semiconductor memory shown in FIG. 6 shows an example of the operation of the input data control unit during the erase operation of the semiconductor memory shown in FIG. 6 shows an example of an erase operation of the semiconductor memory shown in FIG. 6 shows an example of an erase operation of the semiconductor memory shown in FIG. 6 shows an example of the state of the memory core in the erasing operation of the semiconductor memory shown in FIG. 6 shows another example of the erasing operation of the semiconductor memory shown in FIG. The example of the address control part in another embodiment is shown. The example of the semiconductor memory in another embodiment is shown. The example of the input data control part shown in FIG. 35 is shown. FIG. 37 shows an example of the shift register shown in FIG. 36. FIG. 36 shows an example of the erase operation of the semiconductor memory shown in FIG. 36 shows an example of the erase operation of the semiconductor memory shown in FIG. The example of the memory core in another embodiment is shown. An example of a system in which the above-described semiconductor memory is mounted is shown. 4 illustrates an example of a semiconductor memory in another embodiment 43 shows an example of the input data control unit shown in FIG. An example of a system in which the above-described semiconductor memory is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “/” at the beginning or a signal with “B” at the end indicates negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor memory MEM in one embodiment. For example, the semiconductor memory MEM is a non-volatile semiconductor memory such as a flash memory. The semiconductor memory MEM includes a memory block MBLK (MBLK0, MBLK1), a switch unit SW (SW0, SW1) corresponding to each memory block MBLK, a switch control unit SWCNT, and an input data control unit IDCNT. The semiconductor memory MEM is not limited to a flash memory, and may be a nonvolatile semiconductor memory such as an EEPROM, FRAM, MRAM, or ReRAM. Furthermore, the semiconductor memory MEM may be a volatile semiconductor memory such as DRAM or SRAM.

  Each memory block MBLK has memory areas I / O (I / O0, I / O1, I / OP) that hold write data DW (DW0, DW1) and parity data DWP of the write data DW, respectively. Each memory area I / O has a memory cell MC connected to a data line DT (DT0, DT1, DTP) via a corresponding switch unit SW.

  The number of memory cells MC formed in each memory area I / O may be singular or plural. The number of memory blocks MBLK may be more than two. The number of memory areas I / O may be more than three. That is, the number of bits of the write data DW may be greater than 2 bits, and the number of bits of the parity data DWP may be greater than 1 bit. When the parity data DWP is 1 bit, the parity data DWP is generated according to the rule of even parity or odd parity.

  Each switch unit SW has write switches WSW1 and WSW2 and read switches RSW1 and RSW2 for each corresponding memory area I / O. The write switches WSW1-2 are connected in series between the corresponding memory area I / O and the data line DT. The read switch RSW1-2 is connected in series between the corresponding memory area I / O and the data line DT. That is, the write switch WSW1-2 and the read switch RSW1-2 are arranged in parallel between the memory cell and the data line DT.

  The write switch WSW1 receives a write selection signal SWR (SWR0 or SWR1) and turns on for each memory block MBLK during a write operation executed in response to the write command WRC. The write switch WSW2 receives a write control signal IOWR (IOWR0, IOWR1 or IOWRP) during a write operation and is turned on for each memory area I / O.

  The read switch RSW1 is turned on for each memory block MBLK in response to the read selection signal SRD (SRD0 or SRD1) during a read operation executed in response to the read command RDC. The read switch RSW2 receives a read control signal IORD (IORD0, IORD1, or IORDP) during a read operation and is turned on for each memory area I / O.

  In response to the write command WRC, the input data control unit IDCNT sequentially converts the parallel write data DW0-1 and parity data DWP to the memory area I / O of the write memory block that is one of the memory blocks MBLK bit by bit. In order to write data, an input operation for sequentially supplying the corresponding data lines DT is executed. That is, the input data control unit IDCNT has a function of a parallel / serial conversion circuit that converts parallel data into serial data.

  When the input operation is executed in response to the write command WRC, the switch control unit SWCNT outputs a write selection signal SWR0 or SWR1 to turn on the write switch WSW1 corresponding to the write memory block. In addition, when the input operation is executed in response to the write command WRC, the switch control unit SWCNT sets the write switches WSW2 corresponding to the memory areas I / O0-1 and I / OP of the write memory block one by one. In order to turn on sequentially, write control signals IOWR0-1 and IOWRP are output in order. In the following description, an operation in which the write switch SW1 is turned on and the write switches WSW2 are sequentially turned on one by one is referred to as a first switch operation.

  In response to the read command RDC, the switch control unit SWCNT outputs the read selection signal SRD0 or SRD1 to turn on the read switch RSW1 corresponding to the read memory block that is one of the memory blocks MBLK excluding the write memory block. To do. Further, the switch control unit SWCNT sets a read switch corresponding to the data line DT to which the write data DW0-1 or the parity data DWP is not supplied among the memory areas I / O0-1 and I / OP of the read memory block MBLK. In order to turn on RSW2, read control signals IORD0-1 and IORDP are output. In the following description, an operation in which the read switches RSW1 and RSW2 are turned on is referred to as a second switch operation. The second switch operation can be executed in parallel with the first switch operation.

  2 to 4 show an example in which the read operation is executed in parallel during the write operation in the semiconductor memory MEM shown in FIG. That is, FIGS. 2 to 4 show examples in which the second switch operation is executed in parallel with the input operation and the first switch operation. A black rectangle indicates a switch that is on, and a white rectangle indicates a switch that is off. A thick solid line indicates a transmission path of input data ID (ID0, ID1, IDP) written in the memory cell MC or a transmission path of output data OD (OD0, OD1, ODP) read from the memory cell MC.

  For example, in response to one write command WRC, the write operation is sequentially executed bit by bit with respect to the memory areas I / O0, I / O1, and I / OP of the memory block MBLK0. In the read operation, the memory area I corresponding to the data line DT that is not used for transmission of write data among the memory areas I / O0, I / O1, and I / OP of the memory block MBLK1 is read every three read commands RDC. Executed at / O. As described above, in FIGS. 2 to 4, the memory block MBLK0 operates as a write memory block, and the memory block MBLK1 operates as a read memory block. The selection of the memory block MBLK is performed according to an address signal supplied to the semiconductor memory MEM, for example.

  First, in response to the write command WRC, the switch control unit SWCNT outputs a write selection signal SWR0 in order to turn on the write switch WSW1 corresponding to the write memory block MBLK0. The ON state of the write switch WSW1 corresponding to the memory block MBLK0 is maintained during the operations of FIGS.

  As shown in FIG. 2, the switch control unit SWCNT outputs a write control signal IOWR0 to turn on the write switch WSW2 corresponding to the memory area I / O0. Thereby, the data line DT0 is connected to the memory cell MC of the memory area I / O0 of the memory block MBLK0. The input data control unit IDCNT receives parallel write data DW0-1 and parity data DWP in response to the write command WRC, and receives the received data as serial input data ID0, ID1, IDP to the data lines DT0-1, DTP. Supply in order. In FIG. 2, the input data ID0 is written into the memory area I / O0 of the memory block MBLK0.

  In FIG. 2, the switch control unit SWCNT receives the read command RDC after receiving the write command WRC. In response to the read command RDC, the switch control unit SWCNT outputs a read selection signal SRD1 to turn on the read switch RSW1 corresponding to the read memory block MBLK1. In addition, the switch control unit SWCNT outputs read control signals IORD1 and IORDP to turn on the read switches RSW2 corresponding to the memory areas I / O1 and I / OP except the memory area I / O0 performing the write operation. Output. Thus, the data lines DT1 and DTP are connected to the memory cells MC of the memory areas I / O1 and I / OP of the memory block MBLK1, respectively. In FIG. 2, the output data OD1 and ODP are read from the memory areas I / O1 and I / OP of the memory block MBLK1 to the data lines DT1 and DTP. After the output data OD1 and ODP are read, the read switch RSW1 corresponding to the memory block MBLK1 and the read switch RSW2 corresponding to the memory areas I / O1 and I / OP are turned off.

  For example, the semiconductor memory MEM reproduces data held in the memory cell MC in the memory area I / O0 of the memory block MBLK1 based on the read output data OD1 and ODP. Then, the semiconductor memory MEM outputs the reproduced data to the outside as read data together with the output data OD1. Alternatively, the semiconductor memory MEM outputs the output data OD1 and ODP to the outside. Then, the controller that controls the operation of the semiconductor memory MEM reproduces the data held in the memory cell MC in the memory area I / O0 of the memory block MBLK1 based on the output data OD1 and ODP.

  In FIG. 3, the switch control unit SWCNT outputs a write control signal IOWR1 to turn on the write switch WSW2 corresponding to the memory area I / O1. Thereby, the data line DT1 is connected to the memory cell MC of the memory area I / O1 of the memory block MBLK0. Then, the input data ID1 supplied from the input data control unit IDCNT to the data line DT1 is written into the memory area I / O1 of the memory block MBLK0.

  In response to a new read command RDC, the switch control unit SWCNT outputs a read selection signal SRD1 to turn on the read switch RSW1 corresponding to the read memory block MBLK1. Further, the switch control unit SWCNT outputs read control signals IORD0 and IORDP to turn on the read switches RSW2 corresponding to the memory areas I / O0 and I / OP except the memory area I / O1 that is executing the write operation. Output. Thereby, the data lines DT0 and DTP are connected to the memory cells MC of the memory areas I / O0 and I / OP of the memory block MBLK1, respectively.

  In FIG. 3, the output data OD0 and ODP are read from the memory areas I / O0 and I / OP of the memory block MBLK1 to the data lines DT1 and DTP. After the output data OD0 and ODP are read, the read switch RSW1 corresponding to the memory block MBLK1 and the read switch RSW2 corresponding to the memory areas I / O0 and I / OP are turned off. Thereafter, data held in the memory cell MC in the memory area I / O1 of the memory block MBLK1 is reproduced based on the output data OD0 and ODP inside or outside the semiconductor memory MEM.

  In FIG. 4, as in FIGS. 2 and 3, the read operation of the memory block MBLK1 is executed while the input data IDP is being written to the memory area I / OP of the memory block MBLK0. The switch control unit SWCNT outputs a write control signal IOWRP, a read selection signal SRD1, and read control signals IORD0 and IORD1. The write selection signal SWR0 is output from FIG.

  Then, the input data IDP is written to the memory cells MC in the memory area I / OP of the memory block MBLK0, and the output data OD0 and OD1 are read from the memory areas I / O0 and I / O1 of the memory block MBLK1. For example, read data OD0 and OD1 to be read are output to the outside of the semiconductor memory MEM without being reproduced.

  As described above, in this embodiment, the data lines that are not used while the write operation to the memory areas I / O0, I / O1, and I / OP is performed bit by bit using the data lines DT0, DT1, and DTP. Three read operations can be performed using DT. Therefore, in the semiconductor memory MEM in which the write operation and the read operation are executed using the common data line DT, the read operation of another memory block MBLK1 can be executed during the write operation of one memory block MBLK0, and the access efficiency is improved. It can be improved. In particular, it is possible to prevent the execution frequency of the read operation from decreasing even during the write operation, and it is possible to prevent the data read rate from decreasing.

  FIG. 5 shows an example of a semiconductor memory MEM in another embodiment. For example, the semiconductor memory MEM is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM operates in synchronization with the clock signal CLK, but may operate asynchronously with the clock signal CLK. Note that the withstand voltage of a transistor to which a voltage greater than the difference between the power supply voltage VDD and the ground voltage VSS is applied is designed to be higher than the withstand voltage of a normal transistor.

  The semiconductor memory MEM includes a clock buffer 10, a command decoder 12, an address buffer 14, a state machine 16, a timing controller 18, an address controller 20, address predecoders 22 and 24, an input data buffer 26, an output data buffer 28, and an output buffer. 30, a parity generation unit 32, an input data control unit 34, a data reproduction unit 36, an output data control unit 38, and a memory core 40.

  The clock buffer 10 supplies a clock signal CLK received via an external terminal to a circuit that operates in synchronization with the clock signal CLK such as the command decoder 12 and the address buffer 14. Command decoder 12 receives chip enable signal / CE, write enable signal / WE, address signal AD and input data signal DI as command signals in synchronization with clock signal CLK.

  When the command signal indicates a read command R (FIG. 23), the command decoder 12 outputs a read command signal RDC to execute a read operation. When the command signal indicates the write command W (FIG. 23), the command decoder 12 outputs the write command signal WRC to execute the write operation. When the command signal indicates the erase command E (FIG. 26), the command decoder 12 outputs an erase command signal ERSC to execute the erase operation. An example of command signal input is shown in FIG. A sequence of the read operation, the write operation, and the erase operation is shown in FIG.

  The address buffer 14 receives an address signal AD (AD0-AD14) in synchronization with the clock signal CLK, and outputs the received address signal AD to the address control unit 20. The address signal AD is not limited to 15 bits. An example of allocation of the address signal AD is shown in FIG.

  The state machine 16 receives the read command signal RDC, the write command signal WRC, and the erase command signal ERSC, and controls the operation state of the control circuit such as the timing control unit 18 in order to execute the read operation, the write operation, and the erase operation. . For this purpose, the state machine 16 outputs a control signal to the timing control unit 18 and the address control unit 20 according to the received command signal. The state machine 16 outputs a write busy signal WRBSY while executing a write operation based on the write command signal WRC. The state machine 16 outputs an erase busy signal ERSBSY while executing an erase operation based on the erase command signal ERSC.

  The timing control unit 18 reads a read control signal RCNT for executing a read operation based on a control signal from the state machine 16, a write control signal WCNT for executing a write operation, and an erase control signal for executing an erase operation. Output PERS. Each of the read control signal RCNT, the write control signal WCNT, and the erase control signal PERS is at least a 1-bit timing signal. The state machine 16 and the timing control unit 18 are operation control units that control operations of the address control unit 20, the address predecoders 22 and 24, the parity generation unit 32, the input data control unit 34, the data reproduction unit 36, and the memory core 40. Operate.

  Address control unit 20 outputs address signal AD received together with read command signal RDC and write command signal WRC as sector address signal SA, row address signal RA and column address signal CA. The sector address signal SA is an example of a block address signal for selecting one of the sectors SEC. The address control unit 20 outputs the address signal AD received together with the erase command signal ERSC as a sector address signal SA indicating the sector SEC from which data is erased. Further, in the erase operation, the address control unit 20 sequentially generates the row address signal RA and the column address signal CA when the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV shown in FIG. 19 are executed. To do.

  The address control unit 20 outputs a sector error signal SERR when receiving the read command signal RDC for the sector SEC that is executing the write operation or the erase operation. When the state machine 16 receives the sector error signal SERR, the state machine 16 invalidates the read command signal RDC and prohibits execution of a read operation in response to the read command signal RDC. As a result, it is possible to prevent the read operation from being performed repeatedly on the sector SEC during the write operation or the erase operation, and to prevent malfunction of the semiconductor memory MEM. An example of the address control unit 20 is shown in FIG.

  The address predecoder 22 has a latch circuit that holds the row address signal RA and the column address signal CA used for the read operation in response to the read control signal RCNT. The address predecoder 22 decodes the held address signals RA and CA, and generates a predecoded address signal to be supplied to the memory core 40. Address predecoder 22 includes a read decode circuit that holds and decodes row address signal RA received together with the read command, and generates a predecode address signal as a read address decode signal.

  The address predecoder 24 has a latch circuit that holds the row address signal RA and the column address signal CA used for the write operation and the erase operation in response to the write control signal WCNT and the erase control signal ECNT. The address predecoder 24 decodes the held address signals RA and CA, and generates a predecoded address signal to be supplied to the memory core 40. Address predecoder 24 includes a write decode circuit that holds and decodes row address signal RA received together with the write command, and generates a predecode address signal as a write decode address signal. As described above, the semiconductor memory MEM includes the address predecoder 22 for read operation and the address predecoder 24 for write operation and erase operation. An example of the address predecoders 22 and 24 is shown in FIG.

  The input data buffer 26 receives write data supplied to the data input terminals DI (DI0-7) in response to the write command signal WRC, and outputs the received write data to the write data lines DW0-7. The output data buffer 28 outputs the read data received from the output data control unit 38 during the read operation to the data output terminal DO (DO0-7). The data input terminal DI and the data output terminal DO are not limited to 8 bits. The number of bits of the data input terminal DI and the data output terminal DO may be different. For example, the number of bits of the data output terminal DO may be four times the number of bits of the data input terminal DI.

  The output buffer 30 outputs the write busy signal WRBSY, the erase busy signal EBSY, and the sector error signal SERR as flag signals to the flag terminals FLG0-2. The semiconductor memory of this embodiment can read data from another sector SEC during the write operation or erase operation of one sector SEC. However, the read operation for the sector SEC during the write operation or the erase operation cannot be executed. For this reason, the semiconductor memory MEM generates a sector error signal SERR generated when a read command is received for the sector SEC during a write operation or an erase operation, for example, during the next clock cycle that receives the read command. Output as FLG2.

  The parity generation unit 32 generates parity data DWP of the write data DW (DW0-7) received at the data input terminal DI in response to the write command signal WRC. For example, the parity generation unit 32 obtains the bit value of the parity data DWP according to the even parity rule. For this reason, when the number of bits of the logic 1 write data DW is an even number, the logic 0 parity data DWP is generated. When the number of bits of the logic 1 write data DW is an odd number, the logic 1 parity data DWP is generated. In the following description, the parity data DWP is also referred to as write data DWP.

  The input data control unit 34 converts the parallel write data DW (DW0-7, DWP) into serial input data ID (ID0-7, IDP) during the program operation PGM during the write operation and during the preprogram operation PPGM during the erase operation. ) In order to the amplifier AMP. The input data ID0-7 and IDP correspond to the write data DW0-7 and DWP, respectively. In the program operation PGM, write data DW and DWP of logic 0 are sequentially output as input data ID. Further, the input data control unit 34 outputs a write control signal IOWR (any of IOWR0-8) corresponding to the bit of the input data ID supplied to the amplifier AMP, and a read control signal IORD not corresponding to the bit of the input data ID. (8 of IORD0-8) is output.

  For example, when the input data control unit 34 outputs the input data ID0 (logic 0) to the amplifier AMP, it sets the write control signal IOWR0 and the read control signal IORD1-8 to the activation level, and sets the write control signal IOWR1-8 and Read control signal IORD0 is set to an inactive level. The write control signal IOWR (any of IOWR0-8) is activated when the program operation PGM, program verify operation PGMV, preprogram operation PPGM, and preprogram verify operation PPGMV of the memory core 40 are executed.

  Write control signals IOWR0-8 are generated to turn on the write switches WSW2 (FIG. 6) of nine memory areas I / O (I / O0-I / O8). Nine memory areas I / O0-I / O8 hold input data ID0-7 and IDP, respectively. The write control signals IOWR0-8 are supplied to the data reproduction unit 36 for reproducing data that cannot be read by the write operation or the erase operation. Read control signals IORD0-8 are generated to turn on the read switches RSW2 (FIG. 6) of the nine memory areas I / O0-I / O8. Examples of the input data control unit 34 are shown in FIGS.

  The data reproduction unit 36 receives the output data OD (OD0-7, ODP) read from the memory core 40 in response to the read command signal RDC, and reproduces the read data DR (DR0-7) output to the data output terminal DO. To do. The output data ODP is parity bit data (parity output data). The data reproduction unit 36 uses the output data OD excluding the output data OD (either OD0-7 or ODP) corresponding to the activated write control signal IOWR (any of IOWR0-8) to read data Play DR0-7.

  For example, when the write control signal IOWR2 is activated, the data reproducing unit 36 reproduces the logic of the read data DR2 using the output data OD0-1, OD3-7, and ODP. Specifically, when the number of logic 1s of the output data OD0-1, OD3-7, and ODP is an even number, the read data DR2 is set to logic 0. When the number of logic 1s of the output data OD0-1, OD3-7, and ODP is an odd number, the read data DR2 is set to logic 1. When all the write control signals IOWR0-8 are inactivated, the data reproducing unit 36 does not use the parity output data ODP and outputs the output data OD0-7 as the read data DR0-7.

  The output data control unit 38 receives the read data DR0-7 reproduced in response to the read command signal RDC, and outputs the received read data DR0-7 to the output data buffer 28.

  The memory core 40 includes a plurality of sectors SEC (SEC0-31) and a column control circuit YSELCNT, a column switch YSW, an amplifier control circuit AMPCNT, and an amplifier AMP that are common to the sectors SEC0-31. The number of sectors SEC is not limited to 32. Examples of the memory core 40 are shown in FIGS.

  Each sector SEC (SEC0-31) includes a word decoder WDEC, a sector selection control circuit SSELCNT, a sector switch SSW, read switches RSW1-RSW2, write switches WSW1-WSW2, and a memory cell array ARY. The word decoder WDEC, sector selection control circuit SSELCNT, column control circuit YSELCNT, and amplifier control circuit AMPCNT operate in synchronization with a control signal (timing signal) from the timing control unit 18. Sectors SEC0-31 are an example of a memory block and correspond to the memory block MBLK shown in FIG.

  Each sector SEC has the same configuration except that the sector address SA is different. In each of the read operation, the write operation, and the erase operation, one of the sectors SEC is selected by the row predecode address signal from the address predecoders 22 and 24. Further, while one sector SEC is executing a write operation or an erase operation, another sector SEC can execute a read operation.

  The word decoder WDEC in the selected sector SEC receives the address predecoder 22 in the read operation RD, program operation PGM, program verify operation PGMV, preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV shown in FIG. , 24, one of the word lines WL indicated by the row predecode address signal is selected. In the internal erase operation ERS shown in FIG. 19, the word decoder WDEC in the selected sector SEC selects all the word lines WL in the sector SEC.

  The sector selection control circuit SSELCNT in the selected sector SEC has address predecoders 22 and 24 in the read operation RD, program operation PGM, program verify operation PGMV, preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV. One of the sector selection signals SSEL is activated to turn on one of the sector switches SSW indicated by the column predecode address signal from.

  Further, the sector selection control circuit SSELCNT in the selected sector SEC operates as a switch control unit that activates the read selection signal SRD to turn on the read switch RSW1 in the read operation RD. The sector selection control circuit SSELCNT in the selected sector SEC selects the write to turn on the write switch WSW1 in the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERS. It operates as a switch control unit that activates the signal SWR.

  The column control circuit YSELCNT receives the column predecode address signal from the address predecoders 22 and 24 in the read operation RD, the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV. In order to turn on one of the column switches YSW shown, one of the column selection signals YSEL is activated. When the column switch YSW is turned on, the global bit line GBL is connected to the amplifier AMP.

  The amplifier control circuit AMPCNT responds to a control signal (timing signal) from the timing controller 18 in the read operation RD, the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV. Then, a control signal for controlling the operation of the amplifier AMP is output.

  FIG. 6 shows an example of the memory core 40 shown in FIG. The memory cell array ARY of each sector SEC0-31 is partitioned into nine memory areas I / O0-I / O8. The memory area I / O0-7 holds write data DW0-7 supplied to the input data terminals DI0-7, respectively. The memory area I / O 8 holds parity data DWP generated by the parity generator 32 shown in FIG.

  The memory cell array ARY has a plurality of nonvolatile memory cells MC arranged in a matrix. The memory cells MC arranged in the horizontal direction in FIG. 6 are connected to a common word line WL. The memory cells MC arranged in the vertical direction in FIG. 6 are connected to a common local bit line LBL. In FIG. 6, one word line WL and one local bit line LBL connected to one memory cell MC in each memory area I / O0-8 in the sector SEC0 are illustrated.

  Black dots indicate that intersecting wirings are connected, black circles indicate switches that are on, and white circles indicate switches that are off. FIG. 6 shows an example in which a read operation for reading data from the memory areas I / O0-1 and I / O3-8 of the sector SEC31 is executed during a write operation for writing data to the memory area I / O2 of the sector SEC0. ing.

  In each memory area I / O0-8, global bit lines GBL (GBL0-GBL8) shown on the lower side of the figure are connected to four global bit lines GBL <0> -GBL <3> via four column switches YSW. (For example, GBL0 <0> -GLB0 <3>). Global bit lines GBL0 to GBL8 are examples of data lines corresponding to the bits of write data DW0-7 and parity data DWP, and correspond to data line DT shown in FIG.

  The column switch YSW is common to the sectors SEC0-31 and is turned on / off for each memory area I / O0-8. In this example, the global bit line GBL2 in the memory area I / O2 is connected to the global bit line GBL2 <1>. The global bit lines GBL0-1 and GBL3-8 of the other memory areas I / O0-1 and I / O3-8 are global bit lines GBL0 <0> -GBL1 <0>, GBL3 <0> -GBL8 <0>. Connected to.

  Each global bit line GBL <0> -GBL <3> has four local bit lines LBL via the write switch WSW1-2 (or read switch RSW1-2) and four sector switches SSW of the selected sector SEC. Connected to.

  The write switch WSW2 receives the write control signal IOWR0-8 and is controlled to be turned on / off in common to the sectors SEC0-31 for each memory area I / O0-8. The write switch WSW1 is controlled to be turned on / off in common to the memory area I / O0-8 for each sector SEC0-31. The read switch RSW2 receives the read control signal IORD0-8 and is controlled to be turned on / off in common to the sectors SEC0-31 for each memory area I / O0-8. The read switch RSW1 is controlled to be turned on / off in common with the memory area I / O0-8 for each sector SEC0-31. The sector switch SSW is controlled to be turned on / off in common with the memory area I / O0-8 for each sector SEC0-31.

  In this example, the global bit line GBL2 <1> is connected to the local bit line LBL of the memory area I / O2 of the sector SEC0 via the write switch WSW1-2 and the sector switch SSW of the sector SEC0. The global bit lines GBL0 <0> -GBL1 <0>, GBL3 <0> -GBL8 <0> are connected to the memory area I / O0-1 of the sector SEC31 via the read switch RSW1-2 and the sector switch SSW of the sector SEC31. , I / O 3-8 connected to the local bit line LBL.

  As described above, the write operation is performed on the memory area I / O of the sector SEC in which both the write switches WSW1-2 connected in series are turned on. The read operation is performed on the memory area I / O of the sector SEC in which both the read switches RSW1-2 connected in series are turned on. In other words, the read operation is performed on the memory area I / O where the write operation is not performed. In the memory area I / O where the write operation and the read operation are not executed, the write switch WSW1-2 is not turned on at the same time and the read switch RSW1-2 is not turned on at the same time.

  Thus, in the write operation, the input data ID2 is written to the memory cell MC connected to one of the 16 local bit lines LBL in the memory area I / O2. In the read operation, output data OD0-OD1, OD3-OD7, ODP is connected to one of 16 local bit lines LBL in each memory area I / O0-I / O1, I / O3-I / O8. Read from the memory cell MC.

  FIG. 7 shows an example of the memory cell array ARY, sector switch SSW, read switch RSW1-2, write switch WSW1-2, and column switch YSW shown in FIG. FIG. 7 shows the memory area I / O0 of the sector SEC31 shown in FIG. 6 as an example. “31” added to the word line WL, the sector selection signal SSEL, the read selection signal SRD, and the write selection signal SWR indicates the number of the sector SEC. “0” added to the local bit line LBL, the global bit line GBL, the column selection signal YSEL, the read control signal IORD, and the write control signal IOWR indicates the number of the memory area I / O. The numbers enclosed in “<>” indicate the number of each signal line. For example, the memory cell array ARY of each sector SEC0-31 has 64 word lines WL0-WL63.

  Each memory cell MC has a real cell transistor CT including a floating gate FG and a control gate CG. The drain of the cell transistor CT is connected to the local bit line LBL. The source of the cell transistor CT is connected to a source line SL wired along the word line WL. The voltage of the source line SL is set by, for example, a source line driver arranged on the right side of the memory cell array ARY in FIG. An example of the voltage applied to the cell transistor CT is shown in FIG. For example, the sector switch SSW, the read switch RSW1-2, the write switch WSW1-2, and the column switch YSW are formed by n-channel MOS transistors.

  FIG. 8 shows an example of the amplifier AMP shown in FIG. Since the amplifiers AMP connected to the global bit lines GBL0 to GBL8 are the same circuit, the amplifier AMP connected to the global bit line GBL0 will be described.

  The amplifier AMP includes a write amplifier WA, a precharge circuit PRE, and a read amplifier RA. The write amplifier WA operates to set the global bit line GBL0 to the high level voltage VD5 in the program operation PGM and the preprogram operation PPGM that receive the input data ID0 of logic 0. The precharge circuit PRE operates to temporarily precharge the global bit line GBL0 to a high level before the read operation RD, program verify operation PGMV, preprogram verify operation PPGMV, and erase verify operation ERSV are started. . The read amplifier RA operates to latch the logic of the read data read from the memory cell MC to the global bit line GBL0 in the read operation RD, the program verify operation PGMV, the pre-program verify operation PPGMV, and the erase verify operation ERSV.

  The write amplifier WA has a level shifter LSFT, a logic gate, a p-channel MOS transistor P1, and an n-channel MOS transistor N1. The level shifter LSFT converts the high level of the input data ID0 into a voltage VD5 higher than the power supply voltage VDD in order to prevent a leakage current when the p-channel MOS transistor P1 is turned off. The inverter and the NOR gate arranged between the level shifter LSFT and the transistors P1 and N1 operate by receiving the high level voltage VD5 at the power supply terminal.

  The p-channel MOS transistor P1 is turned on when receiving the low level program signal PGM0B, and sets the global bit line GBL0 to the high level VD5. The n-channel MOS transistor N1 is turned on when receiving the high level inhibition signal DIS0, and sets the global bit line GBL0 to the low level VSS (ground voltage). Program signal PGM0B is activated to a low level when input data ID0 is at a low level (logic 0). The inhibit signal DIS0 is activated to a high level when the input data ID0 is at a high level (logic 1), the precharge signal BLPRE0 is at a low level, and the read latch signal RLT0B is at a low level. The precharge signals BLPRE0 to BLPRE8 are temporarily set to the high level at the start of the read operation and the verify operation under the control of the timing control unit 18. The read latch signals RLT0B to RLT8B are temporarily high in order to latch the logic of data read from the memory cells MC to the global bit lines GBL0 to GBL8 during the read operation and the verify operation under the control of the timing control unit 18. Set to level. Here, the verify operation is a program verify operation PGMV, a preprogram verify operation PPGMV, and an erase verify operation ERSV, which will be described later.

  The precharge circuit PRE receives a precharge signal PRE0 having the same logic level as the precharge signal BLPRE0 at its gate, an n channel MOS transistor N2 having a drain connected to the power supply line VDD and a source connected to the global bit line GBL0. Have. The precharge circuit PRE precharges the global bit line GBL0 to the high level VDD when the precharge signal BLPRE0 is at the high level.

  The read amplifier RA has an n-channel MOS transistor N3, a latch circuit LT, and a verify selector VSEL. The n-channel MOS transistor N3 is turned on when the read amplifier latch signal RALT0B is at a high level, and connects the global bit line GBL0 to the latch circuit LT. The latch circuit LT latches the logical level read to the global bit line GBL0 in synchronization with the falling edge of the read amplifier latch signal RALT0B.

  The verify selector VSEL outputs the read data output from the latch circuit LT to the verify output data line OVD0 when the verify signal VRFY0 is at a high level. The verify selector VSEL outputs read data output from the latch circuit LT to the output data line OD0 when the verify signal VRFY0 is at a low level. The precharge signals BLPRE0 to BLPRE8, the read amplifier latch signals RALT0B to RALT8B, and the verify signals VRFY0 to VFRY8 are generated by the amplifier control circuit AMPCNT in response to the timing signal from the timing control unit 18.

  FIG. 9 shows an example of the address control unit 20 shown in FIG. The address control unit 20 includes a column address counter CACOUNT, a row address counter RACOUNT, a column address selector CASEL1, a row address selector RASEL1, and a read sector determination circuit RSJDG. Column address counter CACOUNT and row address counter RACOUNT operate in preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV during the erase operation.

  Column address counter CACOUNT counts in synchronization with address clock signal ACLK, and sequentially generates internal column address signals ICA corresponding to address signals AD3-AD0. The row address counter RACOUNT counts every time the internal column address signal ICA makes a round, and sequentially generates internal row address signals IRA corresponding to the address signals AD9 to AD4. For example, the address clock signal ACLK is generated by the timing control unit 18 every time the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM in the memory area I / O0-I / O8 is executed once. It is generated every time the erase verify operation ERSV of / O0-I / O8 is executed once.

  In this embodiment, the row address counter RACOUNT counts every time the column address counter CACOUNT makes a round, so that the switching frequency of the word line WL selected by the row address signal RA can be lowered. In particular, in the preprogram operation PPGM, a high voltage (VPGM; for example, 9 V) is applied to the word line WL. Therefore, by reducing the switching frequency of the word lines WL, the charge / discharge current of the word lines WL can be reduced, and the power consumption of the semiconductor memory MEM can be reduced.

  Column address counter CACOUNT and row address counter RACOUNT are reset before the first pair of preprogram operation PPGM and preprogram verify operation PPGMV is started in the erase operation, and the counter value is set to zero. The column address counter CACOUNT and the row address counter RACOUNT are reset before the erase verify operation ERSV is started in the erase operation. Therefore, the row address counter RACOUNT counts from zero to the maximum value every time the internal column address signal ICA changes from the maximum value ICAmax to zero.

  Column address selector CASEL1 outputs internal column address signal ICA as column address signal CA in preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV. Column address selector CASEL1 outputs external column address signal ECA received at address terminals AD3-0 as column address signal CA when preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV are not executed.

  The row address selector RASEL1 outputs the internal row address signal IRA as the row address signal RA in the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV. The row address selector RASEL1 outputs the external row address signal ERA received at the address terminal AD9-4 as the row address signal RA when the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV are not executed.

  The read sector determination circuit RSJDG includes a write sector address latch WSALT, a read sector address latch RSALT, and an address comparator ADCMP. The write sector address latch WSALT latches the value of the sector address signal SA (address signal AD14-10) indicating the sector SEC to be accessed in synchronization with the write command signal WRC or the erase command signal ERSC. The read sector address latch RSALT latches the value of the sector address signal SA (address signal AD14-10) indicating the sector SEC to be accessed in synchronization with the read command signal RDC. The address comparator ADCMP outputs a sector error signal SERR when the values of the sector addresses SA latched in the write sector address latch WSALT and the read sector address latch RSALT are the same.

  FIG. 10 shows an example of allocation of address signals received at the address terminal AD shown in FIG. Address signals AD14-AD10 are used as sector address signals SA to select one of 32 sectors SEC0-31. Each sector SEC is selected using a sector predecode signal generated by predecoding address signals AD14-AD13 (SEC (B)) and AD12-AD10 (SEC (A)).

  Address signals AD9-AD4 are used as row address signal RA to select one of 64 word lines WL0-63 in sector SEC. The word line WL is selected using a row predecode signal generated by predecoding the address signals AD9-AD7 (WL (B)) and AD6-AD4 (WL (A)).

  Address signals AD3-AD0 are used as column address signals CA to select one of 16 local bit lines LBL in each memory area I / O. Address signals AD3-AD2 are used to turn on one of the four column switches YSW0-3 for each memory area I / O (that is, to generate a column selection signal YSEL). The address signals AD1-AD0 are used to turn on one of the four types of sector switches SSW0-3 in the sector SEC (that is, to generate the sector selection signal SSEL).

  FIG. 11 shows an example of the address predecoders 22 and 24, the word decoder WDEC, and the sector selection control circuit SSELCNT shown in FIG. The word decoder WDEC and the sector selection control circuit SSELCNT are circuits corresponding to the sector SEC0.

  The address predecoder 22 has an address predecoder RAPDEC and an address decoder RADEC that operate during a read operation. The address predecoder RAPDEC predecodes the sector address signal SA and generates a sector predecode address signal RSPDA for selecting the sector SEC. The address predecoder RAPDEC predecodes the row address signal RA and generates a row predecode address signal RRPDA for selecting the word line WL. The address decoder RADEC decodes the column address signal CA to generate a column decode address signal RCDA.

  A 4-bit column decode address signal RCDA generated from the column address signal CA corresponding to the address signals AD1-AD0 is supplied to the column address selector CASEL2. A 4-bit column decode address signal RCDA generated from the column address signal CA corresponding to the address signals AD3-AD2 is supplied to the column control circuit YSELCNT.

  The address predecoder 24 has an address predecoder WAPDEC and an address decoder WADEC that operate during a write operation and an erase operation. The address predecoder WAPDEC predecodes the sector address signal SA and generates a sector predecode address signal WSPDA for selecting the sector SEC. The address predecoder WAPDEC predecodes the row address signal RA and generates a row predecode address signal WRPDA for selecting the word line WL. The address decoder WADEC decodes the column address signal CA to generate a column decode address signal WCDA.

  A 4-bit column decode address signal WCDA generated from the column address signal CA corresponding to the address signals AD1-AD0 is supplied to the column address selector CASEL2. A 4-bit column decode address signal WCDA generated from the column address signal CA corresponding to the address signals AD3-AD2 is supplied to the column control circuit YSELCNT.

  In this embodiment, as shown in FIG. 10, the 2-bit address signal AD14-AD13 and the 3-bit AD12-AD10 are predecoded to select the sector SEC, and the 4-bit and 8-bit predecode addresses are selected. A signal is generated. Therefore, sector predecode address signal RSPDA and sector predecode address signal WSPDA are each 12 bits (4 bits + 8 bits). The 3-bit address signals AD9-AD7 and 3-bit AD6-AD4 are predecoded to select the word line WL, and two types of 8-bit predecoded address signals are generated. Therefore, the row predecode address signal RRPDA and the row predecode address signal WRPDA are each 16 bits (8 bits + 8 bits).

  The word decoder WDEC includes a row address selector RASEL2, power supply selection circuits WLHSEL and WLLSEL, and a word driver WDRV. The row address selector RASEL2 outputs the row predecode address signal RRPDA as the row predecode address signal RPDA when receiving the activated read sector signal RSEC. The read sector signal RSEC is generated by decoding the sector predecode address signal RSPDA by the sector activation circuit RSACT. That is, the read sector signal RSEC is activated when the read operation of the corresponding sector SEC is executed.

  The row address selector RASEL2 outputs the row predecode address signal WRPDA as the row predecode address signal RPDA when receiving the activated write sector signal WSEC. The write sector signal WSEC is generated by decoding the sector predecode address signal WSPDA by the sector activation circuit WSACT. That is, the write sector signal WSEC is activated when the program operation PGM, program verify operation PGMV, preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV of the corresponding sector SEC are executed. The row address selector RASEL2 is used to set all the word lines WL in the sector SEC to a low level (negative voltage) when receiving the erase mode signal EMD activated during the erase operation of the selected sector SEC. The row predecode address signal RPDA indicating non-selection is output. The erase mode signal EMD is generated for each sector SEC based on the control of the state machine 16, and is activated to a high level during the erase operation.

  The power supply selection circuit WLHSEL outputs a high level voltage VD5 higher than the power supply voltage VDD to the high level voltage line VWLH when receiving the read sector signal RSEC. The power supply selection circuit WLHSEL outputs a high level voltage VPGM higher than the high level voltage VD5 to the high level voltage line VWLH when receiving the write sector signal WSEC. As shown in FIG. 21, the value of the high level voltage VPGM is set according to a program operation PGM, a program verify operation PGMV, a preprogram operation PPGM, a preprogram verify operation PPGMV, and an erase verify operation ERSV.

  The power supply selection circuit WLLSEL outputs the ground voltage VSS to the low level voltage line VWLL when receiving the deactivated erase mode signal EMD. The power supply selection circuit WLLSEL outputs the negative voltage VERS to the low level voltage line VWLL when receiving the activated erase mode signal EMD.

  In the read operation RD, the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV, the word driver WDRV receives the word lines WL0 to WL63 according to the row predecode address signal RPDA. One is set to the high level voltage VWLH, and the other word line WL is set to the low level voltage VWLL. In the internal erase operation ERS, the word driver WDRV sets all the word lines WL0 to WL63 to the low level voltage VWLL (negative voltage VERS) in accordance with the non-selected state row predecode address signal RPDA.

  The sector selection control circuit SSELCNT includes a column address selector CASEL2, a column line driver SSELDRV, a read driver SRDDRV, a power supply control circuit VHCNT, a power supply selection circuit VHSEL, and a write driver SWRDRV.

  The column address selector CASEL2 outputs the column decode address signal RCDA as the column decode address signal CDA when receiving the read sector signal RSEC. The column address selector CASEL2 outputs the column decode address signal WCDA as the column decode address signal CDA when receiving the write sector signal WSEC. When the column address selector CASEL2 receives the erase mode signal EMD, the column address selector CASEL2 outputs a column decode address signal CDA indicating non-selection in order to set the sector selection signals SSEL0 <0> -SSEL0 <3> to a low level.

  The power supply control circuit VHCNT activates the program mode signal PMD to a high level when the program operation PGM and the preprogram operation PPGM are detected based on the write sector signal WSEC, the erase mode signal EMD, and the verify mode signal VMD. . The verify mode signal VMD is generated by the state machine 16 and is activated to a high level when the program verify operation PGMV, the pre-program verify operation PPGMV, and the erase verify operation ERSV are executed. The power supply selection circuit VHSEL outputs a high level voltage VD5 higher than the power supply voltage VDD to the high level voltage line VSSEL when the program mode signal PMD is inactivated. The power supply selection circuit VHSEL outputs a high level voltage VPGM higher than the power supply voltage VDD to the high level voltage line VSSSEL when the program mode signal PMD is activated.

  The column line driver SSELDRV receives the sector selection signal SSEL0 <0 according to the column decode address signal CDA in the read operation RD, the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERSV. > -SSEL0 <3> is set to the high level voltage VSSEL, and the other sector selection signal SSEL is set to the low level voltage VSS. The column line driver SSELDRV sets all the sector selection signals SSEL0 <0> to SSEL0 <3> to the low level voltage VSS in accordance with the column decoding address signal CDA in the non-selected state in the internal erase operation ERS.

  When the read driver SRDDRV receives the activated read sector signal RSEC, the read driver SRDDRV activates the read selection signal SRD0 to the high level voltage VD5. The read driver SRDDRV deactivates the read selection signal SRD0 to the low level voltage VSS when receiving the deactivated read sector signal RSEC. The write driver SWRDRV activates the write selection signal SWR0 to the high level voltage VSSEL when receiving the activated write sector signal WSEC. The write driver SWRDRV deactivates the write selection signal SWR0 to the low level voltage VSS when receiving the deactivated write sector signal WSEC.

  The power supply selection circuit VPWSEL supplies the high level voltage VEPW to the well region PW when receiving the erase mode signal EMD activated during the erase operation of the selected sector SEC. The power supply selection circuit VPWSEL supplies the ground voltage VSS to the well region PW when receiving the deactivated erase mode signal EMD (when other than the erase operation). The well region PW is a back gate of the cell transistor CT shown in FIG. 7, and is electrically isolated for each sector SEC.

  For example, the high level voltages VD5, VPGM, VEPW and the negative voltage VERS are generated by an internal voltage generation circuit formed in the semiconductor memory MEM. As shown in FIG. 21, the value of the high level voltage VPGM generated by the internal voltage generation circuit varies depending on the type of operation to be performed.

  FIG. 12 shows an example of the row address selector RASEL2 and the column address selector CASEL2 shown in FIG. The row address selector RASEL2 has address selectors ASEL that output the row predecode address signals RPDA0-15, respectively. Row predecode address signals RPDA0-15 correspond to 16-bit row predecode address signal RRPDA0-15 or 16-bit row predecode address signal WRPDA.

  The column address selector CASEL2 has address selectors ASEL that output column decode address signals CDA0-3, respectively. Column decode address signals CDA0-3 correspond to 4-bit column decode address signal RCDA or 4-bit column decode address signal WCDA. The address selector ASEL is the same circuit and has NAND gates NAND1, NAND2, and NAND3.

  The NAND gate NAND1 becomes effective when receiving a high level read sector signal RSEC and operates as an inverter. The NAND gate NAND2 becomes effective when receiving a high level write sector signal WSEC and a low level erase mode signal EMD, and operates as an inverter. The NAND gate NAND2 becomes invalid and outputs a high level when receiving a high level erase mode signal EMD. The NAND gate NAND3 operates as a negative logic OR gate.

  FIG. 13 shows an example of the read driver SRDDRV, the power supply selection circuit VHSEL, and the write driver SWRDRV in the sector selection control circuit SSELCNT shown in FIG. FIG. 13 shows a sector selection control circuit SSELCNT corresponding to the sector SEC0.

  The read driver SRDDRV has a shift register LSFT that converts the high level of the read sector signal RSEC from the power supply voltage VDD to the high level voltage VD5, and a buffer circuit BUF that receives the output of the shift register LSFT and outputs the read selection signal SRD0. ing. The buffer circuit BUF receives the high level voltage VD5 as the power supply voltage, and sets the level of the logic 1 read selection signal SRD0 to the high level voltage VD5.

  The power supply control circuit VHCNT sets the program mode signal PMD to high level while the write sector signal WSEC is inactive to high level and the erase mode signal EMD and verify mode signal VMD are inactive to low level. That is, when the program operation PGM of the write operation or the pre-program operation PPGM of the erase operation is executed (when any of the internal erase operation ERS, the program verify operation PGMV, the pre-program verify operation PPGMV, and the erase verify operation ERSV is not performed) The mode signal PMD is activated. The power supply control circuit VHCNT sets the program mode signal PMD to the low level while the write sector signal WSEC is inactivated to the low level, the erase mode signal EMD is activated to the high level, or the verify mode signal VMD is activated to the high level. Set.

  The power supply selection circuit VHSEL includes switch circuits SW1 and SW2 that connect the high level voltage line VVSEL to the voltage line VD5 or the voltage line VPGM. The switch circuit SW1 is turned on when the program mode signal PMD is at a low level and turned off when the program mode signal PMD is at a high level. The switch circuit SW2 is turned off when the program mode signal PMD is at a low level, and turned on when the program mode signal PMD is at a high level. FIG. 13 shows a state where the switch circuit SW2 is turned on and the voltage line VPG is supplied to the high level voltage line VVSEL.

  The write driver SWRDRV has a shift register LSFT that converts the high level of the write sector signal WSEC from the power supply voltage VDD to the high level voltage VSSEL, and a buffer circuit BUF that receives the output of the shift register LSFT and outputs the write selection signal SWR0. ing. The buffer circuit BUF receives the high level voltage VSSEL as a power supply voltage, and sets the level of the logic 1 write selection signal SWR0 to the high level voltage VSSEL.

  FIG. 14 shows an example of the column control circuit YSELCNT shown in FIG. FIG. 14 shows the column control circuit YSELCNT corresponding to the sector SEC0. The column control circuit YSELCNT has AND circuits AND1, AND2 and an OR circuit OR1. The AND circuit AND1 becomes effective when the read control signal IORD0 is activated to a high level, and outputs the column decode address signal RCDA4-7 to the OR circuit OR1. The AND circuit AND2 becomes effective when the write control signal IOWR0 is activated to a high level, and outputs the column decode address signal WCDA4-7 to the OR circuit OR1. The OR circuit OR1 outputs the column decode address signal RCDA4-7 or WCDA4-7 as the column selection signals YSEL0 <0> -YSEL0 <3>.

  FIG. 15 shows an example of the input data control unit 34 shown in FIG. The input data control unit 34 includes a latch circuit LT1, a skip generation circuit SKIP, a shift register SFTR1, and a write bit selector WBSEL.

  The latch circuit LT1 latches the logic of the write data DW0 to DW7 and the parity data DWP in synchronization with the latch clock signal LCLK at the start of the write operation, and outputs the latched logic as internal data signals IDI0 to IDI8. Note that the latch circuit LT1 has a function of resetting the internal data signals IDI0-8 to logic 0 at the start of the erase operation. For example, a reset signal for resetting the latch circuit LT1 is generated by the timing control unit 18. The skip generation circuit SKIP outputs the logic of the internal data signal IDI0-8 as the skip signal SSKIP0-8.

  The shift register SFTR1 operates according to the shift-in signal SIN, the shift clock signal SCK, the reset signal RSTB, and the second cycle signal 2NDCYC, and outputs the output signals OUT0-OUT8 and the shift-out signal SOUT. Output signals OUT0-OUT8 correspond to memory areas I / O0-I / O8 (input data ID0-7, IDP), and when memory cells MC in memory areas I / O0-I / O8 are programmed. Each is set to a high level. An example of the shift register SFTR1 is shown in FIG.

  The write bit selector WBSEL operates in response to the internal data signal IDI0-8, the output signal OUT0-8, the transfer signal TRANS, and the internal erase signal IERSB, and the read control signal IORD0-8, the write control signal IOWR0-8, and the input data signal ID0-7 and IDP are output. An example of the write bit selector WBSEL is shown in FIG.

  For example, the latch clock signal LCLK, the shift-in signal SIN, the shift clock signal SCK, the reset signal RSTB, the second cycle signal 2NDCYC, the transfer signal TRANS and the internal erase signal IERSB are written by the timing controller 18 shown in FIG. And generated during an erase operation.

  FIG. 16 shows an example of the shift register SFTR1 shown in FIG. The shift register SFTR1 includes a switch circuit ISW, a latch circuit ILT, nine stages STG0 to STG8 corresponding to input data ID0-7 and IDP, a switch circuit OSW, a latch circuit OLT, and a feedback switch FBSW.

  The switch circuit ISW has, for example, a CMOS transmission gate, is turned on when the shift clock signal SCKC0 is at a high level, and transmits the logic of the shift-in signal SIN to the latch circuit ILT. The shift clock signal SCKC0 is generated by inverting the logic of the shift clock signal SCK when the second cycle signal 2NDCYC is at a low level. When the second cycle signal 2NDCYC is at a high level, the shift clock signal S2CKC0 that operates the feedback switch FBSW is generated by inverting the logic of the shift clock signal SCK.

  Since the stages STG0 to STG8 that output the output signals OUT0 to OUT8 are the same circuit, the stage STG0 that outputs the output signal OUT0 will be described. The stage STG0 is arranged between a switch circuit FSW, a latch circuit FLT, a switch circuit RSW, and a latch circuit RLT connected in series between the input terminal I1 and the output terminal O1, and between the input terminal I1 and the input of the latch circuit RLT. Skip switch circuit SKSW.

  The switch circuit FSW has, for example, a CMOS transmission gate, and a high level period of the shift clock signal SCKT0 having the same logic as that of the shift clock signal SCK when the skip signal SSKIP0 is inactivated to a low level. Turn on. The stages STG1 to STG8 operate in response to the corresponding skip signals SSKIP1 to SSKIP8, respectively.

  The latch circuit FLT has a clocked NAND gate, holds the logic received at the input while receiving the low level shift clock signal SCKT0, and receives the inverter while receiving the high level shift clock signal SCKT0. Works as. The clocked NAND gate operates as a NAND gate while receiving the low level shift clock signal SCKT0, and sets the output to the high impedance state while receiving the high level shift clock signal SCKT0.

  The latch circuit FLT is reset in response to the low level reset signal RSTB, and sets the output signal OUT0 to the low level. The latch circuit FLT receives the logic level of the input terminal I1 while the shift clock signal SCKT0 is at the high level, inverts the logic level, and outputs it as the output signal OUT0. Latch circuit FLT latches the logic level received in synchronization with the falling edge of shift clock signal SCKT0.

  The switch circuit RSW is turned on during the high level period of the shift clock signal SCKC1 generated by inverting the logic of the shift clock signal SCK when the skip signal SSKIP0 is inactivated to the low level. The latch circuit RLT latches the logic level of the output signal OUT0, inverts the latched logic level, and outputs the inverted signal to the output terminal O1.

  The skip switch circuit SKSW is turned on when the skip signal SSKIP0 is activated to a high level, and transmits the logic in which the logic of the input terminal I1 is inverted to the input of the latch circuit RLT. When the skip signal SSKIP0 is activated, the shift clock signals SCKT0 and SCCK1 are fixed at the low level, so that the switch circuits FSW and RSW are held in the off state, and the output signal OUT0 is maintained at the low level.

  The switch circuit OSW is turned on during a high level period of the shift clock signal SCK9T having the same logic as that of the shift clock signal SCK. The latch circuit OLT has a clocked NAND gate. The clocked NAND gate operates as a NAND gate while receiving the low level shift clock signal SCK9T, and sets the output to a high impedance state while receiving the high level shift clock signal SCK9T.

  The latch circuit OLT is reset in response to the low level reset signal RSTB, and sets the shift out signal SOUT to the low level. Then, the latch circuit OLT receives the logic level of the output terminal of the stage STG8 while the shift clock signal SCKT9 is at the high level, inverts the received logic level, and outputs it as the shift output signal SOUT. Latch circuit OLT latches the logic level received in synchronization with the falling edge of shift clock signal SCKT9.

  The feedback switch FBSW is turned on when the shift clock signal S2CKC0 is at a high level, and transmits the logic level of the output signal OUT8 to the input of the latch circuit ILT. The shift clock signal S2CKC0 is generated by inverting the logic of the shift clock signal SCK when the second cycle signal 2NDCYC is at a high level. Examples of the operation of the shift register LSFT are shown in FIG. 23 and FIG. 26 to FIG.

  FIG. 17 shows an example of the write bit selector WBSEL shown in FIG. The write bit selector WBSEL has bit selectors BS0 to BS8 corresponding to the internal data signals IDI0-8, respectively. Since the bit selectors BS0 to BS8 are the same circuit, the bit selector BS0 will be described.

  The bit selector BS0 has a clocked inverter IVP, a latch circuit LTP, an AND circuit ANDP, and a NAND gate NANDP. The clocked inverter IVP operates as an inverter when the transfer signal TRANS is at a high level, inverts the logic of the output signal OUT0, and transmits it to the latch circuit LTP. For example, the transfer signal TRANS is a signal obtained by delaying the shift clock signal SCK shown in FIG. 16 with a delay circuit. The latch circuit LTP outputs the latched logic to the AND circuit ANDP and the NAND gate NANDP.

  The AND circuit ANDP is an example of a signal generation circuit that generates a write control signal IOWR0 and a read control signal IORD0 whose logic levels are opposite to each other. The AND circuit ANDP has a high-level read control signal IORD0 when the internal erase signal IERSB is activated to a low level, that is, when the internal erase operation ERS of the corresponding memory area I / O0 is being executed. A low level write control signal IOWR0 is output. The AND circuit ANDP outputs the read control signal IORD0 and the write control signal IOWR0 according to the logic of the output signal OUT0 held in the latch circuit LTP when the internal erase signal IERSB is inactivated to a high level. . In this way, the write control signal IOWR0 and the read control signal IORD0 can be generated by a simple AND circuit ANDP. The AND circuit ANDP may be formed as a switch control unit outside the write bit selector WBSEL, independently of the data input control unit 34.

  When the latch circuit LTP is latching the low level output signal OUT0, the AND circuit ANDP outputs a high level read control signal IORD0 and a low level write control signal IOWR0 in order to enable the read operation. When the latch circuit LTP is latching the high-level output signal OUT0, the AND circuit ANDP outputs the low-level read control signal IORD0 and the high-level write control signal IOWR0 in order to execute the write operation.

  Note that the write bit selector WBSEL sets all the output signals OUT0-8 to the low level during the standby period in which no write command is received. At this time, all the read control signals IORD0-8 are activated to a high level, and all the read switches RSW2 are turned on. By turning on the read switch RSW2 in advance before the read command is supplied, the read operation in response to the read command can be started quickly, and the access efficiency can be improved.

  The NAND gate NANDP outputs the high level input data ID0 when the internal erase signal IERSB is activated to the low level. The NAND gate NANDP executes the write operation of the corresponding memory area I / O when the internal erase signal IERSB is deactivated to the high level and the latch circuit LTP latches the high level output signal OUT0. The internal data signal IDI0 is output as input data ID0.

  The AND circuit ANDP of the write bit selector WBSEL has a memory area I / in which write data DW0-7 and DWP are written in the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, and the erase verify operation ERS. It operates as a switch control unit that sequentially activates the write control signal IOWR in order to sequentially turn on the write switch WSW2 corresponding to O. The AND circuit ANDP of the write bit selector WBSEL activates the read control signal IORD to turn on the read switch RSW2 corresponding to the global bit line GBL not connected to the write switch WSW2 that is turned on in the read operation RD. It operates as a switch control unit.

  FIG. 18 shows an example of command input to the semiconductor memory MEM shown in FIG. A read command for executing a read operation is recognized when a low level chip enable signal / CE and a high level write enable signal / WE are received in synchronization with the rising edge of the clock signal CLK. The command decoder 12 shown in FIG. 5 outputs a read command signal RDC when recognizing the read command RD. The semiconductor memory MEM starts a read operation in response to the read command signal RDC. Then, the semiconductor memory MEM reads the data D1 from the memory cell MC indicated by the address signal A1 received at the address terminal AD together with the read command RD, and outputs the read data D1 from the data output terminal DO in synchronization with the next clock signal CLK. To do.

  The write command for executing the write operation receives the program code PC1, PC2, PC3 and the write address PA1 at the address terminal AD together with the low level chip enable signal / CE and the write enable signal / WE, and at the data input terminal DI. Recognized when receiving program code PC1, PC2, PC3 and write data D1. The command decoder 12 receives the write address PA1 supplied to the address terminal AD and the write data D1 supplied to the data input terminal DI in synchronization with the next clock signal CLK that has recognized the write command, and receives the write command signal WRC. Is output. The semiconductor memory MEM starts a write operation in response to the write command signal WRC.

  The erase command for executing the erase operation receives the erase code EC1, EC2, EC3 and the erase address EA1 at the address terminal AD together with the low level chip enable signal / CE and the write enable signal / WE, and erases at the data input terminal DI. Recognized when receiving codes EC1, EC2, and EC3. The command decoder 12 receives the erase address EA1 (sector address SA) supplied to the address terminal AD in synchronization with the next clock signal CLK that has recognized the erase command, and outputs an erase command signal ERSC. The semiconductor memory MEM starts an erase operation in response to the erase command signal ERSC.

  FIG. 19 shows an example of a sequence of read operation, write operation and erase operation of the semiconductor memory MEM shown in FIG. The sequence shown in FIG. 19 is executed under the control of the state machine 16 shown in FIG.

  When receiving the read command RDC during the standby state STBY, the semiconductor memory MEM performs the read operation RD of the memory cell MC specified by the address signal AD. Data read from the memory cell MC is output to the data output terminal IO. The state machine STM returns to the standby state STBY after the read operation RD is completed. The standby state STBY is a state in which no command signal is supplied to the semiconductor memory MEM.

  When receiving the write command WRC during the standby state STBY, the semiconductor memory MEM performs the program verify operation PGMV of the memory cell MC specified by the address signal AD. The program verify operation PGMV is executed to confirm that the memory cell MC is in a program state (logic 0; threshold voltage is high). The semiconductor memory MEM performs the program operation PGM when the threshold voltage of the memory cell MC is lower than a predetermined value (Fail). Then, the program verify operation PGMV and the program operation PGM are repeated until the threshold voltage of the memory cell MC exceeds a predetermined value. The semiconductor memory MEM returns to the standby state STBY when the threshold voltage of the memory cell MC exceeds a predetermined value (Pass). That is, the write operation is completed. As described above, the write operation includes the program verify operation PGMV and the program operation PGM. During execution of the write operation, the semiconductor memory MEM outputs the write busy signal WRBSY as a flag signal to the flag terminal FLG0.

  When the semiconductor memory MEM receives an erase command ERSC during the standby state STBY, the semiconductor memory MEM performs a preprogram verify operation PPGMV. The pre-program verify operation PPGMV is the same operation as the program verify operation PGMV, and is executed to confirm that the memory cell MC is in the program state (logic 0; threshold voltage is high). The semiconductor memory MEM performs the preprogram operation PPGM when the threshold voltage of the memory cell MC is lower than a predetermined value in the preprogram verify operation PPGMV (Fail). The preprogram operation PPGM is the same operation as the program operation PGM. The preprogram verify operation PPGMV is executed in all the memory cells MC in the sector SEC while sequentially updating the address signal AD.

  Thereby, all the memory cells MC in the sector SEC are set to a program state with a high threshold voltage. After all the memory cells MC are set to the programmed state, the internal erase operation ERS is executed, so that the threshold voltage of the memory cell MC in the erased state can be prevented from varying.

  When the preprogram verify operation PPGMV of all the memory cells MC in the sector SEC is completed (Pass), the erase verify operation ERSV is executed. The erase verify operation ERSV is executed to confirm that the memory cell MC is in the erased state (logic 1; threshold voltage is low). The erase verify operation ERSV is executed in all the memory cells MC in the sector SEC while sequentially updating the address signal AD.

  In the erase verify operation ERSV, the semiconductor memory MEM performs the internal erase operation ERS when at least one of the threshold voltages of the memory cells MC in the sector is higher than a predetermined value (Fail). The internal erase operation ERS is executed for each sector SEC. The semiconductor memory MEM returns to the standby state STBY when the threshold voltages of all the memory cells MC in the sector SEC are in the erased state (Pass). As described above, the erase operation includes the pre-program verify operation PPGMV, the pre-program operation PPGM, the erase verify operation ERSV, and the internal erase operation ERS. During execution of the erase operation, the semiconductor memory MEM outputs the erase busy signal EBSY as a flag signal to the flag terminal FLG1.

  FIG. 20 shows an example of the threshold voltage distribution of the cell transistor CT shown in FIG. The erased state is a state in which the memory cell MC holds logic 1, and the threshold voltage of the cell transistor CT is relatively low. The program state is a state in which the memory cell MC holds logic 0, and the threshold voltage of the cell transistor CT is relatively high.

  The threshold voltage of the cell transistor CT is whether or not the value of the cell current flowing between the source and drain of the cell transistor CT is larger than the reference current when the gate voltage VG is applied to the control gate CG (that is, the word line WL). Is determined. For example, the reference current is generated using a cell current of a reference memory cell formed in the memory cell array ARY.

  The program verify operation PGMV and the pre-program verify operation PPGMV are executed with the gate voltage VG set to a high level voltage VPGM (for example, 6V). The erase verify operation ERSV is executed by setting the gate voltage VG to the high level voltage VPGM (for example, 3V).

  The read operation RD is executed by setting the gate voltage VG to the high level voltage VD5 (for example, 5V). Then, when the value of the cell current flowing through the cell transistor CT is larger than the value of the reference current, it is determined that the logic 1 is held in the memory cell MC. When the value of the cell current flowing through the cell transistor CT is smaller than the value of the reference current, it is determined that the logic 0 is held in the memory cell MC. Note that the value of the high level voltage VD5 at the time of the read operation RD is set to an intermediate value (for example, 4.5 V) between the high level voltage VPGM at the program verify operation PGMV and the high level voltage VPGM at the erase verify operation ERSV. May be.

  FIG. 21 shows an example of signal line voltages in the read operation, write operation and erase operation of the semiconductor memory MEM shown in FIG. Note that the voltage values shown in FIG. 21 are examples, and values other than these may be used. The read sector signal RSEC is activated to a high level H when the read operation RD is executed. The write sector signal WSEC is activated to a high level H when the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, the internal erase operation ERS, and the erase verify operation ERSV are executed.

  The erase mode signal EMD is activated to a high level H when the internal erase operation ERS is executed. The verify mode signal VMD is activated to a high level H when the program verify operation PGMV, the pre-program verify operation PPGMV, and the erase verify operation ERSV are executed. Program mode signal PMD is activated to high level H when program operation PGM and pre-program operation PPGM are executed.

  The high level voltage line VWLH for setting the word line WL to the high level is set to the high level voltage VD5 during the read operation RD, and the high level voltage VPGM during the other operations PGM, PGMV, PPGM, PPGMV, ERS, and ERSV. Set to The value of the high level voltage VPGM varies depending on the type of operation to be performed. The low level voltage line VWLL for setting the word line WL to the low level is set to the negative voltage VERS during the internal erase operation ERS, and is set to the ground voltage VSS during the other operations RD, PGM, PGMV, PPGM, PPGMV, and ERSV. The

  The high level voltage line VSSEL for setting the high level of the sector selection signal SSEL and the read selection signal SRD is set to the high level voltage VPGM during the program operation PGM and the preprogram operation PPGM, and the ground voltage VSS during the internal erase operation ERS. In other operations RD, PGMV, PPGMV, and ERSV, the high level voltage VD5 is set.

  The voltage of the well region PW that is the back gate of the cell transistor CT is set to the high level voltage VEPW during the internal erase operation ERS, and is set to the ground voltage VSS during the other operations RD, PGM, PGMV, PPGM, PPGMV, and ERSV. The

  FIG. 22 shows an example of the voltage applied to the cell transistor CT in the read operation, write operation and erase operation of the semiconductor memory MEM shown in FIG. Note that the voltage values shown in FIG. 22 are examples, and values other than these may be used. The source line SL is set to the floating state FLT during the internal erase operation ERS, and is set to the ground voltage VSS during the other operations RD, PGM, PGMV, PPGM, PPGMV, and ERSV.

  In the read operation RD, program verify operation PGMV, preprogram verify operation PPGMV, and erase verify operation ERSV, the local bit line LBL is precharged to the power supply voltage VDD by the precharge circuit PRE shown in FIG. The power supply voltage VDD is not limited to 1.8V. In the program operation PGM and the pre-program operation PPGM, the local bit line LBL is set to the high level voltage VD5 by the write amplifier WA shown in FIG. Other voltages are set according to FIG.

  FIG. 23 shows an example of the operation of the input data control unit 34 during the write operation of the semiconductor memory MEM shown in FIG. In this example, the semiconductor memory MEM receives the write command W and executes the write operation of the write memory block that is the sector SEC selected by the address signal AD. Note that the timing at which the write command W is supplied indicates a clock cycle in which the write data D1 is supplied in FIG. The semiconductor memory MEM continuously receives a read command R for a read memory block that is a sector SEC different from the sector SEC in which the write operation is executed, and repeatedly executes the read operation. That is, FIG. 23 shows an example in which the second switch operation is executed in parallel with the input operation and the first switch operation. The definitions of the input operation, the first switch operation, and the second switch operation are the same as those in FIG.

  The program active signal PGMMAC is a basic timing for activating the sector SEC when executing the program operation PGM, the program verify operation PGMV, the preprogram operation PPGM, the preprogram verify operation PPGMV, the internal erase operation ERS, and the erase verify operation ERSV. Signal. The read active signal RDACT is a basic timing signal for activating the sector SEC when executing the read operation RD. The program active signal PGMMAC and the read active signal RDACT are generated by the timing control unit 18, for example.

  In this example, the write data D1 supplied to the data input terminals DI0-7 is “1101 1110” in binary, and the parity data DWP (even parity) is “0”. Therefore, the internal data signals IDI2, IDI7, IDI8 are set to the low level, and the internal data signals IDI0, IDI1, IDI3-IDI6 are set to the high level (FIG. 23 (a)). The write operation is an operation for setting the memory cell MC of logic 1 (erased state) to logic 0. Therefore, in the example of FIG. 23, the write operation is sequentially performed on the memory areas I / O2 and I / O7 corresponding to the logic 0 bit of the write data D1 and the memory area I / O8 corresponding to the parity data DWP. Executed.

  The number in “<>” shown in the program active signal PGMMAC indicates the number of the memory area I / O. In one activation period of the program active signal PGMMAC, the program verify operation PGMV and the program operation PGM of one memory area I / O are performed. That is, the write operation in response to the write command W is executed bit by bit.

  The timing control unit 18 activates the verify signal VRFY (one of VRFY0 to VRFY8) corresponding to the memory area I / O that executes the program verify operation PGMV to a high level. The verify selector VSEL shown in FIG. 8 receives the activation of the verify signal VRFY and outputs the logic read from the memory cell MC in the memory area I / O that executes the program verify operation PGMV, to the verify output data line OVD (OVD0− One of the OVDs 9). Then, when the read data on the verify output data line OVD is logic 0, it is determined that the memory cell MC has been programmed (verify pass).

  The timing control unit 18 shown in FIG. 5 generates the shift-in signal SIN and the shift clock signal SCK in response to the write command W (FIG. 23B). In the write operation, the second cycle signal 2NDCYC is inactivated to the low level. Therefore, the shift clock signal SCKC0 is generated in synchronization with the shift clock signal SCK (FIG. 23 (c)). The switch circuit ISW is turned on in synchronization with the shift clock signal SCKC0, the high level of the shift-in signal SIN is latched by the latch circuit ILT, and the low level is supplied to the input terminal I1 of the stage STG0.

  The skip generation circuit SKIP shown in FIG. 15 outputs skip signals SSKIP0-8 having the same logic as the internal data signals IDI0-8. Therefore, the skip signals SSKIP0-1 and 3-6 are set to a high level, and the skip signals SSKIP2 and 7-8 are set to a low level L (FIG. 23 (d)). In response to the low level skip signals SSKIP2 and 7-8, the shift clock signal SCKC0 and the shift clock signals SCKC3 and 8-9 obtained by inverting the level of the shift clock SCK are generated (FIG. 23 (e)). Further, shift clock signals SCKT2 and 7-8 having the same level as the shift clock SCK are generated together with the shift clock signal SCKT9 (FIG. 23 (f)).

  The shift clock signals SCKT0, 1, 3-6 and the shift clock signals SCCC1, 2, 4-7 corresponding to the high level skip signals SSKIP0, 1, 3-6 are set to the low level (FIG. 23 (g, h )).

  The skip switch circuits SKSW of the stages STG0, 1, 3-6 that receive the high level skip signals SSKIP0, 1, 3-6 are turned on, and the input terminal I1 is transmitted to the input of the latch circuit RLT. Thereby, the inversion level of the shift-in signal SIN is transmitted to the input terminal I1 of the stage STG2. The switch circuit FSW of the stage STG2 is turned on in response to the high level shift clock signal SCKCT2, and transmits the high level received at the input terminal I1 to the latch circuit FLT. The latch circuit FLT latches the low level and changes the output signal OUT2 to the high level (FIG. 23 (i)).

  The switch circuit RSW of the stage STG2 is turned on when the shift clock SCKC3 changes to high level (FIG. 23 (j)). For this reason, the latch circuit FLT of the stage STG2 is connected to the latch circuit RLT via the switch circuit RSW. The logic held in the latch circuit FLT of the stage STG2 is held in the latch circuit RLT, and the output terminal O1 of the stage STG2 outputs a low level. By the high level skip signal SSKIP3-6, the output terminal O1 of the stage STG2 is connected to the input terminal I1 of the stage STG7 via the skip switch circuit SKSW and the latch circuit RLT. Therefore, the low level of the output terminal O1 of the stage STG2 is transmitted to the input terminal I1 of the stage STG7.

  The switch circuits FSW and RSW of the stages STG0, 1 and 3-6 having the skip switch circuit SKSW which is turned on are turned off in response to the low level shift clock signals SCCK and SCKT. Therefore, the latch circuit FLT is held in the reset state and outputs low level output signals OUT0, 1, and 3-6, respectively.

  The bit selector BS2 of the write bit selector WBSEL shown in FIG. 17 latches the high level output signal OUT2 in synchronization with the transfer signal TRANS generated from the shift clock signal SCK, and sets the write control signal IOWR2 to high level. Then, the read control signal IORD2 and the input data ID2 are set to the low level (FIG. 23 (k)). The write bit selector WBSEL sets the other write control signals IOWR0-1 and 3-8 to the low level and sets the other read control signals IORD0-1 and 3-8 to the high level.

  As a result, the write operation of the memory area I / O2 is executed, and the read operations of the other memory areas I / O0, 1, and 3-8 can be executed. The high level of the write control signal IOWR2 and the low level of the read control signal IORD2 are held until the transfer signal TRANS in response to the next shift clock SCK is generated (FIG. 23 (l)). The next shift clock SCK is generated in response to the completion of the write operation of the memory area I / O2.

  In response to the next shift clock SCK, the shift clock SCKT7 changes to high level, and the shift clock signal SCCK8 changes to low level (FIG. 23 (m, n)). The switch circuit FSW of the stage STG7 is turned on in response to the high level shift clock signal SCKCT7, and transmits the low level received at the input terminal I1 to the latch circuit FLT. Thus, the latch circuit FLT latches the low level and changes the output signal OUT7 to the high level (FIG. 23 (o)).

  The switch circuit RSW of the stage STG7 is turned on when the shift clock SCKC8 changes to high level (FIG. 23 (p)). Therefore, the logic held in the latch circuit FLT of the stage STG7 is transferred to the latch circuit RLT, and the output terminal O1 of the stage STG7 outputs a low level.

  The bit selector BS7 of the write bit selector WBSEL latches the high level output signal OUT7 in synchronization with the transfer signal TRANS. The bit selector BS7 sets the write control signal IOWR7 to the high level, and sets the read control signal IORD7 and the input data ID7 to the low level ((q) in FIG. 23). Note that the stage STG2 receiving the high level at the input terminal I1 sets the output signal OUT2 to the low level in synchronization with the rising edge of the shift clock signal SCKT2 (FIG. 23 (r)). Therefore, the write control signal IOWR2 and the input data ID2 are set to the low level, and the read control signal IORD2 is set to the high level (FIG. 23 (s)).

  Thereby, the write operation of the memory area I / O 7 is executed, and the read operation of the other memory areas I / O 0-6 and 8 can be executed. Thereafter, the output signal OUT8 changes to high level in synchronization with the next shift clock signal SCK, and the write control signal IOWR8 is set to high level (FIG. 23 (t, u)). The read control signal IORD8 and the input data ID8 are set to the low level (FIG. 23 (v)). Then, the write operation of the memory area I / O8 is executed, and the read operation of the other memory area I / O0-7 can be executed.

  In response to the next shift clock signal SCK, the shift clock signal SCKT9 is generated, and the switch circuit OSW is turned on (FIG. 23 (w)). As a result, the low level output from the output terminal O1 of the stage STG8 is latched by the latch circuit OLT, and the shift-out signal SOUT is set to the high level (FIG. 23 (x)). Then, the write operation is completed.

  The timing control unit 18 outputs a latch clock signal LCLK (FIG. 15) in response to the completion of the write operation. As a result, the latch circuit LT1 is initialized, all the internal data signals IDI0-8 are set to the low level, and the skip signals SSKIP0-8 are changed to the low level (FIG. 23 (y, z)).

  Note that the write operation of the memory area I / O7 ends during a period in which the read active signal RDACT is activated to a high level (during execution of the read operation) (FIG. 23A). In order to prevent the read data and the write data from colliding on the global bit line GBL, the timing control unit 18 sets the program active signal PGMMAC for the next write operation to a high level after the read operation is completed. It is activated (FIG. 23B).

  FIG. 24 shows an example of the write operation of the semiconductor memory MEM shown in FIG. In this example, similarly to FIG. 23, the semiconductor memory MEM receives the write data D1 of “1101 1110” in binary numbers and the program address PGMAD together with the write command W, and executes the write operation. The semiconductor memory MEM continuously receives a read command R for another sector SEC while executing a write operation in one of the sectors SEC, and executes the read operation. The timing at which the write command W is supplied indicates the clock cycle in which the write data D1 is supplied in FIG. 18, as in FIG.

  An arrow extending in a horizontal direction indicated by a solid line indicates a period during which a write operation (PGMV, PGM) of one memory area I / O is being performed. A white rectangular frame indicates a memory area I / O in which a write operation is not performed and a read operation can be performed. A rectangular frame marked with X indicates a memory area I / O in which a read operation cannot be performed by a write operation.

  While the write operation of the memory area I / O2 is being executed, the read operation of the memory area I / O2 cannot be executed. This is because the global bit line GBL2 connected to the memory area I / O2 is used for data read from the memory cell MC for the input data ID2 and the program verify operation PGMV. Therefore, the data reproducing unit 36 shown in FIG. 5 uses the output data OD0-1, 3-7, ODP read from the other memory areas I / O0-1, 3-8 to use the memory area I / O2. The output data OD2 held in is reproduced (FIG. 24A).

  Similarly, while the write operation of the memory area I / O 7 is being performed, the data reproducing unit 36 reproduces data to be read from the memory area I / O 7 where the read operation cannot be performed (FIG. 24B). While the write operation of the memory area I / O 8 is being performed, the data reproducing unit 36 reproduces data to be read from the memory area I / O 8 where the read operation cannot be performed (FIG. 24C).

  When the write operation is not executed, the read data can be read from all the memory areas I / O0-8. At this time, the data reproducing unit 36 masks the output data (ODP in FIG. 5) from the memory area I / O 8 as indicated by the broken X, and outputs the output data OD0-7 as read data DR0-7. It outputs (FIG.24 (d)).

  FIG. 25 shows an example of the state of the memory core 40 in the write operation of the semiconductor memory MEM shown in FIG. FIG. 25 shows an example in which the memory core 40 includes five memory areas I / O0 to I / O3 and I / O8 and two sectors SEC0 to SEC1 in order to simplify the description. The memory area I / O 8 stores parity data DWP. The rectangles indicate the read switches RSW1 and RSW2 and the write switches WSW1 and WSW2. A black rectangle indicates an on state, and a white rectangle indicates an off state.

  In this example, a write operation is performed to write data to the memory area I / O2 of the sector SEC0. During the execution of the write operation, the read operation of the sector SEC1 is executed. The local bit line LBL of the memory area I / O2 of the sector SEC0 is connected to the global bit line GBL2 via the write switch WSW1-2 that is turned on by the activation of the write selection signal SWR0 and the write control signal IOWR2. The global bit line GBL2 is used for programming the input data ID2 into the memory cell MC and reading the verify output data OVD2 from the memory cell MC.

  The local bit line LBL of the memory area I / O0 of the sector SEC1 is connected to the global bit line GBL0 via the read switch RSW1-2 that is turned on by the activation of the read selection signal SRD1 and the read control signal IORD0. Similarly, the local bit lines LBL of the memory areas I / O1, 3, 8 of the sector SEC1 are also connected to the global bit lines GBL1, 3, 8 respectively. The global bit lines GBL0, 1, 3, and 8 are used for reading the output data OD0, 1, 3, and ODP from the memory cell MC in the sector SEC1.

  26 to 29 show an example of the operation of the input data control unit 34 during the erase operation of the semiconductor memory MEM shown in FIG. Detailed description of the same operations as those in FIG. 23 is omitted. In this example, the semiconductor memory MEM receives an erase command E and executes an erase operation of an erase memory block that is a sector SEC selected by an address signal AD. Note that the timing at which the erase command E is supplied indicates a clock cycle in which the erase address EA1 (sector address) is supplied in FIG. During execution of the erase operation, the semiconductor memory MEM continuously receives the read command R for another sector SEC and repeatedly executes the read operation.

  As shown in FIG. 9, the erase operation includes a preprogram verify operation PPGMV, a preprogram operation PPGM, an erase verify operation ERSV, and an internal erase operation ERS. In FIG. 26 to FIG. 28, the pre-program verify operation PPGMV and the pre-program operation PPGM are executed. The read command R at the right end in FIG. 26 indicates the read command R at the left end in FIG. The read command R at the right end in FIG. 27 indicates the read command R at the left end in FIG.

  The preprogram verify operation PPGMV and the preprogram operation PPGM are executed in all the memory cells MC in the sector SEC. Therefore, the input data control unit 34 shown in FIG. 15 resets all internal data signals IDI0-8 to logic 0 (FIG. 26 (a)). As a result, all skip signals SSKIP0-8 are set to the low level L. That is, the operation of skipping stages STG0-8 of shift register SFTR1 is prohibited, and shift register SFTR1 generates output signals OUT0-OUT8 in order.

  The pre-program verify operation PPGMV is the same as the program verify operation PGMV except that it is executed for all the memory cells MC in the sector SEC. The pre-program operation PPGM is the same operation as the program operation PGM except that it is executed for all the memory cells MC in the sector SEC. The preprogram verify operation PPGMV and the preprogram operation PPGM are executed in pairs for each memory area I / O of one address value RA and CA. 23. Except that the output signal OUT0 is activated instead of the output signal OUT2 until the shift-in signal SIN and the shift clock signal SCK are generated and the pre-program verify operation PPGMV and the pre-program operation PPGM are started. It is the same.

  In the erase operation, after the first shift clock signal SCK is generated, the second cycle signal 2NDCYC is activated to a high level (FIG. 26B). Therefore, the shift clock signal S2CKC0 is generated in synchronization with the subsequent shift clock signal SCK (FIG. 26 (c)). The phase of the shift clock signal S2CKC0 is opposite to the phase of the shift clock signal SCK. While the shift clock signal S2CKC0 is at the high level, the feedback switch FBSW shown in FIG. 16 is turned on, and the output terminal O1 (= OUT8) of the stage STG8 is connected to the input terminal I1 of the stage STG0 via the latch circuit ILT. The That is, the shift register SFTR1 operates as a cyclic shift register.

  Specifically, when the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM of nine memory areas I / O corresponding to one address value RA and CA is completed, the shift register SFTR1 outputs the shift out signal SOUT. Then, the operation of outputting the output signal OUT0 from the stage STG0 is started again. At this time, the timing control unit 18 generates the address clock signal ACLK to be supplied to the address control unit 20 shown in FIG. 9 in response to the shift-out signal SOUT. Then, a pair of preprogram verify operation PPGMV and preprogram operation PPGM of nine memory areas I / O corresponding to the next address values RA and CA is executed. For example, in FIG. 28, when the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM <8> in the memory area I / O 8 at the address (RA = 0, CA = 0) is completed, the next address (RA = 0, A pair of the preprogram verify operation PPGMV and the preprogram operation PPGM <0> in the memory area I / O0 of CA = 1) is started. The address values RA and CA are updated in the order of the column address signal CA and the row address signal RA, as shown in FIG.

  The pair of the pre-program verify operation PPGMV and the pre-program operation PPGM <8> shown in FIG. Is shown. By this write operation, all the memory cells MC in the sector SEC on which the erase operation is executed are set to logic 0 (program state). In other words, in the sector SEC in which the erase operation is performed, the threshold voltages of all the cell transistors CT are relatively high and set to the programmed state. After the threshold voltages of all the cell transistors CT are set to the programmed state, the internal erase operation ERS is executed, so that the threshold voltage of the cell transistor CT becomes negative at the time of the internal erase operation ERS, that is, over-erase is performed. Can be prevented.

  Before the internal erase operation ERS is started, the timing control unit 18 activates the internal erase signal IERSB to the low level (FIG. 29A). The write bit selector WBSEL shown in FIG. 17 activates all the read control signals IORD0 to IORD8 to a high level and deactivates all the write control signals IOWR0 to IOWR8 to a low level based on the low level internal erase signal IERSB. To do. The write bit selector WBSEL sets all input data ID0 to ID8 to a high level. This prevents the write operation from being executed in the sector SEC that executes the internal erase operation ERS.

  In the sector SEC in which the internal erase operation ERS is executed, the read selection signal SRD is not activated and the read switch RSW1 is maintained in the off state. For this reason, even if the read switch RSW2 is turned on by the activation of the read control signals IORD0 to IORD8, the local bit line LBL in the sector SEC where the internal erase operation ERS is executed is not connected to the global bit line GBL. Local bit line LBL is held in floating state FLT as shown in FIG.

  After the internal erase signal IERSB is activated, the program active signal PGMMAC is activated and the internal erase operation ERS is executed (FIG. 29 (b)). The internal erasing operation ERS is executed for a preset time. The timing control unit 18 stops generating the shift clock signal SCK during the internal erase operation ERS. Therefore, the shift register SFTR1 stops the shift operation and continues to activate the output signal OUT0 to the high level (FIG. 29 (c)).

  After the end of the internal erase operation ERS, the timing control unit 18 deactivates the internal erase signal IERSB and activates the program active signal PGMMACT to start the erase verify operation ERSV (FIG. 29 (d, e)). . The output value of the address control unit 20 returns to RA = 0 and CA = 0 in response to the address clock signal ACLK before the start of the erase verify operation ERSV. The shift register SFTR1 activates the output signal OUT0. Therefore, the erase verify operation ERSV <0> of RA = 0 and CA = 0 in the memory area I / O0 is started.

  The output of the shift clock signal SCK is resumed after the first erase verify operation ERSV <0> is executed (FIG. 29 (f)). Since the second cycle signal 2NDCYC is held at the high level H, the shift register SFTR1 operates as a cyclic shift register. The erase verify operation ERSV is executed to confirm that all the memory cells MC in the sector SEC in which the internal erase operation ERS has been executed are set to logic 1.

  The erase verify operation ERSV is executed bit by bit while sequentially changing the memory areas I / O0 to I / O8, as in the preprogram verify operation PPGMV. When the erase verify operation ERSV of the nine memory areas I / O0 to I / O8 corresponding to one address value RA and CA is completed, the shift register SFTR1 starts the operation of outputting the output signal OUT0 from the stage STG0 again. The timing control unit 18 outputs an address clock signal ACLK in order to update the address values RA and CA. Then, the erase verify operation ERSV of nine data corresponding to the next address values RA and CA is sequentially executed, and the logic of all the memory cells MC that have executed the erase operation is confirmed. The address values RA and CA are updated in the order of the column address signal CA and the row address signal RA as shown in FIG. 9 during the erase verify operation ERSV.

  The timing control unit 18 activates a verify signal VRFY (any one of VRFY0 to VRFY8) corresponding to the memory area I / O that executes the erase verify operation ERSV to a high level. The verify selector VSEL shown in FIG. 8 receives the activation of the verify signal VRFY and outputs the logic read from the memory cell MC in the memory area I / O that executes the erase verify operation ERSV to the verify output data line OVD (OVD0− OVD9). When the read data on the verify output data line OVD is logic 1, it is determined that the data in the memory cell MC has been erased (verify pass).

  Note that the erase verify operation ERSV can be executed in the same time as the read operation RD. Therefore, during the erase verify operation ERSV, the timing control unit 18 may generate the program active signal PGMMAC with the same cycle as the read active signal RDACT.

  30 and 31 show an example of the erase operation of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations and the same notations as those in FIG. 24 are omitted. FIG. 30 shows an example of the pre-program verify operation PPGMV and the pre-program operation PPGM in the erase operation. The memory region I / O that is executing the pre-program verify operation PPGMV and the pre-program operation PPGM cannot execute a read operation. Read data from the memory area I / O where the read operation cannot be performed is reproduced using data read from the other memory area I / O, as in FIG.

  The first preprogram verify operation PPGMV and preprogram operation PPGM <8> in FIG. 31 show the operation of the last address (RA = 63, CA = 15) in the sector SEC from which data is erased. In this example, the pre-program verify operation PPGMV is passed and the internal erase operation ERS is started. During the internal erase operation ERS, the read data can be read from all the memory areas I / O0 to I / O8. At this time, similarly to FIG. 24, the output data from the memory area I / O8 is masked, and the data output from the memory areas I / O0 to I / O7 is output as read data.

  After the erase operation ESR, the erase verify operation ERSV is executed as in FIG. Read data from the memory area I / O that cannot be read by the erase verify operation ERSV is reproduced using data read from the other memory area I / O, as in FIG.

  FIG. 32 shows an example of the state of the memory core 40 in the internal erase operation ERS of the semiconductor memory MEM shown in FIG. Detailed description of the same elements as those in FIG. 25 will be omitted. 32 also shows an example in which the memory core 40 has five memory areas I / O0 to I / O3 and I / O8 and two sectors SEC0 to SEC1, as in FIG.

  In this example, an internal erase operation ERS is executed to erase data in the memory cell MC in the sector SEC0. During the execution of the internal erase operation ERS, the read operation of the sector SEC1 is executed. As described with reference to FIG. 29, during the internal erase operation ERS, all the read control signals IORD0 to IORD8 are activated and all the read switches RSW2 are turned on. By turning on the read switch RSW2 in advance before the read command is supplied, the read operation in response to the read command can be started quickly, and the access efficiency can be improved. In the read operation during the internal erase operation ERS, data is read from all the memory areas I / O0 to I / O3 and I / O8 of the sector SEC1. However, in the read operation during the internal erase operation ERS, the output data from the memory area I / O8 is masked, and the data output from the memory areas I / O0 to I / O2 is output as read data.

  Note that the state of the memory core 40 in the preprogram verify operation PPGMV, the preprogram operation PPGM, and the erase verify operation ERSV is the same as that in FIG. That is, the local bit line LBL of the memory region I / O on which the preprogram verify operation PPGMV, the preprogram operation PPGM, and the erase verify operation ERSV are executed is connected to the global bit line GBL. The data held in the memory area I / O where the preprogram verify operation PPGMV, the preprogram operation PPGM, and the erase verify operation ERSV are executed is reproduced using the read data from the other memory areas I / O. The

  FIG. 33 shows another example of the erase operation of the semiconductor memory MEM shown in FIG. Detailed description of the same operations and the same notations as those in FIGS. 24 and 31 will be omitted. In this example, the erase verify operation ERSV of the memory area I / O2 at the address (RA = 18, CA = 3) of the sector SEC0 fails, and the internal erase operation ERS is executed again. After the internal erase operation ERS is completed, the erase verify operation ERSV of the same memory area I / O2 at the same address (RA = 18, CA = 3) is executed again. Thereafter, the erase verify operation ERSV is executed for each memory area I / O for all the remaining address values RA and CA in the sector SEC0.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, during the period in which the program operation PGM, the program verify operation PGMV, the pre-program operation PPGM, the pre-program verify operation PPGMV, and the erase verify operation ERSV are executed, the read operation can be executed in response to the read command, Can be output to output terminal DO.

  The semiconductor memory MEM independently includes an address predecoder 22 that includes a latch circuit and is used for a read operation, and an address predecoder 24 that includes a latch circuit and is used for a write operation and an erase operation. Therefore, it is possible to receive and hold the address signal AD necessary for the read operation while holding the address signal AD necessary for the write operation or the erase operation during the write operation or the erase operation. Therefore, the read operation can be executed in parallel during the write operation or the erase operation.

  When the semiconductor memory MEM receives a read command for the sector SEC during the write operation or the erase operation, the semiconductor memory MEM invalidates the read command and prohibits the execution of the read operation. Thereby, it is possible to prevent the write operation or the erase operation and the read operation from being performed redundantly, and to prevent malfunction of the semiconductor memory MEM. Further, the semiconductor memory MEM outputs a sector error signal SERR when the read command is invalidated. Thereby, a controller such as a CPU accessing the semiconductor memory MEM can know the invalidity of the read command and can prevent receiving illegal read data. As a result, malfunction of the system SYS can be prevented and the reliability of the system SYS can be improved.

  By turning on all the read switches RSW2 during the standby period in which no write command is received, a read operation in response to the read command can be started quickly, and access efficiency can be improved.

  The semiconductor memory MEM can recognize a memory area I / O from which data cannot be read from the state of the state machine 16 that controls execution of a write operation or an erase operation. Therefore, the read data can be reproduced by 1-bit parity data DWP by forming the parity generation unit 32 and the data reproduction unit 36 in the semiconductor memory MEM.

  FIG. 34 shows an example of the address control unit 20A in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the semiconductor memory MEM excluding the address control unit 20A is the same as that in FIG. That is, the semiconductor memory MEM in which the address control unit 20A is formed is a nonvolatile semiconductor memory such as a flash memory.

  The address control unit 20A is formed by replacing the column address counter CACOUNT and column address selector CASEL1, and the row address counter RACOUNT and row address selector RASEL1 with respect to FIG. That is, the row address counter RACOUNT counts in synchronization with the address clock signal ACLK and updates the value of the internal row address signal IRA. The column address counter CACOUNT counts every time the internal row address signal IRA makes a round, and updates the value of the internal column address signal ICA.

  The column address counter CACOUNT and the row address counter RACOUNT are reset before the preprogram operation PPGM, preprogram verify operation PPGMV, and erase verify operation ERSV are started, and the counter values are set to zero. For this reason, the column address counter CACOUNT counts in synchronization with the change of the internal row address signal IRA from the maximum value IRAmax to zero. The other configuration of the address control unit 20A is the same as that of the address control unit 20 shown in FIG. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 35 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor memory MEM of this embodiment has a timing control unit 18B and an input data control unit 34B instead of the timing control unit 18 and the input data control unit 34 shown in FIG. Similar to the timing control unit 18, the timing control unit 18B operates as an operation control unit. Other configurations of the semiconductor memory MEM are the same as those in FIG. That is, the semiconductor memory MEM is a flash memory. Instead of the address control unit 20, an address control unit 20A shown in FIG. 34 may be formed.

  The timing controller 18B deletes the function of generating the second cycle signal 2NDCYC (FIG. 16) from the timing controller 18 shown in FIG. Further, the timing control unit 18B makes the generation intervals of the address clock signal ACLK and the shift clock signal SCK supplied to the address control unit 20 during the erase operation different from the generation intervals by the timing control unit 18 shown in FIG.

  For example, the address clock signal ACLK is generated by the timing control unit 18B every time the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM of each memory area I / O is completed, and the memory area I / O is erased. It is generated every time the verify operation ERSV is completed.

  For example, the shift clock signal SCK is generated every time the address values RA and CA are completed in the pair of the pre-program verify operation PPGMV and the pre-program operation PPGM and the erase verify operation ERSV. In other words, the shift clock signal SCK is applied to the completion of the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM for all the memory cells MC and the erase verify operation ERSV for all the memory cells MC in each memory area I / O. Generated in response to the completion of. For example, the timing control unit 18B detects one cycle of the address values RA and CA when the address value returns from RA = 63, CA = 15 to RA = 0, CA = 0.

  As a result, every time the preprogram operation PPGM of all the memory cells MC in the memory area I / O is completed in the selected sector SEC, the memory area I / O to which data is written is switched and activated. The write control signal IOWR and the read control signal IORD are switched. In the selected sector SEC, the memory area I / O in which data is written is switched and activated for each erase verify operation ERSV of all the memory cells MC in the memory area I / O. The read control signal IORD is switched. In other words, the write switch WSW2 and the read switch RSW2 that are turned on are switched every time all the preprogram operations PPGM and all the erase verify operations ERSV of each memory area I / O are completed.

  FIG. 36 illustrates an example of the input data control unit 34B illustrated in FIG. The input data control unit 34B has a shift register SFTR2 instead of the shift register SFTR1 shown in FIG. Shift register SFTR2 does not receive second cycle signal 2NDCYC. The other configuration of the input data control unit 34B is the same as that of the input data control unit 34 shown in FIG.

  FIG. 37 shows an example of the shift register SFTR2 shown in FIG. The shift register SFTR2 deletes the circuit that generates the shift clock signal S2CKC0, the feedback switch FBSW, and the feedback path that connects the output signal OUT8 to the latch circuit ILT from the shift register SFTR1 shown in FIG. The other configuration of the shift register SFTR2 is the same as that of the shift register SFTR1 shown in FIG.

  38 and 39 show an example of the erase operation of the semiconductor memory MEM shown in FIG. Detailed description of the same operations and the same notations as those in FIGS. 24, 30 and 31 will be omitted. 38 and 39 show operations corresponding to FIGS. 30 and 31. In this embodiment, in the pair of preprogram verify operation PPGMV and preprogram operation PPGM and the erase verify operation ERSV, the memory area I / O is switched after the address values RA and CA are completed.

  For example, as shown in FIG. 38, at the start of the erase operation, the pair of the preprogram verify operation PPGMV and the preprogram operation PPGM is executed in the memory area I / O0 until the address signals RA and CA are completed. Similarly, as shown in FIG. 39, the erase verify operation ERSV is executed in the memory area I / O0 until the address signals RA and CA are completed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, even in the semiconductor memory MEM in which the memory area I / O is switched after the address values RA and CA are completed in the pre-program verify operation PPGMV, the pair of the pre-program operation PPGM and the erase verify operation ERSV, one sector SEC is written. During the operation or the erase operation, the read operation of another sector SEC can be executed, and the access efficiency can be improved.

  FIG. 40 shows an example of a memory core 40C in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the semiconductor memory MEM excluding the memory core 40C is the same as that in FIG. That is, the semiconductor memory MEM in which the memory core 40C is formed is a nonvolatile semiconductor memory such as a flash memory.

  In this embodiment, the memory core 40C has a word decoder WDEC and a sector selection control circuit SSELCNT for each memory area I / O0-I / O8 in each sector SEC0-SEC31. Read switches RSW1-RSW2 and write switches WSW1-WSW2 shown in FIGS. 6 and 7 are not formed. Read control signals IORD0 to IORD8 for controlling the read switch RSW2 shown in FIGS. 6 and 7 are supplied to the column control circuit YSELCNT and used for controlling the column switch YSW. Write control signals IOWR0 to IOWR8 for controlling the write switch WSW2 shown in FIGS. 6 and 7 are supplied to the column control circuit YSELCNT and used for controlling the column switch YSW.

  Read selection signals SRD0 to SRD31 for controlling the read switch RSW1 shown in FIGS. 6 and 7 are supplied to the sector selection control circuit SSELCNT and used for controlling the sector switch SSW. Write selection signals SWR0 to SWR31 for controlling the write switch WSW1 shown in FIGS. 6 and 7 are supplied to the sector selection control circuit SSELCNT and used for controlling the sector switch SSW.

  In this embodiment, since the word decoder WDEC and the sector selection control circuit SSELCNT are formed for each memory area I / O0-I / O8, in each sector SEC, the word line WL for each memory area I / O0-I / O8. Can be selected individually. Thereby, the read operation of the same sector SEC can be executed while the write operation is executed in one sector SEC. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. In the semiconductor memory MEM of this embodiment, the address control unit 20A shown in FIG. 34 may be formed instead of the address control unit 20 shown in FIG. Further, instead of the input data control unit 34 shown in FIG. 15, an input data control unit 34B shown in FIG. 36 may be formed.

  FIG. 41 shows an example of a system SYS on which the above-described semiconductor memory MEM is mounted. The system SYS (user system) includes at least a part of a microcomputer system such as a portable device. The system SYS may be a system-on-chip in which a plurality of macros are integrated on a substrate such as silicon, or a system-in-package in which a plurality of chips are mounted on a package substrate.

  For example, the system SYS includes any one of the above-described semiconductor memories MEM, a CPU (Central Processing Unit), a ROM (Read Only Memory), and peripheral circuits PERI1 and PERI2. The CPU, ROM, peripheral circuits PERI1, PERI2, and semiconductor memory MEM are connected to each other by a system bus SBUS. For example, the semiconductor memory MEM holds parameters and data that are used in the system SYS and updated sequentially. The ROM stores a program executed by the CPU.

  The CPU executes a program stored in the ROM, accesses the semiconductor memory MEM, and controls the operation of the system SYS. That is, the CPU operates as a controller that controls access to the semiconductor memory MEM. Each peripheral circuit PERI1, PERI2 controls an input device or an output device connected to the system SYS. The input device is a switch, a microphone, a camera, a touch panel, a switch, or the like. The output device is a display, a speaker, a printer, or the like.

  FIG. 42 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The semiconductor memory MEM of this embodiment includes an input data buffer 26D, an output data buffer instead of the input data buffer 26, the output data buffer 28, the input data control unit 34, the output data control unit 38 and the memory core 40 shown in FIG. 28D, an input data control unit 34D, an output data control unit 38D, and a memory core 40D. Further, the semiconductor memory MEM does not include the parity generation unit 32 and the data reproduction unit 38 illustrated in FIG. Other configurations of the semiconductor memory MEM are the same as those in FIG. That is, the semiconductor memory MEM is a flash memory.

  Instead of the address control unit 20, an address control unit 20A shown in FIG. 34 may be formed. Further, a timing control unit 18B shown in FIG. 35 may be formed instead of the timing control unit 18. At this time, the input data control unit 34D has the shift register SFTR2 shown in FIG. 37 instead of the shift register SFTR1 shown in FIG.

  The input data buffer 26D receives write data and parity data via the data input terminals DI (DI0 to DI7) and the parity data input terminals DIP (DIP0 to DIP3), and receives the write data lines DW0-7 and parity data lines DWP0-3. Output to. The input data buffer 26D is the same circuit as the input data buffer 26 shown in FIG. 5 except that it receives 4-bit parity data via the parity data input terminal DIP.

  The output data buffer 28D receives the read data OD (OD0-7) and parity data ODP (ODP0-3) received from the output data control unit 36 during the read operation, as data output terminals DO (DO0-7) and parity data output terminals DOP ( Output to DOP0-3). The output data buffer 28D is the same circuit as the output data buffer 28 shown in FIG. 5 except that 4-bit parity data ODP is output to the parity data output terminal DOP.

  The input data control unit 34D converts the parallel write data DW (DW0-7, DWP0-3) into serial input data ID (ID0-7, DWP0-3) in the program operation PGM during the write operation and the preprogram operation PPGM during the erase operation. Output sequentially to the amplifier AMP as IDP0-3). Further, the input data control unit 34D activates the write control signal IOWR (any of IOWR0 to IOWR11) corresponding to the input data ID supplied to the amplifier AMP to a high level, and the read control signal IORD not corresponding to the input data ID. (All except one of IORD0 to IORD11) are activated to high level. The write control signal IOWR8-11 and the read control signal IORD8-11 are generated to control access to the memory areas I / O8-I / O11 corresponding to the parity data DWP0-3. The input data control unit 34D is the same circuit as the input data control unit 34 shown in FIG. 5 except that it outputs the write DWP0-3, the write control signal IOWR8-11, and the read control signal IORD8-11. An example of the input data control unit 34D is shown in FIG.

  The output data control unit 38D receives the output data OD0 to OD7 and ODP0 to ODP3, and outputs the received output data to the output data buffer 28D. The output data control unit 38D is the same circuit as the output data control unit 38 shown in FIG. 5 except that the output data ODP0 to ODP3, which are parity data, are output.

  The memory core 40D is the same as the memory core 40 shown in FIG. 5 except that the memory area I / O is increased from 9 to 12 (I / O0-I / O11). Memory areas I / O0-I / O7 hold data received at data input terminals DI0-DI7, and memory areas I / O8-I / O11 hold parity data received at parity data input terminals DIP0-DIP3. Since the number of memory areas I / O increases, the number of amplifiers AMP, the number of column switches YSW, and the like increase. Accordingly, the number of control signals such as the column selection signal YSEL generated by the column control circuit YSELCNT and the like increases.

  FIG. 43 shows an example of the input data control unit 34D shown in FIG. The input data control unit 34D increases the number of bits of the internal data signal IDI0-11, the skip signal SSKIP0-11, and the output signal OUT0-11 as the number of bits of the write data DW (DW0-7, DWP0-3) increases. is doing. For this reason, the number of stages STG of the shift register SFTR1 is twelve. The other configuration of the input data control unit 34D is the same as that of the input data control unit 34 shown in FIG.

  FIG. 44 shows an example of a system SYS on which the above-described semiconductor memory MEM is mounted. Detailed description of the same elements as those in FIG. 41 is omitted. The system SYS is formed by adding an error correction system ECCSYS to the system SYS of FIG. Other configurations of the system SYS are the same as those of the system SYS of FIG. That is, the system SYS includes at least a part of a microcomputer system such as a portable device.

  The error correction system ECCSYS has a parity generation unit and a data reproduction unit. The parity generation unit receives write data WD0-WD7 for writing to the semiconductor memory MEM from the system bus SBUS and outputs the data input signal DI0-7 to the semiconductor memory MEM. In addition, the parity generation unit generates parity data input signals DIP0-3 using the write data WD0-WD7 and outputs them to the semiconductor memory MEM. Then, the write operation of the memory cell MC corresponding to the logic 0 signal among the data input signals DI0-7 and the parity data input signals DIP0-3 is executed.

  The data reproducing unit receives the data output signals DO0-7 and the parity data output signals DOP0-3 from the semiconductor memory MEM during the read operation of the semiconductor memory MEM. The data reproducing unit corrects errors included in the data output signals DO0-7 using the parity data output signals DOP0-3, and outputs them to the system bus SBUS as read data signals RD0-7. That is, the data reproducing unit reproduces any of the data output signals DO0-7 that cannot be read from the memory cell MC based on the data output signals DO0-7 and the parity data output signals DOP0-3 by the write operation or the erase operation. To do.

  When the semiconductor memory MEM is executing any one of the program verify operation PGMV, the program operation PGM, the preprogram verify operation PPGMV, the preprogram operation PPGM, and the program verify operation PPGMV, the error correction system ECCSYS is in which memory area I / O It cannot be determined whether or not a write or erase operation is being performed. That is, the error correction system ECCSYS cannot determine which bit of the data output signal DO0-7 has an error due to the write operation or the erase operation. However, in this embodiment, 1-bit error detection and error correction in the data output signal DO0-7 can be executed by adding 4-bit parity data to 8-bit data.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, even when the semiconductor memory MEM does not have the parity generation unit 32 and the data reproduction unit 38 shown in FIG. 5, the error correction system ECCSYS is formed on the system SYS, so that the write operation and the erase operation are performed. A read operation can be performed during.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 ... Clock buffer; 12 ... Command decoder; 14 ... Address buffer; 16 ... State machine; 18, 18B ... Timing control part; 20, 20A ... Address control part; 22, 24 ... Address predecoder; 28, 28D... Output data buffer; 30... Output buffer; 32... Parity generation unit; 34, 34B, 34D ... Input data control unit; , 40D, memory core, AMP, amplifier, AMPCNT, amplifier control circuit, ARY, memory cell array, CT, cell transistor, DT, data line, DW, write data, DWP, parity data, ECCSYS, error correction system, ERS, internal Erase operation; ERSV ... Erase verify IDCNT Input data control unit I / O Memory area MBLK Memory block MC Memory cell MEM Semiconductor memory PGM Program operation PGMV Program verify operation PPGMV Preprogram verify operation RASEL2 RD ... Read operation; RDC ... Read command; RRPDA ... Row predecode address signal; RSW1, RSW2 ... Read switch; SEC ... Sector; SERR ... Sector error signal; SFTR1, SFTR2 ... Shift register; Selection control circuit; SSW, sector switch; SW, switch unit; SWCNT, switch control unit; SYS, system; WBSEL, write bit selector, WDEC, word decoder, WDRV,. Dodoraiba; WL ‥ word line; WRC ‥ write command; WRPDA ‥ row predecode address signals; WSW1, WSW2 ‥ write switch; YSELCNT ‥ column control circuit; YSW ‥ column switch

Claims (13)

A plurality of memory blocks having a plurality of memory areas including memory cells that hold a plurality of bits of write data and parity data of the write data for each bit;
A plurality of data lines corresponding respectively to the bits of the write data and the parity data;
A first write switch and a second write switch connected in series between each memory region corresponding to each data line and each data line;
A first read switch and a second read switch connected in series between each memory region corresponding to each data line and each data line;
In response to a write command, in order to sequentially write the write data and the parity data to a write memory block that is one of the memory blocks, the parallel write data and the parity data are sequentially supplied to the corresponding data lines. An input data control unit for executing an input operation to be performed;
When the input operation is executed, the first write switch corresponding to the write memory block is turned on, and the first data switch corresponding to the write data line corresponding to the data line to which the write data and the parity data are sequentially supplied is supplied. In response to a read command, the first read switch corresponding to a read memory block that is one of the memory blocks excluding the write memory block is turned on. In order to read data from the memory area corresponding to the read data line, which is the data line to which the write data and the parity data are not supplied, from the memory area of the read memory block to the data line, The first corresponding to the read data line The semiconductor memory characterized by comprising a switch control unit that performs a second switching operation for turning on the read switch in parallel with the first switch operation. In the write operation, a program operation for sequentially writing the write data and the parity data to the write memory block and a program verify operation for confirming that the write data and the parity data have been written to the write memory block are executed. An operation control unit for controlling the operation of the input data control unit and the operation of the switch control unit,
The semiconductor memory according to claim 1, wherein the switch control unit executes the first switch operation when the program operation and the program verify operation are executed. The switch control unit has a write control signal for turning on the second write switch, and a read control signal for turning on the second read switch, each having a logic opposite to the logic of the write control signal. The semiconductor memory according to claim 1, further comprising: a signal generation circuit that generates A plurality of word lines wired in common to the memory areas of the memory blocks and connected to the memory cells;
An address buffer for receiving a block address signal indicating the memory block and a row address signal indicating the word line in each memory block;
A write decode circuit that holds and decodes the row address signal received together with the write command and generates a write decode address signal;
A read decode circuit that holds and decodes the row address signal received together with the read command and generates a read address decode signal;
A plurality of word decoders each provided corresponding to the memory block and selected according to the block address signal;
Each of the word decoders
An address selector that is activated in response to the block address signal, selects the write decode address signal in response to the write command, and selects the read decode address signal in response to the read command;
A word line driver that selects one of the word lines in response to the write decode address signal or the read decode address signal selected by the address selector;
The semiconductor memory according to claim 1, further comprising: In response to an erase command for erasing data held in an erase memory block which is one of the memory blocks, a pre-program operation for writing data to all the memory cells in the erase memory block, A pre-program verify operation for confirming that data has been written to all the memory cells, an internal erase operation for erasing data written to all the memory cells of the erase memory block, and all of the erase memory blocks An operation control unit for controlling an operation of the input data control unit and an operation of the switch control unit to execute an erase verify operation for confirming that data of the memory cell is erased;
Address control for sequentially generating internal row address signals indicating the word lines in the erase memory block when the pre-program operation and the pre-program verify operation are executed and when the erase verify operation is executed With parts,
The write decode circuit holds and decodes the internal row address signal when the pre-program operation and the pre-program verify operation are executed and when the erase verify operation is executed, and a write decode address signal Produces
The input data control unit performs the input operation to sequentially write the write data and the parity data to the erase memory block during the pre-program operation,
5. The semiconductor memory according to claim 4, wherein the switch control unit executes the first switch operation when the pre-program operation, the pre-program verify operation, and the erase verify operation are executed. The operation control unit generates an address clock for each completion of the pair of the pre-program operation and the pre-program verify operation and for each erase verify operation,
The address control unit generates the next internal row address signal in response to the address clock,
The input data control unit performs completion of the pair of the pre-program operation and the pre-program verify operation for all the memory cells in each memory region, and the erase verify operation for all the memory cells in each memory region. In response to each of the completion, the data line for supplying the write data or the parity data is switched,
The switch control unit completes a pair of the pre-program operation and the pre-program verify operation for all the memory cells in each memory region, and completes the erase verify operation for all the memory cells in each memory region. The semiconductor memory according to claim 5, wherein the second write switch circuit that is turned on is switched in response to The semiconductor memory according to claim 6, wherein the switch control unit turns off all the second write switches and turns on all the second read switches during the internal erase operation. The error control circuit for invalidating the read command when an address signal received together with the read command indicates the write memory block is provided. Semiconductor memory. The semiconductor memory according to claim 8, further comprising an error terminal that outputs an error signal to the outside of the semiconductor memory when the read command is invalidated by the error control circuit. 10. The switch controller according to claim 1, wherein the switch controller turns off all the second write switches and turns on all the second read switches during a standby period in which the write command is not received. The semiconductor memory according to any one of the above. A parity generator for generating the parity data of the write data received at a data input terminal;
A data reproducing unit that reproduces data that cannot be read from the memory cell based on the data read to the read data line by supplying the write data or the parity data to the write data line; The semiconductor memory according to claim 1, wherein the semiconductor memory is a semiconductor memory. A semiconductor memory according to any one of claims 1 to 11, and
And a controller for controlling access to the semiconductor memory. A semiconductor memory according to any one of claims 1 to 10, and
A controller for controlling access to the semiconductor memory;
A parity generation unit that generates the parity data of the write data received from the controller and supplies the generated parity data to the semiconductor memory;
Data that cannot be read from the memory cell by the write data or the parity data being supplied to the write data line is read to the read data line and reproduced based on the data received from the semiconductor memory A system comprising: a playback unit.

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