JPH09205372A - Code correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce table capacity and to shorten processing time, regarding a code correction device correcting the code errors in transferred data. SOLUTION: A 4-bit conversion is performed for the I information on the received data of a 5-bit length which is received and stored in a reception buffer 22 by a conversion pattern in a 5-4 bit code conversion part 24. Based on this information, a reception table 26 performs a cyclic code calculation for an IDC(identification code) as fixed data in a cyclic code calculation part 28 and generates an FCS(frame check sequence). After the table data including this FCS is converted into 5-bit in a 4-5 bit code conversion part 29, a hamming distance is calculated in the hamming distance arithmetic part 23 with the buffer data from the reception buffer 22 and a control part 25 makes data valid data when this hamming distance value is in an allowable range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code correction device for correcting a code error in transferred data.

[0002]

2. Description of the Related Art In recent years, in data communication, error correction has been performed by adding data of an FCS calculation unit (frame check sequence) to a frame of transmission data, and error correction can be performed efficiently and at high speed. Required.

Here, FIG. 5 shows an explanatory view of a conventional transfer data format. FIG. 5 shows one frame of the transfer data 11 in the high level data link control procedure, and the leading and trailing fields 12a and 12b are indicated by the flag sequence (F). In addition, a field 13 indicating an address and control IDC (ID code) from the leading end portion, a field 14 indicating information (I), and F
And a field 15 indicating CS. For example, the address and control of the IDC 13 are each 8 bits, the information (I) 14 is an arbitrary bit length, and the FCS 15 is 16 bits.
Shown in bits.

The FCS 15 is a 16-bit sequence for frame transmission error detection, and the generator polynomial X ¹⁶ + X
^It shows the result of calculation by ¹² + X ⁵ +1. IDC13
And I14 are the calculation targets. That is, on the transmission side, the IDC 13 and I 14 generate the FCS 15 by cyclic code calculation and transfer it. Then, on the receiving side, among the received data received, the IDC 13 and the received F
An error code signal is corrected bit by bit using a bit correction table, which will be described later, so that CS15 matches.

As described above, the received data is conventionally subjected to error detection and the error detected is invalid data. However, by performing correction using the FCS 15 described above, a frame is generated by a periodic noise signal. It is expected that a large improvement in reception stability can be expected when there is a high probability that some of the data will be destroyed or when correction processing of several bits is performed.

By the way, when error correction is performed by FCS,
The cyclic code calculation values of the entire frame for all n-bit error patterns are prepared as a table, and the error bits of the received data are referred to the table to obtain the corrected data. As another method, each bit of the received data is sequentially changed so that the FCS is changed in the order of shorter Hamming distance.
There is a method of verifying.

Here, the Hamming distance means the number of different bits in corresponding bit strings in two bit strings having the same length. Therefore, the FCS with a predetermined number of bits
Error correction when the number of different bits (Hamming distance) is in the range of the predetermined number of bits when the correction processing is performed by, and an error occurs when the number of different bits exceeds the predetermined number of bits. It is the end.

[0008]

However, performing error correction by FCS requires a table of all n-bit number error patterns, and all the error patterns are also set for each Hamming distance. There is a problem in that the number of settings in the table becomes huge and the memory capacity becomes large, and there is a problem in that it is difficult to realize while correction processing takes time and the processing speed is limited.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a code correction device which reduces the table capacity and the processing time.

[0010]

In order to solve the above-mentioned problems, according to claim 1, received data including an FCS (frame check sequence) is used to identify information and arbitrary information included in the received data. In the code correction device for detecting and correcting the error code, the received data is obtained by dividing the predetermined bit length in the initial unit of the first bit length into the second bit length in each unit. And a first bit conversion means for converting predetermined information of the received data into a first bit length according to a conversion pattern to be instructed, and a cyclic code is calculated by using the converted information of the first bit length to calculate the FCS. FCS calculation means for generating
Second bit conversion means for converting the corrected reception data of the first bit length including the generated FCS from the CS calculation means into a second bit length, the correction reception data from the second bit conversion means, and Hamming distance calculation means for calculating the Hamming distance from the received data of the second bit length when received, and control means for making the effective information a Hamming distance value from the Hamming distance calculation means within a preset range. , And the code correction device is configured.

As described above, according to the first aspect of the invention, the first
Of the received data in which the bit length has been converted to the second bit length, predetermined information is converted by the first bit conversion means into the first bit length based on the conversion pattern, and based on this, the FCS calculation means performs cyclic code calculation. To generate an FCS,
Hamming distance calculation is performed between the corrected reception data including the converted data having the second bit length converted by the second bit conversion means and the received data having the second bit length when received. Use valid information when it is within the allowable range. As a result, the conversion pattern table used for error correction can be set in a combination according to the second bit length, the table capacity can be reduced, and the processing time required for error correction can be shortened. Is possible.

[0012]

1 is a block diagram of an embodiment of the present invention.
A block diagram is shown. FIG. 1 is a block diagram of the code correction device 21.
FIG. 7 is a diagram showing the data received, and the data shown in FIG.
The first bit length of each mat, for example, 4 bit length
IDC (ID as fixed data that is unit identification information
Code), information (I) that is optional information, and FCS (frame
The frame check sequence) is set to 5 bits which is the second bit length.
IDC transmitted after being converted to₁, I₁, FC
S₁It is. And the IDC which is the received identification information
₁, Information I which is arbitrary information₁And FCS₁Is S described later
Once stored in the reception buffer 22 via the / P return unit 22a
And a Hamming distance calculation unit that is a Hamming distance calculation unit.
23. It is also stored in the receive buffer 22.
Out of the things I ₁Is the only first bit conversion means
It is sent to the 5-4 bit code conversion unit 24 (described later).
You.

The 5-4 bit code conversion unit 24 issues a bit conversion instruction (steps 1, 2, ...
According to the instruction), I ₁ is converted into 4-bit I and sent to the reception table 26. In addition, the reception table 26
Shows the IDC of 4 bits as fixed data.
The received I is sent to the cyclic code calculation unit 28, which is a cyclic code calculation unit, to perform cyclic code calculation, and the result is received. The reception table 26 and the cyclic code calculation unit 28
Constitutes the FCS calculation means.

Then, in the reception table 26, the received cyclic code calculation value is replaced with FCS, and the table data (IDC, I and FCS) which is the corrected reception data is converted into the second value.
Is sent to the 4-5 bit code conversion unit 29, which is the conversion means of the above, and converted into 5 bits. 4-5 bit code conversion unit 29
Then, the supplied table data is converted into a 5-bit code and sent to the Hamming distance calculator 23.

The Hamming distance calculation unit 23 compares the buffer data, which is stored in the reception buffer 22 and is sent as the received data of 5 bits, with the table data sent from the reception table 26. Then, the Hamming distance is calculated and the value is sent to the control unit 25. In the control unit 25, a preset allowable number of bits,
The result sent from the Hamming distance calculation unit 23 is compared, and if the comparison result is not within the allowable range, the 5-4 bit code conversion unit 24 is instructed to bit-convert the I of the reception buffer 22 for the next pattern. And repeat.

If the comparison result is within the allowable range, it is determined that the code has been corrected, and the 4-bit I and FCS in the reception table 26 are sent to the valid data table 27 to be temporarily stored and the valid data is stored. The data table 27 sends the IDC, code-corrected I and FCS to the control unit 25. Then, the corrected 4-bit received data is output from the control unit.

Here, FIG. 2 shows an explanatory diagram of the bit conversion in the present invention, and FIG. 3 shows an explanatory diagram of the bit conversion table of FIG. FIG. 2 is a block diagram of 4-5 bit conversion on the transmission side. In FIG. 2, on the transmission side, the original transmission data (for example, 16 bits) is divided into 4-bit units, and this is input to the bit conversion table 31 as 4-bit parallel data to convert it into 5-bit parallel data, and P / S (parallel / serial) converter 32
Output to The P / S converter 32 converts the 5-bit parallel data into 5-bit serial data and transmits it. On the receiving side, the received 5-bit serial data is S / P
The (serial / parallel) return unit 22 a returns the parallel data and stores it in the reception buffer 22.

At this time, the bit conversion table 31 shows the correspondence for converting a hexadecimal 4-bit code as 4-bit input data into a hexadecimal 5-bit modulation code (conversion data) as shown in FIG. ing. This correspondence is H
The ratio of / L (“1” / “0”) is set to 2: 3 or 3: 2, and is appropriately set so as to have 2 to 4 inflection points. The conversion table 31 shown in FIG. 3 is the 5-4 bit conversion table 24 ₂ and the 4-5 bit conversion table 29 _{2 of FIG.}
But also.

In the 5-4 bit code conversion unit 24, the 5 bit data I sent from the reception buffer 22 is
Converted to 4 bits by the 5-4 bit conversion table 24,
This 4-bit data is sent to the reception table 26.
Then, in the 4-5 bit conversion unit 29, the reception table 2
4-bit table data sent from
It is converted into 5 bits by the bit conversion table, and this 5-bit table data is sent to the Hamming distance calculation unit 23.

Therefore, returning to FIG. 1, when the allowable value of the Hamming distance set by the control unit 25 is set to 2, for example, the error pattern table 27 provided in the reception table 26 is
The Hamming distance calculation unit 23 does not have 8 or more through the target 5-bit demodulation code, and the table capacity only for this is sufficient. By the way, in the case of a 4-bit demodulation code, there are a total of 14 error patterns, that is, 4 patterns at the hamming distance 1 and 10 patterns at the hamming distance 2, and the table capacity can be reduced by the 5 bits. Is something that can be done.

Therefore, FIG. 4 shows a flowchart of the error correction of FIG. In FIG. 4, the code correction device 2 is also used.
1 is a standby state for receiving transmission data from the transmission side (step (S) 1), and when it is received, the reception buffer 22
To be stored. Among them, 5 bits I ₁ is converted into 4 bits by the 5-4 bit code conversion unit 24 according to the conversion pattern instructed by the control unit 25 and sent to the reception table 26 (S2). The 4-bit conversion of I is performed with all the conversion patterns until it falls within the range (S3).

In the reception table 26, I from the 5-4 bit conversion section 24 and IDC as fixed data are sent to the cyclic code calculation section 28 to perform cyclic code calculation (S4), and the result is replaced with FCS. The table data including this FCS is converted into 5 bits by the 4-5 bit conversion unit 29 (S5). The Hamming distance calculation unit 23 compares the table data converted into 5 bits with the buffer data from the reception buffer 22, calculates the Hamming distance, and sends the result to the control unit 25 (S6).

In the control unit 25, the Hamming distance calculation unit 25
It is determined whether or not the Hamming distance from is within the set allowable value range (S7).
And FCS are sent to the valid data table 27, and further IDC, I, and FCS are sent to the control unit 25 to be output, and the processing ends. If the Hamming distance is out of the allowable range, the 5-4 bit code converting unit 24 is instructed to perform 4-bit conversion of I in the next conversion pattern in the ascending order of the Hamming distance and repeats (S2 to S7). ).

If the Hamming distance is out of the allowable range even in the conversion with all the conversion patterns (S
3), the error ends. Thus, the error correction by the reception table 26 can be performed at high speed by using the error pattern table 27 having a small table capacity as described above.

[0025]

As described above, according to the first aspect of the present invention, the predetermined information in the received data obtained by converting the first bit length into the second bit length is converted by the first bit conversion means based on the conversion pattern. Converted to the first bit length, and based on this, F
CS calculation means performs cyclic code calculation to generate FCS,
The corrected received data including the FCS is converted into the second bit length by the second bit conversion means, and a Hamming distance calculation is performed with the received data of the second bit length when received, and the control means performs the Hamming distance. By setting the value as valid information when the value is within the allowable range, it is possible to set the table used for error correction of the FCS operation unit in a combination according to the second bit length, and to reduce the table capacity. At the same time, the processing time required for error correction can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of bit conversion in the present invention.

FIG. 3 is an explanatory diagram of a bit conversion table in FIG.

FIG. 4 is a flowchart of the code correction of FIG.

FIG. 5 is an explanatory diagram of a conventional transfer data format.

[Explanation of symbols]

 21 code correction device 22 5-4 bit conversion table 23 Hamming distance calculation unit 24 FCS calculation unit 25 memory 26 control unit 27 error pattern table 31 bit conversion table 32 P / S conversion unit 33 S / P conversion unit

Claims (1)

[Claims] 1. FCS (frame check sequence)
In a code correction device that uses the FCS to detect and correct an error code of identification information and arbitrary information included in the received data from the received data including the received data, the received data has a predetermined bit length equal to the initial first bit. A unit divided into length units is converted into a second bit length for each unit, and first information for converting predetermined information of the received data into a first bit length according to an instructed conversion pattern.
Bit conversion means, FCS operation means for calculating a cyclic code using the converted information of the first bit length, and FCS operation means for generating an FCS; Second for converting the corrected reception data into the second bit length
Bit conversion means, hamming distance calculation means for calculating a hamming distance from the corrected reception data from the second bit conversion means, and the reception data having the second bit length when received, and the hamming distance calculation A code correction device comprising: a control unit that uses, as effective information, a Hamming distance value from the unit within a preset range.