JPH09205102A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine the distance between a base layer and a base electrode (base lead-out electrode) independently of the diffusion depth of a graft base layer, and realize satisfactory production cost. SOLUTION: In a first process, an offset insulating film pattern 17a is formed on a region where a base layer is to be formed, of an element forming region 15 provided on a semiconductor substrate 10, and a part of the element forming region 15 is exposed to a lateral portion of the offset insulating film pattern 17a. In a second process, after a semiconductor layer 20 which is to be a base lead-out electrode is formed in a state of being connected to the exposed element forming region 15, conductive impurity is introduced by ion implantation into the element forming region 15 immediately below the offset insulating film pattern 17a, thereby forming a base connecting layer 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including at least a vertical bipolar transistor.

[0002]

2. Description of the Related Art In a device forming region laterally surrounded by a device isolation region, a graft base layer is formed by impurity diffusion from a semiconductor layer such as polysilicon, and a sidewall insulating film formed in an emitter opening. A structure of a bipolar transistor having an emitter extraction electrode which is separated from the semiconductor layer by a (so-called sidewall insulating film) is known. An example of such a structure will be described with reference to FIG.

As shown in FIG. 5, a conventional bipolar transistor 100 has the following structure. That is, the n-type epitaxial layer 112 is formed on the p-type silicon substrate 111, and the buried layer 113 for taking out the collector is formed in a part between them to form the base extraction electrode 121 on the front surface side. Are formed. The graft base layer 122 is formed by diffusion from the base extraction electrode 121 to the semiconductor substrate 110. Here, the patterning of the base extraction electrode 121 on the base layer side is performed by forming the opening 123. A sidewall insulating film 124 is formed on the sidewall of the opening 123. A polysilicon layer 125 connected to the semiconductor substrate 110 is formed on the sidewall insulating film 124. This polysilicon layer 12
5 to the semiconductor substrate 110 to diffuse the base layer 126
And an emitter layer 127 are formed. Further, between the base layer 126 and the graft base layer 122, a high-concentration base connecting layer 128 is formed so as to be connected to each. Further, a collector extraction diffusion layer 114 connected to the buried layer 113 is formed.

Bipolar transistor 100 having the above structure
Then, by separating the emitter extraction electrode made of the polysilicon layer 125 and the base extraction electrode 121 by the sidewall insulating film 124, the base resistance and the base-collector capacitance are reduced.

On the other hand, in the bipolar transistor 100 described above, since the distance between the polysilicon layer 125 serving as the emitter extraction electrode and the base extraction electrode 121 is reduced, the emitter layer 127 and the high-concentration base connection layer 128 are separated. Get closer. Then, when the transistor operates, particularly when a reverse bias is applied between the emitter and the base, the electric field strength increases in the vicinity of the emitter layer 127 and the high-concentration base connecting layer 128. Therefore, charged particles accelerated by the electric field and further charged particles avalanche doubled in the high electric field region are injected into the adjacent region of the emitter layer 127 to generate an interface state,
It was increasing the recombination current.

Therefore, there is a means for preventing an increase in electric field strength in a region near the emitter layer in the state where a reverse bias is applied between the emitter and the base.
No. 6,086,045. The outline will be described below with reference to FIG. FIG. 6 shows a method of manufacturing a vertical npn bipolar transistor having a structure in which a polysilicon layer to be an emitter extraction electrode and a polysilicon layer to be a base extraction electrode are separated by using a sidewall insulating film.

As shown in (1) of FIG. 6, an n ⁺ type buried layer 212 is formed on the p type silicon substrate 211, and an n type epitaxial layer 213 is further formed on the p type silicon substrate 211. To form. Then, the element isolation region 214 having a so-called trench structure is formed in the n-type epitaxial layer 213 by selective anisotropic etching and a technique of burying an insulating film. The element formation region 215 is separated by the element separation region 214. The deep element isolation region 214 is formed so that the inside thereof is filled with polysilicon 216 as shown in the figure. Also forming the n ⁺ -type collector contact diffusion layer 241 to be connected to the n ⁺ -type buried layer 212.

Next, chemical vapor deposition (hereinafter referred to as CVD,
By CVD, an abbreviation of Chemical Vapor Deposition) is used to form a silicon oxide film 217 on the entire surface of the n-type epitaxial layer 213. Next, a resist film 218 is formed on the silicon oxide film 217, and the resist film 21
After selectively exposing No. 8, processing such as development and baking is performed. Then, the first opening 219 is formed in the silicon oxide film 217 by anisotropic etching using the resist film 218 as a mask. This first opening 219
Is formed so that a part thereof overlaps with the element isolation region 214 and extends to the element formation region 215 side by the width L ₁ . Therefore, at the bottom of the first opening 219, the n-type epitaxial layer 21 that is the surface of the substrate is formed.
The surface of _No. 3 is exposed with the width L ₁ .

After that, the resist film 218 is removed. Next, as shown in (2) of FIG. 6, a polysilicon layer 220 is formed on the entire surface by, eg, CVD. The polysilicon layer 220 covers the silicon oxide film 217 in which the first opening 219 is formed, and is connected to the surface of the n-type epitaxial layer 213 at the bottom of the first opening 219. Subsequently, the surface of the deposited polysilicon layer 220 is flattened, and then, for example, boron ions (B ⁺ ) are ion-implanted into the polysilicon layer 220 as impurities. After this ion implantation, the polysilicon layer 220 is patterned by forming a resist mask by a lithography technique and reactive ion etching using the resist mask. After performing the above patterning, a silicon oxide film 221 is formed on the entire surface. And
A resist film 222 is formed by a lithography technique, and an opening 223 is formed in the resist film 222.
The opening 223 is formed in a pattern that exists above the inside of the silicon oxide film 217 on the element forming region 215, and is formed, for example, by a width L ₂ from the end of the first opening 219 to the inside.

Next, as shown in FIG. 6C, the silicon oxide film 221, the polysilicon layer 220 and the silicon oxide are anisotropically etched by reactive ion etching using the resist film 222 as a mask. A second opening 224 penetrating the film 217 is formed in a state where the opening shape of the opening (223) formed in the resist film (222) is transferred. In the formation of the second opening 224, a part of the silicon oxide film 217 is formed on the side of the second opening 224 with a width L ₃
It remains with (≈L ₂ ).

Thereafter, by ion implantation, an n ⁺ type deep impurity region 225 is formed in the vicinity of the interface between the p type silicon substrate 211 and the n type epitaxial layer 213 below the region to be the base layer. Furthermore, by the ion implantation method,
A connection base layer 226 for connecting the base layer (229) and the graft base layer (231) is formed.

Next, a silicon oxide film for forming a sidewall insulating film is deposited on the entire surface by the CVD method. Then, etch back the silicon oxide film,
A sidewall insulating film 227 to be a sidewall insulating film is formed on the sidewall of the second opening 224. In the region sandwiched by the sidewall insulating film 227, the connection base layer 22 is formed.
The n-type epitaxial layer 213 on which 6 is formed is exposed.

Next, as shown in FIG. 6D, a polysilicon layer 228 is formed on the sidewall of the sidewall insulating film 227 by, for example, the CVD method. Then, an n-type impurity and a p-type impurity are ion-implanted into the polysilicon layer 228 by an ion implantation method. Then, a base layer 229 and an emitter layer 230 are formed by diffusing impurities from the polysilicon layer 228. Further, the graft base layer 231 is formed by diffusing impurities from the polysilicon layer 220.

The following steps will be described by omitting the drawings. First, a contact hole for taking out the collector and the base is formed, and then a base electrode, an emitter electrode and a collector electrode are formed to complete the bipolar transistor. By forming a boron silicate glass (BSG) layer instead of the silicon oxide layer 117,
By forming the connecting base layer 126 by diffusion from the boron silicate glass (BSG), it becomes possible to secure the connection between the graft base layer and the base layer. Further, in the configuration in which the silicon oxide layer 117 is a combination of a thin thermal oxide film and a CVD silicon oxide film,
It is possible to suppress the increase in the film thickness difference due to the accelerated oxidation.

[0015]

However, when the bipolar transistor is manufactured by the conventional technique described above, the base connection layer (226) and the base extraction electrode (220) formed in the second opening (224). And need to be connected. When connecting to the graft base layer (231) formed by diffusion from the base extraction electrode (220), it is necessary to set so as to satisfy the relationship of distance L ₂ ≦ [depth of the graft base layer (231)]. . Therefore, the distance L ₂ has an upper limit. An excessive increase is not desirable because an increase in the diffusion depth of the graft base layer (231) causes a decrease in collector-base breakdown voltage and an increase in collector-base junction capacitance. Therefore, it is usually necessary to set L ₂ ≦ 0.3 μm to 0.5 μm. Therefore, there is a limit in improving the breakdown voltage of the emitter / base.

As disclosed in JP-A-2-159726, the silicon oxide film (217) is formed of a boron silicate glass (BSG) layer, and the base connection layer (226) is formed by diffusion from the BSG layer. Although it is possible to increase the distance L ₂ by forming)), the resistance value of the polysilicon layer on which the base extraction electrode (220) is formed by the outdiffusion of boron from the BSG layer is increased by that method. There was a problem of fluctuation. That is,
This is because the polysilicon layer is also used as a resistor. In order to prevent this outward diffusion, it is necessary to form an impurity diffusion prevention layer, which leads to an increase in manufacturing cost.

The present invention has been made to solve the above-mentioned problems, and determines the distance between the base layer and the base electrode (base extraction electrode) independently of the diffusion depth of the graft base layer, and the production cost is improved. It is an object of the present invention to provide a method for manufacturing a bipolar transistor having excellent characteristics.

[0018]

The present invention is a method of manufacturing a semiconductor device, which has been made to achieve the above object. That is, in the first manufacturing method, in the first step, the offset insulating film pattern is formed on the region where the base layer of the element formation region provided on the semiconductor substrate is formed, and at the side of the offset insulating film pattern. A part of the element formation region is exposed. Then, in the second step, after forming a semiconductor layer to serve as an extraction electrode in a state of connecting to the exposed element formation region, a conductive impurity is introduced into the element formation region directly below the offset insulating film pattern by an ion implantation method. To form the base connection layer.

In the second manufacturing method, in the first step, an element isolation region is formed in the semiconductor substrate to provide a plurality of element formation regions, and then the first insulating film and the second insulating film are formed on the semiconductor substrate. And are laminated. Then, in a second step, the second insulating film on the first element formation region in which the vertical bipolar transistor of the plurality of element formation regions is formed is removed, and subsequently, the base layer of the first element formation region is removed. Forming an offset insulating film pattern with the first insulating film on the region where the
In addition, a part of the first element formation region is exposed on the side of this offset insulating film pattern. At the same time, the second insulating film and the first insulating film on the second element formation region in which the lateral bipolar transistor of the plurality of element formation regions is formed are formed.
At least one opening is formed by patterning the insulating film. Further, in a third step, after forming a semiconductor layer in a state of connecting to the exposed first element formation region and second element formation region, the first element formation region directly below the offset insulating film pattern is formed by an ion implantation method. To form a base connection layer by selectively introducing conductive impurities,
It is a manufacturing method including each step.

In the third manufacturing method, in the first step, an element isolation region is formed on the semiconductor substrate to provide a plurality of element formation regions, and then a first insulating film is formed on the semiconductor substrate. Then, in a second step, an offset insulating film pattern is formed of the first insulating film on a region of the first element forming region in which the bipolar transistor is formed, of the plurality of element forming regions, in which the base layer is formed, and The first insulating film on the side of the offset insulating film pattern is removed to expose a part of the first element formation region. At the same time, the opening is formed by removing the first insulating film on the second element formation region in which the capacitor is formed among the plurality of element formation regions. Further, in a third step, a second insulating film is formed in the opening on the second element formation region. Then in a fourth step, at least the exposed first
After forming a semiconductor layer to be connected to the element forming region and the second insulating film, a conductive impurity is selectively introduced into the first element forming region immediately below the offset insulating film pattern by an ion implantation method to form a base connection. It is a manufacturing method including each step of forming a layer.

In any of the manufacturing methods described above, the base connection layer is formed by introducing conductive impurities into the element forming region directly below the offset insulating film pattern by the ion implantation method, and then the offset insulating film pattern is formed. Even if the base layer formed in the element forming region immediately below the and the graft base layer formed in the element forming region near the side portion of the offset insulating film pattern are widely separated, Connected by a connection layer.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION An example of the first embodiment of the present invention will be described.
This will be described with reference to the manufacturing process diagram of FIG. In the drawings, as an example, a method of manufacturing a vertical npn bipolar transistor will be described.

As shown in FIG. 1A, for example, by solid phase diffusion, a second conductivity type (hereinafter referred to as n ⁺ type) is formed on the upper layer of the first conductivity type (hereinafter referred to as p type) silicon substrate 11. To do
⁺ Indicates a high concentration), and the buried layer 12 is formed. Further, the n-type epitaxial layer 13 is formed on the p-type silicon substrate 11 by the epitaxial growth method. At this time, the n ⁺ type buried layer 12 is slightly diffused to the lower side of the n type epitaxial layer 13.
In this way, the semiconductor substrate 10 including the p-type silicon substrate 11 and the n-type epitaxial layer 13 is formed. Then, the n-type epitaxial layer 13 is formed by selective anisotropic etching and an insulating film burying technique.
Then, for example, an element isolation region 14 having a so-called trench structure is formed. The element formation region 1 is formed by the element isolation region 14.
5 are separated. As shown in the figure, the deep element isolation region 14 may be formed so that the polysilicon layer 16 is embedded therein. Further, by selective ion implantation, n ⁺ which is connected to the n ⁺ type buried layer 12 is connected.
A collector collector diffusion layer 41 of the mold is formed.

Next, the first step is performed. In this process, chemical vapor deposition (hereinafter referred to as CVD, CVD is Chemical V
The first insulating film 17 is formed on the entire surface of the epitaxial layer 13 by the apour deposition method. This first
The insulating film 17 is made of a film having a diameter of silicon oxide, for example, a film made of boron silicate glass (BSG). Or a normal silicon oxide film formed by the CVD method, or a silicon oxide film formed by thermal oxidation and C
It is also possible to form the film by stacking a silicon oxide film formed by the VD method.

Next, a resist film 18 is formed on the first insulating film 17. Subsequently, after selectively exposing the resist film 18, processing such as development and baking is performed. Then, the first opening 19 is formed in the first insulating film 17 by anisotropic etching using the resist film 18 as a mask. At the same time, the offset insulating film pattern 17a made of the first insulating film 17 is formed on the region where the base layer is formed.
To form The first opening 19 is formed in the element isolation region 14
And a part thereof are formed so as to overlap each other, and the element formation region 15
It is formed so as to extend to the side by a width L ₁ . This width L ₁ is determined depending on the mask alignment accuracy of lithography, and is, for example, about 0.2 μm. In this way, the offset insulating film pattern 17a made of the first insulating film 17 is formed on the element forming region 15, and the first insulating film pattern 17a is formed.
At the bottom of the opening 19, the surface of the n-type epitaxial layer 13, which is the surface of the substrate, is exposed with the width L ₁ .

After that, the resist film 18 is removed.
Hereinafter, the resist film formed as the etching mask or the ion implantation mask is to be removed after each step is completed.

Next, as shown in FIG. 1B, the semiconductor layer 20 is formed on the entire surface by, eg, CVD. The semiconductor layer 20 is made of, for example, a polysilicon layer and covers the first insulating film 17 including the offset insulating film pattern 17a in which the first opening 19 is formed, and particularly the bottom of the first opening 19 is formed. Then, the n-type epitaxial layer 13
Connect to the surface. Then, the deposited semiconductor layer 20.
The surface of is flattened.

After that, the second step is performed. In this step,
As impurities, for example, boron ions (B ⁺ ) are ion-implanted into the semiconductor layer 20. In this way, the semiconductor layer 20 containing the first conductivity type (p ⁺ type) impurities is formed. At this time, the impurities are introduced into the n-type epitaxial layer 13 directly below the first insulating film 17 by optimizing the ion implantation conditions.

For example, the film thickness of the semiconductor layer 20 is 150 n.
m, and the thickness of the first insulating film 17 is 100 nm, boron ions (B ⁺ ) are used as impurities, the implantation energy is set in the range of 5 keV to 20 keV, and the dose amount is 1 × 10 ¹⁵ pieces / cm 3. Boron is introduced into the semiconductor layer 20 by the ion implantation method set in the range of ² to 1 × 10 ¹⁶ pieces / cm ² .

At the same time, boron ions (B ⁺ ) are used as impurities, and the implantation energy is 30 keV-5.
Set in the range of 0 keV and the dose amount is 5 × 10 ¹² pieces / c
Boron was introduced into the n-type epitaxial layer 13 immediately below the first insulating film 17 by the ion implantation method set in the range of m ² to 1 × 10 ¹⁴ pieces / cm ² . The latter ion implantation method allows the base connection layer 21 to be stably formed. In the ion implantation method for forming the base connection layer 21, a mask pattern (not shown) having an opening is formed on a region where the base connection layer 21 is formed, and then this mask pattern is used as an ion implantation mask. Preferably. In this way, the base connection layer 21 is formed by ion implantation, so that the base connection layer 21 is formed without significantly increasing the number of steps and increasing the cost.

After the ion implantation, the semiconductor layer 2 is formed by forming a resist mask by a lithography technique and reactive ion etching using the resist mask.
0 is patterned. At this time, the patterned semiconductor layer 20 is formed in a state where the first opening 19 is buried and the offset insulating film pattern 17a is deposited, for example.

After the above patterning, the second insulating film 22 is formed on the entire surface. The second insulating film 22 is
For example, a silicon oxide film is used. Then, a resist film 23 is formed by a lithography technique, and an opening 24 is formed in the resist film 23. The opening 24 is
The pattern is formed so as to exist above the inside of the first insulating film 17 on the element forming region 15, and is formed inside from the end of the first opening 19 by a width L ₂ , for example. That is, the opening 23 is formed so as not to extend above the pattern of the semiconductor layer 20.

Next, as shown in FIG. 1C, the second insulating film 22 is anisotropically etched by reactive ion etching using the resist film 22 as a mask.
Then, an opening that penetrates the offset insulating film pattern 17a, that is, a second opening 25 is formed. In this etching, fine processing is possible, and the offset insulating film pattern 17a and the underlying n-type epitaxial layer 1 are formed.
Since 3 has etching selectivity, the n-type epitaxial layer 13 is not excessively etched. Therefore, the fluctuation of the base width of the base layer (intrinsic base layer) formed on the upper layer of the n-type epitaxial layer 13 is prevented. In addition, the second opening 25 formed by the above etching
In the formation of, a part of the offset insulating film pattern 17a remains on the side portion of the second opening 25 with a width L ₃ .
By the remaining offset insulating film pattern 17a,
A sufficient breakdown voltage between the graft base layer and the emitter layer, which will be formed later, is ensured.

Then, by ion implantation, an n ⁺ type deep impurity region 42 is formed in the vicinity of the interface between the n ⁺ type buried layer 12 and the n type epitaxial layer 13 below the region to be the base layer.

Next, after a silicon oxide film is formed on the entire surface by the CVD method, the silicon oxide film is anisotropically etched by etch back to form a sidewall insulating film 26 on the side wall of the second opening 25. Form. In the region sandwiched by the sidewall insulating film 26, the n-type epitaxial layer 13 in which the connection base region 21 is formed is exposed. At this time, the sidewall insulating film 2
The width of 6 may be thin because a part of the offset insulating film pattern 17a already remains and functions for separation. For example, the sidewall insulating film 26 has a width of 0.
About 2 μm is sufficient.

Then, as shown in FIG. 1D, a p-type impurity is added to the base connection layer 21 in the second opening 25 in which the sidewall insulating film 26 is formed by, for example, the CVD method. A polysilicon layer 27 containing is formed. Then, an n-type impurity is ion-implanted into the polysilicon layer 27 by an ion implantation method. Thus, the polysilicon layer 27 to be a conductive layer containing the second conductivity type (n-type) impurities is formed. Then, by performing heat treatment, the impurities in the polysilicon layer 27 are diffused into the n-type epitaxial layer 13, and the element formation region 1 is formed.
5, a p-type base layer (intrinsic base layer) 28 is formed on the n-type epitaxial layer 13, and an n ⁺ -type emitter layer 29 is formed on the p-type base layer 28.
At the same time, the p ⁺ type graft base layer 30 is formed on the n type epitaxial layer 13 by impurity diffusion from the semiconductor layer 20. Therefore, the p-type base layer 28 and the p ⁺ -type graft base layer 30 are connected by the p-type base connection layer 21.

The following steps will be described by omitting the drawings. First, a contact hole for taking out the collector and the base is formed, and then a base electrode, an emitter electrode and a collector electrode are formed to complete the bipolar transistor 1.

In the manufacturing method of the first embodiment, the offset insulating film pattern 17 is previously formed by the ion implantation method.
Since the conductive base layer 21 is formed by introducing a conductive impurity into the element forming region 15 immediately below a, the connection between the graft base layer 30 and the base layer 29 formed in the element forming region 15 is thereafter performed. Be certain. Further, in this manufacturing method, the base connection layer 21 is formed without causing a significant increase in steps and manufacturing cost. As a result, the width L ₂ of the offset insulating film pattern 17a can be set arbitrarily. For example, the width L ₂ is, for example, 0.4 μm
It can be easily increased to about 1.0 μm. Furthermore, since the base connection layer 21 is formed by ion implantation, the number of steps is small and the cost is not increased significantly. The first insulating film 17 is made of a thin thermal oxide film and C
With the configuration in which the VD silicon oxide film is combined, it is possible to suppress the increase in the film thickness difference due to the accelerated oxidation.

Next, an example of the manufacturing method of the second embodiment will be described with reference to the manufacturing process diagrams of FIGS. In the figure, the same components as those described with reference to FIG. 1 are designated by the same reference numerals. The figure shows a semiconductor device in which a vertical npn bipolar transistor, a lateral pnp bipolar transistor, and a capacitor are formed on the same semiconductor substrate.

As shown in FIG. 2A, the n ⁺ type buried layers 12 and 51 are formed on the p type semiconductor substrate 11 by, for example, solid phase diffusion. Further, the n-type epitaxial layer 13 is formed on the p-type semiconductor substrate 11 by the epitaxial growth method. At this time, the n ⁺ type buried layers 12 and 51 are slightly diffused to the lower layer side of the n type epitaxial layer 13. Then, a local oxidation method [eg, LOCOS (Local Oxidation of Silicon) method]
Thus, part of the n-type epitaxial layer 13 is oxidized to form the element isolation region 14. The element isolation region 14 may be an element isolation having a trench structure.
The element isolation region 14 serves as a first element formation region 31 which becomes a formation region of a vertical npn bipolar transistor.
The element formation region 15 (corresponding to the element formation region 15 described with reference to FIG. 1) is separated from the second element formation region 52 which is the formation region of the lateral pnp bipolar transistor, and the capacitor formation region 71 which is the region where the MIS type capacitor is formed.

Next, a mask pattern (not shown) is formed by a lithography technique, and an ion implantation method using the mask pattern is used to form a p ⁺ -type element isolation diffusion layer 91 on the lower surface side of the required element isolation region 14 by the ion implantation method. To form. Then, the mask pattern is removed. In the following description, the mask pattern used in the ion implantation method will be removed after the ion implantation step. Also,
The mask pattern used for etching is to be removed after the etching process. Furthermore, a mask pattern (not shown) by lithography, by ion implantation using the mask pattern, the epitaxial layer 13 of the n-type, the n ⁺ -type connecting the buried layer 12 of n ⁺ -type collector to form the extraction diffusion layer 41, to form an n ⁺ -type base contact diffusion layer 53 to be connected to the n ⁺ -type buried layer 51. At the same time, an n ⁺ type diffusion layer 72 which will be an electrode of the capacitor is formed on the n type epitaxial layer 13 in the capacitor forming region 71.

Next, for example, chemical vapor deposition (hereinafter referred to as CVD
That is, CVD is an abbreviation for Chemical Vapor Deposition, and the first insulating film 17 is formed on the entire surface of the epitaxial layer 13. The first insulating film 17 is made of, for example, a silicon oxide film. Next, a mask pattern serving as an etching mask is formed by a lithography technique, and the capacitor forming region 7 is formed by etching using the mask pattern.
A part of the first insulating film 17 on 1 is removed to form a capacitor opening 73.

After that, a characteristic stabilizing insulating film 90 for stabilizing the characteristics of the lateral pnp bipolar transistor is formed by, for example, 30 nm to 100 by the low pressure CVD method.
It is formed to have a constant film thickness in the range of nm. The characteristic stabilizing insulating film 90 is also used as the capacitor dielectric film of the MIS capacitor, and is formed of, for example, a silicon nitride (Si ₃ N ₄ ) film. FIG. 2A shows the state after the characteristic stabilizing insulating film 90 is formed.

Next, as shown in FIG. 2B, a mask pattern (not shown) is formed on the second element formation region 52 and the capacitor formation region 71 by the lithography technique.
After forming, the characteristic stabilizing insulating film 90 is patterned by etching using the mask pattern as a mask. As a result, the first insulating film 17 remains on the region of the first element forming region 31 where the base is formed,
A laminated film of the first insulating film 17 and the characteristic stabilizing insulating film 90 remains on the region of the second element forming region 52 where the base is formed. Further, a capacitor dielectric film 74 connected to the n ⁺ type diffusion layer 72 in the capacitor opening 72 is formed on the capacitor formation region 71. The characteristic stabilizing insulating film 90 prevents unnecessary impurities from being introduced into the base region of the lateral pnp bipolar transistor when forming the base connection layer of the vertical npn bipolar transistor.

After that, a mask pattern 91 is formed of a resist, for example, by a lithography technique. Openings 92 are formed in the mask pattern 91 on the regions where the graft base layer of the first element forming region 31 is formed and on the regions of the second element forming region 52 where the emitter and collector are formed. There is. 2B shows the state after the mask pattern 91 is formed.

Next, as shown in (1) of FIG. 3, the first insulating film 1 on the first element formation region 31 is etched by using the mask pattern (91) as an etching mask.
A first opening 19 is formed at 7. At this time, the offset insulating film pattern 17a made of the first insulating film 17 is formed on the region where the base is formed. Further, an emitter opening 54 and a collector opening 55 are formed in the first insulating film 17 and the characteristic stabilizing insulating film 90 on the second element formation region 52.

Then, a semiconductor layer (20) is formed on the entire surface by CVD, for example, with polysilicon. continue,
Boron ions (B ⁺ ) are ion-implanted into the semiconductor layer (20) by an ion implantation method. At this time, by optimizing the ion implantation conditions, impurities are also introduced into the n-type epitaxial layer 13 in the first element formation region 15 immediately below the first insulating film 17 to form the base connection layer 21.

For example, the film thickness of the semiconductor layer 20 is 150 n.
m, and the thickness of the first insulating film 17 is 100 nm, boron ions (B ⁺ ) are used as impurities, the implantation energy is set in the range of 5 keV to 20 keV, and the dose amount is 1 × 10 ¹⁵ pieces / cm 3. Boron is introduced into the semiconductor layer 20 by the ion implantation method set in the range of ² to 1 × 10 ¹⁶ pieces / cm ² .

At the same time, boron ions (B ⁺ ) were used as impurities, and the implantation energy was 30 keV-5.
Set in the range of 0 keV and the dose amount is 5 × 10 ¹² pieces / c
Boron was introduced into the n-type epitaxial layer 13 immediately below the first insulating film 17 by the ion implantation method set in the range of m ² to 1 × 10 ¹⁴ pieces / cm ² . The latter ion implantation method allows the base connection layer 21 to be stably formed. In the ion implantation method for forming the base connection layer 21, a mask pattern (not shown) having an opening is formed on a region where the base connection layer 21 is formed, and then this mask pattern is used as an ion implantation mask. Preferably. At this time, lateral pn
Since the characteristic stabilizing insulating film 90 made of silicon nitride functions as a stopper for ion implantation on the base formation region of the p bipolar transistor, boron ions (B ⁺ ) are not introduced.

After that, a mask pattern (not shown) to be an etching mask is formed by a lithography technique, and then the semiconductor layer (20) is patterned by etching using the mask pattern. As a result, the base extraction electrode 3 is formed on the first element formation region 31.
2 is formed, and an emitter extraction electrode 56 and a collector extraction electrode 57 are formed on the second element formation region 52. Further, a capacitor electrode 75 is formed on the capacitor formation region 71 so as to cover the capacitor dielectric film 74.

After that, the second insulating film 22 is formed on the entire surface by a CVD method, for example, a silicon oxide film. FIG. 3A shows the state after the second insulating film 22 is formed.

Next, the vertical n
After forming a register pattern (not shown) having an opening on the region where the emitter opening of the pn bipolar transistor is formed, the second insulating film 2 is formed by etching using the register pattern as an etching mask.
The second opening 25 is formed in the semiconductor layer 20, the semiconductor layer 20, and the offset insulating film pattern 17a.

Next, a silicon oxide film is formed on the entire surface by the CVD method, and then the silicon oxide film is anisotropically etched by etch back to form a sidewall insulating film 26 on the side wall of the second opening 25. Form. In the region sandwiched by the sidewall insulating film 26, the n-type epitaxial layer 13 in which the connection base region 21 is formed is exposed. At this time, the sidewall insulating film 2
The width of 6 may be thin because a part of the offset insulating film pattern 17a already remains and functions for separation. For example, the sidewall insulating film 26 has a width of 0.
About 2 μm is sufficient.

Then, as shown in FIG. 3B, a p-type impurity is added to the base connection layer 21 in the second opening 25 in which the sidewall insulating film 26 is formed by, for example, the CVD method. A polysilicon layer 27 containing is formed. Then, an n-type impurity is ion-implanted into the polysilicon layer 27 by an ion implantation method. Thus, the polysilicon layer 27 to be a conductive layer containing the second conductivity type (n-type) impurities is formed.

Then, heat treatment is performed to diffuse the impurities in the polysilicon layer 27 into the n-type epitaxial layer 13 and form a base layer 28 on the n-type epitaxial layer 13 in the element forming region 15. At the same time, the emitter layer 29 is formed on the base layer 28. At the same time, the graft base layer 30 is formed on the n-type epitaxial layer 13 by diffusing impurities from the semiconductor layer 20.
At the same time, an emitter layer 58 is formed on the n-type epitaxial layer 13 in the second element formation region 52 by diffusion from the emitter extraction electrode 56, and diffusion from the collector extraction electrode 57 causes the second element formation region 52 to be formed. The collector layer 59 is formed on the n-type epitaxial layer 13 in FIG.

After that, a mask pattern (not shown) is formed on the region where the emitter lead-out electrode of the vertical npn bipolar transistor is formed by a lithography technique, and the poly mask is etched by using the mask pattern as an etching mask. Silicon layer (2
7) is patterned to form the emitter extraction electrode 32. (2) of FIG. 3 shows the emitter extraction electrode 3
2 shows the state after forming 2.

Next, as shown in FIG. 4, the second insulating film 2 is selectively formed by lithography and etching.
2 is etched to reach the second insulating film 22, the connection hole 33 reaching the base extraction electrode 32 of the vertical npn bipolar transistor, the connection hole 60 reaching the emitter extraction electrode 56 of the lateral pnp bipolar transistor, and the collector extraction electrode 57. A connection hole 61 and a connection hole 76 reaching the capacitor electrode 75 are formed. At the same time, a vertical npn is formed on the second insulating film 22 and the first insulating film 17.
Bipolar transistor collector extraction diffusion layer 41
, A connection hole 34 reaching the base extraction electrode 53 of the lateral pnp bipolar transistor,
A connection hole 77 is formed to reach the n ⁺ type diffusion layer 72 which will be the electrode of the capacitor.

Then, by a normal wiring forming technique, a base electrode 35 connected to the base extraction electrode 32 through the connection hole 33, an emitter electrode 36 connected to the emitter extraction electrode 32, and a collector extraction diffusion layer 41 through the connection hole 34. The collector electrode 37 is formed. At the same time, the base electrode 63 connected to the base extraction diffusion layer 53 through the connection hole 62 and the emitter electrode 6 reaching the emitter extraction electrode 56 through the connection hole 60.
4 and the collector extraction electrode 5 through the connection hole 61.
A collector electrode 65 reaching 7 is formed. Further, an electrode 78 connected to the capacitor electrode 75 through the connection hole 76,
Then, an electrode 79 connected to the n ⁺ type diffusion layer 72 through the connection hole 77 is formed. FIG. 4 shows a state after forming each electrode. By the manufacturing method as described above, the vertical npn bipolar transistor 1 and the lateral pnp bipolar transistor 2 are formed on the same semiconductor substrate 10.
And a capacitor 3 are formed.

In the description of the second embodiment, the vertical npn bipolar transistor 1, the lateral pnp bipolar transistor 2 and the capacitor 3 are formed on the same semiconductor substrate 10.
Although the manufacturing method for forming the above is described, for example, the process for manufacturing the capacitor is omitted to form the vertical npn bipolar transistor and the lateral pnp bipolar transistor, or the process for manufacturing the lateral pnp bipolar transistor is omitted. A vertical npn bipolar transistor and a capacitor may be formed. When the vertical npn bipolar transistor and the capacitor are formed, the first n-type bipolar transistor on the capacitor formation region 71 is formed.
At the same time as forming the capacitor opening 73 in the insulating film 17, the first opening 19 is formed in the first insulating film 17 on the first element formation region 15.

In the manufacturing method of the second embodiment, similar to the manufacturing method of the first embodiment, a conductive impurity is previously introduced into the element forming region 15 immediately below the offset insulating film pattern 17a by the ion implantation method. Then, the connection base layer 21 is formed, and thereafter, the element formation region 15 is formed.
The connection between the graft base layer 30 and the base layer 29, which is formed in the above step, becomes reliable. Further, the base connection layer 21 is formed without causing a large increase in the number of steps and manufacturing cost.
As a result, the offset insulating film pattern 17a allows the distance between the emitter layer 29 and the graft base layer 30 to be set arbitrarily.

In the manufacturing method of the second embodiment, the characteristic stabilizing insulating film 90 is formed on the first insulating film 17,
Ion implantation for conductivity of the semiconductor layer 20 and formation of the base connection layer 21 is performed with the characteristic stabilizing insulating film 90 left on the element formation region 52, so that it becomes the base layer of the lateral pnp bipolar transistor 1. No p-type impurity is introduced into the n-type epitaxial layer 13 in the second element formation region 52 by this ion implantation. Therefore, a short circuit between the collector and the emitter does not occur. In addition, the insulating film on the surface region of the n-type epitaxial layer 13 serving as the base layer of the lateral pnp bipolar transistor 1 is the first insulating film 17 and the characteristic stabilizing insulating film 90.
Since it is formed by and, high breakdown voltage is achieved.

[0062]

As described above, according to the present invention,
By introducing a conductive impurity into the element formation region directly below the offset insulating film pattern by the ion implantation method to form a base connection layer, after that, a base layer formed in the element formation region directly below the offset insulating film pattern is formed. Even if the graft base layer formed in the element forming region near the side portion of the offset insulating film pattern is largely separated, the base layer and the graft base layer can be connected by the base connecting layer. Therefore, it is possible to arbitrarily set the distance between the emitter layer and the graft base layer.
The breakdown voltage between the emitter and the base can be improved. Further, since the base layer and the graft base layer can be connected to each other without depending on the diffusion depth of the graft base layer, the diffusion depth of the graft base layer can be reduced. Therefore, the collector-base breakdown voltage can be improved and the collector-base junction capacitance can be reduced.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a first embodiment according to the present invention.

FIG. 2 is a manufacturing process diagram (1) of the second embodiment according to the present invention.

FIG. 3 is a manufacturing process diagram (2) of the second embodiment according to the present invention.

FIG. 4 is a manufacturing process diagram (3) of the second embodiment according to the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

FIG. 6 is a manufacturing process diagram of a conventional technique.

[Explanation of symbols]

 10 semiconductor substrate 15 element formation region 17a offset insulating film pattern 20 semiconductor layer 21 base connection layer

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device including a vertical bipolar transistor, comprising forming an offset insulating film pattern on a region of a semiconductor substrate on which a base layer is formed and forming the offset insulating film. A first step of exposing a part of the element formation region on a side of the pattern; and a step of forming a semiconductor layer to be an extraction electrode in a state of connecting to the exposed element formation region, and then performing the ion implantation method to form the offset insulating film. And a second step of forming a base connection layer by introducing a conductive impurity into the element formation region immediately below the pattern. 2. A method of manufacturing a semiconductor device including a vertical bipolar transistor, comprising forming an element isolation region on a semiconductor substrate to provide a plurality of element formation regions, and then forming a first insulating film on the semiconductor substrate. A first step of stacking and forming a second insulating film, and removing the second insulating film on the first element formation region of the plurality of element formation regions where the vertical bipolar transistor is formed, Subsequently, an offset insulating film pattern is formed of the first insulating film on a region of the first element forming region where a base layer is formed, and a part of the first element forming region is formed on a side portion of the offset insulating film pattern. With exposing
The second element formation region on which the lateral bipolar transistor of the plurality of element formation regions is formed is formed on the second element formation region.
A second step of patterning an insulating film and the first insulating film to form at least one opening; and forming a semiconductor layer in a state of connecting to the exposed first element formation region and second element formation region. And a third step of forming a base connection layer by selectively introducing a conductive impurity into the first element formation region immediately below the offset insulating film pattern by an ion implantation method. And a method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein after forming the first insulating film and before forming the second insulating film, capacitors of the plurality of element forming regions are formed. A method of manufacturing a semiconductor device, characterized in that the first insulating film on the formed region is removed. 4. A method of manufacturing a semiconductor device including a vertical bipolar transistor, comprising forming an element isolation region on a semiconductor substrate to provide a plurality of element formation regions, and then forming a first insulating film on the semiconductor substrate. A first step of forming, and an offset insulating film pattern of the first insulating film on a region of the plurality of device forming regions where a base layer of a first device forming region where a vertical bipolar transistor is formed is formed. A part of the first element forming region is exposed by removing the first insulating film on the side of the offset insulating film pattern, and a capacitor of the plurality of element forming regions is formed. A second step of removing the first insulating film on the two-element forming region to form an opening, and a third step of forming a dielectric film on the opening on the second-element forming region, The dew After forming the semiconductor layer to the connected to the first element forming region and a dielectric film, the first directly under the offset insulating film pattern by ion implantation
A fourth step of forming a base connection layer by selectively introducing a conductive impurity into the element formation region.