JPH09203910A - Linear solid switching element and its production as well as plane display element formed by using this linear solid switching element as pixel selcting means - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a linear solid switching element which is simple in structure and easy in production and a process for producing the same as well as a large-sized active addressing type plane display element of high fineness formed by using this linear solid switching element as a pixel selecting means. SOLUTION: An insulating film 2, a-Si film 3, N(+)a-Si film 4, metallic film 5, etc., necessary for constituting the active switching element are formed on a fine wire 1 consisting of a metal. These multilayered films are worked to form a channel part, etc., by which the active switching element of the linear solid structure is formed. The linear solid-state switching element obtd. by forming the fine wire 1 (metallic wire) of the metal described above as a gate line and one piece of a wire (gate switching wire) from which the active switching element hangs down by one line at the gate bus line as one micromechanical part is used for the pixel selecting means of the plane display element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear solid state switch element, a method for manufacturing the same, and a flat display element using the linear solid state switch element as a pixel selecting means.

[0002]

2. Description of the Related Art Recently, a flat display element (so-called flat display panel or a flat display element also called a flat panel) has been used in place of a cathode ray tube as a monitor of information equipment or a video display means of a television receiver. ) Is often used.

Examples of this type of flat display element include a liquid crystal panel, an EL panel and a plasma panel.

In these flat display elements, a liquid crystal layer that transmits / blocks light in the direction of the alignment axis of molecules, an EL layer that emits or discharges by the application of an electric field, or a gas layer is provided in a two-dimensional array of cells. Then, the pixels are configured to display the image by selectively driving the pixels.

When distinguishing such flat display elements by the difference in driving method for selecting each pixel, a simple addressing type (so-called simple matrix type) is used in which pixels are selected at the intersections of electrodes arranged in two directions. ) And an active addressing type (or an active matrix type) in which a switch element including a transistor and a diode is provided in each pixel and the switch element is selectively driven to perform pixel selection. .

Of these, the active addressing type flat display element is a simple matrix type flat panel which is time-division driven because it is a system in which each pixel is constantly driven by a switch element provided for each pixel (duty ratio 1.0). The contrast is better than that of the display element, and it is an essential element especially as a flat display element for color images.

Here, the basic structure of the above-mentioned active addressing type flat display element, which is the object of the present invention, and in particular, the structure and manufacturing process of the switch element which is the pixel selection mechanism, will be described with reference to a thin film transistor (TFT) type. The liquid crystal display element will be described as a typical example.

FIG. 17 is a plan view for explaining one pixel and its periphery of a TFT type active addressing type liquid crystal flat display element, and FIG. 18 is a sectional view taken along line 3-3 of FIG.

As shown in FIG. 17, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) G.
It is arranged in a region where L and two adjacent video signal lines (drain signal lines or vertical signal lines) DL intersect (in a region surrounded by four signal lines).

In the figure, GI is an insulating film, GT is a gate electrode, AS is an i-type semiconductor layer, SD is a source or drain electrode, PSV is a protective film, BM is a light-shielding film, LC is a liquid crystal layer, and TFT is a thin film transistor. , ITO is a transparent pixel electrode, g and d are conductive films, C _{ad d} is a storage capacitor, and AOF is an anodized film.

Each pixel includes a thin film transistor TFT which is a switch element, a transparent pixel electrode ITO1 and a storage capacitor element C _add .

In the figure, the scanning signal lines GL extend in the horizontal direction, and a plurality of scanning signal lines GL are arranged in the vertical direction. The signal lines DL extend in the vertical direction, and a plurality of signal lines DL are arranged in the horizontal direction.

As shown in FIG. 18, a TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with the liquid crystal layer LC as a reference, and a color filter FIL and a light shielding black are formed on the upper transparent glass substrate SUB2 side. A matrix pattern BM is formed.

On both surfaces of the transparent glass substrates SUB1 and SUB2, a silicon oxide film SiO formed by a dip processing transistor is formed.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

The TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

Each pixel has a plurality (two in this case) of TFTs.
(TFT1, TFT2) are provided redundantly. Each of the TFT1 and the TFT2 is configured to have substantially the same size (the channel length and the channel width are the same), and the gate electrode GT, the gate insulating film GI, the i-type semiconductor layer AS, the pair of source electrodes SD1 and the drain electrode SD2. have.

The source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal flat display element, the polarity is reversed during operation, so the source and drain are switched during operation. However, in the following description, for convenience, one is fixed to the source and the other is fixed to the drain.

The gate electrode GT is formed in a shape protruding in the vertical direction from the scanning signal line GL, and the gate electrodes GT of the TFT1 and TFT2 are integrally formed as a common gate electrode.

The gate electrode GT is formed of a single-layer second conductive film g2, and for example, an aluminum (Al) film formed by sputtering is used. An anodic oxide film AOF is formed thereon.

The gate electrode GT is formed in a large size so as to completely cover the i-type semiconductor layer AS, and the i-type semiconductor layer AS is formed.
It is configured so that it is not exposed to outside light or backlight.

The scanning signal line GL is composed of a second conductive film g2, and the second conductive film g2 is formed in the same step as the second conductive film of the gate electrode GT and is integrally formed. An aluminum anodic oxide film AOF is also formed on the scanning signal line GL. Insulating film GI is TFT1, T
In FT2, the i-type semiconductor layer A together with the gate electrode GT
It is used as a gate insulating film for applying an electric field to S. This insulating film GI has a thickness of 20 by plasma CVD or the like.
A 0 to 2700 Å silicon nitride film is formed on the gate electrode GT and the scanning signal line GL.

The insulating film GI also contributes to the electrical insulation between the scanning signal line GL and the video signal line DL.

The i-type semiconductor layer AS has a thickness of 20 formed as islands independent of each of the TFT1 and TFT2.
It is formed of 0 to 2200 Å amorphous silicon (a-Si). The layer d0 is a phosphorus (P) -doped N (+)-type amorphous silicon semiconductor layer for ohmic contact, the i-type semiconductor layer AS exists on the lower side, and the conductive layer d2 (d
It is left only where 3) exists.

The i-type semiconductor layer AS is also provided between both the intersections of the scanning signal line GL and the video signal line DL, and the i-type semiconductor layer AS at this intersection is the scanning signal line GL at the intersection. And a short circuit between the video signal line DL and the video signal line DL are reduced.

The transparent pixel electrode ITO1 constitutes one of the pixel electrodes of the liquid crystal display section and is connected to both the source electrode SD1 of the TFT1 and the source electrode SD1 of the TFT2.

Even if one of the TFT1 and TFT2 has a defect, it can be repaired by cutting it off with a laser beam or the like.

The transparent pixel electrode ITO1 is a transparent conductive film (Indium-Tin-Oxi) formed by sputtering.
de: ITO, Nesa film) thickness 1000-200
It is composed of the first conductive film d1 of 0Å.

Source electrode SD1 and drain electrode SD2
Is composed of a second conductive film d2 which is in contact with the N (+) type semiconductor layer d0, and a third conductive film d3 formed thereon.

The second conductive film d2 has a thickness of 5 by sputtering.
It is formed of a chromium (Cr) film of 100 to 1000 Å. This chromium film is a barrier layer that improves adhesion to the N (+) type semiconductor layer d0 and prevents aluminum of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0. In addition,
This third conductive film d3 is made of a refractory metal (Mo,
Ti, Ta, W) film, refractory metal silicide (MoS
i, TiSi, TaSi, WSi) film may be used.

The third conductive film d3 is formed by sputtering aluminum to a thickness of 3000 to 5000Å.

The video signal line DL has a second conductive film d2 and a third conductive film d2 in the same layer as the source electrode SD1 and the drain electrode SD2.
3

A protective film PSV1 is formed on the thin film transistors TFT1 and TFT2 and the transparent pixel electrode ITO1 by a silicon oxide SiO film formed by plasma CVD or the like or a silicon nitride film with a thickness of about 1 μm.

FIG. 19 is an explanatory diagram of a matrix portion of an active matrix type color flat display element using TFTs as switching elements and its peripheral circuits. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally. is there.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to the respective pixels of green, blue and red. Y means the scanning signal line GL, and the subscripts 1,
2, 3, ... End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho. The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a power supply circuit for obtaining a stabilized voltage obtained by dividing a plurality of voltages from a single voltage source and a TFT (cathode ray tube information) from a host (upper processing unit).
It includes a circuit for converting into information for use.

C _add is a storage capacitor, which acts to reduce the influence of the gate potential change ΔV _{g on} the midpoint potential (pixel electrode potential) V _1c when the TFT switches.
This can be expressed in the following formula.

ΔV _1c = {C _gs / (C _gs + C _add + C _pix )} × ΔV _g where C _gs is the gate electrode GT and the source electrode S of the TFT
C _pix is a parasitic capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (C).
ΔV _1c , which is the capacitance formed between the pixel electrode and the OM), is the change in the pixel electrode potential due to ΔV _g . This variation ΔV _1c causes a direct current component added to the liquid crystal, but becomes smaller as the holding capacitance C _add increases.

Next, an example of a method of manufacturing the above-mentioned flat display element on the side of the switch element carrying substrate (SUB1) is shown in FIG.
This will be described with reference to FIGS. 21 and 22.

20 to 21 show the steps for manufacturing a switch element composed of a TFT in order.

The letters in the center of each figure are abbreviations of process names, and the left side shows the processing flow seen in the cross-sectional shape in the pixel portion and the right side in the vicinity of the gate terminal.

With the exception of step D, steps A to I are classified according to each photographic process (a series of operations from coating a photoresist, exposing through a mask to developing: a thin film photolithography technique). All the cross-sectional views of the respective steps show the stage where the photoresist after the processing after the photolithography process is finished.

Step A (FIG. 20) First, silicon oxide S is formed on both surfaces of the transparent glass substrate SUB1.
After forming a film of iO by dipping, baking is performed,
The first conductive film g1 made of chromium having a thickness of 1100Å
Sputtered, and after photoprocessing, selectively etch the first conductive film g1 to connect to the gate terminal, the drain terminal, the anodized bus line connected to the gate terminal, the bus line short-circuiting the drain terminal, and the anodized bus line. Anodized pad is formed.

Step B (FIG. 20) Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Is formed by sputtering, and after photographic processing, the second conductive film g2 is selectively etched with a mixed solution of phosphoric acid, nitric acid, and glacial acetic acid. Step C (FIG. 20) After the anodic oxidation mask is formed by photo processing, the substrate SUB1 is immersed in the anodic oxidation liquid to perform constant current formation and then constant voltage formation to form an AlO layer having a predetermined thickness. To do.

As a result, the conductive film g2 is anodized to form the anodized film AOF on the scanning signal line GL, the gate electrode GT and the like.

Step D (FIG. 21) Silicon nitride SiN is formed by plasma CVD,
Further, an i-type amorphous Si film is provided, and further an N (+)-type amorphous Si film is formed.

Step E (FIG. 21) After photoprocessing, dry etching is performed to obtain N (+) type amorphous Si.
The film and the i-type amorphous Si film are selectively etched to form islands of the i-type semiconductor layer AS.

Step F (FIG. 21) After the photographic processing, the Si nitride film is selectively etched by dry etching.

Step G (FIG. 22) The first conductive film d1 made of ITO is provided by sputtering, and after photoprocessing, the uppermost layer of the gate terminal and the drain terminal and the transparent pixel electrode are formed by etching. Step H (FIG. 22) A second conductive film d2 is formed by sputtering, and Al−
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is formed by sputtering. After the photo processing, the third conductive film d3 is etched with the same etching solution as in step B, and the second conductive film d2 is etched with the same etching solution as in step A to form a video signal line, a source electrode, and a drain electrode. To do.

Next, an N (+) type amorphous Si film is provided by dry etching, and then the Si nitride film is selectively etched to selectively form the N (+) semiconductor layer d0 between the source and the drain. Remove.

Step I (FIG. 22) A silicon nitride film is provided by plasma CVD, and after photographic processing,
The protective film PSV1 is formed by selectively etching the Si nitride film by dry etching.

By passing through the above steps A to I, TF
A substrate having a switching element made of T is obtained.

The so-called TFT type liquid crystal flat display element is constituted by bonding the other substrate to this substrate and sandwiching the liquid crystal layer between the two substrates to use the TFT as a switching element. The flat display element can be configured by using EL, particularly organic EL, electrochromic or the like instead of liquid crystal.

[0055]

The flat display device as described above tends to become larger and finer in the future.
It is required to manufacture at a low cost at least as high as that of a cathode ray tube. However, in the manufacturing using the thin film photolithography technique as described with reference to FIGS. 20 to 22, the number of steps is large and it is very difficult to reduce the cost.

That is, since the above-described manufacturing process is essentially the same as the semiconductor manufacturing process, the measures against foreign substances accompanying the increase in size of the flat display element become more and more strict, and the device and the clean room are simply increased in size. In addition to the increase in costs of incidental equipment, it is necessary to further upgrade the clean room and improve the accuracy of equipment such as inspection and repair, resulting in a significant increase in process costs.

On the other hand, what has been or is being put into practical use as a flat display element is limited to the above-mentioned liquid crystal, electrochromic, organic EL, plasma and the like. In addition, these flat display elements are required to be manufactured with high yield and high efficiency as switching elements for making them active addressing type.

A first object of the present invention is to provide a linear solid state switch element having a simple structure and easy to manufacture.

Further, a second object of the present invention is to provide a manufacturing method capable of obtaining the linear solid state switch element without using the thin film photolithography technique having a large number of steps as described in the above-mentioned prior art. Especially.

Further, a third object of the present invention is to provide a flat display element suitable for a pixel selecting means of a large-sized and high-definition active addressing flat display element using the linear solid state switching element as a pixel selecting means. To do.

[0061]

The present invention is an active
It is characterized in that the active switch element constituting the addressing type flat display element is configured by micromechanical means without using the thin film photolithography technique similar to the semiconductor manufacturing.

A technical problem in constructing an active addressing type switch element by the above micromechanical means is how to form a minute TFT element as an individual component and how to form those phases. The point is whether to connect.

To solve this problem, the basic idea of the present invention is to form a multi-layer film required for the construction of an active switch element on a thin metal wire and process the multi-layer film to form a linear solid structure. The active switch element is formed by.

When this linear solid-state switch element is used as a pixel selection means for a flat panel display element, the thin metal line (metal line) is used as a gate line, and one line in which an active switch element hangs by one line on a gate bus line. (Here, it is temporarily called a gate switch line.) Is one micromechanical component.

In other words, in order to achieve the first object of the present invention, the first invention according to claim 1 is such that an insulating layer formed on the entire surface of the metal wire and a film is formed on the insulating layer. It is characterized in that it is composed of a plurality of field-effect transistor arrays each including one or a plurality of semiconductor layers and a conductor layer divided into a plurality along the longitudinal direction of the metal line.

In order to achieve the first object of the present invention, the second invention according to claim 2 is the same as the first invention, wherein the insulating layer is a SiO ₂ layer or a Si ₃ N ₄ layer. The semiconductor layer is either an a-Si layer or a p-Si layer, and an N (+) type a-Si layer formed on the semiconductor layer.
It is a layer or an N (+) type p-Si layer.

Further, in order to achieve the first object of the present invention, the third invention according to claim 3 is the oxidation obtained by oxidizing the surface of the metal wire by the insulating layer in the first invention. A film, and the semiconductor layer is either an a-Si layer or a p-Si layer and an N (+) type a-Si layer or an N (+) type p-Si layer formed thereon. Characterize.

Further, in order to achieve the second object of the present invention, the fourth invention according to claim 4 forms an insulating layer made of SiO ₂ or Si ₃ N ₄ on the entire surface of the metal wire. The step of forming an a-Si layer or a p-Si layer on the insulating layer, the a-Si layer or p-S
forming a N (+) type a-Si layer on any of the i layers, forming a metal layer on the N (+) type a-Si layer, and forming the metal layer and N ( +) Type a-Si layer or the metal layer and the N (+) type p-Si layer are separated along the longitudinal direction of the metal line, and the metal line serves as a gate line, and the separated metal layers are adjacent to each other. At least one of which is a drain electrode and the other is a source electrode, and a plurality of field effect switch rows are formed in the longitudinal direction.

Further, in order to achieve the second object of the present invention, the fifth invention according to claim 5 is a step of forming an a-Si or p-Si layer on the entire surface of the metal wire, The a
-Si or p-Si is oxidized to form a SiO ₂ layer, an a-Si layer or p-S is formed on the SiO ₂ layer.
forming an i layer, forming the surface of the a-Si layer or p-Si layer into an N (+) a-Si layer or p-Si layer, the N (+) type a-Si layer or the N (+) Type p
Forming a metal layer on the -Si layer, and the metal layer and the N (+) type a-Si layer or the N (+) type p-Si layer or the metal layer and the N (+) type a-Si Layer or N
The (+) type p-Si layer and the a-Si or p-Si layer are separated along the longitudinal direction of the metal line, the metal line is used as a gate line, and the adjacent one of the separated metal layers is drained. And a step of forming a plurality of field effect switch arrays in which the other is a source electrode in the longitudinal direction, and a method for manufacturing a linear solid state switch element.

Further, in order to achieve the second object of the present invention, the sixth invention according to claim 6 oxidizes the surface of the metal wire to form a metal oxide on the entire surface of the metal wire. Forming an insulating layer, forming an a-Si layer or a p-Si layer on the metal oxide insulating layer, a-
A step of forming an N (+) a-Si layer or a p-Si layer on the surface of the Si layer or the p-Si layer, said N (+) a-S
forming a metal layer on the i layer or the p-Si layer, and separating the metal layer along the longitudinal direction of the metal line, using the metal line as a gate line, and adjoining the separated metal layer At least one of which is a drain electrode and the other is a source electrode, and a plurality of field effect switch rows are formed in the longitudinal direction.

Further, in order to achieve the second object of the present invention, the seventh invention according to claim 7 is the N (+) a-Si layer or p-type layer according to the fourth to sixth inventions. It is characterized in that the Si layer is formed by an ion implantation method or a laser doping method.

Further, in order to achieve the second object of the present invention, the eighth invention according to claim 8 is the SiO ₂ , Si ₃ N ₄ , a-Si according to the _{fourth to} sixth inventions. , P-
Si for plasma spraying, ion cluster beam, ion plating, thermal vapor phase CVD, plasma vapor phase CV
It is characterized by being formed by any one of D, epitaxial liquid phase growth, and melt liquid phase growth.

Further, in order to achieve the second object of the present invention, the ninth invention according to claim 9 is the metal layer and N (+) a-Si layer according to the fourth to sixth inventions. Alternatively, the means for separating the p-Si layer along the longitudinal direction of the metal line uses any one of laser ablation processing, photolithography processing, and mechanical cutting processing.

In order to achieve the third object of the present invention, a tenth aspect of the present invention is to form an insulating layer formed on the entire surface of a metal wire, and to form the insulating layer on the insulating layer. A plurality of field-effect transistor arrays each including a filmed semiconductor layer and a plurality of conductor layers divided along the longitudinal direction of the metal line, wherein the metal line is a gate line and the conductor layer adjacent to the plurality of metal lines is adjacent to the gate line. The pixel switch line and the gate line are formed by arranging linear solid-state switch elements, one of which is a drain electrode and the other of which is a source electrode, on the surface of the substrate surface.

In order to achieve the third object of the present invention, the eleventh invention according to claim 11 is the pixel switch according to any one of the first to third inventions or the tenth invention. Any of a connecting metal film or a connecting metal bump that has an organic insulating film on the entire surface of the linear solid state switching element except a part of the source electrode and the drain electrode, and that is connected to the source electrode and the drain electrode on the substrate. It is characterized by having.

Further, in order to achieve the third object of the present invention, the twelfth invention according to claim 12 is the transparent substrate having independent transparent pixel electrodes on one surface, and the other of the substrates. On the surface, there is a small electrode connected to the source electrode of the linear solid state switch element of the ninth invention and connected to the transparent pixel electrode, and a drain line connected to the drain electrode.

Further, in order to achieve the third object of the present invention, the thirteenth invention according to the thirteenth invention has an insulating film for covering the small electrode and the drain line in the twelfth invention. Characterize.

Further, in order to achieve the third object of the present invention, a fourteenth invention according to a fourteenth aspect has an independent transparent pixel electrode on one surface, and the ninth pixel on the other surface. Second substrate having a transparent first substrate having a small electrode connected to the source electrode of the linear solid state switching element of the invention and communicating with the transparent pixel electrode, and a drain wire connected to the drain electrode. It is characterized by having and.

Further, in order to achieve the third object of the present invention, the fifteenth invention according to claim 15 insulates the drain line in the thirteenth invention except for the connection portion with the source electrode. The wire is covered with a film.

In order to achieve the third object of the present invention, the sixteenth invention according to the sixteenth invention is such that the drain wire in the fourteenth invention is formed on the second substrate surface. It is a conductive film.

Further, in order to achieve the third object of the present invention, the seventeenth invention according to claim 17 is insulating except for the portion where the drain wire in the fourteenth invention is connected to the drain electrode. It is a wire covered with a film.

Further, in order to achieve the third object of the present invention, the eighteenth invention according to claim 18 is formed on the first transparent substrate according to any one of the tenth to seventeenth inventions. It is characterized in that a transparent substrate having uniform transparent electrodes opposed to each other on the transparent pixel electrode side through a liquid crystal layer is provided.

Further, in order to achieve the third object of the present invention, the nineteenth invention according to claim 19 is formed on the first transparent substrate according to any one of the tenth to eighteenth inventions. A transparent substrate having uniform transparent electrodes opposed to each other on the transparent pixel electrode side via an electrochromic layer is provided.

Further, in order to achieve the third object of the present invention, the twentieth invention according to claim 20 is formed on the first transparent substrate according to any one of the tenth to nineteenth inventions. It is characterized in that a transparent substrate having uniform transparent electrodes opposed to each other on the transparent pixel electrode side via an organic EL layer is provided.

Further, in order to achieve the third object of the present invention, the twenty-first invention according to the twenty-first invention is the effective screen area of any one of the eighteenth to twentieth inventions. A groove for burying the gate line and / or the drain line is provided outside.

[0086]

BEST MODE FOR CARRYING OUT THE INVENTION As film forming means for forming the above-mentioned multilayer film on a metal wire, plasma spraying, ion cluster beam, ion plating, vapor phase CVD on the surface of the metal wire.
(Thermal CVD, plasma CVD, etc.), liquid phase growth (epitaxial, melting, etc.), etc., and an insulating film such as SiO ₂ , Si ₃ N ₄ or the like, amorphous Si ( a-Si) or polycrystalline Si (p-Si), N
(+) A-Si layers are sequentially formed, and a metal film is further formed thereon.

Although the above film formation is a thin film forming process,
According to the conventional semiconductor technology, the gate oxide film may be formed by oxidizing the Si film or the surface of the metal line.

For the N (+) a-Si layer, a semiconductor-like doping means, that is, ion implantation, laser doping, or the like can be used. further,
In order to form the p-Si layer, a method of annealing a-Si with an excimer laser may be used.

Further, as means for forming a plurality of rows of the field effect type switching elements in the longitudinal direction of the metal wire, ablation of excimer laser, ordinary photolithography, or mechanical cutting is used to cope with, for example, the pixel pitch. The uppermost metal layer is separated at intervals.

FIG. 1 is an explanatory view of a structural example of a linear solid state switch element according to the present invention, in which (a) is a perspective view and (b) is a sectional view.

In the figure, 1 is a metal wire, 2 is an insulating layer (gate insulating layer), 3 is a channel portion, 4 is an N (+) type a.
-Si layer, 5 is a drain electrode, and 5'is a source electrode.

This linear solid-state switch element is a field effect transistor switch for switching operation of a pixel, and comprises an insulating layer 2 formed on the surface of a metal wire 1 and an N (+) type a.
-The Si layer 4, and the drain electrode 5 and the source electrode 5'constitute a unit field effect transistor. A plurality of the field effect transistors are arranged along the longitudinal direction of the metal wire 1 to form one linear solid state switch element.

That is, the metal line 1 constitutes a gate electrode, and the N (+) type a-Si layer 4 formed thereon, the drain electrode 5 and the source electrode 5'constitute a field effect transistor.

The channel portion 3 which constitutes one field effect transistor is formed by removing the metal layer on the surface up to the N (+) type a-Si layer, and the above-mentioned drain is formed by the electrodes separated by the channel portion 3. The electrode 5 and the source electrode 5'are formed.

When used as a switch element for active addressing of a flat display element, N (+) together with the electrodes between the field effect type transistors of one unit described above.
The type a-Si layer 4 and the a-Si or p-Si layer are also removed, and only the insulating layer 2 is left, but when the pixels are separated, the N (+) type a-Si layer 4 is also removed. Just enough.

Removal of each of the above layers is performed by using a laser (for example,
Excimer laser) ablation or ordinary photolithography or mechanical cutting or polishing may be used.

When the linear solid state switching element thus constructed is used as an active addressing means for a flat panel display element, a required number of the linear type solid state switching elements are arranged on a plane and an inorganic insulating film or an inorganic insulating film is formed on the gate-switch line. An insulating layer is formed of an organic insulating film, and part of the insulating film of the source / drain portions is removed in order to connect to the pixel line and the signal line. However, as described later, when the drain line and the pixel electrode are insulated, it is not always necessary to insulate the gate-switch line itself.

It is important to match the thermal expansion of the metal wire for the gate and the substrate. The selection of the coefficient of thermal expansion of the metal wire can be set to a coefficient of thermal expansion corresponding to a wide range of substrate materials by using various alloys.

Further, the surface of the metal wire needs to be treated to have a surface roughness of, for example, 0.1 μm or less so that the uniformity of film formation can be maintained.

FIG. 2 is an explanatory view of another structural example of the linear solid state switch element according to the present invention, in which (a) is a perspective view,
(B) is a sectional view.

In this example, the drain electrode 5 and the source electrode 5'are formed by partially removing the metal film formed on the uppermost layer at a position on the opposite surface parallel to the longitudinal direction of the metal line. Therefore, in this type, the channel portion is formed at two places 3, 3 '.

The film formation and removal of each layer in this structural example are the same as those described with reference to FIG.

Next, a plurality of methods for manufacturing this linear solid state switching element will be described.

[Manufacturing Method 1] The above-mentioned plasma spraying, ion cluster beam, ion plating, vapor phase CVD (thermal CVD, plasma CVD) on the entire surface of the metal wire 1.
Etc.) or liquid phase growth (epitaxial, melting, etc.) of SiO ₂ or Si ₃ N ₄ to form an insulating layer (gate insulating layer) 2.

An a-Si layer or a p layer is formed on the insulating layer 2.
Any one of the —Si layers is formed, and ion doping (hereinafter simply referred to as ion) or laser doping (hereinafter simply referred to as) is performed on either the a-Si layer or the p-Si layer.
N (+) type a-Si using any of laser doping)
Layer 4 is deposited.

Then, a metal layer is formed on the N (+) type a-Si layer 4, and the metal layer is ablated by a laser (for example, excimer laser) along the longitudinal direction of the metal wire 1, or A row of a plurality of field-effect switches, which are separated by ordinary photolithography or mechanical cutting, use the metal line as a gate line, one of the separated metal layers as a drain electrode, and the other as a source electrode in the longitudinal direction. To form.

[Manufacturing Method 2] An insulating layer 2 made of SiO ₂ or Si ₃ N ₄ is formed on the entire surface of the metal wire in the same manner as in Manufacturing Method 1, and the upper layer is either ion-doped or laser-doped. Using N on the a-Si layer or surface
A (+) type Si layer is formed on the Si layer, and an a-Si layer or a p-Si layer is further formed on the Si layer, and then a metal layer is formed on the Si layer. Then, the metal layer 1 is separated along the longitudinal direction of the metal wire 1 by ablation of the same laser (for example, excimer laser) as described above, or by ordinary photolithography or mechanical cutting, and the metal wire 1 is separated. A row of a plurality of field effect switches is formed in the longitudinal direction using the gate line, the adjacent one of the separated metal layers as the drain electrode 5 and the other as the source electrode 5 ′.

[Manufacturing Method 3] a- is formed on the entire surface of the metal wire 1.
An insulating layer 2 made of Si or p-Si is formed, and
-Si or p-Si is thermally or anodized to form SiO.
After forming the _second layer, wherein forming the a-Si layer or p-Si layer on the SiO ₂ layer, these surfaces the ion doping, using either laser doped N (+) type Si layer 4 Then, a metal layer is formed on the N (+) type Si layer 4.

Then, the metal layer is separated along the longitudinal direction of the metal wire 1 by ablation with the same laser (for example, excimer laser) as described above, or by ordinary photolithography or mechanical cutting, and the metal layer is separated. A line of field effect switches is formed in the longitudinal direction in which the line 1 is a gate line, one of the separated metal layers is adjacent to the drain electrode 5 and the other is adjacent to the source electrode 5 ′.

[Manufacturing Method 4] The surface of the metal wire 1 is oxidized to form an insulating layer 2 made of a metal oxide on the entire surface of the metal wire 1, and a- is formed on the insulating layer 2 of the metal oxide. Si
After forming the layer or the p-Si layer, an N (+) type Si layer is formed on the surface of the a-Si layer or the p-Si layer by using either ion doping or laser doping.

Then, a metal layer is formed on the N (+) type Si layer, and the metal layer is ablated along the longitudinal direction of the metal wire 1 by the same laser (for example, excimer laser), Alternatively, a plurality of electric fields are formed by separating the metal lines 1 by a usual photolithography or mechanical cutting, and using the metal line 1 as a gate line, the adjacent one of the separated metal layers as a drain electrode 5, and the other as a source electrode 5 ′. An effect switch row is formed in the longitudinal direction.

In this way, a plurality of field effect switch rows are formed along one metal line. A large number of linear solid state switch elements whose pitches between the field effect switches are matched to the pixel pitch are arranged in a plane to form a liquid crystal layer and an organic EL device.
An active addressing type flat display element can be formed by laminating the layer or the plasma forming layer.

FIG. 3 is a schematic perspective view illustrating an example of a pixel electrode substrate which constitutes a flat display element according to the present invention.
6 is a pixel electrode substrate, 7 is a drain line, 8 is a small source electrode, 9 is a pixel-small electrode conducting portion, and 10 is a transparent pixel electrode.

The pixel electrode substrate 6 has a basic structure in which an independent transparent pixel electrode 10 is formed on one side of a transparent substrate and a small source electrode 8 and a drain line 7 corresponding to a pixel are formed on the opposite side thereof. The small electrodes 8 and the drain lines 7 are covered with an insulating film, and the corresponding portions of the insulating film are removed in order to establish conduction with the source / drain electrodes of the switch element.

On the other hand, a thin hole is made between each pixel electrode 10 and the small electrode 8 which faces each pixel electrode, and a conductor is inserted therein to establish conduction.

FIG. 4 is a perspective view for explaining the schematic structure of another example of the flat panel display device according to the present invention. 11 is a counter substrate for a flat panel display device, and the same reference numerals as those in FIGS. To do.

As shown in the figure, the gate line (hereinafter also referred to as a gate / switch line) 1 has its drain electrode 5 connected to the drain line 7 on the pixel electrode substrate 6, and the source electrode 5'is a small electrode. 8 is connected. In this case, if the gate switch line 1 is insulated, the drain line 7 and the small electrode 8 do not necessarily need to be insulated.

FIG. 5 is a perspective view for explaining the schematic structure of still another example of the flat panel display device according to the present invention. Reference numeral 12 denotes a drain line substrate, and the same reference numerals as those in the above embodiments correspond to the same portions. Depending on the electrode arrangement of the switch part of the gate switch line 1, it may be convenient to form the drain line 7 and the small electrode 8 on different substrates.

That is, an independent pixel electrode is formed on one side of the transparent substrate 6, and a small electrode 8 corresponding to a pixel is formed on the opposite side.
Is formed, and a thin hole is formed between each pixel electrode and the opposing small electrode 8 to establish conduction.

On the other hand, a drain line 7 covered with an insulating film is formed on another transparent substrate 12, and a through hole is opened corresponding to the drain electrode 5 of the switch element 1.

FIG. 6 is a perspective view for explaining the schematic structure of still another example of the flat panel display device according to the present invention, and the same reference numerals as those in the above embodiment correspond to the same portions.

In this embodiment, the substrate 12 on which the drain line 7 in FIG. 5 is formed is not used, but a simple line 7'is used.
May be directly connected to the drain electrode 5.

The switch element in FIGS. 5 and 6 has the structure described in FIG. 1. However, when a flat display element is formed by using the switch having the structure described in FIG. It can have a different structure.

FIG. 7 is a perspective view for explaining the schematic structure of still another example of the flat display element according to the present invention, and the same reference numerals as those in the above embodiment correspond to the same portions. The substrate 6 is shown in FIG.
The small electrode 8 is formed on the inner surface of the substrate 12, the drain wire 7 is formed on the inner surface of the substrate 12, the switch wire 1 is sandwiched between the two substrates, and the drain electrode of the switch wire 1 is formed on the substrate 12. 7 and the source electrode 5 ′ of the switch line 1 is in contact with the small electrode 8 of the substrate 6.

Further, in FIG. 9B, a groove 6'is formed on the inner surface of the substrate 6, a small electrode 8 is embedded in the bottom surface, and a switch wire 1 is embedded in the groove 6'and the source electrode thereof is embedded. 5 '
Is brought into contact with the small electrode 8 and the drain electrode 5 is brought into contact with the drain wire formed on the substrate 12.

With such a structure, the substrate 6
The gap between the substrate and the substrate 12 can be reduced.

Also in the configuration of FIG. 7, the drain line 7 may be linear as shown in FIG.

FIG. 8 is a perspective view for explaining the schematic structure of still another example of the flat panel display device according to the present invention, which is a structural example in which the cross section of the gate line is rectangular, and 9 is the pixel electrode 10 and A conductor for conduction with the small electrode 8 and a bump 13 are provided.

In the figure, the drain electrode 5 formed on the switch line 1, the drain line 7 formed on the substrate 6, the source electrode 5'formed on the switch line 1 and the small electrode 8 formed on the substrate 6 are The bumps 13 made of a low melting point metal are used and are connected by thermocompression bonding or laser welding.

FIG. 9 is a perspective view for explaining the schematic structure of still another example of the flat panel display device according to the present invention. In particular, when the gate line and the drain line are made of wire material, the dotain line is used as a substrate. The structure fixed by embedding is shown.

As shown in the drawing, a groove is cut in the periphery and the end of the substrate 6, the wire is embedded in the groove, and an adhesive is applied to the end to fix the wire.

FIG. 10 shows driving I on the substrate having the structure shown in FIG.
FIG. 14 is a partial cross-sectional view illustrating a structure in which C is mounted,
Is an adhesive for fixing the terminal portion, 15 is a circuit board, and 16 is a drive I
C.

As shown in the figure, the driving IC 16 is mounted on the circuit board 15 and fixed to the board 6 with the adhesive material 14, and its terminals are the via holes 15 ′ formed by the board 15.
Done through.

FIG. 11 is a plan view of a main part for explaining still another configuration example of the flat display element according to the present invention. The switch according to the present invention is used as a switch element for active addressing of a so-called horizontal electric field type flat display element. It uses an element.

In the figure, the pixel electrode 10 and the common electrode 17 are arranged in a comb shape in a position parallel to the substrate surface, and are drawn out by the pixel electrode lead-out line 10 'and the common electrode lead-out line 17', respectively. There is.

The above-described configurations enable active addressing of a flat display element. However, when liquid crystal is used as an actual display medium, the other substrate is used as a color filter substrate to display color liquid crystal. The element can be configured.

Besides, electrochromic, organic EL, or the like can be used as the display medium.

Examples of the present invention will be described in more detail below.

Example 1 A flat display element using the switching element according to the present invention has a diagonal of 50 inches and an aspect ratio of 1.
An HD-TV having a pixel size of 6: 9 and a pixel size of 0.6 mm was constructed.

As the metal wire of the gate-switch wire 1, a fine Inconel wire having a diameter of 20 μm was used. The coefficient of thermal expansion of this line is 4.8 × 10 ⁻⁶ at 30 ° to 350 °.

Various films are formed on the metal wire by using thermal CVD of a quartz cylinder, and 300 n of SiO ₂ is used as a gate insulating film.
m, a-Si as a semiconductor layer is 200 nm, N (+) a
-Si was continuously formed in a thickness of 30 nm, and then a Ta film was formed in a thickness of 200 nm by an ion cluster beam method.

In any film formation, the wire was pulled at a constant speed to make the film thickness uniform.

Ta film and N (+) a-S in the channel portion
For removal of i film, pulse width of 0.5 ps and wavelength of 248 nm
Excimer laser ablation was used. FET
Has a channel length of 15 μm and a width of 62.8 (= 20 ×
The shape shown in FIG. 1 was adopted for π).

FIG. 12 is a schematic diagram of an illumination image forming system when an excimer laser is used to remove the channel portion.
Reference numerals 8 and 18 'are laser lights for ablation.

As shown in FIG. 13, this image forming optical system is composed of two opposing 1: 5 reduction image forming lenses.
A wire is placed at the image point.

As for the image forming method, the same principle as that of the optical system of the mask exposure device is used. The mask is illuminated by the Keller illumination system and the image is formed by the image forming lens. In this case, the mask is a dielectric multilayer mirror and constitutes an opaque portion for excimer light.

As shown in FIG. 14, a set of openings has a set corresponding to the channel length (a) and a transistor separation part (b), which is a total of 50 sets.

Since the lens is 1: 5, the image plane is 30 μm.
The area is m × 10 mm, and the area is reduced to 1/25.

The energy density of the illumination light to the mask is 60
mJ /-, and 1J /-on the image plane. With this energy density, the metal film and the N (+) layer are removed in one shot.

The oscillation frequency of the energy laser is 2.5
Since the frequency is kHz, it is possible to process a wire of 1500 m in 60 seconds by running the wire at an accurate speed of 25 m / second. This is the amount of gate-switch lines needed to construct a so-called 50 inch diagonal display. The laser light source used here is one, and the output beam is divided into two.

A solder resist is applied to the gate-switch line thus processed, and the resist is removed with a width of 20 μm on the source and drain electrodes by the same means as in the above-described FET processing. The solder is placed on the source and drain electrodes through a bath of molten low temperature solder.

The substrate is so-called 7059 glass having a thickness of 1.1 mm, and 4800 holes of 0.08 mmφ are opened in the horizontal direction at a pitch of 0.2 mm. 1000 such horizontal lines are formed.

The upper and lower connections of the holes are made by a sintered body of metal paste. The ITO transparent electrode is connected to one surface of the substrate, and the small electrode and the drain wire connected to the source electrode of the transistor as shown in FIG. 3 are connected to the other surface.

FIG. 15 is a partial view for explaining a detailed example of the connecting portion between the small electrode and the drain line.

In this example, an excimer laser display element is manufactured in advance using the above-mentioned substrate and color filter substrate.

Then, the gate switch line 1000
The book is fixed to the frame while applying tension at a pitch of 0.6 mm, aligned with the substrate, and connected by solder reflow with an infrared lamp.

As shown in FIG. 10, the end portion of the gate line is fixed by utilizing the groove formed in the end portion, and the driving IC is connected to the end portion to connect the field effect type active addressing type liquid crystal. A display element is obtained.

FIG. 16 is a developed perspective view for explaining an example of a flat display module using a field effect type active addressing type liquid crystal display element according to the present invention.
L is a liquid crystal display module, SHD is a metal shield case that is an upper frame, WD is a display window that defines the effective screen of the liquid crystal display module, PNL is a liquid crystal panel including the liquid crystal display element according to the present invention, and PCB1 is a drain side circuit. Substrate, PCB2 is gate side circuit board, PCB3 is interface circuit board, PRS is prism sheet, SPS
Is a diffusion sheet, GLB is a light guide, RFS is a reflection sheet,
BL is a backlight, LP is a cold cathode fluorescent lamp that constitutes the lamp of the backlight BL, LS is a reflection sheet, GC is a rubber bush, LPC is a lamp cable, and MCA is a lower side having an opening MO for installing a light guide GLB. Case, JN
1, 2, 3 are joiners for connecting circuit boards, TCP
1, 2 are tape carrier packages, INS 1, 2, 3
Is an insulating sheet, GC is a rubber cushion, BAT is a double-sided adhesive tape, and ILS is a light shielding spacer.

The above-mentioned components are laminated between the metal shield case SHD and the lower case MCA and sandwiched and fixed to form the liquid crystal display module MDL.

On the back surface of the liquid crystal panel PNL, there is provided a backlight BL in which various optical sheets are laminated on the light guide GLB, and the image formed on the liquid crystal display panel PNL is illuminated and displayed on the display window WD. indicate.

In the above-mentioned embodiments, the liquid crystal is used as the display medium, but other than this, organic EL, electrochromic,
Alternatively, it goes without saying that the present invention can be applied to various flat display elements using plasma gas discharge.

[0162]

As described above, according to the present invention,
It is possible to provide a linear solid-state switching element having a simple structure and easy to manufacture.

Further, it is possible to obtain the manufacturing method for obtaining the linear solid-state switch element without using the thin film photolithography technique having the large number of steps as described in the prior art.

Furthermore, by using the linear solid state switching element according to the present invention as the pixel selecting means, it is possible to provide a large-sized and high-definition active addressing type flat display element.

[Brief description of drawings]

FIG. 1 is an explanatory view of a structural example of a linear solid state switch element according to the present invention.

FIG. 2 is an explanatory view of another structural example of the linear solid state switching element according to the present invention.

FIG. 3 is a schematic perspective view illustrating an example of a pixel electrode substrate that constitutes a flat display element according to the present invention.

FIG. 4 is a perspective view illustrating a schematic structure of another example of the flat panel display device according to the present invention.

FIG. 5 is a perspective view illustrating a schematic structure of still another example of the flat panel display device according to the present invention.

FIG. 6 is a perspective view illustrating a schematic structure of still another example of the flat panel display device according to the present invention.

FIG. 7 is a perspective view illustrating a schematic structure of still another example of the flat panel display device according to the present invention.

FIG. 8 is a perspective view illustrating a schematic structure of still another example of the flat panel display device according to the present invention.

FIG. 9 is a perspective view illustrating a schematic structure of still another example of the flat panel display device according to the present invention.

10 is a partial cross-sectional view illustrating a structure in which a drive IC is mounted on the substrate having the structure shown in FIG.

FIG. 11 is a main-portion plan view illustrating still another configuration example of the flat panel display element according to the present invention.

FIG. 12 is a schematic diagram of an illumination imaging system when an excimer laser is used to remove a channel portion.

13 is a schematic diagram of an image forming optical system of the illumination image forming system of FIG.

14 is a structural diagram of a dielectric multi-layered film mask used for sewing the imaging optical system of FIG.

FIG. 15 is a partial view illustrating a detailed example of a connection portion between a small electrode and a drain line.

FIG. 16 is a developed perspective view illustrating an example of a flat display module using a field effect type active addressing type liquid crystal display element according to the present invention.

FIG. 17 is a plan view illustrating one pixel and its periphery of a TFT type active addressing type liquid crystal flat display element.

18 is a sectional view taken along line 3-3 of FIG.

FIG. 19 shows an active circuit using a TFT as a switching element.
FIG. 3 is an explanatory diagram of a matrix portion of a matrix type color flat display element and its peripheral circuits.

FIGS. 20A to 20C sequentially show steps for manufacturing a switch element made of a TFT.

FIG. 21 shows a sequence of steps for manufacturing a switch element composed of a TFT.

22A to 22C sequentially show steps for manufacturing a switch element made of a TFT.

[Explanation of symbols]

 1 metal wire 2 insulating layer (gate insulating layer) 3 channel part 4 N (+) type a-Si layer 5 drain electrode 5'source electrode

Claims (21)

[Claims] 1. An insulating layer formed on the entire surface of a metal wire, one or a plurality of semiconductor layers formed on the insulating layer, and a conductor layer divided into a plurality along the longitudinal direction of the metal wire. A linear solid-state switch element, which is configured by a plurality of field-effect transistor arrays. 2. The insulating layer according to claim 1, wherein the insulating layer is SiO _2.
Layer or Si ₃ N ₄ layer, the semiconductor layer is either an a-Si layer or a p-Si layer, and an N (+) type a-Si layer or N (+) formed on the semiconductor layer. Type p-S
A linear solid-state switch element, which is an i-layer. 3. The insulating layer according to claim 1, which is an oxide film formed by oxidizing the surface of the metal wire, and the semiconductor layer is formed on either the a-Si layer or the p-Si layer. N (+) type a-Si layer or N (+) type p-S
A linear solid-state switch element, which is an i-layer. 4. SiO ₂ or Si ₃ is formed on the entire surface of the metal wire.
Depositing an insulating layer made of N ₄ , depositing either an a-Si layer or a p-Si layer on the insulating layer,
N on either the a-Si layer or the p-Si layer
A step of forming a (+) type a-Si layer, the N (+) type a
A step of forming a metal layer on the -Si layer, and the metal layer and the N (+) type a-Si layer or the metal layer and the N (+)
Separating the mold p-Si layer along the longitudinal direction of the metal wire,
At least forming a plurality of field effect switch rows in the longitudinal direction using the metal line as a gate line, the adjacent one of the separated metal layers as a drain electrode, and the other as a source electrode. And a method for manufacturing a linear solid state switching element. 5. A-Si or p-S is formed on the entire surface of the metal wire.
forming an i layer, forming an SiO ₂ layer by oxidizing the a-Si or p-Si, forming an a-Si layer or a p-Si layer on the SiO ₂ layer, The surface of the a-Si layer or p-Si layer is N (+) a-Si
Layer or p-Si layer, the N (+) type a-S
forming a metal layer on the i layer or the N (+) type p-Si layer, and the metal layer and the N (+) type a-Si layer or the N (+) type p-Si layer, or Metal layer and N
(+) Type a-Si layer or N (+) type p-Si layer and a-
A field effect type device in which a Si or p-Si layer is separated along the longitudinal direction of the metal line, the metal line is used as a gate line, and one of the separated metal layers is adjacent to the drain electrode and the other is used as the source electrode. And a step of forming a plurality of switch rows in the longitudinal direction, the method of manufacturing a linear solid-state switch element. 6. A step of oxidizing the surface of a metal wire to form an insulating layer made of a metal oxide on the entire surface of the metal wire, and an a-Si layer or p-Si layer on the insulating layer of the metal oxide.
Forming a layer, forming an N (+) a-Si layer or p-Si layer on the surface of the a-Si layer or p-Si layer, the N (+) a-Si layer or p-Si layer A step of forming a metal layer on the layer, and separating the metal layer along the longitudinal direction of the metal line, the metal line as a gate line, and the adjacent one of the separated metal layers as a drain electrode. And a step of forming a plurality of field-effect switch rows with the other as a source electrode in the longitudinal direction, the method for manufacturing a linear solid state switch element. 7. The N according to any one of claims 4 to 6.
A method of manufacturing a linear solid-state switch element, which comprises forming the (+) a-Si layer or the p-Si layer by an ion implantation method or a laser doping method. 8. The Si according to any one of claims 4 to 6.
O ₂ , Si ₃ N ₄ , a-Si, p-Si are plasma sprayed, ion cluster beam, ion plating,
A method for manufacturing a linear solid state switch element, which is formed by any one of thermal vapor phase CVD, plasma vapor phase CVD, epitaxial liquid phase growth, and melt liquid phase growth. 9. The laser ablation means according to claim 4, wherein the metal layer and the N (+) a-Si layer or the p-Si layer are separated along the longitudinal direction of the metal line. A method for manufacturing a linear solid-state switch element, characterized by using any one of processing, photolithography processing, and mechanical cutting processing. 10. A plurality of insulating layers formed on the entire surface of a metal wire, a semiconductor layer formed on the insulating layer, and a plurality of conductor layers divided along the longitudinal direction of the metal wire. A field effect transistor array, the metal line is a gate line,
A plane characterized in that the pixel switch line and the gate line are formed by arranging linear solid-state switch elements, each having a drain electrode on one side and a source electrode on the other side, adjacent to one of the plurality of divided conductor layers, to form the pixel switch line and the gate line. Display element. 11. A linear solid-state switch element constituting the pixel switch according to any one of claims 1 to 10 has an organic insulating film on the entire surface except a part of the source electrode and the drain electrode, and the substrate is provided on the substrate. A flat display device comprising either a connection metal film or a connection metal bump connected to the source electrode and the drain electrode. 12. A transparent substrate having independent transparent pixel electrodes on one surface, and the transparent substrate on the other surface of the substrate.
Or a drain electrode connected to the drain electrode and a small electrode connected to the source electrode of the linear solid-state switch element and communicating with the transparent pixel electrode. 13. A flat panel display device according to claim 12, further comprising an insulating film covering the small electrodes and the drain lines. 14. A small pixel which has an independent transparent pixel electrode on one surface and is connected to the source electrode of the linear solid state switch element according to claim 10 on the other surface and communicates with the transparent pixel electrode. A second substrate having a transparent first substrate having an electrode and a drain wire connected to the drain electrode
A flat display element, comprising: 15. The flat display element according to claim 12, wherein the drain line is a wire covered with an insulating film except for a connection portion with the source electrode. 16. The flat display element according to claim 14, wherein the drain line is a conductive film formed on the surface of the second substrate. 17. The flat display element according to claim 14, wherein the drain wire is a wire covered with an insulating film except a portion connected to the drain electrode. 18. The transparent substrate according to claim 10, further comprising a transparent substrate having a uniform transparent electrode facing the transparent pixel electrode formed on the first transparent substrate via a liquid crystal layer. A flat panel display device characterized by. 19. The transparent substrate having a uniform transparent electrode facing the transparent pixel electrode formed on the first transparent substrate via an electrochromic layer, according to claim 10. A flat display element characterized by the above. 20. The organic EL device according to claim 10, wherein the transparent pixel electrode side formed on the first transparent substrate is provided with an organic EL device.
A flat display element comprising a transparent substrate having uniform transparent electrodes opposed to each other with a layer interposed therebetween. 21. The flat display element according to claim 18, further comprising a groove for burying the gate line and / or the drain line outside the effective screen area of any one of the substrates.