JPH09200659A - Display device, image processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the circuit scale small by providing an interpolation means conducting multiplication with a multiple of the n-th power of 2 with image data from an input means and addition to the data and a means displaying output image data from the interpolation means. SOLUTION: A synchronizing separator section 101 receives a video signal s101 and separates it into an image signal s102 and a synchronizing signal. A synchronizing signal measurement section 102 receives a horizontal synchronizing signal and vertical synchronizing signal cs101 and a synchronizing signal polarity discrimination signal cs102 and provides an output of the measurement result to a system control circuit 191. An interpolation processing section 105 applies vertical interpolation processing to an RGB image signal s103 obtained from an A/D converter section 103. That is, data of 1/32 to 32/32 are generated from the image data and switching of each AND gate is controlled depending on each of the data. In this embodiment, since a coefficient of the interpolation arithmetic operation is approximated by the n-th power of 2, the arithmetic operation itself is conducted by bit shift and addition 7 subtraction of data. A display section 15 displays the image signal processed by a signal processing section 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, an image processing device and a method thereof, and more particularly to an interpolation process of image data.

[0002]

2. Description of the Related Art Currently, personal computers (hereinafter referred to as P
As a display device of a host computer such as C) or a workstation (hereinafter, WS), a so-called CRT display device of raster scan type is widely used. And
In recent years, flat panel display devices such as liquid crystal panels and plasma displays have been attracting attention from the viewpoints of space saving, energy saving, ergonomics and the like.

A video signal, that is, a signal in which analog image data and vertical and horizontal synchronizing signals or a composite synchronizing signal thereof are combined is transmitted and received between the host computer and the CRT display device. There are numerous specifications for signal types, and in particular, a PC handles a plurality of video signals having different resolutions.

For example, an IBM PC compatible machine has 3
20 pixels x 200 lines (same below), 640 x 40
0,720 x 400, 640 x 350, 640 x 48
0,800 x 600, 1024 x 768, 1280 x 1
There are some such as 024 that can be displayed.

On the other hand, there is a so-called multi-sync CRT display device in the CRT display device, which detects the state of the synchronizing signal of the input video signal and determines the scanning period and the swing width of the scanning line. An image corresponding to each video signal is displayed by synchronizing with the synchronizing signal of the video signal.

At this time, with respect to some host computers, the state of the video signal or its synchronizing signal is measured in advance, and the measurement result is stored as a display parameter in the memory in the apparatus, and the synchronizing signal of the input video signal is stored. When the state is detected, if the host computer can be identified from the detection result, the display parameters in the memory are used to perform good display.

On the other hand, in the dot matrix display such as the current liquid crystal panel or plasma, the display control is suitable for the control by the digital signal. Therefore, the method of converting the input analog image signal into the digital signal and then displaying it. Is often taken. At this time, the sampling in the horizontal direction has the performance of the current dot matrix display, that is, one pixel is larger than the shadow mask of the CRT and is difficult to control. Therefore, one pixel of the video signal is displayed on the display panel 1. It is common to sample and display corresponding to pixels.

Therefore, in order to display multi-sync in which video signals of various resolutions are displayed on a fixed resolution dot matrix display, it is necessary to enlarge or reduce the screen by interpolation or thinning.

The most commonly used interpolation methods at present are the nearest neighbor interpolation method, the linear interpolation method and the cubic convolution interpolation method.

[0010]

However, the nearest neighbor interpolation method is a method in which the input data at the closest position is used as the interpolation data, and has the advantage of easy hardware implementation. However, there is a problem that the image quality after interpolation is significantly deteriorated.

The linear interpolation method is a method for obtaining interpolation data by using input data located on both sides of the interpolation data, and the scale and image quality at the time of hardware implementation are in the middle among the above three methods. Is the way to be located.

The cubic convolution interpolation method has the advantage that the deterioration of the image quality after interpolation is the least.
The scale at the time of hardware conversion becomes large, which leads to cost increase.

In view of the above problems, it is an object of the present invention to make it possible to reduce the circuit scale while maintaining good image quality.

[0014]

SUMMARY OF THE INVENTION In order to solve the conventional problems and to achieve the above-mentioned object, the present invention provides an input means for inputting image data and two input means for the image data from the input means. An interpolation means for obtaining interpolation image data by performing multiplication and addition with a coefficient represented by the n-th power (n is an integer), and a display means for displaying an image related to the output image data of the interpolation means are configured. Has been done.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a display device including an embodiment of the present invention.

The display device of the present embodiment is NTSC, PAL,
A composite video signal such as SECAM, a component video signal in which a luminance signal and a color difference signal are separated, and an analog computer input signal such as a PC or WS can be input.

In FIG. 1, reference numeral 11 is a processing unit for analog image signals from a host computer such as a PC or WS. The processing unit 11 includes a synchronization signal separation unit 101, a synchronization signal measurement unit 102, an A / D conversion unit 103, and a clock generation unit 10.
4, interpolation unit 10 and on-screen display (OS
D) It is composed of the switching unit 106.

Each block of the processing unit 11 will be described below.

Reference numeral 101 denotes a sync signal separation unit, which inputs an RGB image signal from a host computer or the like and a video signal s101 composed of a sync signal such as composite sync, separate sync or sync on green, and synchronizes with the image signal s102. Separated into signal. Further, a negative horizontal / vertical sync signal cs101 and a sync signal polarity determination signal cs102 are generated from the separated sync signals.

The separated image signal s102 is output to the A / D converter 103.

The sync signal cs101 is output to the sync signal measuring unit 102, the clock generating unit 104, the interpolation processing unit 105, and the system control circuit 191.

Here, the sync signal polarity discrimination signal cs102
Indicates the polarity of the input synchronization signal s101, and the synchronization signal measuring unit 102 and system control circuit 191
Is output to

Reference numeral 102 denotes a sync signal measuring unit, which
Vertical sync signal cs101 and sync signal polarity determination signal cs
Enter 102 and send the measurement results to the control bus cs1 as described below.
It outputs to the system control circuit 191 via 19.

The operation of the synchronization signal measuring section 102 will be described below.

FIG. 2 is a block diagram showing the configuration of the synchronization signal measuring section 102.

In FIG. 2, reference numeral 201 denotes a clock generator, which is a clock cs203 having a sufficiently high frequency necessary for the measurement operation of the period of the horizontal synchronizing signal (hereinafter HD signal) cs201 and the vertical synchronizing signal (hereinafter VD signal) cs202. Generate cs204.

Reference numeral 202 denotes a counter for measuring the period of the HD signal, which is the clock c from the clock generator 201 during the period from the fall of the HD signal to the fall of the next HD signal.
Count s203. Then, the count result c
S205 is written in the FIFO 205 as PHD1 in synchronization with the fall of the HD signal as described later.

Reference numeral 203 denotes a HD signal blanking period TH.
A counter that measures D (the level of the HD signal is 0 because it has a negative polarity).
The clock cs203 from the clock generator 201 is counted during the period until the signal falls. Then, the count result cs206 is written in the FIFO 205 as THD in synchronization with the fall of the HD signal, as described later.

Reference numeral 202 denotes a counter for measuring the period of the HD signal, which is a clock c from the clock generator 201 during the period from the rising of the HD signal to the rising of the next HD signal.
Count s203. Then, the count result c
S205 is written in the FIFO 206 as PHD2 in synchronization with the fall of the HD signal as described later.

Reference numeral 205 denotes a FIFO, which is the PHD described above.
1, THD and VD value data are stored for a period of 1 VD or more, and these data are stored in a bus cs1 via a read / write control circuit (hereinafter, R / W control circuit) 230.
It outputs to 19.

Reference numeral 206 denotes a FIFO, which is the same as the PHD2 described above.
The R / W control circuit 230 stores the data for a VD period or more.
Via the bus cs119.

Reference numeral 211 denotes a counter for measuring the number of HD signals in one VD cycle, which counts the clock cs204 from the clock generator 201 for one cycle period from the rising of the VD signal to the rising of the next VD signal.
Then, the count result cs213 is VD as TVD.
The register 2 is synchronized with the rising edge of the D signal as described later.
14 is written.

Reference numeral 214 is a register, which is the above-mentioned NHD, PV.
The D, VTD and the polarity discrimination signal cs102 are stored in synchronization with the VD signal and are output to the bus cs119 via the R / W control circuit 230 in response to the completion of writing of these values.

Reference numeral 221 denotes a HD number comparison register, which sets the number of HD signals to be compared to cs119 and the R / W control circuit 230.
To memorize.

Reference numeral 222 is a comparator, which is a counter 211.
And the output value of the register 221 are compared, and if they match, the cs222 is activated and a control signal is output to the cs119 via the R / W control circuit 230.

Reference numeral 230 is an R / W control circuit,
O205, 206, register 214, HD number comparison register 221, comparator 222, and control bus cs11
Controls the transmission of data to and from 9.

In such a structure, in this embodiment, the contents of the FIFOs 205 and 206 are as shown in FIG.
It looks like 4.

Returning to FIG. 1 again, the description will be continued.

Reference numeral 103 denotes an A / D converter, the detailed structure of which is shown in FIG.

In FIG. 5, reference numeral 330 denotes an A / D conversion circuit, which is an analog RGB signal s102 after the sync signal is separated.
The dot clock cs10 from the clock generator 104
3 is sampled and converted into a digital signal.

Reference numerals 331 to 333 denote latch circuits, which reduce the transfer rate of A / D-converted digital image data to 1/2 according to the dot clock cs103 and the control signal cs104 from the clock generator 104. ,
It is output as a digital RGB image signal s113.

Next, 104 is a clock generator,
A clock for sampling the image data s102 as described above, that is, a dot clock is generated.

Regarding the operation of the clock generator 104, FIG.
This will be described with reference to FIG.

FIG. 6 is a block diagram showing the configuration of the clock generator 104, which includes a phase comparator 305, charge pump type loop filters (hereinafter referred to as filters) 306 to 308, a voltage controlled oscillator (VCO) 310 and a frequency divider 304. It is composed of a PLL circuit having a basic structure.

Reference numeral 317 is a control circuit for communicating with the bus cs119 connected to the system control circuit 191 and storing control data for controlling the operation of the clock generator 104.

HD of the video signal input as described above
The signal is input to the I / F level control circuit 301. I /
In response to the control signal cs301, the F level control circuit 301 converts the level into a level suitable for an interface that has supplied a signal to the sync separation circuit 101, such as TTL or PECL, and outputs the level to the polarity inversion circuit 302.

The polarity reversing circuit 302 changes the polarity of the input synchronization signal so that the phase comparison operation can be performed at both the rising and falling edges of the HD signal when the phase comparison circuit 305 in the subsequent stage performs the phase comparison operation. It is controlled, and the polarity is switched according to the control signal cs302 and output to the delay circuit 303.

The delay circuit 303 inputs the HD signal and the dot clock, and performs a programmable delay adjustment of one dot clock period or more for the HD signal.
The delay time can be changed according to the control signal cs303.

As described above, the input video signal is separated into the sync signal and the image signal. Since these signals are input to different processing systems, the A / D converter 103
There is a phase difference between the image data input to the A / D conversion sampling clock generated by the clock generation unit 104. Therefore, the delay circuit 303 adjusts the phases of the image data and the sampling clock. The adjusted HD signal is used as the reference HD signal s302, and the phase comparison circuit 305 and the output level switching circuits 315 and 316 are used.
Is output to

The frequency divider 304 has a dot clock signal s30 output from a programmable counter 312 described later.
3 is divided by the division ratio set by the system control circuit 191, and the division ratio is controlled by the control signal cs305.

FIG. 7 shows the configuration of the frequency divider 304.

The frequency divider control signal cs304 includes three signals of a clock, data and a latch, and data is serially transferred to the shift register 320 in synchronization with the clock signal. After the data transfer is completed, the data in the shift register 320 is transferred to the register 321 of the main divider by the latch signal.

Reference numeral 323 is for determining that the value of the main divider 322 becomes 0, and when it becomes 0, the load signal c
The s320 is output to the main divider 322. The main divider 322 receives the load signal cs320 and transfers the data of the register 321 to the main divider 322.

The phase comparator 305 is a delay-adjusted reference H.
D signal s302 and output signal s304 from frequency divider 304
Enter and compare their phases. Then, the voltage signal corresponding to the phase difference is output to the filter 306.

Further, the phase comparator 305 outputs a phase lock signal cs314 indicating whether or not the phase is locked, and outputs it to the system control circuit 191 via the control circuit 317.

The filter 306 comprises a charge pump 306 and low pass filters 307 and 308. The filter 306 removes high frequency components and noise in the output signal from the phase comparator 305 and supplies a DC voltage to the VCO 306, and controls the response speed of the PLL by changing the charge pump current as follows. To do.

That is, the control circuit 317 sets the value set by the system control circuit 191 as the control signal cs307 to D.
The charge pump current is controlled by outputting it to the / A converter 309, converting it into a current corresponding to the value, and supplying it to the charge pump 306.

The response characteristic of the PLL is composed of a resistor and a capacitor, and has a predetermined filter coefficient.
07 or 308. As described above, in this embodiment, the response speed of the PLL can be controlled by adjusting the gain of the output signal of the phase comparator 305 and the filter constant.

The VCO 310 outputs a signal having a frequency according to the voltage of the output signal of the filter 306. Also,
The free-run frequency of the VCO 310 is determined by the output signal of the D / A converter 311. That is, the control circuit 3
Reference numeral 17 outputs a value corresponding to the frequency set by the system control circuit 191 to the D / A converter 311 as a control signal cs308, and the VCO self-oscillates at a frequency corresponding to the output voltage of the D / A converter 311. .

The programmable counter 312 is a VCO3.
It is a circuit that divides the output signal of 10 by the frequency division ratio set by the system control circuit 191, and the frequency division ratio is set by the control signal cs309 from the control circuit 317.

This counter 312 makes it possible to obtain a signal having a frequency lower than the variable frequency range of the VCO 310, and as a result, the lock range of the PLL can be expanded. On the contrary, since the variable frequency range of the VCO 310 can be narrowed, the stability of the oscillation operation of the VCO 310 is improved. Programmable counter 31
The output signal of 2 is the frequency divider 3 as the dot clock s303
04 and the delay circuit 313.

The delay circuit 313 adjusts the phase of the dot clock s303 and the reference HD signal s302 for the following reasons.

That is, the PLL circuit in the clock generator 104 locks the phase difference between the reference HD signal and the output signal of the frequency divider, that is, the frequency of the reference HD signal and the frequency of the output of the frequency divider are made equal. However, the phase difference is not adjusted. Therefore, since there is a phase difference between the reference HD signal and the dot clock, the delay circuit 3
13 delays the output signal of the programmable counter 312 according to the control signal cs310, and adjusts the phase difference between these signals. The output signal of the delay circuit 313 is output to the level switching circuits 314 and 315.

The level switching circuits 314 to 316 are TT
The output level is converted according to the clock supply destination such as L, ECL, or PECL.

The level switching circuit 314 is the delay circuit 31.
The dot clock s303 from 3 is input, converted to a level suitable for ECL, and output to the A / D conversion unit 103.

The level switching circuit 315 is the delay circuit 31.
The dot clock s303 from 3 and the reference HD signal s302 as a reset signal are input and converted to a level suitable for ECL and TTL, and the dot clock s303 is 1 /
Output the signal divided by two.

FIG. 8 shows an operation timing chart of the level switching circuit 315.

The low state of the reset signal s302 is detected at the rising edge b of the clock s303, and the output s10 is output.
4 and s106 are set to the reset state during the 4-cycle period of the clock s303.

At this time, in order to reliably latch the low state at the rising edge b, it is necessary to satisfy the setup time for b. Therefore, the delay circuit 313 adjusts the phase difference between the reset signal s302 and the dot clock s302 so that the setup time is satisfied. After that, the signals cs104 and cs106 are activated at the rising edge of the clock s303.

The ECL complementary signal cs104 is output as a demultiplexer signal of the A / D converter 103, and the TTL single end signal cs106 is output as a master clock of the interpolation circuit 105.

Next, the method of measuring the input video signal, identifying the model, and determining the display mode will be described.

9 and 10 show timing waveforms of general video signals.

In order to display an image satisfactorily on the dot matrix panel used in this embodiment, the outputs PHD1, PHD2, PVD, VD value, 1VD of the above-mentioned synchronizing signal measuring section
In addition to the parameters that can be directly obtained from the actually supplied sync signal such as the number of HD signals in the video, sync pulse width THD, VHD, horizontal / vertical display start time, front porch, back porch, and dot of image signal Parameters such as clocks are needed.

In this embodiment, in the memory 194,
The above-mentioned parameters of the output video signal of the host computer expected to be connected are measured in advance and stored as a display mode table. The display mode table also stores one set of default parameters used when the display mode cannot be specified. This default parameter is set to a value that seems to be most suitable based on the resolution of the display panel of the display device in this embodiment and a general video signal.

11 to 13 are diagrams showing some examples of the synchronizing signal of the video signal.

FIG. 11 shows the most general VD signal T
Although the polarity of the HD signal is inverted in synchronization with VD, the period of the HD signal is constant and the edge is constant at the trailing edge.

FIG. 12 shows a type in which the period of the HD signal changes in synchronization with the VD signal TVD, but the edge is constant at the falling edge.

FIG. 13 shows a type in which the cycle of the HD signal becomes constant when the detection edge is changed in synchronization with the VD signal TVD.

In this embodiment, as described above, in order to convert the image signal into the digital signal at the input, it is necessary to first form the sampling clock of the image signal synchronized with the HD signal. To this end, the system control circuit 191
After determining the model and the display mode as described later, various parameters are set in the control circuit 317 of the clock generation unit 104, so that the dot clock signal s303 and the various clock signals cs103 to cs10 generated from them.
By controlling the generation of 5, the desired sampling clock is obtained.

FIG. 14 is a diagram showing a rough flow of the operation when performing a series of control from the measurement of the input video signal, the specification of the model, and the determination of the display mode in this embodiment.

As shown in FIG. 14, this control can be divided into two: a sync signal change measuring module 701 and a display mode discrimination and control module 702.
The three modules operate independently.

The synchronization signal change measuring module 701 has some change such as changing the host device, disconnecting the cable connected to the host device, changing the display mode and changing the frequency of the synchronization signal. Is a module for detecting the display mode and issuing a display mode change request to the display mode determination and control module 702.

Display mode discrimination and control module 702
Is a module that receives a change request from the synchronization signal change detection module 701 and determines the display mode and controls the display mode.

Next, the operation of the sync signal change detection module 701 will be described with reference to FIG.

It is now assumed that the display is operating in some display mode. Then, first, in step S701, the system control circuit 191 observes the phase lock signal cs314 output from the clock generator 104. If the phase lock is released, it is determined that the input video signal has changed, and the process proceeds to step S704. .

In step S704, the system controller 19
The change end flag in 1 is cleared and a display mode change request is output to the display mode determination and control module.

When the phase is locked,
In step S702, the synchronization signal measuring unit 102 outputs H
The periods of the D signal and the VD signal are read out, and step S70
In step 3, compare with the previously read one. If they are the same, it is considered that the input video signal has not changed, and the process returns to step S701.

If the comparison result is different from the previous result, it is determined that a change has occurred, and the flow advances to step S704 to issue a display mode change request to the display mode determination and control module.

Thereafter, in step S705, the change processing flag is set in the system control circuit 191, and the end of the change processing is awaited. When the change process ends, step S706
And waits for the time required for the clock generator 104 to be phase-synchronized with the input image signal.
Observe 314.

Then, if the phase is locked, the process returns to step S701. If not, this module determines that it is not compatible and proceeds to step S707 to perform exception processing.

Next, the operation of the display mode determination and control module will be described with reference to FIG.

In this module, first, in step S751, the system control circuit 191 controls the R / W control circuit 230 of the sync signal measuring unit 102 to synchronize each parameter P for one VD period in synchronization with the rising edge of the VD signal.
HD1, PHD2, PVD, VD value, H during 1VD period
The number of D signals and THD, VHD are stored in the FIFO 205, 20
6 and the register 214.

Next, each parameter read in step S752 is compared with the contents of the display parameter table of the above-mentioned various host devices in the memory 194, and it is determined whether or not the model can be specified as one model.

If a match is found in the table, it can be specified as one model, and step S75
Proceed to 6. If it is not possible to specify one model, the process proceeds to step S754. If it is possible to specify a plurality of models, it is determined in step S755 whether the model setting switch of the key matrix 192 is set. To check.

Then, it is determined whether the setting display mode by the setting of the model setting switch is among the modes of the plurality of models specified in step S754. If there is a plurality of model modes, the setting mode by the model setting switch is specified as one mode, and the process proceeds to step S756.

In step S756, it is determined whether or not there is one type of falling period PHD1 of the HD signal. If there is one, the process proceeds to step S757 and the memory 19
Each parameter is read from the display mode table of No. 4. Then, the clock is output to the control circuit 317 of the clock generation unit 104 to control the frequency divider 304, the D / A converters 309, 311 and the like to generate a desired clock.

After that, in step S758, the change processing end flag is set, and the synchronization signal measurement module is notified of the end of the change processing.

On the other hand, the fall period PHD1 of the HD signal
If it is not one type, the process proceeds to step S759. If it is not one type, but the period detection edge is changed to one type in the middle, for example, the rising edge of the VD signal as shown in FIG. Including i fall HD
If the period PHD1 is t1, and then the number of N−i−1 PHD2 is t1, the process proceeds to step S760. Then, among the parameters of the display mode specified from the display mode table in the memory 194, the frequency divider 304, D / A
The parameters for controlling the converters 309 and 311 are output to the control circuit 317.

Next, proceeding to step S761, the number of HD signals at the changing point of the HD cycle detection edge, PHD (i-1).
And PHD (N-1) are read from the specified mode table, and the HD number comparison register 2 of the synchronization signal measuring unit 102 is read.
Write in 21.

Thereafter, the process proceeds to step S762, the change processing end flag is set, and in step S763, the value of the HD number comparison register of the sync signal measuring unit 102 and the number of HD signals in the input video signal match, and the comparator 222 outputs It is detected whether the control signal cs222 of 1 has become active. When the control signal cs222 becomes active, the process proceeds to step S764, and it is determined whether the detection edge of the next HD cycle is to fall or rise, that is, in the example of FIG. 13, the count value of the HD signal is PHD.
If it is (i-1), it is determined to fall, and if it is PHD (N-1), it is determined to be fall. If it is a fall, step S
At 765, the polarity inversion circuit 30 is supplied to the clock generation unit 104.
2 is controlled so that the phase comparator 305 performs the phase comparison detection operation at the falling edge, and if the phase rises, the phase comparator 305 performs the phase comparison detection operation at the rising edge in step S766.

Then, returning to step S763, the phase comparison edge is changed by repeating this operation.

On the other hand, in step S759, one model (display mode) can be specified, but when there are a plurality of types of HD signals, for example, i PHD1 including the rising edge of the VD signal as shown in FIG. Is t1, and then the N-i PHD1s are t2, step S7
In 67, the number of HD signals at the changing point of the HD cycle of the parameter of the specified mode from the display mode table of the memory 194, PHD (i-1) and PHD (N-1) are read out, and the HD number of the synchronization signal measuring unit 102 is read. Comparison register 221
Write to.

Thereafter, in step S768, the change processing end flag is set, and in step S769, it is detected whether the HD number comparison register 221 and the number of HD signals match and the control signal cs222 from the comparator 222 is activated. . When the control signal cs222 becomes active, the corresponding parameter is read from the display mode table in step S770, and the clock generation operation of the clock generation unit 104 is controlled as described above. Then, it returns to step S769.

Even if the HD cycle changes in this way, the dot clock signal s303 and each clock signal cs103 to
The cs105 can be controlled to have a desired frequency and phase.

Now, step S754 or S755
If the display mode of the input video signal cannot be specified in step S721, step S75 is executed.
Similar to 6 and 759, it is determined whether the HD cycle of the video signal becomes 1 or becomes 1 if the HD detection edge is changed.

If there is one HD cycle, step S
At 772, substantially the same processing as the processing of steps S757 to 758 is performed. That is, first, the parameters of the default mode are read from the display mode table of the memory 194, and the operation of the clock generator 104 is controlled as described above. After that, in step S773, the change processing end flag is set to notify the synchronization signal measurement module of the end of the change processing.

On the other hand, if the falling period PHD1 is not one type, the process proceeds to step S774 and step S7.
Similar to 59, the number is not simply one type, but if the period detection edge is changed in the middle to be one type, for example, as shown in FIG. The cycle PHD1 is t1, and then N-i-
If one PHD2 is t1, step S
Processing similar to that of 760 to 766 is performed.

That is, in step S775, the memory 1
The parameters of the default display mode are read from the display mode table 94 and output to the clock generation unit 104. Next, proceeding to step S776, the number of HD signals at the changing point of the HD cycle detection edge, PHD (i-1) and PHD
(N-1) is read and written in the HD number comparison register 221 of the synchronization signal measuring unit 102.

After that, the flow advances to step S777 to set a change processing end flag. Then, in step S778, the value of the HD number comparison register 221 and the count value of the HD signal match, and the control signal cs22 from the comparator 222.
Detects if 2 has become active. When the control signal cs222 becomes active, the process proceeds to step S779, it is determined whether the detection edge of the next HD cycle is to fall or rise, and the clock generation unit 104
The polarity reversing circuit 302 is controlled. At this time, the phase comparison enable signal cs305 is temporarily set to the inhibit state (operation prohibited state) before and after the polarity inversion so that the phase difference detection operation is not disturbed.

When the control of the detection edge of the HD signal is completed, the process returns to step S778, and the above operation is repeated to control the phase comparison edge according to the input video signal.

On the other hand, if it is not possible to specify one display mode in step S774 and there are a plurality of HD cycles within the VD period, for example, in the case of FIG. 12, step S774.
Proceed to 782.

In FIG. 12, i PHD1s are t1 including the rising edge of the VD signal, and then N−i PHs.
There are two types of HD periods in which D1 is t2. Now i
> N-i, the one having the maximum number of appearances in the HD period in FIG. 12 is the one having the period t1, and the number of the HD signal immediately before the change from this maximum period to another period is i. −
H, which is 1 and is the immediately preceding H that changes from the other period to the maximum period.
The number of D signals is N-1.

In such a case, in step S782, the maximum HD cycle and the number of appearances of the plurality of types of HD cycles are first detected, and the other HD is detected from the maximum number of HD cycles.
The HD signal number NHD1 before changing to the cycle and the HD signal number NHD2 before changing to the maximum number of HD cycles from other cycles are set in the HD number comparison register 221 of the synchronization signal measuring unit 102.

Then, in step S783, the memory 19
The parameters of the default display mode are read from the display mode table of 4 and output to the clock generation unit 104,
The clock generation operation is controlled as described above.

Thereafter, in step S784, the change processing end flag is set, and the flow advances to step S785. In step S785, it is detected whether the value of the HD signal comparison register 221 and the count value of the HD signal match, and the comparator 222 outputs the active control signal cs222. When the control signal cs222 becomes active, the process proceeds to step S786, which indicates that the control signal is the previous HD signal that changes from the maximum number of HD cycles to another cycle, or another cycle. To the maximum number of HD
It is determined whether or not it indicates that the HD signal is one before the period. (That is, it is determined whether the next HD cycle is the maximum number of HD cycles or another cycle.)

If the result of determination is that the number of HD cycles is not the maximum, the process advances to step S787 to control the clock generator 104 so as to prohibit the operation of the phase comparator 305.

If it is the maximum number of HD cycles, the flow advances to step S788 to control the clock generator 104 so as to allow the comparison operation of the phase comparator 305. Then, the process returns to step S785 and the above operation is repeated.

With this configuration, the PLL is locked with respect to the maximum number of HD signals in one cycle of the VD signal, a clock phase-synchronized with the maximum number of HD signals is generated, and the PLL The unlock period can be minimized. Therefore, the PL due to the change of the synchronization signal
Disturbance of L can be minimized and a stable clock can be generated, so that a good display operation can be performed.

In the present embodiment, as described above, regarding the determination of the display mode, the control signal cs indicating the locked / unlocked state of the phase comparator 305 in the clock generator 104.
According to 314, it is confirmed whether the judgment is correct.

The confirmation operation using the lock / unlock control signal will be described below with reference to the flowchart of FIG.

When the mode discrimination module described above is completed, the system control circuit 191 confirms the state of the control signal cs314 from the clock generator 104 in step S1001. Then, when the PLL is in the unlocked state, it is determined that the display mode of the input image signal and the output signal from the host computer are changed to those having different specifications, and the process proceeds to step S1002. If the PLL is locked, the confirmation process ends.

In step S1002, the frequency of the HD / VD signal is newly received from the synchronization signal measuring section 102.
Then, in step S1003, the HD signal frequency is between the lowest frequency (Hbottom, hereafter Hb) that can be supported and the predetermined frequency AHz, and the lowest frequency (Vbottom, hereafter Vb) that the VD signal can support is the predetermined frequency. Determine if it is between BHz.

If the frequency of each synchronizing signal is between these frequencies, a predetermined mode 0 is set in step S1004.
As the mode 0 between the modes up to M, the clock generator 104 and the display operation according to the mode 0 are controlled. Then, in step S1005, it is determined again whether or not the PLL is locked. If locked, it is determined in step S1006 that the current mode is mode 0, and the process ends. If it is in the unlocked state again in step S1005, it is determined that the current mode is not mode 0, and the process proceeds to the determination process.

Then, in steps S1003 to S10 described above.
The processing up to 05 is repeated up to the mode M. If the input image signal has not been specified from mode 0 to mode M, it is determined that the current input image signal cannot be handled, and in step S1015, processing at the time of inability to be handled, for example, is displayed on the display unit 15. And finish.

Reference numeral 105 denotes an interpolation section, which is a digitized RGB image signal s obtained from the A / D conversion section 103.
Vertical interpolation processing is performed on 103, and the resolution is converted to a resolution that matches the display resolution of the display panel 15.

First, the algorithm used in this interpolation section will be described.

Here, the interpolation processing performed by the interpolation unit 105 will be described in detail with reference to FIGS. As the interpolation processing method, the most commonly used methods include the nearest neighbor interpolation method, the linear interpolation method (first-order interpolation method), and the third-order convolutional interpolation method.

The nearest neighbor interpolation method is a method in which the pre-interpolation pixel closest to the pixel to be interpolated is used as the interpolation pixel.

The linear interpolation method is a method of obtaining image data of pixels to be interpolated using image data of pixels on both sides of the pixel to be interpolated. For example, as shown in FIG. 17, when the pixel b is interpolated at the positions (between the pixels a1 and a2) at the distances u and v from the pixels a1 and a2 arranged at the distance interval 1, respectively, the image of the pixel b The data is obtained by the equation (1).

B = a1 × u / (u + v) + a2 × V / (u + v) (1)

On the other hand, the cubic convolutional interpolation method is a method of obtaining image data of two pixels on both sides of the pixel to be interpolated and image data of the pixel to be interpolated using the cubic convolution function. The cubic convolution function f is given by the equation (2) where t is the distance between the pixel to be interpolated and two pixels on both sides arranged at the distance interval 1.

F (t) = sin (πt) / (πt) (2) The formula (2) depends on the range of t, and formulas (3), (4), and (5)
It is deployed like.

F (t) = 1-2 | t | ² + | t | ³ (0 ≦ | t | <1) (3) f (t) = 4-8 | t | +5 | t | ² − | t | ³ (1 ≦ | t | <2) (4) f (t) = 0 (2 ≦ ltl) (5)

For example, as shown in FIG. 22, the pixels a1, a2, a3, a4 arranged at the distance interval 1 to u are respectively arranged.
Positions at a distance of 1, u2, u3, u4 (pixels a2 and a
When the pixel b is interpolated (between 3), the image data of the pixel b is obtained by the equation (6) using the cubic convolution function f.

B = a1 (4-8 × u1 + 5 × u1 ² −u1 ³ ) + a2 (1-2 × u2 ² + u2 ³ ) + a3 (1-2 × u3 ² + u3 ³ ) + a4 (4-8 × u4 + 5 × u4) ^{2 -u4 3)} (6)

Here, using equations (1) and (6), as an example, a case of performing interpolation processing from 768 pixels to 960 pixels by a linear interpolation method (first-order interpolation method) and a third-order convolutional interpolation method , FIG. 19 will be described. In the case of this example, the interpolation data of 8 pixels is created from the data before interpolation of 5 pixels. Therefore, the image data bn after linear interpolation and the image data b after interpolation by the cubic convolutional interpolation method
n is given by equation (7) and equation (8) using the image data an before interpolation.

B5n + 1 = a4n + 1 (n = 0, 1, 2, ...) b5n + 2 = (4/5) × a4n + 1 + (1/5) × a4n + 2 b5n + 3 = (3/5) × a4n + 2 + (2/5) × a4n + 3 b5n + 4 = (2/5) × a4n + 3 + (3/5) × a4 (n + 1) b5n + 5 = (1/5) × a4 (n + 1) + (4/5) × a4 (n + 1) +1 (7) b5n + 1 = a4n + 1 (n = 0,1,2 ...) b5n + 2 = (-4/125) * a4n + (29/125) * a4n + 1 + (116/125) * a4n + 2 + (-16/125) * a4n + 3 b5n + 3 = (-12/125) * a4n + 1 (62/125) * a4n + 2 + (93/125) * a4n + 3 + (-18/125) * a4 (n + 1) b5n + 4 = (-18/125) * a4n + 2 + (93 / 125) * a4n + 3 + (62/125) * a4 (n + 1) + (-12/125) * a4 (n + 1) +1 b5 (n + 1) = (-16/125) * a4n + 3 + (116/125) * a4 (n + 1) ) + (29/125) × a4 (n + 1) +1 + (-4/125) × a4 (n + 1) +2 (8)

However, if the interpolation processing by the linear interpolation method or the cubic convolutional interpolation method is executed by the hardware (ASIC) using the equations (7) and (8), the calculation of complicated fractions is required. Therefore, the scale becomes unrealistic.

Therefore, in this embodiment, in order to realize the interpolation processing by the linear interpolation method or the cubic convolution interpolation method with a small-scale hardware (ASIC), the coefficients of the expressions (7) and (8) are used. Is approximated by the sum of the exponents of 2. The approximation results of equations (7) and (8) are shown in equations (9) and (10), respectively.

B5n + 1 = a4n + 1 (n = 0, 1, 2, ...) b5n + 2 = (1/2 + 1/4) × a4n + 1 + (1/4) × a4n + 2 b5n + 3 = (1/2 + 1/8) × a4n + 2 + (1/4 + 1 / 8) xa4n + 3 b5n + 4 = (1/4 + 1/8) * a4n + 3 + (1/2 + 1/8) * a4 (n + 1) b5n + 5 = (1/4) * a4 (n + 1) + (1/2 + 1/4) * a4 ( n + 1) +1 (9) b5n + 1 = a4n + 1 (n = 0,1,2 ...) b5n + 2 = (-1/16) * a4n + (1/4) * a4n + 1 + (1/2 + 1/4 + 1/8 + 1/16) * a4n + 2 + (-1/8) * a4n + 3 b5n + 3 = (-1/8) * a4n + 1 + (1/2) * a4n + 2 + (1/2 + 1/4) * a4n + 3 + (-1/8) * a4 (n + 1) b5n + 4 (-1/8) * a4n + 2 + (1/2 + 1/4) * a4n + 3 + (1/2) * a4 (n + 1) + (-1/8) * a4 (n + 1) +1 b5 (n + 1) = (-1 / 8) × a4n + 3 + (1/2 + 1/4 + 1/8 + 1/16) × a4 (n + 1) + (1/4) × a4 (n + 1) +1 + (− 1/16) × a4 (n + 1) +2 (10)

The approximation from equation (7) to equation (9) was performed so that the number of coefficient terms was as small as possible and the maximum approximation error was within 1/20. Further, the approximation from the equation (8) to the equation (10) is also performed so that the number of coefficient terms is as small as possible and the maximum approximation error is within 1/32.

If it is desired to reduce the deterioration of the image quality due to the interpolation processing, the maximum approximation error is further reduced by adding a term smaller than 1/64. On the contrary, when it is desired to make the hardware (ASIC) smaller, the approximation error increases but the hardware (ASIC) scale can be reduced by omitting small terms such as 1/64 and 1/32. it can.

Similarly, the approximation result in the case of performing interpolation from 480 pixels to 960 pixels is expressed by equation (11) for linear interpolation and equation (1) for cubic convolutional interpolation.
See 2).

B2n + 1 = an + 1 (n = 0,1,2 ...) b2 (n + 1) = (1/2) × an + 1 + (1/2) × an + 2 (11) b2n + 1 = an + 1 (n = 0,1,2 ... ) B2 (n + 1) = (-1/8) * an + (1/2 + 1/8) * an + 1 + (1/2 + 1/8) * an + 2 + (-1/8) * an + 3 (12)

Further, similarly, from 600 pixels to 960
The approximation result when the interpolation to the pixel is performed is expressed by Equation (13) for linear interpolation and Equation (1) for cubic convolutional interpolation.
See 4).

B8n + 1 = a5n + 1 (n = 0, 1, 2, ...) b8n + 2 = (1/2 + 1/8) × a5n + 1 + (1/4 + 1/8) × a5n + 2 b8n + 3 = (1/4) × a5n + 2 (1/2 + 1 / 4) × a5n + 3 b8n + 4 = (1/2 + 1/4 + 1/8) × a5n + 2 + (1/8) × a5n + 3 b8n + 5 = (1/2) × a5n + 3 + (1/2) × a5n + 4 b8n + 6 = (1/8) × a5n + 4 + ( 1/2 + 1/4 + 1/8) × a5 (n + 1) b8n + 7 = (1/2 + 1/4) × a5n + 4 + (1/4) × a5 (n + 1) b8 (n + 1) = (1/4 + 1/8) × a5 (n + 1) ) + (1/2 + 1/8) * a5 (n + 1) +1 (13) b8n + 1 = a5n + 1 (n = 0,1,2 ...) b8n + 2 = (-1/16 + -1 / 32) * a5n + (1 4 + 1/8 + 1/16 + 1/32) * a5n + 1 + (1/2 + 1/4) * a5n + 2 + (-1/8) * a5n + 3 b8n + 3 = (-1/8) * a5n + 1 + (1/2 + 1/4 + 1/8) * a5n + 2 + (1/4 + 1/32) × a5n + 3 + (− 1/32) × a5n + 4 b8n + 4 = (− 1/64) × a5n + 1 + (1/8 + 1/64) × a5n + 2 + (1/2 + 1/4 + 1/8 + 1/16 + 1/32) Xa5n + 3 + (-1/16 + -1 / 32) * a5n + 4 b8n + 5 = (-1/8) * a5n + 2 + (1/2 + 1/8) * a5n + 3 + (1/2 + 1/8) * a5n + 4 + (-1/8) Xa5 (n + 1) b8n + 6 = (-1/16 + -1 / 32) * a5n + 3 + (1/2 + 1/4 + 1/8 + 1/16 + 1/32) * a5n + 4 + (1/8 + 1 / 4) xa5 (n + 1) + (-1/64) x a5 (n + 1) +1 b8n + 7 = (-1/32) xa5n + 3 + (1/4 + 1/32) xa5n + 4 + (1/2 + 1/4 + 1/8) x a5 (n + 1) + (-1/8) * a5 (n + 1) +1 b8 (n + 1) = (-1/8) * a5n + 4 + (1/2 + 1/4) * a5 (n + 1) + (1/4 + 1/8 + 1 / 16 + 1/32) × a5 (n + 1) +1 + (− 1/16 + −1 / 32) a5 (n + 1) +2 (14)

Next, a configuration example of the interpolation processing unit 105 will be described in detail with reference to FIG.

FIG. 21 is a detailed block diagram of a vertical interpolating device for vertically interpolating the input effective display image data and enlarging and displaying it on the dot matrix display.

In the figure, 401 is an input circuit for inputting digital image data output from the AD converter, 402 is a control input circuit for controlling vertical interpolation processing, and 402a is set by the system control circuit. A memory for storing the setting data, 402b is a setting supply circuit for supplying the stored setting data to another processing device, 403
Is a sync input circuit for inputting a clock and a sync signal, 40
Reference numeral 4 denotes an output circuit that outputs image data and a synchronization signal to a digital processing circuit at a subsequent stage, 405 denotes an output clock supply circuit that determines a transfer rate when the output circuit outputs image data, and 406 denotes an input image. Reference numeral 407 denotes an interpolation control circuit that controls the vertical interpolation processing circuit 406 by performing digital processing using data to increase horizontal lines.

In such a configuration, the input circuit 401
Is the data signal line S1 output from the A / D conversion unit 103.
Image data input via the synchronization input circuit 4
The signal is output to the vertical interpolation processing circuit 406 in synchronism with each signal input to 03. The vertical interpolation processing circuit 406 is stored in the memory 402a of the control input circuit 402, performs processing based on the setting data supplied by the setting supply circuit 402b, and outputs the output circuit in synchronization with the clock supplied from the output clock supply circuit 405. Image data is sent from the switch 404 to the switch 106. When the vertical interpolation processing is not performed, the clock supplied from the synchronization input circuit 403 is used to output the image data from the output circuit 404 to the switch 106.

FIG. 22 is a diagram showing a detailed configuration of the vertical interpolation processing circuit 406 and the interpolation control circuit 407 shown in FIG.

In the figure, 406a is a flip-flop (F / F) for synchronizing the image data and the synchronizing signal.
F) circuit, 406b is an input FIFO memory that stores data for one horizontal line, 406C is an arithmetic circuit that performs arithmetic processing on image data input using interpolation coefficients, and 406d is interpolation arithmetic. And an output FIFO memory 406e for storing image data after the output FI.
The output of the FO memory 406d is selected and the switch 40 at the subsequent stage is selected.
6 f is a switch for transferring to 6 f, 406 f is a switch for selecting a through path when the interpolation coefficient is 1, that is, when interpolation is not performed, and 407 a is for controlling the input timing of image data and the data writing timing and reading timing of the FIFO memory 406 b. Input FIFO control circuit,
An output FIFO 407b controls the timing of the arithmetic circuit and the write timing of the output FIFO memory 406b.
O write control circuit, 407c is an output FIFO control circuit for controlling the read timing of 407d, 407d is a display position detection circuit for detecting a display start position, and 407e is image data and a synchronization signal output from the vertical interpolation processing circuit 406. Output display position correction circuit for adjusting the timing of
Reference numeral 7f is an arithmetic control circuit for controlling the index of each line.

In such a configuration, the input circuit 401
The input image data is synchronized by the control signal of the input FIFO control circuit 407a in the F / F circuit 406a, and the image data is transferred to the input FIFO memory 406b. Each input FIFO memory 406b has one
The input FIFO control circuit 407a controls the image data such that the image data delayed by horizontal lines is sequentially transferred.

The arithmetic circuit 406c is the arithmetic control circuit 407.
Image data of the same horizontal column is input to the arithmetic circuit 406c by a control signal from f, a vertical interpolation line is generated, and the vertical interpolation line is stored in the output FIFO memory 406d under the control of the output FIFO control circuit 407c. The stored image data is read by a signal from the output FIFO control circuit 407c, and the switch 406e and the switch 40e
The image data is transferred to the switch 106 via 6f. At the time of transfer, a signal synchronized with the image data is generated by the output display position correction circuit 407e and transferred.

FIG. 23 is a block diagram showing the structure of the arithmetic circuit 406c for the input image data.

In the figure, the exponent arithmetic circuit 406c1
Is the F / F circuit 406a or the input FIFO memory 40.
The image data of each line is received from 6b and multiplied by a predetermined index individually, and the image data is transferred to the 4-input adder 406c2 for addition. The image data of the addition result is sent to the code processing circuit 406c3 and is changed to the minimum value "00" (6 bits, hexadecimal number) when the calculation result is negative, and the maximum value "3F when it exceeds the maximum value. ”
It is changed to (6 bits, hexadecimal).

FIG. 24 is a diagram showing a detailed structure of the exponential calculation circuit 406c1.

In the figure, values of 1/32 to 32/32 are created for the input image data, and opening / closing of each AND gate is controlled according to the value. That is, in the present embodiment, the coefficient of the interpolation calculation is approximated by the power of 2 so that the actual calculation itself can be performed by bit shift and addition / subtraction of each data. Therefore, the arithmetic control circuit 407f may actually control which of the AND gates is opened. The 2's complement calculator converts the image data of the preceding stage into a negative number. The selector selects the image data that has passed through the 2's complement calculator and the image data that does not pass through, and transfers the image data to the 4-input adder 406c2.

FIG. 25 shows horizontal 640 which is one of the display modes of VGA which is a graphic card of IBM Corporation.
FIG. 8 is a schematic operation explanatory diagram for performing vertical interpolation processing in the case of dots and 350 vertical lines.

In this case, in the input image signal, horizontal 640 dots are sampled twice per dot to be expanded to 1280 dots, vertical is increased from 350 lines to 490 lines by the vertical interpolation processing of the interpolation unit 105, and the dot matrix display is used. Further, by expanding 2 lines within 15, the vertical with an approximate aspect ratio is increased to 980 lines. Dot matrix display 1.5
Then, the display is performed in the effective display area of horizontal 1280 dots and vertical 980 lines.

In the interpolation process, image data is input at the timing shown in FIG. In this example, the time for one horizontal line is 31.778 uS, of which 25.4 uS.
22uS contains valid image data. Also,
In the case of this vertical interpolation processing, the output is 7 for the input line 5.
The line must be created. Therefore, the equation (a) in the figure is obtained and the output cycle is 22.699 uS.
Depends on. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 39.1
Determined from 6 MHz to 28.196 MHz. Regarding the relationship between the input timing and the output timing, it is necessary to start output after two lines are input and output seven lines while five lines are input.

Next, in (c), the input line and the output FIFO are
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

FIG. 26 is a schematic operation explanation for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA standard. In this case, in the input image signal, the effective display period of 800 horizontal dots is sampled at 1280 to be expanded to 1280 dots, and the vertical is increased from 600 lines to 960 lines whose vertical aspect ratio is approximated by the vertical interpolation processing of the interpolation unit 105. . As a result, on the dot matrix display 15, display is performed in an effective display area of 1280 horizontal dots and 960 vertical lines.

In the interpolation processing, the image data is input at the timing shown in FIG. In the case of this example, the time for one horizontal line is 28.444 uS, of which 22.2
22uS contains valid image data. Also,
In the case of this vertical interpolation processing, the output is 8 for the input line 5.
The line must be created. Therefore, the equation (a) in the figure is obtained and the output cycle is 17.778 uS.
Depends on. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 55.3
Determined from 85 MHz to 36.000 MHz. The relationship between the input timing and the output timing is that the output starts after 2 lines are input, and the output is changed to 8 after 5 lines are input.
Need to do the line.

Next, in (c), the input line and the output FIFO are
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

FIG. 27 is a schematic operation diagram for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA standard. In this case, in the input image signal, the effective display period of 800 horizontal dots is sampled at 1280 to be expanded to 1280 dots, and the vertical is increased from 600 lines to 960 lines whose vertical aspect ratio is approximated by the vertical interpolation processing of the interpolation unit 105. . As a result, on the dot matrix display 15, display is performed in an effective display area of 1280 horizontal dots and 960 vertical lines.

In the interpolation processing, in the case of this example in which image data is input at the timing shown in (b) in the figure, the time for one horizontal line is 26.400 uS, of which 20.00
Valid image data is included in 0 uS. Also, in the case of this vertical interpolation processing, eight lines of output must be created for the input line 5. Therefore, in the figure (a)
The output cycle is determined to be 16.500 uS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In this example, 63.3663
Determined from MHz to 38.7878 MHz. Regarding the relationship between the input timing and the output timing, it is necessary to start output after two lines are input and output eight lines while five lines are input.

Next, in (c), an input line and an output FIFO are provided.
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

FIG. 28 is a schematic operation explanation for performing vertical interpolation processing in the case of 800 dots in the horizontal direction and 600 lines in the vertical direction of the VESA standard. In this case, in the input image signal, the effective display period of 800 horizontal dots is sampled at 1280 to be expanded to 1280 dots, and the vertical is increased from 600 lines to 960 lines whose vertical aspect ratio is approximated by the vertical interpolation processing of the interpolation unit 105. . As a result, on the dot matrix display 15, horizontal 1280 dots and vertical 960 lines are displayed in the effective display area.

In the interpolation processing, the image data is input at the timing shown in FIG. In the case of this example, the time for one horizontal line is 20.800 uS, of which 16.0
Valid image data is included in 00uS. Also,
In the case of this vertical interpolation processing, the output is 8 for the input line 5.
The line must be created. Therefore, the expression (a) in the figure is obtained and the output cycle is 13.000 uS
Depends on. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 78.0
It is determined from 48 MHz to 49.231 MHz. The relationship between the input timing and the output timing is that the output starts after 2 lines are input, and the output is changed to 8 after 5 lines are input.
Need to do the line.

Next, in (c), an input line and an output FIFO are provided.
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

FIG. 29 is a schematic operation diagram for performing vertical interpolation processing in the case of 1024 horizontal dots and 768 vertical lines in the VESA standard. In this case, in the input image signal, the effective display period of 1024 dots in the horizontal direction is sampled at 1280 and expanded to 1280 dots, and the vertical is increased from 768 lines to 960 lines whose vertical aspect ratio is approximated by the vertical interpolation processing of the interpolation unit 105. . As a result, in the dot matrix display 15, the horizontal 1280
The dots and the vertical lines are displayed in an effective display area of 960 lines.

In the interpolation processing, the image data is input at the timing shown in FIG. In the case of this example, the time for one horizontal line is 17.707 uS, of which 13.6
Valid image data is included in 53uS. Also,
In the case of this vertical interpolation processing, the output is 5 for the input line 4.
The line must be created. Therefore, the equation (a) in the figure is obtained and the output cycle is 14.1656u.
Determined by S. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 63.
Determined from 2 MHz to 45.2 MHz. Regarding the relationship between the input timing and the output timing, it is necessary to start the output after inputting 2 lines and output for 5 lines while inputting 4 lines.

Next, in (c), an input line and an output FIFO are provided.
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

FIG. 30 shows Apple's Macintosh.
h-series 1 mode horizontal 1024 dots, vertical 76
9 is a schematic operation description for performing vertical interpolation processing in the case of 8 lines. In this case, the input image signal is sampled at 1280 during the effective display period of 1024 horizontal dots and 1280
The dots are enlarged and the vertical direction is changed from 768 lines to the interpolation unit 10.
The vertical interpolation processing of No. 5 increases the vertical with an approximate aspect ratio to 960 lines. This allows the dot matrix display 15 to display 1280 dots horizontally and 9 dots vertically.
The display is performed in the effective display area of 60 lines.

In the interpolation processing, the image data is input at the timing shown in FIG. In the case of this example, the time for one horizontal line is 16.6 uS, of which 12.8 uS
It contains valid image data. Also, in the case of this vertical interpolation processing, 5 lines of output must be created for the input line 4. Therefore, the equation (a) is used and the output cycle is determined to be 13.28 uS. Furthermore, the output cycle of the output is determined from the relationship of the valid data period. In the case of this example, 67.5 MHz to 48.
2MHz is decided. As for the relationship between the input timing and the output timing, it is necessary to output five lines after inputting two lines and starting output for four lines.

Next, in (c), the input line and the output FIFO are
The relationship of the O memory 406d is described, and when the line of the cycle number of the input line on the left is input, control is performed so that the line of the cycle line number illustrated in the figure is input in each output FIFO memory. Be seen.

In the interpolation process as described above, in the case of the horizontal 800 dots and vertical 600 lines described with reference to FIGS. 26 to 28, unlike the other cases, the third line is input and the interpolation line There is a case where data output is started and data is output before data to be interpolated is input. Therefore, the start of the output of the interpolated line data is controlled so that the interpolated line is output from a predetermined time after the data of the third line is input.

Referring again to FIG. 1, a TV (television) signal processing unit 12 includes a TV tuner 121, a decoder unit 122, an OSD switching circuit 123, an interlaced / non-interlaced conversion circuit 124, and a horizontal interpolation processing circuit 125. Consists of.

A TV tuner 121 receives the modulated TV radio wave s106, performs tuning, amplification and detection, and outputs a composite analog image signal s109 such as NTSC, PAL, SECAM and the like and an audio signal s115. is there.

Reference numeral 122 is a color decoder,
Composite image signal s10 from the V tuner 121
9 or external input s107 is subjected to A / D conversion, color difference demodulation, matrix conversion into RGB signals,
The interlaced digital RGB signal s110 and the control signal cs108 are output.

Further, the S signal 108 (YC separated image signal)
Can also be input, and the color decoder 122 can be used for A / D
Conversion and matrix conversion into RGB signals are performed, and s110 and cs108 are similarly output.

Reference numeral 123 is an OSD switching circuit, which is an interless RGB image signal s110 from the decoder 122.
And a signal s118 from the OS control circuit 193 described later.

Reference numeral 124 denotes an interlace / non-interlace (field / frame) conversion circuit for converting the interlaced RGB image signal from the switch 123,
Interlace / non-interlace (field / frame) conversion. That is, from a 50 (60) Hz non-interlaced (field) signal, 50 (60) H
z non-interlaced (frame) signal converted to non-interlaced 50 (60) Hz RGB image signal s11
It is output as 2.

Reference numeral 125 denotes a horizontal interpolation processing circuit, which outputs the non-interlaced RGB image signal s112 to the display unit 1.
Interpolation processing is performed so that the horizontal resolution becomes equal to the horizontal resolution of 5, and the RGB image signal s113 is output. Since the interpolation processing performed here is interpolation processing with double the resolution in the horizontal direction, it is performed by reading the same data twice.

Reference numeral 13 denotes a changeover switch for switching between the PC / WS processing unit 11 and the TV signal processing unit 12, which is controlled by the system control unit 191 through the cs 112.
/ Image data s105 of the WS processing unit 11, synchronization signal cs
107 and the image data s113 of the TV signal processing unit 12,
The synchronization signal cs110 is switched, and the image data s114 and the synchronization signal cs111 are output.

Reference numeral 14 denotes a digital image processing section, which performs various kinds of processing and control for displaying the digital image data s114 from the switch 13 on the dot matrix panel 15.

Next, the processing performed in the digital processing section 14 will be described in detail with reference to FIG.

In FIG. 31, a video input signal s11 of NTSC or the like which is switched by the switch 132 and input.
3 and the computer input signal s105 are subjected to γ correction processing and gradation adjustment processing in the contrast adjusting means 501.

This gamma correction process will be described with reference to FIG. FIG. 32 shows that γ = 2.2, 8-bit input, 8
It is a figure which shows the relationship between input data and output data in the case of bit output. When the input data is, for example, a, γ = 1.
When 0, the output data is a, but when γ = 2.2, the output data is b (<a), and an image with a higher contrast than that when γ = 1.0 is obtained.

Next, the gradation adjustment processing will be described with reference to FIG.

When the gradation adjustment processing is not performed, a linear output value is obtained with respect to the input value as in 100% of FIG. 33. However, when 50% gradation adjustment is performed, 0 to 64, and The output values corresponding to the input data from 192 to 255 are attached to 0 and 255, respectively, and the input data in the meantime changes by twice the change amount of the input data, as shown in FIG.

Also, the value of gradation adjustment is made small (% is lowered).
As a result, a more contrasted image can be obtained. The adjustment value in the γ correction process and the gradation adjustment can be determined by operating the key input unit 192, and the system control circuit 191 that has received the determination value.
Thus, the contrast conversion circuit 501 is controlled.

Gamma-corrected and tone-adjusted data s
501 is a halftone processing circuit 502, for example, ED
Halftone processing such as (error diffusion) method and dither method is performed.

The motion detection circuit 504 steals the display data before the halftone processing, detects a line that has changed by a certain value or more, and outputs the result to the system control circuit 191.
Transfer to Of the frame display data stored in the memory 503, the system control circuit 191 outputs to the display control circuit 505 only the display data of the line in which the motion is detected, together with the line address data.

Reference numeral 15 designates a display section using a so-called dot matrix display using liquid crystal for image display, and comprises a display control circuit 505 and a display panel 506 using a dot matrix display as shown in FIG. The image signal processed by the 1.4 digital processing unit is displayed.

In FIG. 31, the signal processing unit 1 as described above.
The image signal s503 from the No. 4 is input to the display control circuit 505, and an image corresponding to the input image data is displayed on the panel 506.
Display at the vertical position specified by the above line address data.

Reference numeral 17 is an audio processing block, which is composed of a delay adjusting circuit 171, a sound quality adjusting and amplifying circuit 172, and a speaker 173.

Reference numeral 171 denotes a delay adjustment circuit, which adjusts the time lag between the image display on the display unit 15 and the sound output from the speaker 173.

In the display section 15, a slight delay occurs in image display in the upper left and right corners of the display screen depending on the operating temperature of the main body. For this reason, when it is necessary to synchronize the moving image with the sound like a TV signal, a temporal mismatch occurs between the image affected by the temperature and the sound not affected by the temperature.

To solve this phenomenon, the temperature information of the display unit 15 is fed back to the system control circuit 191 through the system control bus cs119, and the delay time of the delay adjustment circuit 171 is adjusted by the control signal cs120 based on the information. The audio input signal 115 or s115a is delayed so that the image and the audio are synchronized with each other by control to generate the delayed audio signal s116. That is, when there is no image display delay, no audio delay is generated, and when there is image display delay, an audio delay is generated.

However, the audio delay time to be generated is derived from the correlation table of the temperature of the display section 15 and the image display delay time which is stored in the memory 194 in advance. By performing this delay adjustment, the image and the sound can be synchronized independently of the temperature of the display unit 15.

Reference numeral 172 is a voice adjustment / amplification circuit, to which the delay-adjusted voice signal s116 is input. The sound quality adjustment circuit has functions such as voice adjustment, stereo / mono switching, left and right speaker balance adjustment, tone control, surround processing, and the like, and is adjusted by the control from the system control circuit 191 to the user's favorite sound quality. Then, it is amplified so that the speaker 173 can be driven.

Reference numeral 18 denotes a power supply unit, which is a power supply output cs1.
Reference numeral 81 supplies power to the TV signal processing unit 12, cs182 supplies power to the computer signal processing unit 11, cs183 supplies power to the digital processing unit 14, and cs184 supplies power to other units.

The power supply section 18 is controlled by the system control circuit 191 through the control signal cs121, and the T
V signal processing unit 12 and computer signal processing unit 1
1, the power of the digital processing unit 14 is controlled to be turned on and off.

Subsequently, necessary information is displayed on the screen of the display unit 15 to facilitate various adjustment processing by the operator.
The display operation of SD (on-screen display) will be described with reference to FIGS. 34 to 37.

The system control circuit 191 operates in accordance with the OSD display request from the key input processing by the operator.
For the control circuit 193, the OSD display start position (horizontal,
(Vertical), display pattern, font size, display color, blinking presence / absence, space between fonts, etc. to transfer an OSD like the display examples shown in FIGS. 34 to 37.
Display.

34 and 35 are examples of the OSD display of the menu screen in the adjustment item selection processing. 34 and 35 show a case where the language selection is selected as the setting item as an example. FIG. 34 shows a display example in the case where the background of the characters is not a watermark, and the item means of the selected language (LANGUAGE) has a different color from the background of other items or blinks. Is distinguished from other items by. Further, FIG. 35 shows a display example in which the background of characters is a watermark. In this case, only the background of the selected item is colored instead of the watermark.

FIG. 36 shows an example of the OSD display when the language selection (LANGUAGE) is selected by the adjustment item selection processing on the menu screens shown in FIGS. 34 and 35. In this case, since it is a two-person selection type, every time the UP or DOWM key is pressed, English (ENGL
ISH) and Japanese (JAPANESE) are selected alternately.

FIG. 37 shows an example of OSD display when brightness adjustment is selected in the menu selection. In this case, the adjustment value is changed stepwise by the UP and DOWM keys, and the setting value is, for example, 255 steps, and when the OSD display level is 10 steps, the OSD display is displayed every time the set value is increased or decreased by about 25. Increases or decreases the level of.

Next, the font size displayed in the OSD will be described with reference to FIG. When the composite video signal s106 such as NTSC / PAL and the YC separated video signal s108 are displayed, the OSD display data s1 is displayed.
In the conversion circuit 124 for converting data in field units into data in frame units, the data 18 is vertically enlarged to double its size. Further, the size is doubled in the horizontal direction by the interpolation circuit 125. And finally the display unit 15
The same data is displayed in 2 lines in the vertical direction, which means that the size is further increased to 2 times in the vertical direction, and the total size is 2 times in the horizontal direction and 4 times in the vertical direction. Be expanded to. Therefore, the font size used for the OSD display is double the size in the horizontal direction and is the size in the vertical direction.
On the screen No. 5, it is possible to display a quadruple size font in both the horizontal and vertical directions.

On the other hand, when the computer input signal s101 is displayed, the OSD display data s118 is switched to the computer input signal s101 by the switch means 106, and when the computer input signal s101 is output.
The same data is read four times in order to read at the same clock speed. Therefore, the size is enlarged four times in the horizontal direction. Therefore, as the font size used for the OSD display, a font having a size of 1 times in the horizontal direction and a size of 4 times in the vertical direction is used, so that the horizontal direction and the vertical direction on the display unit 15 have the same quadruple size as the above case. The font can be displayed.

Further, FIG. 39 shows a list of items displayed by OSD when displaying a video signal and a computer signal. In this embodiment, OSD display of different contents is performed as shown in FIG. 39 at each display.

Therefore, in the present embodiment, different font sizes, different read clock speeds, and different video signal display and computer signal display
OSD display of different display contents is performed.

The OSD control circuit 193 switches the OSD data s118 to the image data s1 by switching the switch 123 in the case of a video input signal such as NTSC and the switch 106 in the case of a computer input signal.
10 and s104 are switched and output.

The switch 132 is switched by the system control circuit 191 based on the operator's selection by the key input processing, and the video input signal s113 of NTSC or the like,
The computer input signal s105 is switched and transferred to the digital signal processing unit 14.

Now, the key input process from the operator will be described in detail with reference to the flow of FIG. 40 and FIG. 41 showing an example of keys for receiving the key input from the user.

In FIG. 40, the system control circuit 191 performs a key scan on the key matrix circuit 192 in step s1102. In step s1102, it is determined whether there is a key input as a result of the key scan,
If there is no key input, the key input processing is immediately terminated. Otherwise, if there is a key input, the process proceeds to step s1103. In step s1103, it is determined whether the detected key input is the TV / PC switching key in FIG. 40, and if it is the TV / PC switching key, the TV / PC mode switching processing in step s1104 is performed. . The TV / PC switching processing includes: 1, switching control of the switch 13, setting of TV / PC switching information in the interpolation processing unit 105, and OSD display of TV / PC switching information. After the TV / PC switching process ends, the key input process ends. In step s1105, it is determined whether the detected key input is the volume UP key in FIG. 40. If it is the volume UP key, step s110
6 volume UP processing is performed. The volume UP processing includes: 1, volume UP setting 2 to the audio processing circuit 172, and OSD display of the updated volume. After the volume UP process ends, the key input process ends. In step s1107, it is determined whether or not the detected key input is the volume DOWN key in FIG. 41. If it is the volume DOWN key, step s11
08 volume down processing is performed. The sound volume DOWN processing consists of 1, sound volume DOWN setting 2 to the sound processing circuit 172, and OSD display of the updated sound volume. After the volume down process is completed, the key input process is completed. In step s1109, it is determined whether or not the clear key and the set key shown in FIG. 41 have been simultaneously pressed continuously for a certain period or longer, and if so, it is determined that the reset key has been detected, and the reset processing of step s1110 is performed. . This reset processing is as follows: 1. Read the factory default settings from the memory 194, set them to the decoder 122 2, read the factory default settings from the memory 194, set them to the audio processing circuit 172 3, and read from the memory 194. The factory default settings are read and set in the clock generation circuit 104. The factory default settings are read from the memory 194 and set in the interpolation processing circuit 105. After the reset process ends, the key input process ends. In step s1111, it is determined whether or not the detected key input is the menu key, and if it is the menu key, the process proceeds to step s1112. Otherwise, if any key other than the above, that is, any of the set key, the UP key, the DOWN key, and the clear key is detected, the key input process is immediately terminated without doing anything. At step s1112, the current TV mode or P
It is determined whether the mode is the C mode, the process proceeds to step s1113 when in the TV mode, and the step s11 when in the PC mode.
Proceed to 28.

In step s1113, the operator performs a process of selecting a setting item while looking at the menu screen. The process of step s1113 or step s1128 will be described below with reference to the flow of FIG.

In FIG. 42, in step s1501, the OSD display is performed with the previously selected item selected. In step s1502, wait is performed until there is a key input process from the operator. In step s1503, the key input by the operator is the TV / PC switching key,
It is determined whether the volume is the UP key or the DOWN key, and if so, the process returns to step s1502 without doing anything. In step s1504, it is determined whether the key input by the operator is the menu key, and if so, the process ends. If not, the process proceeds to step s1505.

At step s1505, if it is determined whether or not the key input by the operator is the set key, the setting item is decided, and the process proceeds to step s1114 or s1129. In step s1506, it is determined whether the key input by the operator is the clear key, and if so, the selected item is initialized in step s1507, and the process returns to step s1501. If not, it proceeds to step s1508. Step s15
At 08, it is determined whether or not the operator has pressed the clear key and the set key at the same time for a certain period of time.
Reset processing is performed and the processing ends. If not, it proceeds to step s1510.

In step s1510, it is determined whether or not there is a key input by the operator. If so, the selection item is set to the previous item in step s1511, and the process returns to step s1501. If not, it proceeds to step s1512. In step s1512, it is determined whether the key input by the operator is the DOWN key. If so, step s1513.
In step s1501 after the selection item is changed to the next item
Return to Otherwise, if all of the above keys are not present, nothing is done and the process returns to step s1501.

Therefore, the menu key is input in step s1504, or step s1508
The key input process ends only when the reset request is issued in step s1505, and the process of step s1113 or step s1128 in FIG. 40 ends only when the key input by the operator in step s1505 is the set key.

After the menu selection processing is completed, step s11
In step 14, it is determined whether or not the adjustment item selected in step s1113 is language selection. If it is the language selection, the language selection processing of step s1115 is performed. In step s1116, it is determined whether or not the selected process is the input selection. If it is the input selection, the input selection (composite signal input / YC separated signal input) process of step s1117 is performed.

In step s1118, it is determined whether the selected process is sound quality selection. If it is sound quality selection, the sound quality selection process of step s1119 is performed. In step s1120, it is determined whether or not the selected process is contrast adjustment. If it is contrast adjustment, the contrast adjustment process of step s1121 is performed. In step s1122, it is determined whether the selected process is brightness adjustment,
If it is brightness adjustment, step s1123.
Brightness adjustment processing.

In step s1124, it is determined whether or not the selected processing is saturation adjustment, and if it is saturation adjustment, the saturation adjustment processing in step s1125 is performed. In step s1126, it is determined whether or not the selected processing is hue adjustment, and if it is hue adjustment, the hue adjustment processing of step s1127 is performed.
Otherwise, if a process other than the above is selected, the process ends immediately.

Now, step s1115 language selection processing will be described with reference to FIG.

In FIG. 43, in step s1601, the language selection screen is displayed in OSD, and in step s1602.
Then wait until there is a key input from the operator. At step s1603, the key input from the operator is TV / P.
C switch key or volume UP key or volume DO
It is determined whether the key is the WN key, and if so, the process returns to step s1602. If not, it proceeds to step s1604. Step s160
At 4, it is determined whether the key input from the operator is the menu key or the set key, and if so, the process returns to the menu selection processing s1113. If not, the process proceeds to step s1606.

In step s1606, it is determined whether or not the key input from the operator is the clear key, and if so, the set value in step s1607 is set to the value set when the processing was started. Then, the process returns to step s1601. If not, step s
Proceed to 1608. In step s1608, it is determined whether the operator has pressed the clear key and the set key at the same time for a certain period of time or more. If so, it is determined that a reset request has been made, and the reset process of step s1609 is performed to perform the language adjustment. The process and the key input process are ended. If not, the process proceeds to step s1610.

In step s1610, it is determined whether the key input from the operator is the UP key. If yes, in step s1611 the set value is set to the previous item or the set location is set. UP. If not, it proceeds to step s1612. In step s1612, it is determined whether the key input from the operator is the DOWN key. If yes, in step s1613, the setting value is changed to the next item or the setting value is DOWN. . Otherwise, if the key input from the operator is not any of the above keys, nothing is done and the process returns to step s1601. Steps
The same processing is performed for the input type selection processing of 1117, the sound quality selection processing of step s1119, the contrast adjustment processing of step s1121, the brightness adjustment processing of step s1123, the saturation adjustment processing of step s1125, and the hue adjustment processing of step s1127. .

In step s1128, step s11
In the same manner as in 13, the process of selecting the setting item is selected through the menu screen in the PC mode. In step s1129, it is determined whether or not the selected process is language selection, and if it is language selection, the language selection process of step s1130 is performed. If not, the process proceeds to step s1131. In step s1131, it is determined whether or not the selected process is sound quality selection. If it is sound quality selection, the sound quality selection process of step s1132 is performed. If not, it proceeds to step s1133.

In step s1133, it is determined whether or not the selected process is γ selection. If it is γ selection, the γ selection process of step s1134 is performed.
If not, it proceeds to step s1135. In step s1135, it is determined whether the selected process is gradation selection. If it is gradation selection, the gradation selection process of step s1136 is executed. If not, it proceeds to step s1137. In step s1137, it is determined whether or not the selected process is phase adjustment, and if it is phase adjustment, the phase selection process of step s1138 is performed. If not, it proceeds to step s1139.

In step s1139, it is determined whether or not the selected process is position adjustment, and if it is position adjustment, the display position adjusting process in step s1140 is performed. If not, step s1141
Proceed to. Determines in step s1141 whether the selected process is DPMS adjustment, and if DPMS adjustment
If it is adjustment, DPMS in step s1142
Perform adjustment processing. If not, step s1
Proceed to 143. In step s1143, it is determined whether the selected process is model setting, and if it is model setting, the model setting process of step s1144 is performed. Otherwise, if a process other than the above is selected, the key input process is immediately terminated. The system control circuit 191 performs the above determination processing, OSD display control, various adjustment selection processing control, and the like.

Thus, in this embodiment, the display panel 15
In order to convert to a resolution that matches the display resolution of, when performing pixel interpolation, the coefficient of the interpolation calculation is approximated by the power of 2 and
Interpolation calculation is performed by adding and subtracting these n-th power coefficients.

Therefore, as in this embodiment, the video signal is set to 1
When the interpolation calculation is performed after conversion into a digital signal of a plurality of bits of pixels, this calculation can be performed only by bit shift and addition / subtraction.

Therefore, the circuit scale can be reduced as compared with the case of multiplying a plurality of bits of data, and the operation can be performed at high speed even when it is realized by software.

[0238]

As described above, according to the present invention, the input image data is multiplied by the coefficient represented by 2 n,
Since interpolation data is obtained by applying and addition,
For example, when digital processing is performed, interpolation data can be obtained by bit shift processing and addition operation thereof, and the circuit size can be reduced while maintaining good image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device as an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a synchronization measuring unit in FIG.

FIG. 3 is a diagram showing storage contents of the FIFO shown in FIG.

FIG. 4 is a diagram showing stored contents of a register shown in FIG.

5 is a diagram showing a configuration of an A / D conversion unit in FIG.

6 is a diagram showing a configuration of a clock generation unit in FIG.

FIG. 7 is a diagram showing a configuration of the frequency divider of FIG.

FIG. 8 is a diagram for explaining the operation of the level conversion circuit of FIG.

FIG. 9 is a diagram showing an example of a video signal handled in the embodiment of the present invention.

FIG. 10 is a diagram showing an example of a video signal handled in an embodiment of the present invention.

FIG. 11 is a diagram showing an example of a video signal handled in the embodiment of the present invention.

FIG. 12 is a diagram showing an example of a video signal handled in an embodiment of the present invention.

FIG. 13 is a diagram showing an example of a video signal handled in the embodiment of the present invention.

FIG. 14 is a diagram for explaining control of a display operation according to a change of a sync signal in the example of the present invention.

15 is a flow chart for explaining the operation of the synchronization signal change detection module in FIG.

16 is a flowchart for explaining the operation of the display mode determination / control module in FIG.

FIG. 17 is a flowchart for explaining display mode confirmation processing in the embodiment of the present invention.

FIG. 18 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1.

FIG. 19 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1.

20 is a diagram for explaining the operation of the interpolation processing unit in FIG.

FIG. 21 is a diagram showing a configuration of an interpolation processing unit in FIG. 1.

22 is a diagram showing a configuration of a main part of FIG.

FIG. 23 is a diagram showing a configuration of a main part of FIG. 22.

FIG. 24 is a diagram showing the configuration of the exponential arithmetic circuit of FIG. 23.

FIG. 25 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1.

FIG. 26 is a diagram for explaining the operation of the interpolation processing unit in FIG.

27 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1. FIG.

28 is a diagram for explaining the operation of the interpolation processing unit in FIG.

FIG. 29 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1.

FIG. 30 is a diagram for explaining the operation of the interpolation processing unit in FIG. 1.

FIG. 31 is a diagram showing a configuration of a digital signal processing unit and a display unit of FIG. 1.

32 is a diagram showing a configuration of a γ / gradation correction circuit of FIG. 30.

33 is a diagram showing the configuration of the halftone processing circuit of FIG. 30. FIG.

FIG. 34 is a diagram showing a display example of the OSD in the embodiment of the present invention.

FIG. 35 is a diagram showing a display example of the OSD in the embodiment of the present invention.

FIG. 36 is a diagram showing a display example of the OSD in the embodiment of the present invention.

FIG. 37 is a diagram showing a display example of the OSD in the embodiment of the present invention.

FIG. 38 is a diagram for explaining an image display operation in the embodiment of the present invention.

FIG. 39 is a diagram showing OSD display items in the embodiment of the present invention.

FIG. 40 is a flow chart for explaining the OSD display operation in the embodiment of the present invention.

41 is a diagram showing a key input unit in FIG. 1. FIG.

FIG. 42 is a flow chart for explaining the OSD display operation in the embodiment of the present invention.

FIG. 43 is a flow chart for explaining the OSD display operation in the embodiment of the present invention.

[Explanation of symbols]

 11 processing unit 12 TV signal processing unit 14 digital signal processing unit 15 display unit 101 synchronization separation unit 102 synchronization measurement unit 104 clock generation unit 105 interpolation processing unit 191 system control circuit 194 memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/36 520 G06F 15/66 355C

Claims (12)

[Claims] 1. Interpolated image data by multiplying and adding an input unit for inputting image data and a coefficient represented by the n-th power of 2 (n is an integer) to the image data from the input unit. And a display unit for displaying an image related to the output image data of the interpolation unit. 2. The input means inputs a plurality of types of image data having mutually different numbers of pixels in the horizontal direction, and the interpolation means determines the coefficient in accordance with the type of image data from the input means. The display device according to claim 1, wherein: 3. The interpolation means further determines the coefficient based on the number of horizontal pixels that can be displayed by the display means and the number of pixels of image data from the input means. The display device according to 2. 4. The input means includes a receiving means for receiving analog image data, and a converting means for sampling the analog image data according to a clock to obtain digital image data of one sample multi-bit. The display device according to claim 1. 5. The display device according to claim 5, wherein the interpolation means determines the coefficient according to the number of bits per sample of the digital image data. 6. The interpolation means obtains the interpolation data by multiplying a plurality of image data from the input means by the different coefficients and then adding the plurality of multiplication results. The display device according to claim 1. 7. An image comprising input means for inputting digital image data, bit shift means for performing bit shift processing on the digital image data, and addition means for adding digital image data from the bit shift means. Processing equipment. 8. The input means inputs a plurality of types of digital image data having different horizontal sample numbers, and the bit shift means performs the bit shift according to the type of digital image data from the input means. The image processing device according to claim 7, wherein the amount is determined. 9. A display means for displaying an image related to the digital image data from said adding means, wherein said bit shift means further comprises the number of horizontal samples which can be displayed by said display means and the digital data from said input means. The image processing apparatus according to claim 7, wherein the bit shift amount is determined based on the number of samples of image data. 10. The image processing apparatus according to claim 7, wherein the addition means adds a plurality of image data to which different bit shift amounts are given by the bit shift means. 11. A step of inputting image data, and an interpolation step of performing interpolation and multiplication with the n-th power of 2 (n is an integer) on the input image data to obtain interpolated image data. A step of displaying an image related to the image data obtained by the interpolation step. 12. An image processing method comprising inputting digital image data, performing bit shift processing on the digital image data, and adding the digital image data subjected to the bit shift processing.