JPH09199625A - Semiconductor device and substrate for mounting semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package for effectively preventing crack and warpage and a substrate for mounting IC chips used for it. SOLUTION: A specific part of a glass epoxy substrate 21 for mounting IC chips is penetrated from one surface side to the other surface side and is eliminated for forming an eliminated part 20, one portion of a reverse side which is opposite to a circuit formation surface of an IC chip 3 is fixed to a substrate 21 while the IC chip 3 is located in the region of the eliminated part 20, at the same time one portion 20a of the eliminated part 26 exists around the IC chip 3 in the fixed state, and mold resin 7 is deposited also to the reverse side of the IC chip 3 via the part, thus forming the mold resins 7 and 7a on the front and reverse sides of the IC chip 3 in one piece.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor element mounting substrate, for example, a plastic BGA (B
The present invention relates to a semiconductor package having a connection electrode structure called “all grid array” and a double-sided wiring board for mounting a semiconductor element used in this package.

[0002]

2. Description of the Related Art Conventionally, a semiconductor package 10 having a plastic BGA has a structure shown in FIG. 39, for example. That is, a substrate 1 constituting a double-sided or multilayer printed wiring board (a substrate generally made of paper, glass fiber or the like and impregnated with epoxy, polyimide, BT (bismaleimide triazine) resin or the like, or a substrate of the resin alone. : A semiconductor integrated circuit chip (IC chip) 3 is mounted on the chip mounting portion with a silver paste 2 which is a conductive adhesive, for example, and the bonding pad 4 of the IC chip 3 and the substrate 1 are mounted on the chip mounting portion.
The copper wiring 5 plated with gold or the like is wire-bonded with a gold wire 6, the IC chip 3 side of the substrate 1 is molded with an epoxy resin 7, and the solder ball 8 is connected to the copper wiring 9 on the opposite side. It is provided by connecting.

Specifically, this package 10 has an external shape as shown in FIG. 40, and the substrate 1 shown in FIG.
(However, the wirings 5 and 9 are not shown.) A large number of mount regions 17 are provided in a row on the IC chip 3, and each mount region is mounted with the IC chip 3 as indicated by a chain double-dashed line. 7 and then cut at the positions of the four slots 11 to separate the packages.

The structure of this package 10 will be described in more detail with reference to FIG. 42. The IC chip 3 is adhered to the substrate 1 by the silver paste 2 in the mount area 17, and the pad 4 on the chip 3 is the gold wire 6 on the substrate 1. Connected to wiring 5,
The wiring is led to the wiring 9 under the substrate 1 and further to the solder balls 8 through the through holes 12 (13 in the figure is a solder resist).

However, such a conventional plastic B
GA package 10 is the back surface of chip 3 (mounting surface)
Is widely adhered to the substrate 1 by the silver paste 2, so when the solder ball 8 is used to solder this package to the copper wiring 15 on the printed wiring board (motherboard) 14 shown by phantom lines, The popcorn-shaped crack 16 from the starting point easily occurs. Regarding this, Nikkei Electronics (1994.2.2.
It is also mentioned in P71 of 14).

The cause of the cracks 16 is that the silver paste 2 has a high hygroscopic property, and the moisture absorbed in the silver paste 2 becomes steam during reflow heating during soldering onto the printed wiring board 14 and becomes moisture inside the package. Substrate 1 that expands rapidly
This is because the IC chip 3 is peeled off from the mold resin 7 and the stress. This peeling starts from the adhesion region 17 of the IC chip 3, and tends to become a crack 16 in the substrate 1 and extend toward the end thereof.

In addition to the occurrence of such cracks 16, FIG.
As shown in Table 1, the difference in the coefficient of thermal expansion between the mold resin 7 (for example, epoxy resin) and the constituent material of the substrate 1 (for example, BT resin: bismaleimide triazine) is considerably large as shown in Table 1 below. Therefore, when the temperature changes from the resin mold temperature (the mold temperature is, for example, 180 ° C.) to room temperature, a dent may occur in the central portion of the package 10 and the package 10 may warp. Then, due to the stress strain due to this warpage, cracks occur at the interface between the two.

[0008]

In the semiconductor package 10 described above, the wiring 5 on both sides of the substrate 1 is actually used as shown in FIG.
9 and 9 may be formed as an integral continuous film by copper plating (through hole plating) via the through holes 12, and the through holes 12 may be filled with a solder resist 13 to cover both surfaces of the substrate 1.

In the mount area 17 where the IC chip 3 is bonded with the silver paste 2, a through hole 18 called a thermal via is formed in the substrate 1, and the heat generated in the IC chip 3 causes the silver paste 2 and the thermal via 18 to be generated. It passes through to the solder balls 8 and escapes to the board 14 on which the package 10 is mounted. The thermal via
18 is filled with the solder resist 13, and the upper part thereof is covered with the silver paste 2.

However, in the substrate structure shown in FIG. 44, the solder resist 13 filling the thermal vias 18 is a material which easily absorbs moisture, and this causes the moisture resistance to deteriorate. That is, the moisture absorbed by the solder resist 13 is leached into a portion such as the silver paste 2 or is vaporized at the time of heating as described above and rapidly expands, and package cracks are generated or promoted similarly to the above.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of effectively preventing a package from being cracked or warped, and a semiconductor element mounting substrate used for the same.

[0013]

That is, the present invention provides a semiconductor element mounting substrate (for example, a glass epoxy substrate described later).
A predetermined portion of 21) penetrates from one surface side to the other surface side and is cut away to form a cutout portion (for example, a cutout portion 20 described later).
And a semiconductor element (for example, an IC chip 3 described later) is positioned in the region of the cutout portion, a part of the back surface of the semiconductor element opposite to the circuit forming surface is part of the mounting substrate. In addition, a part of the cutout portion is present around the semiconductor element in this fixed state, and a molding material (for example, a molding resin 7 which will be described later) is also provided on the back surface of the semiconductor element via this portion. ) Is applied to the semiconductor device, and the molding material on the front surface and the back surface of the semiconductor element are integrated with each other.

According to this semiconductor device (semiconductor device of the first invention), the semiconductor element is fixed to the mounting base in a state where the semiconductor element is located in the region of the notch formed in the mounting base. Backside of semiconductor element (mounting side)
Only a part of the above will be fixed with a mount material such as silver paste, and even if the mount material is hygroscopic, the amount of water vapor generated during heating is reduced. Moreover, in this case, the molding material directly enters the cutout portion of the mounting base (that is, below the back surface of the semiconductor element), and a part of the cutout portion existing around the semiconductor element is used to form the semiconductor element. By applying the molding material on the back side,
Since the molding materials on the front surface and the back surface of the semiconductor element are integrated with each other, the adhesion between the semiconductor element and the molding material becomes good.

As a result, due to the moisture absorbed by the mounting material, the stress for peeling off the semiconductor element from the mounting substrate or the molding material during heating becomes small and the stress is absorbed sufficiently. Popcorn-like package cracks as described above are less likely to occur.

Further, the area of the mounting substrate existing on the back surface of the semiconductor element is reduced by the above-mentioned cutout portion, and even if there is a difference in the coefficient of thermal expansion between the molding material and the mounting substrate, both occur during the temperature cycle. The stress between them is reduced, and the warpage of the package as described above is reduced. The peeling between the two due to this warp is reduced, and package cracks are less likely to occur.

In the semiconductor device according to the first aspect of the present invention, as a preferable mount structure, a protruding piece portion (for example, a protruding piece portion 30 described later) protruding into the notch of the mounting base body is provided integrally with the mounting base body. A part of the back surface of the semiconductor element is fixed to the protruding piece.

Also, in order to prevent the molding material from leaking inward from the end boundary between the mounting base and the mold during the molding of the semiconductor element, the mounting material is mounted in the mount base at the notch. It is preferable that the opening area on the side of the substrate for fixing the back surface of the semiconductor element is larger than the opening area on the opposite side.

The present invention, like the semiconductor device of the first invention described above, improves the moisture resistance of the package and effectively prevents the occurrence of cracks. A through hole (for example, a thermal via 38 described later) penetrating from one surface side to the other surface side is formed in a mounting base body (for example, a glass epoxy substrate 21 described later) for fixing the above, and through the through hole, The heat generated by the semiconductor element is radiated from the one surface side to the other surface side, and the through hole has a moisture penetration preventing material (for example, a copper plating layer, a solder ball 8 or a solder 8 described later).
There is also provided a semiconductor device covered or filled by a).

According to this semiconductor device (semiconductor device of the second invention), the through hole provided in the mounting base (in particular, the heat of the semiconductor element is radiated from one surface side of the mounting base to the other surface side). Since the through hole) is covered or filled with a moisture invasion preventive material, even if a hygroscopic material such as a solder resist is present in the through hole, invasion (release) of water from the through hole is prevented, or Since the hygroscopic material is removed from the inside of the through hole, moisture does not enter from the through hole during heating, so that no water vapor is generated and a semiconductor device having sufficient moisture resistance without package cracks is obtained.

In this case, the moisture infiltration preventing material which covers or fills the through-hole is at least a part of the mounting base (for example, copper plating layers 65 and 69 described later), solder balls (for example, 8 described later) or solder (for example, 8). For example, 8
a), of which the solder (for example, 8a described below) filled in the through holes is supplied from a solder ball (for example, 8 described below) attached to the other surface side of the mounting base. Is good.

Further, the semiconductor device of the second invention or the semiconductor device based on the same is provided with the mounting base and the mold structure or the protruding piece portion used for the semiconductor device of the first invention or the semiconductor device based on the semiconductor device. It is desirable to have.

In any of the above-described semiconductor devices of the first and second inventions or the semiconductor devices based on these inventions, in practice, the conductivity is provided on both surfaces of the mounting base through the through holes formed in the mounting base. Layers (for example, copper wirings 5 and 9 described later) are connected to each other, and a semiconductor element fixed to one surface side of the mounting substrate is connected to a conductive layer (for example copper wiring 5 described below) on the one surface side. At the same time, the conductive layer (for example, the copper wiring 9 described later) on the other surface side of the mounting base is connected to the printed wiring board (for example, the printed wiring board 14 described later).

The present invention also provides a semiconductor device according to the first invention,
The present invention also provides the above-mentioned semiconductor element mounting substrate used in either the semiconductor device of the second invention or the semiconductor device based on these inventions.

[0025]

Embodiments of the present invention will be described below.

1 to 16 show an embodiment in which the present invention is applied to a padless plastic BGA. However, parts common to those in the examples shown in FIGS. 39 to 44 are denoted by common reference numerals, and description thereof may be omitted (the same applies hereinafter).

The semiconductor package 40 of this embodiment mainly has the following characteristic configurations (1) to (3).

(1) In the glass epoxy substrate 21 on which the IC chip 3 is mounted, the region immediately below the IC chip 3 is
The area larger than the IC chip 3 and including the IC chip 3 is cut into a substantially square shape, and projecting piece portions 30 each having a tongue shape are formed integrally with the substrate 21 diagonally from the four corners of the cut portion 20. The IC chip 3 is formed on these four projecting piece portions 30 and fixed (mounted) by the silver paste 22 on the back surface opposite to the circuit forming surface (see FIGS. 1 to 7). That is, this package 40 should be called, so to speak, a padless BGA.

(2) In this mounted state, I
The C-tip 3 is located in the region of the cutout portion 20, and a part 20a of the cutout portion 20 exists as a slit-shaped gap around the cutout portion 20 (see FIGS. 4 and 5). Through the recessed portion 20 (therefore, the back surface of the IC chip 3) at the time of mold pressing and is adhered as the mold resin 7a.
It is integrated via a, and the periphery of the IC chip 3 is almost entirely covered with the molding resin 7 (see FIGS. 1 and 2).

(3) Reference numeral 33 in FIGS. 1 and 2 denotes a solder resist, which is also filled in the through holes 38 and the thermal vias 48, and the solder balls 8 are attached to the back surfaces of these through holes. doing. Note that FIG.
Shows a state in which the substrate 21 on which the IC chip 3 is mounted is connected to the copper wiring 15 of the printed wiring board 14 by reflowing the solder balls 8.

The semiconductor package 40 of this embodiment can mainly exert the following remarkable effects (A) to (D) due to the above-mentioned characteristic structure.

(A) Popcorn-like package cracks can be prevented from occurring. Immediately below the IC chip 3 is filled with a mold compound (mold resin) 7a, and the IC chip 3 is fixed (dotted) to the substrate 21 with silver paste 22 in only four corners in a dot shape or a dot shape, and Since the adhesion between the silicon chip 3 and the mold compound 7 is good, popcorn-like cracks are less likely to occur as compared with the BGA package having the conventional structure, and the shape retention of the package is good even during temperature cycling. In other words, the silver paste 22 absorbs moisture and suppresses or reduces the generation of water vapor, which is generated from there as a starting point and cannot be avoided by the conventional structure, and also sufficiently absorbs the stress that tends to separate the chip 3 and the mold compound 7. In order to
Cracks are less likely to occur.

(B) The amount of warpage of the package is reduced. As described above, in the plastic BGA package having the conventional structure, the central portion of the package may be dented at room temperature due to the difference in thermal expansion coefficient between the mold compound and the substrate material (BT resin). The cutout 20 reduces the amount of the substrate 21 (that is, there is almost no substrate under the chip 3 in the central portion of the package), so that the warpage of the package is reduced as compared with the conventional structure.

(C) It becomes difficult for package cracks to occur during temperature cycling. During the temperature cycle, as described above, the mold compound 7 and the substrate 21 exhibit different thermal expansion coefficients, and due to the difference between them, they are easily separated from each other, and cracks are likely to occur from them, but in this embodiment, the substrate 21 Since the amount is greatly reduced by the aforesaid eliminator 20, warpage is reduced and this crack is less likely to occur.

(D) Through hole 38 and thermal via
Since the solder ball 8 is provided immediately below 48, it is not necessary to separately provide a region for attaching the solder ball as compared with the conventional example of FIG. 44, and the area of the substrate 21 is reduced by that much.
This is advantageous for downsizing and effective use of the substrate.

Further, in the semiconductor package 40 of this embodiment, the thickness t ₁ of the mold resin 7 on the substrate 21 shown in FIG.
May be, for example, 1.3 mm, and the thickness t _{2 of the} substrate 21 may be, for example, 0.6 mm. If the thickness t _{2 of the} substrate 21 is increased, the thickness of the molding resin 7a existing on the back surface of the IC chip 3 also increases, so that the difference in the thickness of the molding resin existing on the front surface and under the back surface of the IC chip 3 becomes larger. It becomes smaller, and the occurrence of cracks during thermal cycling can be prevented more effectively.

Regarding the problem of the warp of the package described above, the conventional structure (standard B) shown in FIGS.
GA) and the structure of the present embodiment (padless BGA) shown in FIGS. 1 to 7 were compared, and the respective warpage amounts were obtained as follows.

Here, the following three kinds of members C, B and A having different thermal expansion coefficients were superposed in order from the bottom and adhered to correspond to the structure of the package.

The physical property value and size of each member are represented by the following parameters. Linear expansion coefficient of member A: α _A , elastic coefficient: E _A Linear expansion coefficient of member B: α _B , elastic coefficient: E _B Linear expansion coefficient of member C: α _C , elastic coefficient: E _C Cross sectional area of member A : A _A , cross section of member B: A _B , member C
Cross section area: A _C , length of member A: l _A , length of member B:
l _B , length of member C: l _C.

It is generally known that the warpage amount σ of the entire laminate when the temperature changes by t ° C. is approximated by the following equation (a).

This formula (a) is added to the padless B of this embodiment.
GA and standard BGA (with pad) of the conventional example
Substitute the following values for and. In this case, three-dimensional numerical values should actually be substituted, but simplified two-dimensional numerical values are substituted and the ratio of the difference between the warp amounts is checked as shown below.

Standard BGA (conventional example) Padless BGA (present example) l _A : 28.5 mm 28.5 mm l _B : 11.8 mm 11.8 mm l _C : 31.0 mm 16.5 mm A _A : 28.5 mm ² 28.5 mm ² A _B : _{^{3.3mm 2 3.3mm 2 A C: 19.22mm}} 2 10.23mm 2 E A: 2700kgf / mm 2 2700kgf / mm 2 E B: 21000kgf / mm 2 21000kgf / mm 2 E C: 710kgf / mm 2 710kgf / mm 2 α A : 1.5 × 10 ^-5 / ° C 1.5 × 10 ^-5 / ° C α _B : 3.0 × 10 ^-6 / ° C 3.0 × 10 ^-6 / ° C α _C : 2.0 × 10 ^-5 / ° C 2.0 × 10 ^-5 / ° C t : ｜ 25 ℃ -175 ℃ ｜ = 150 ℃ 150 ℃

In the case of standard BGA (conventional example), the warpage amount σ _ST (mm) of the entire member is σ _ST = (150 × 28.5 × 11.8 × 31.0 (28.5 × 2700 × 1.5 × 10 ⁻⁵ + 3.3 × 21000 × 3.0 × 10 ^-6 +19.22 × 710 × 2.0 × 10 ^-5 )) / (11.8 × 31.0 × 28.5 × 2700 + 31.0 × 28.5 × 3.3 × 21000 + 28.5 × 11.8 × 19.22 × 710) = 0.027 (b )

In the case of padless BGA (this embodiment), the warpage amount σ _{PL of the} entire member is σ _PL = (150 × 28.5 × 11.8 × 16.5 (28.5 × 2700 × 1.5 × 10 ⁻⁵ + 3.3 × 21000 × 3.0) × 10 ^-6 ＋10.23 × 710 × 2.0 × 10 ^-5 )) / (11.8 × 16.5 × 28.5 × 2700 +16.5 × 28.5 × 3.3 × 21000 ＋28.5 × 11.8 × 10.23 × 710) = 0.025… (c)

Therefore, the ratio of the difference in the warp amount is {(b)-(c)} / (c) = 8 (%), and when the standard BGA is a padless BGA, the warp amount of the package is 8%. Is expected to decrease.

Next, the manufacturing process of the padless BGA package 40 of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 8, a substrate 21 using BT resin is prepared, and as shown in FIG. 9, a through hole 38 and a thermal via 48 are formed by drilling with a drill or the like.

Then, as shown in FIG.
Conductive layer 50 is plated over the entire surface including 38 and thermal via 48. This plating layer can be formed by chemical plating or electroplating of copper.

Then, as shown in FIG.
50 is patterned by etching by photolithography to form copper wirings 5 and 9 on the front and back of the substrate 21, respectively, and these are connected to each other through the through hole 38 or the thermal via 48.

Then, as shown in FIG.
A solder resist 33 is applied to a predetermined area including the 38 and the thermal via 48 by screen printing, the through hole 38 and the thermal via 48 are filled with the solder resist 33, and a part of the copper wirings 5 and 9 is connected by wire bonding or the like. Areas other than that are covered with the solder resist 33.

Next, as shown in FIG. 13, the substrate 21 in the mounting area 47 of the IC chip is cut and removed as shown by the broken line to form the tongue piece portion 30 together with the cutout portion 20.

Next, as shown in FIG. 14, the mount area
The IC chip 3 is adhered onto the 47 with the silver paste 22 and fixed (mounted).

Then, as shown in FIG. 15, the substrate 21 is placed on a heater block (not shown), and while heating the substrate 21 to a predetermined temperature, ultrasonic waves are applied to a capillary (not shown) to remove gold. After the wire 6 is bonded to the bonding pad 4 of the IC chip 3, the wire 6 is guided onto the copper wiring 5 of the substrate 21, pressure-bonded to the copper wiring 5, and wire bonding is performed.

Next, as shown in FIG. 16, the substrate 21 on which the IC chip 3 is mounted is set between the lower mold 51 and the upper mold 52 indicated by imaginary lines, and the inside of the cavity 53 corresponding to the shape of the mold resin is set. A mold compound is injected into and is solidified to mold the mold resin 7, and the package 40 is manufactured.
At this time, the injected mold compound flows under the back surface of the IC chip 3 through the gap 20a shown in FIG.
It is attached to the back surface as a.

Next, on the back surface side of the substrate 21, solder balls 8 are attached to the conductive layer 9 at the positions of the through holes 38 and the thermal vias 48, and the padless BGA package 40 as shown in FIGS. To complete. In addition, the solder ball 8 drops the vacuumed solder ball onto the back surface of the substrate 21 from above the flux (not shown), and adheres it onto the conductive layer 9 through a reflow process.

17 to 18 show another embodiment in which the present invention is applied to a padless plastic BGA.

According to this example, in the substrate 21, the cutout portion
The cross section of the board wall portion 21a (here, the end portion of the protruding piece portion 30) facing 20 is enlarged stepwise from the mount side of the IC chip 3 to the opposite side, and a step 21b is formed by the notch. The configuration is characteristic, and the other configurations are the same as those of the above-described embodiment, and the same effect is obtained.

That is, as schematically shown in FIG. 18, at the time of resin molding, the mold compound 7 ′ injected into the cavity 53 flows as shown by an arrow and flows not only on the front surface of the IC chip 3 but also on its back surface. Filled, but at this time, the substrate
Since the above step 21b is formed on the tongue piece portion 30 of 21, the mold compound 7'causes a pressure to press the step 21b toward the lower mold 51 as shown in the enlarged view of FIG. 18 (a).

As a result, the wall portion 21a of the substrate 21 does not float up from the lower mold 51 and a gap is not formed between them, so that the back surface of the IC chip 3 can be filled with the mold compound well. On the other hand, when the wall 21a of the substrate 21 does not have the above-described step, the wall 21a may be lifted up from the lower mold 51 by the pressure of the mold compound 7 ', as shown in FIG. 18 (c). Yes, the resulting gap 54
A phenomenon (flashing) in which the mold compound 7'intrudes into the inside and leaks from the place where the mold compound is necessary is apt to occur, and the filling property to the place may be deteriorated. Although the step 21b has one step, it goes without saying that it may have two steps or more.

The effect similar to that described with reference to FIG.
As shown in (b), it can also be obtained by forming a linear inclined surface 21c on the end surface of the wall portion 21a of the substrate 21 and continuously enlarging the cross section of the wall portion 21a. That is, the inclined surface 21
This is because the mold compound 7'presses c and the force of pressing the wall portion 21a against the lower mold 51 acts. Although the inclined surface 21c has a linear shape, it may have a polygonal line shape, a curved shape, or a combination of a straight line and a curved line.

FIG. 19 shows the IC chip 3 in comparison with the example of FIG.
The projecting piece for mounting has a pair of tongue pieces 30 similar to those described above on a diagonal line, and a cutout portion on another diagonal line.
It has a connecting piece portion 60 extending so as to straddle 20. In the connecting piece portion 60, the central portion 60a is bulged to some extent, and the IC chip is mounted on the central portion 60a through the silver paste, and the thermal via 48 is formed.

Therefore, in addition to the effect similar to that of the above-described embodiment, since the mounting area is enlarged by the connecting piece portion 60, the IC chip can be fixed more than enough.

20 and 21 show various other protruding piece portions. However, the thermal vias are omitted for simplicity of illustration.

In each of these various protruding pieces, as shown in FIG.
(B), FIG. 20 (F), FIG. 21 (B), FIG. 21 (C), FIG.
(D), FIG. 21 (E), and FIG. 21 (G) show examples in which the length, position, and shape of the tongue piece 30 are modified, and FIG. 20 (A) and FIG.
20 (C), 20 (D), 20 (G), 20 (H), 21
21 (F), FIG. 21 (H), and FIG. 21 (I) show examples in which the position and shape of the connecting piece portion 60 are modified. Also, FIG.
(E) shows a modification of the combination of the tongue piece portion 30 and the connecting piece portion 60. It will be easily understood that both examples have the same effects as described above.

However, considering the stability of the IC chip 3 to be mounted, it is desirable that the four corners of the IC chip be mounted from the standpoint of preventing misalignment during molding, and so on.
20 (A), 20 (B), and FIG.
20 (E), FIG. 20 (F), FIG. 20 (G), and FIG. 20 (H) are preferable, and considering the problems due to the amount of silver paste and the substrate area, the example of FIG. (B), Figure 20 (C), Figure
20 (D), 21 (A), 21 (B), 21 (C), 21
The examples of (D), FIG. 21 (E), and FIG. 21 (G) are preferable.

FIG. 22 shows another embodiment in which the present invention is applied to a padless plastic BGA.

According to this example, the recess 21d is formed in the substrate 21 in the mounting area 47 of the IC chip 3, the thickness of the substrate 21 is processed to be small, and the IC chip 3 is mounted on the recess 21d. The height of the upper surface of the subsequent IC chip 3 is lowered (desirably, the height is substantially the same as the upper surface of the substrate 21).

That is, since the height of the bonding pad 4 of the IC chip 3 is lower than that in the above-described example, wire bonding with the wiring 5 is facilitated, and the height around which the wire 6 is drawn is reduced. Only the thickness of the molding resin 7 (thus, the thickness of the package 40) can be reduced. In addition, the possibility that the wire 6 contacts the edge portion of the IC chip 3 to cause an electrical short circuit is reduced. In this case, the substrate
If the thickness of 21 is increased, the IC chip 3 can be easily accommodated within the range of the thickness of the substrate 21, and the amount of the resin 7a adhering to the back surface of the substrate 21 is increased to further improve the crack resistance. Other than that, the same effects as the above-described example can be obtained.

FIG. 23 shows another embodiment in which the present invention is applied to a padless plastic BGA.

In this example, the through hole 38 of the substrate 21 is not a solder resist but a part 7 of the mold resin 7.
It is characteristic that b is filled.

Therefore, the resin portion 7 is
Since b is included, the mold resin 7 is, so to speak, a substrate
Since it has an anchoring effect on 21, the adhesive force or mechanical coupling force between them is improved as compared with the above-mentioned example. This makes cracking and peeling less likely to occur during thermal cycling.

24 to 35 show another embodiment in which the present invention is applied to a padless plastic BGA.

The present embodiment is aimed at improving the structure of the thermal via 48 for releasing the heat generated by the IC chip 3 to the printed wiring board 14 side, and the inside of the thermal via 48 is a solder resist 33. While being filled, the thermal via 48 or the solder resist 33 is completely covered from the front and back by the second copper plating layers 65 and 69. Others are the same as the above-mentioned example.

The solder resist 33 with which the thermal via 48 is filled is originally liable to absorb moisture and easily deteriorate the moisture resistance of the package, but the copper plating layer 65 according to this embodiment is used.
And 69 prevent absorption (moisture absorption) of moisture into the solder resist 33, and also prevent leakage of moisture to the outside even if the solder resist 33 has already absorbed moisture.

In this way, the invasion of water by the solder resist 33 can be effectively prevented, so that a structure with good moisture resistance without package cracks is obtained. Then, the hygroscopic silver paste 22 is present on the thermal via 48, but since the copper plating layers 65 and 69 prevent the invasion of water, the amount of hygroscopicity to the silver paste 22 also results. It can be reduced, and the expansion of water vapor described above can be reduced.

Even in the through holes 38 other than the thermal vias 48, the front and back of the solder resist 33 are covered with the same copper plating layers 65 and 69 as described above, so that the solder resist 33 in the through holes 38 can be passed through. It is also possible to prevent moisture from entering.

Since the solder ball 8 is provided directly below the thermal via 48 (further, the through hole 38),
Compared with the conventional example of 44, it is not necessary to separately provide a region required for attaching solder balls, and the area of the substrate 21 is reduced by this amount, which is advantageous for downsizing and effective use of the substrate.

A method of manufacturing the structure of this embodiment will be described. First, as shown in FIG. 26, a glass epoxy laminated substrate 21 using BT resin is prepared, and this is punched with a drill or the like as shown in FIG. Opening is performed to form a thermal via 48 (a through hole 38 is also formed, but this is omitted in the drawing: the same applies hereinafter).

Next, as shown in FIG. 28, a conductive layer 50 is plated on the entire surface including the thermal vias 48. This plating layer can be formed by chemical plating or electroplating of copper.

Next, as shown in FIG. 29, a resin (solder resist) 33 is applied and filled in the thermal via 48 portion, and as shown in FIG. 30, the front and back surfaces of the solder resist 33 are flattened by polishing. To do.

Then, as shown in FIG. 31, copper layers 75 and 79 are formed on the front and back surfaces of the substrate 21 by chemical plating or electroplating, respectively.

Next, as shown in FIG. 32, photoresists 70 and 71 are provided at predetermined locations by pattern exposure and development, and as shown in FIG. 33, the photoresists 70 and 71 are used as masks to form copper layers 75 and 50. , 79 and 50 are etched in the same pattern to form copper layers 65 and 5, 69 and 9 in a predetermined pattern.

Then, after removing the photoresists 70 and 71 as shown in FIG. 34, a solder resist 33 'is applied to the back surface of the substrate 21 as shown in FIG. Then, as shown in FIG. 25, the IC chip 3 is mounted on the front surface of the substrate 21 via the silver paste 22, and the solder balls 8 are attached to the back surface thereof.

FIG. 36 shows another embodiment in which the present invention is applied to a padless plastic BGA.

In this embodiment, as compared with the examples of FIGS. 24 and 25, the second copper plating layer 69 is not formed on the back surface of the substrate 21, and the solder balls are directly formed under the solder resist 33 of the thermal via 48. The difference is that 8 is attached (such a structure may be similar in the through hole 38).

Even with this structure, the copper plating layer 65 can prevent moisture from entering from the solder resist 33, and at the same time the solder ball 8 itself covers the solder resist 33 from the back side. It has the same moisture invasion prevention function as 69, and the copper plating layer
There is an advantage that 69 can be omitted.

FIG. 37 shows another embodiment in which the present invention is applied to a padless plastic BGA.

In the case of this embodiment, as compared with the example of FIG. 36, the thermal vias 48 are made hollow before the solder ball 8 attaching step, and the thermal vias are attached when the solder balls 8 are attached.
The inside of 48 is filled with the solder 8a supplied from the solder ball 8 (such a structure may be the same in the through hole 38). The copper plating layer 65 is applied to the upper part of the thermal via 48 in the same manner.

Even with this structure, the infiltration of water through the thermal vias 48 can be prevented by the solder balls 8, the solder 8a and the copper plating layer 65 as in the example of FIG.

FIG. 38 shows still another embodiment in which the present invention is applied to a padless plastic BGA.

In the structure of this embodiment, the copper plating layer 65 on the thermal via 48 is omitted in the example of FIG. 37. However, even if the copper plating layer 65 does not exist, the solder balls 8
And, the infiltration of water through the thermal via 48 can be considerably prevented by the solder 8a.

Although the embodiments of the present invention have been described above, the above-mentioned embodiments can be further modified based on the technical idea of the present invention.

For example, the shape of the notch 20 formed on the substrate 21 which is the above-mentioned mounting base, the shape and position of the protruding piece 30 or the connecting piece 60, the material of the substrate 21, the mounting method of the IC chip 3, and The bonding method, and further, the material and structure of the moisture intrusion prevention material can be variously changed. Even if the protruding piece 30 is not provided, the IC chip 3 can be mounted on the substrate 21 around the cutout portion 20, but the cutout portion 20 is mounted around the IC chip 3 after mounting.
Just leave a part of.

In this case, for example, in the examples of FIGS. 24 to 35, the moisture invasion preventing structure is mainly described for the thermal via 48, and the padless BGA described in the examples of FIGS. 1 to 16 is used together with this structure. Although adopted, such a combination is desirable. However, this padless BGA is shown in Fig. 24.
~ In the example of Fig. 35, it is not necessary to dare to adopt it. Similarly, in the examples of FIGS. 1 to 16, it is not necessary to intentionally adopt the moisture intrusion prevention structure of FIGS. Further, this moisture intrusion prevention structure may be adopted only in the thermal via 48 or only in the through hole 38, but it is preferable to adopt it in both.

The present invention can be applied to a package having a structure other than that described above, and the method of connecting to a printed wiring board may be variously changed.

[0096]

As described above, according to the semiconductor device of the first aspect of the invention, the semiconductor element is located in the region of the notch formed in the mounting substrate, and the circuit forming surface of the semiconductor element is formed. Since a part of the back surface located on the opposite side is fixed to the mounting base, only a part of the back surface of the semiconductor element is fixed with a mounting material such as silver paste. Even if it is a substance, the amount of water vapor generated during heating is reduced. Moreover, in this case, the molding material is also adhered to the back surface of the semiconductor element through a part of the above-mentioned notch existing around the semiconductor element, and the molding materials on the front surface and the back surface of the semiconductor element are integrated with each other. So
Adhesion between the semiconductor element and the molding material becomes good.

As a result, the moisture for absorbing the moisture of the mount material causes the stress for peeling off the semiconductor element from the mount substrate or the mold material during heating to be small and absorbed sufficiently. Popcorn-like package cracks as described above are less likely to occur.

Further, the area of the mounting substrate existing on the back surface of the semiconductor element is reduced by the above-mentioned cutout portion, and even if there is a difference in the coefficient of thermal expansion between the molding material and the mounting substrate, both of them are generated during the temperature cycle. The stress between them is reduced, and the warpage of the package as described above is reduced. The peeling between the two due to this warp is reduced, and package cracks are less likely to occur.

According to the semiconductor device of the second invention,
Since the through holes (particularly the through holes for radiating the heat generated by the semiconductor element from one surface side to the other surface side of the mounting substrate) provided in the mounting base are covered or filled with the moisture intrusion preventing material. Even if there is a hygroscopic material such as a solder resist in the through-holes, the invasion (release) of water from it is blocked or the hygroscopic material is removed from the through-holes. Water vapor is not generated from the through holes, and the semiconductor device has sufficient moisture resistance without package cracks.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a padless plastic BGA package according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a part of FIG.

FIG. 3 is a cross-sectional view of the same package connected to a printed wiring board.

FIG. 4 is an IC chip mounting substrate used in the package and a plan view after mounting the same.

FIG. 5 is a plan view, a side view, an enlarged view of a part thereof, and a rear view of an example of the package.

FIG. 6 is a plan view of an example of an IC chip mounting substrate used for the package and an enlarged view of a part thereof.

FIG. 7 is a detailed plan view of the same IC chip mounting substrate.

FIG. 8 is a sectional view of a step of the manufacturing method of the same package.

FIG. 9 is a sectional view of another process step in the method for manufacturing the same package.

FIG. 10 is a cross-sectional view of another process step in the method of manufacturing the same package.

FIG. 11 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 12 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 13 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 14 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 15 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 16 is a sectional view of still another process step in the method of manufacturing the package.

FIG. 17 is a cross-sectional view of a portion of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 18 is a cross-sectional view at the time of resin molding when manufacturing the same package.

FIG. 19 is a plan view of an example of an IC chip mounting substrate used for a padless plastic BGA package according to another embodiment of the present invention and an enlarged view of a part thereof.

FIG. 20 is a plan view of various IC chip mounting substrates used in a padless plastic BGA package according to another embodiment of the present invention.

FIG. 21 is a plan view of various IC chip mounting substrates used in a padless plastic BGA package according to another embodiment of the present invention.

FIG. 22 is a partial cross-sectional view of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 23 is a cross-sectional view of a portion of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 24 is a sectional view of an essential part of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 25 is a cross-sectional view of a part of the same package.

FIG. 26 is a cross-sectional view of a step in the method of manufacturing the package.

FIG. 27 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 28 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 29 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 30 is a cross-sectional view of another process step in the method of manufacturing the same package.

FIG. 31 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 32 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 33 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 34 is a cross-sectional view of another process step in the method of manufacturing the package.

FIG. 35 is a cross-sectional view of yet another process step in the method of manufacturing the package.

FIG. 36 is a sectional view of an essential part of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 37 is a cross-sectional view of an essential part of a padless plastic BGA package according to another embodiment of the present invention.

FIG. 38 is a cross-sectional view of essential parts of a padless plastic BGA package according to still another embodiment of the present invention.

FIG. 39 is a sectional view of a conventional plastic BGA package.

FIG. 40 is a plan view, a side view, an enlarged view of a part thereof, and a rear view of an example of the package.

FIG. 41 is a plan view of an example of an IC chip mounting substrate used in the package.

FIG. 42 is a cross-sectional view of a part of the same package in which a crack is generated.

FIG. 43 is a schematic side view of a package in which a warp occurs.

FIG. 44 is a detailed cross-sectional view of a part of the package.

[Explanation of symbols]

 1, 21 ... IC chip mounting substrate 2, 22 ... Silver paste 3 ... IC chip 4 ... Bonding pad 5, 9, 15 ... Copper wiring 6 ... Wire 7 ... Mold resin 7a ・ ・ ・ Mold resin part 7 '・ ・ ・ Mold compound 8 ・ ・ ・ Solder ball 8a ・ ・ ・ Solder 10,40 ・ ・ ・ Plastic BGA package 12,38 ・ ・ ・ Through hole 13,33 ・ ・ ・Solder resist 14 ・ ・ ・ Printed wiring board 17,47 ・ ・ ・ Mounting area 18,48 ・ ・ ・ Thermal via 20 ・ ・ ・ Notch 20a ・ ・ ・ Gap 21a ・ ・ ・ Wall 21b ・ ・ ・ Step 21c ・..Sloping surfaces 30 ... Projecting pieces 50, 65, 69 ... Copper plating layers 51, 52 ... Mold 53 ... Cavity

Claims (10)

[Claims] 1. A predetermined portion of a semiconductor element mounting substrate penetrates from one surface side to the other surface side to be cut away to form a cutout portion, and the semiconductor element is within a region of the cutout portion. A part of the back surface of the semiconductor element opposite to the circuit forming surface is fixed to the mounting base in the state of being located at, and a part of the cutout portion is provided around the semiconductor element in this fixed state. The semiconductor device in which the molding material on the front surface and the back surface of the semiconductor element is integrated with each other by applying the molding material to the back surface of the semiconductor element via this portion. 2. A protruding piece portion projecting into a cutout portion of a mounting base body is integrally provided with the mounting base body, and a part of a back surface of a semiconductor element is fixed to the protruding piece portion. The semiconductor device described in. 3. The mount area of the mount base in which the rear surface of the semiconductor element of the mount base is fixed is larger than the open area of the opposite surface side of the mount base. The semiconductor device described. 4. A semiconductor device in which a through hole penetrating from one surface side to the other surface side is formed in a mounting substrate for fixing a semiconductor element, and the through hole is covered or filled with a moisture intrusion preventing material. . 5. The semiconductor device according to claim 4, wherein the through hole is formed to radiate the heat generated by the semiconductor element from one surface side of the mounting substrate to the other surface side thereof. 6. The water entry preventing material with which the through hole is covered or filled comprises at least a part of a conductive layer of a mounting base, a solder ball or a solder.
Alternatively, the semiconductor device described in 5. 7. The semiconductor device according to claim 6, wherein the solder filled in the through hole is supplied from a solder ball attached to the other surface side of the mounting base. 8. The semiconductor device according to claim 4, which has the mount base and the mold structure or the protruding piece according to any one of claims 1 to 3. 9. A semiconductor element fixed to one surface side of the mounting base is connected to conductive layers on both surfaces thereof through through holes formed in the mounting base, and a semiconductor element fixed to the one surface side is electrically conductive on the one surface side. 9. The semiconductor device according to claim 1, wherein the semiconductor layer is connected to a layer and the conductive layer on the other surface side of the mounting substrate is connected to a printed wiring board. 10. The semiconductor element mounting substrate according to claim 1.