JPH09199303A - Electronic device and its manufacture - Google Patents
Electronic device and its manufactureInfo
- Publication number
- JPH09199303A JPH09199303A JP783296A JP783296A JPH09199303A JP H09199303 A JPH09199303 A JP H09199303A JP 783296 A JP783296 A JP 783296A JP 783296 A JP783296 A JP 783296A JP H09199303 A JPH09199303 A JP H09199303A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- electrode
- substrate
- film
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000011521 glass Substances 0.000 claims abstract description 58
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 239000000843 powder Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 37
- 238000010304 firing Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims 2
- 239000002994 raw material Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 230000004907 flux Effects 0.000 description 6
- 239000011247 coating layer Substances 0.000 description 5
- 229910020617 PbO—B2O3—SiO2 Inorganic materials 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000001856 Ethyl cellulose Substances 0.000 description 2
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 2
- 239000000020 Nitrocellulose Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000003763 carbonization Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 description 2
- 229920001249 ethyl cellulose Polymers 0.000 description 2
- 235000019325 ethyl cellulose Nutrition 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229920001220 nitrocellulos Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229940116411 terpineol Drugs 0.000 description 2
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- LSNNMFCWUKXFEE-UHFFFAOYSA-N Sulfurous acid Chemical compound OS(O)=O LSNNMFCWUKXFEE-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 229910000037 hydrogen sulfide Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- BSWGGJHLVUUXTL-UHFFFAOYSA-N silver zinc Chemical compound [Zn].[Ag] BSWGGJHLVUUXTL-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えばチップ型Ｐ
ＴＣサーミスタ等の電子素子に関する。BACKGROUND OF THE INVENTION The present invention relates to, for example, a chip type P
The present invention relates to electronic devices such as TC thermistors.
【０００２】[0002]
【発明が解決しようとする課題】チップ型ＰＴＣサーミ
スタとして種々のものが知られているが、角形チップ状
の基体の両端部に電極を備え、電極形成部を除く基体表
面の殆どが外気に対して露出した構造のものが基本的な
ものである。このようなＰＴＣサーミスタは、例えば半
導体セラミックス製の原板を長尺状の短冊形に成形し、
この短冊形体の両端縁に電極を形成した後、複数個にス
ライスすることで得られている。Various types of chip-type PTC thermistors are known, but electrodes are provided at both ends of a rectangular chip-shaped substrate, and most of the substrate surface excluding the electrode forming part is exposed to the outside air. The exposed structure is the basic one. In such a PTC thermistor, for example, an original plate made of semiconductor ceramics is formed into a long strip shape,
It is obtained by forming electrodes on both end edges of this strip and then slicing into a plurality of pieces.
【０００３】しかし、上記構造のＰＴＣサーミスタは、
基体の表面の殆どが外気に対して露出している為、外気
の影響を受け、特性の劣化がもたらされ、信頼性が低下
する。例えば、塩化水素、アンモニア、硫化水素、亜硫
酸ガス等の腐食性ガス雰囲気下で使用されると、これら
のガスによって基体そのものが侵食を受け、特性の劣化
がもたらされ、信頼性が低下する。又、腐食性ガス雰囲
気下ではなく、真空雰囲気下で使用されても、基体を構
成する材料中の酸素成分等が抜けることが有り、特性の
劣化がもたらされ、信頼性が低下する。However, the PTC thermistor having the above structure is
Since most of the surface of the substrate is exposed to the outside air, it is affected by the outside air, resulting in deterioration of the characteristics and reduced reliability. For example, when used in a corrosive gas atmosphere such as hydrogen chloride, ammonia, hydrogen sulfide, or sulfurous acid gas, these gases corrode the substrate itself, resulting in deterioration of characteristics and deterioration of reliability. Further, even when used in a vacuum atmosphere rather than in a corrosive gas atmosphere, oxygen components and the like in the material forming the substrate may escape, resulting in deterioration of characteristics and deterioration of reliability.
【０００４】又、チップ型ＰＴＣサーミスタを回路基板
に実装する場合、基体の表面にフラックス等の薬剤が付
着することも有り、残存フラックスによって基体の特性
劣化がもたらされ、信頼性が低下する。又、チップ型Ｐ
ＴＣサーミスタを回路基板に半田付けした場合、半田が
電極部のみでなく基体の表面にも付き、短絡が起き、所
望の抵抗値にならない場合が有る。Further, when the chip type PTC thermistor is mounted on a circuit board, chemicals such as flux may adhere to the surface of the substrate, and the residual flux causes deterioration of the characteristics of the substrate and lowers reliability. Also, chip type P
When the TC thermistor is soldered to the circuit board, the solder may be attached not only to the electrode portion but also to the surface of the substrate, and a short circuit may occur, so that the desired resistance value may not be obtained.
【０００５】このような欠点を解決する為、図３に示す
如く、基体１１の少なくとも両主表面をガラスのコーテ
ィング層１２で被覆し、この基体１１の両端部に、基体
１１の端面とコーティング層１２の両端縁部それぞれを
覆うように電極１３を形成したことを特徴とするチップ
型ＰＴＣサーミスタが提案（実公平５−４７４４４号公
報）されている。In order to solve such a drawback, as shown in FIG. 3, at least both main surfaces of the substrate 11 are coated with a glass coating layer 12, and the end face of the substrate 11 and the coating layer are formed on both ends of the substrate 11. A chip type PTC thermistor is proposed (Japanese Utility Model Publication No. 47474/1993), which is characterized in that the electrodes 13 are formed so as to cover both end edges of the electrode 12.
【０００６】しかし、この提案のものでも充分なもので
なかった。すなわち、基体１１の少なくとも両主表面が
ガラスのコーティング層１２で被覆されていることか
ら、基体１１に対するコーティング層１２による保護は
厚いものの、電極１３が基体１１の端面とコーティング
層１２の両端縁部を覆うように形成されている為、つま
り電極１３の端部１３ａ，１３ｂが外に突出した構造と
なっている為、電極１３の端部１３ａ，１３ｂからの剥
離が起き易い。ところで、電極１３に、端部１３ａ，１
３ｂからの剥離が起きると、これは所望の抵抗値になら
ない。[0006] However, the proposal is not sufficient. That is, since at least both main surfaces of the substrate 11 are coated with the glass coating layer 12, the electrode 11 is protected from the end face of the substrate 11 and both edge portions of the coating layer 12 although the coating layer 12 protects the substrate 11 thickly. Since it is formed so as to cover the electrode 13, that is, the end portions 13a and 13b of the electrode 13 are projected outward, peeling from the end portions 13a and 13b of the electrode 13 easily occurs. By the way, the end portions 13a, 1
When delamination from 3b occurs, it does not have the desired resistance value.
【０００７】よって、基体１１の保護と、電極１３の剥
離が起きないようにすることは極めて大事である。従っ
て、本発明の課題は、基体の保護と、電極の剥離が起き
ないようにした電子素子を提供することである。Therefore, it is extremely important to protect the substrate 11 and prevent the electrode 13 from peeling off. Therefore, it is an object of the present invention to provide an electronic device which protects a substrate and prevents peeling of electrodes.
【０００８】[0008]
【課題を解決するための手段】前記本発明の課題は、電
子素子の基体と、この基体の表面を覆う保護膜と、前記
基体に電気的に接続して設けられた前記保護膜成分を含
有する電極とを具備し、前記保護膜と電極との境界領域
は両者の成分が融合してなることを特徴とする電子素子
によって達成される。The object of the present invention includes a substrate of an electronic device, a protective film covering the surface of the substrate, and the protective film component electrically connected to the substrate. The electronic device is characterized in that the boundary region between the protective film and the electrode is formed by fusing the components of both electrodes.
【０００９】特に、電子素子の基体と、この基体の表面
を覆うガラス膜と、前記基体に電気的に接続して設けら
れた前記ガラス成分を含有する電極とを具備し、前記ガ
ラス膜と電極との境界領域は両者の成分、特にガラス成
分が融合してなることを特徴とする電子素子によって達
成される。又、電子素子の基体と、この基体の表面を覆
うようガラスペーストを塗布・焼成することにより構成
されたガラス膜と、前記基体に電気的に接続して設けら
れた導電性粉末１００重量部に対してガラスフリットを
１〜１５重量部含有する導電性ペーストを塗布・焼成す
ることにより構成された電極とを具備し、前記ガラス膜
と電極との境界領域は両者の成分、特にガラス成分が融
合してなることを特徴とする電子素子によって達成され
る。In particular, it is provided with a substrate of an electronic device, a glass film covering the surface of the substrate, and an electrode containing the glass component, which is provided in electrical connection with the substrate, and the glass film and the electrode. The boundary area between and is achieved by an electronic device characterized in that both components, particularly a glass component, are fused. In addition, the base of the electronic element, the glass film formed by coating and firing a glass paste so as to cover the surface of the base, and 100 parts by weight of the conductive powder electrically connected to the base are provided. On the other hand, an electrode constituted by applying and firing a conductive paste containing 1 to 15 parts by weight of glass frit, and the boundary region between the glass film and the electrode is a fusion of both components, particularly a glass component. This is achieved by an electronic device characterized by
【００１０】又、電子素子の基体の表面にガラスペース
トを塗布するＡ工程と、電子素子の基体に電気的に接続
されるようガラスフリットを含有する導電性ペーストを
塗布するＢ工程と、前記Ａ，Ｂ塗布工程の後で焼成する
焼成工程とを具備することを特徴とする電子素子の製造
方法によって達成される。A step of applying a glass paste on the surface of the base of the electronic element, a step B of applying a conductive paste containing a glass frit so as to be electrically connected to the base of the electronic element, and the step A , B coating step, and a firing step of firing after the B application step.
【００１１】尚、保護膜（ガラス膜）や電極に用いられ
るガラスとしては、硼珪酸鉛ガラス（例えば、ＰｂＯ；
２０モル％以上〜８０モル％未満，Ｂ2 Ｏ3 ；２０モル
％以上〜８０モル％未満，ＳｉＯ2 ；１０モル％未満の
ＰｂＯ−Ｂ2 Ｏ3 −ＳｉＯ2系のガラス）等を用いるこ
とが出来る。勿論、これ以外のガラスであっても良い。The glass used for the protective film (glass film) and the electrodes is lead borosilicate glass (for example, PbO;
Less than 20 mol% to 80 mol%, B 2 O 3; 20 less mol% to 80 mol%, SiO 2; less than 10 mol% PbO-B 2 O 3 -SiO 2 system glass) such as the use of Can be done. Of course, other glass may be used.
【００１２】形成される保護膜（ガラス膜）の厚さは
０．１〜６０μｍ（望ましくは１〜５０μｍ、より望ま
しくは５〜５０μｍ）程度であるのが好ましい。電極に
用いられる導電性材料としては、例えばＡｇ，Ａｌ，Ｎ
ｉ，Ｃｕ，Ａｇ−Ｇａ，Ａｇ−Ｚｎ，Ａｇ−Ｉｎ−Ｇａ
等の金属の中から選ばれるものを用いることが出来る。The thickness of the protective film (glass film) formed is preferably about 0.1 to 60 μm (preferably 1 to 50 μm, more preferably 5 to 50 μm). As the conductive material used for the electrodes, for example, Ag, Al, N
i, Cu, Ag-Ga, Ag-Zn, Ag-In-Ga
It is possible to use a metal selected from such metals.
【００１３】電極を構成する為、導電性ペースト中に含
ませるガラスフリットの含有量は、導電性粉末１００重
量部に対してガラスフリットが望ましくは１〜１５重量
部、更に望ましくは５〜１２重量部、もっと望ましくは
７〜１０重量部である。すなわち、ガラスフリットの含
有量を上記のようにすることによって、ガラス膜と電極
との境界領域における融合・一体化が極めて好ましいも
のになる。The content of the glass frit contained in the conductive paste for forming the electrode is preferably 1 to 15 parts by weight, more preferably 5 to 12 parts by weight, based on 100 parts by weight of the conductive powder. Parts, more preferably 7 to 10 parts by weight. That is, by setting the content of the glass frit as described above, the fusion and integration in the boundary region between the glass film and the electrode becomes extremely preferable.
【００１４】尚、電極部分を除いた基体全表面が保護膜
（ガラス膜）で覆われることが好ましいが、部分的に基
体が露出していても良い。そして、上記のように構成さ
せると、特に基体の表面にガラスペーストを塗布すると
共に、ガラスフリットを含有する導電性ペーストを塗布
し、焼成することにより、保護膜としてのガラス膜と電
極膜との境界領域はガラス成分が融合して一体化し、図
３で示されるような電極膜が剥離し易い構造のものから
剥離し難い構造のものに変化している。すなわち、電極
膜がガラス膜を覆うタイプのものとは異なり、融合一体
化したものとなっている。この為、電極膜が剥離し難い
ものとなっている。かつ、基体の表面が保護膜（ガラス
膜）で覆われているから、基体が雰囲気ガス等によって
悪影響を受け難く、品質の耐久性にも富む。It is preferable that the entire surface of the substrate except the electrode portion is covered with a protective film (glass film), but the substrate may be partially exposed. When configured as described above, the glass paste is applied to the surface of the substrate, the conductive paste containing the glass frit is applied, and the glass paste as a protective film is formed. In the boundary region, the glass components are fused and integrated, and the structure in which the electrode film as shown in FIG. 3 is easily peeled is changed from the structure in which peeling is difficult. That is, unlike the type in which the electrode film covers the glass film, the electrode film is integrated and integrated. Therefore, the electrode film is difficult to peel off. In addition, since the surface of the substrate is covered with the protective film (glass film), the substrate is less likely to be adversely affected by atmospheric gas and the like, and the quality is excellent in durability.
【００１５】又、回路基板に実装する場合、表面にフラ
ックス等の薬剤が付着しても、残存フラックスによって
基体の特性劣化がもたらされ難く、信頼性が高い。又、
回路基板に半田付けした場合、表面に半田が付いても短
絡が起きない。Further, when mounted on a circuit board, even if a chemical such as flux adheres to the surface, the residual flux is unlikely to cause deterioration of the characteristics of the substrate, and the reliability is high. or,
When soldered to a circuit board, short circuit does not occur even if the surface is soldered.
【００１６】[0016]
【発明の実施の形態】図１は本発明に係る電子素子の１
実施形態の概略断面図、図２は本発明の電子素子の製造
工程（ガラス膜および電極膜の塗布工程後であって、焼
成前）での概略断面図である。１は、例えばチタン酸バ
リウム等の半導体材料からなる直方体形状の電子素子の
基体である。DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows an electronic device 1 according to the present invention.
FIG. 2 is a schematic cross-sectional view of an embodiment, FIG. 2 is a schematic cross-sectional view in a manufacturing process of an electronic device of the present invention (after a coating process of a glass film and an electrode film and before firing). Reference numeral 1 denotes a rectangular parallelepiped electronic element substrate made of a semiconductor material such as barium titanate.
【００１７】２は、基体１の主表面に設けられたガラス
膜（保護膜）である。３は、基体１の両端面に設けられ
た電極膜である。ガラス膜２や電極膜３は、次のように
して形成される。先ず、所定の幅を有する短冊状に形成
された原料板体１ａの両主表面に、ガラス粉末ペースト
２ａをスクリーン印刷等の方法で焼成後の厚さが５〜５
０μｍとなるよう塗布する。又、ガラスフリットを含有
する導電性ペースト３ａを原料板体１ａの両端面に焼成
後の厚さが５〜５０μｍとなるよう塗布する。Reference numeral 2 is a glass film (protective film) provided on the main surface of the substrate 1. Reference numeral 3 is an electrode film provided on both end surfaces of the base 1. The glass film 2 and the electrode film 3 are formed as follows. First, the glass powder paste 2a has a thickness of 5 to 5 after firing by a method such as screen printing on both main surfaces of the raw material plate 1a formed in a strip shape having a predetermined width.
It is applied so as to have a thickness of 0 μm. Further, the conductive paste 3a containing the glass frit is applied to both end faces of the raw material plate 1a so that the thickness after firing becomes 5 to 50 μm.
【００１８】ガラス粉末ペースト２ａは、エチルセルロ
ースあるいはニトロセルロース等の高温で炭化するより
も分解・揮発性が高いバインダ樹脂をテルピネオール等
の溶剤に２〜１５ｗｔ％となるよう混合・分散させた溶
液１重量部に対して、ＰｂＯ−Ｂ2 Ｏ3 −ＳｉＯ2 系ガ
ラス（ＰｂＯ；４０モル％，Ｂ2 Ｏ3 ；５５モル％，Ｓ
ｉＯ2 ；５モル％）の粉末を６〜１０重量部添加し、充
分に混練したものである。導電性ペースト３ａは、エチ
ルセルロースあるいはニトロセルロース等の高温で炭化
するよりも分解・揮発性が高いバインダ樹脂をテルピネ
オール等の溶剤に２〜１５ｗｔ％となるよう混合・分散
させた溶液１重量部に対して、Ａｇ粉末８〜１８重量
部、前記と同じＰｂＯ−Ｂ2 Ｏ3 −ＳｉＯ2 系ガラスの
粉末を０．１〜２重量部（Ａｇ粉末１００重量部に対し
てＰｂＯ−Ｂ2 Ｏ3 −ＳｉＯ2 系ガラスの粉末は１〜１
５重量部の範囲内となるよう）添加し、充分に混練した
ものである。The glass powder paste 2a is 1 weight of a solution prepared by mixing and dispersing a binder resin, such as ethyl cellulose or nitrocellulose, which has a higher decomposition and volatility than carbonization at a high temperature, in a solvent such as terpineol in an amount of 2 to 15 wt%. against part, PbO-B 2 O 3 -SiO 2 based glass (PbO; 40 mol%, B 2 O 3; 55 mole%, S
6 to 10 parts by weight of powder (iO 2 ; 5 mol%) was added and sufficiently kneaded. The conductive paste 3a is based on 1 part by weight of a solution prepared by mixing and dispersing a binder resin, such as ethyl cellulose or nitrocellulose, which has higher decomposition and volatility than carbonization at high temperature, in a solvent such as terpineol so as to be 2 to 15 wt%. Te, Ag powder 8 to 18 parts by weight, the same PbO-B 2 O 3 -SiO 2 based powder 0.1 to 2 parts by weight of glass (Ag powder PbO-B 2 O 3 with respect to 100 parts by weight - The powder of SiO 2 glass is 1 to 1
5 parts by weight) and sufficiently kneaded.
【００１９】そして、図２に示す如く、ガラス粉末ペー
スト２ａや導電性ペースト３ａが塗布された後、これを
焼成炉に入れて４５０〜９００℃に保持して焼成する
と、ガラス膜２や電極膜３が形成される。この後、原料
板体１ａを長手方向において所定の幅にスライスするこ
とによって図１に示されるチップ型ＰＴＣサーミスタが
得られる。Then, as shown in FIG. 2, after the glass powder paste 2a and the conductive paste 3a are applied, they are put in a firing furnace and held at 450 to 900 ° C. to be fired. 3 is formed. After that, the raw material plate 1a is sliced into a predetermined width in the longitudinal direction to obtain the chip type PTC thermistor shown in FIG.
【００２０】上記のように構成させたチップ型ＰＴＣサ
ーミスタは、導電性ペースト３ａにガラス粉末ペースト
２ａのガラス成分と同じ成分のものが含まれているの
で、焼成時に、導電性ペースト３ａとガラス粉末ペース
ト２ａとの境界部分が融合・一体化したものとなる。す
なわち、図３に示した電極膜３がガラス膜２を覆うタイ
プのものとは異なり、融合一体化したものとなってい
る。この為、電極膜３が剥離し難いものとなっている。In the chip type PTC thermistor configured as described above, the conductive paste 3a contains the same component as the glass component of the glass powder paste 2a. The boundary with the paste 2a is fused and integrated. That is, unlike the type in which the electrode film 3 shown in FIG. 3 covers the glass film 2, the electrode film 3 is fused and integrated. Therefore, the electrode film 3 is difficult to peel off.
【００２１】因みに、上記実施形態になる本発明品と図
３タイプの比較品とについて、電極膜３の剥離特性を調
べると、本発明品の方が格段に剥離し難いものであっ
た。かつ、基体１の表面がガラス膜２で覆われているか
ら、基体１が雰囲気ガス等によって悪影響を受け難く、
チップ型ＰＴＣサーミスタの品質耐久性にも富む。又、
ＰＴＣサーミスタを回路基板に実装する場合、表面にフ
ラックス等の薬剤が付着しても、残存フラックスによっ
て基体１の特性劣化がもたらされ難く、信頼性が高い。Incidentally, when the peeling characteristics of the electrode film 3 of the product of the present invention according to the above-described embodiment and the comparative product of the type shown in FIG. 3 were examined, it was found that the product of the present invention was much more difficult to peel. Moreover, since the surface of the base body 1 is covered with the glass film 2, the base body 1 is less likely to be adversely affected by atmospheric gas or the like.
The chip type PTC thermistor is also highly durable. or,
When the PTC thermistor is mounted on a circuit board, even if a chemical such as flux adheres to the surface, the residual flux is unlikely to cause deterioration of the characteristics of the base body 1 and is highly reliable.
【００２２】又、ＰＴＣサーミスタを回路基板に半田付
けした場合、表面に半田が付いても短絡が起きない。
尚、スライスした面にもガラス粉末ペースト２ａを塗布
し、焼成すれば、基体１の四つの主表面にガラス膜２が
設けられたものとなる。又、導電性ペースト３ａを塗布
した後、ガラス粉末ペースト２ａを塗布し、この後焼成
する手順であっても、ガラス粉末ペースト２ａを塗布し
た後、導電性ペースト３ａを塗布し、この後焼成する手
順であっても良い。Further, when the PTC thermistor is soldered to the circuit board, even if solder is attached to the surface, no short circuit will occur.
When the glass powder paste 2a is applied to the sliced surface and baked, the glass film 2 is provided on the four main surfaces of the substrate 1. Further, even in the procedure of applying the glass powder paste 2a after applying the conductive paste 3a and then firing, even after applying the glass powder paste 2a, applying the conductive paste 3a and then firing. It may be a procedure.
【００２３】[0023]
【発明の効果】本発明によれば、保護膜と電極との境界
領域は両者の成分が融合してなるので、電極が剥離し難
く、かつ、基体の表面が保護膜で覆われているから、基
体が雰囲気ガス等によって悪影響を受け難く、品質の耐
久性にも富む。According to the present invention, the boundary area between the protective film and the electrode is a fusion of both components, so that the electrode is less likely to peel off and the surface of the substrate is covered with the protective film. In addition, the substrate is not easily adversely affected by atmospheric gas and the like, and has excellent quality durability.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の電子素子（チップ型ＰＴＣサーミス
タ）の１実施形態の概略断面図FIG. 1 is a schematic cross-sectional view of one embodiment of an electronic device (chip type PTC thermistor) of the present invention.
【図２】本発明の電子素子（チップ型ＰＴＣサーミス
タ）の製造工程での概略断面図FIG. 2 is a schematic cross-sectional view in a manufacturing process of an electronic element (chip type PTC thermistor) of the present invention.
【図３】従来のチップ型ＰＴＣサーミスタの概略断面図FIG. 3 is a schematic sectional view of a conventional chip type PTC thermistor.
１ 電子素子の基体 ２ ガラス膜（保護膜） ２ａ ガラス粉末ペースト ３ 電極膜 ３ａ ガラスフリットを含有する導電性ペースト 1 Substrate of Electronic Element 2 Glass Film (Protective Film) 2a Glass Powder Paste 3 Electrode Film 3a Conductive Paste Containing Glass Frit
Claims (4)
う保護膜と、前記基体に電気的に接続して設けられた前
記保護膜成分を含有する電極とを具備し、 前記保護膜と電極との境界領域は両者の成分が融合して
なることを特徴とする電子素子。1. A substrate for an electronic device, a protective film covering the surface of the substrate, and an electrode containing the protective film component provided electrically connected to the substrate, the protective film comprising: An electronic element characterized in that the boundary area with the electrode is formed by fusing both components.
の構成材料はガラスを含有するものであることを特徴と
する請求項１の電子素子。2. The electronic device according to claim 1, wherein the constituent material of the protective film is glass, and the constituent material of the electrode contains glass.
ることにより構成されたものであり、電極は導電性粉末
１００重量部に対してガラスフリットを１〜１５重量部
含有する導電性ペーストを塗布・焼成することにより構
成されたものであることを特徴とする請求項１又は請求
項２の電子素子。3. The protective film is formed by applying and firing glass paste, and the electrode is applied with a conductive paste containing 1 to 15 parts by weight of glass frit per 100 parts by weight of conductive powder. The electronic element according to claim 1 or 2, which is configured by firing.
を塗布するＡ工程と、 電子素子の基体に電気的に接続されるようガラスフリッ
トを含有する導電性ペーストを塗布するＢ工程と、 前記Ａ，Ｂ塗布工程の後で焼成する焼成工程とを具備す
ることを特徴とする電子素子の製造方法。4. A step of applying a glass paste on the surface of the base of the electronic element, a step B of applying a conductive paste containing a glass frit so as to be electrically connected to the base of the electronic element, and the step A , B, and a firing step of firing after the application step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP783296A JPH09199303A (en) | 1996-01-19 | 1996-01-19 | Electronic device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP783296A JPH09199303A (en) | 1996-01-19 | 1996-01-19 | Electronic device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09199303A true JPH09199303A (en) | 1997-07-31 |
Family
ID=11676583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP783296A Pending JPH09199303A (en) | 1996-01-19 | 1996-01-19 | Electronic device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09199303A (en) |
-
1996
- 1996-01-19 JP JP783296A patent/JPH09199303A/en active Pending
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