JPH09191450A - Scanning line converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate flicker generated when a noninterlace image is converted into an interlace image by providing an inverse characteristic of a vertical high frequency-horizontal low frequency component to a DC signal and providing the resulting output when a DC detection means detects the DC so as to interleave a prescribed line from the image. SOLUTION: R, G, B signals received from input terminals 1a-1c are converted into Y and two color difference signals R-Y, B-Y at a matrix circuit 10. The Y signal and the color difference signals R-Y, B-Y whose horizontal frequency band is halved by LPFs 30a, 30b are given respectively to A/D converter circuits 3a-3c. The output signal is fed to frame memories 7a-7c directly or via a flicker elimination circuit. The output signal is fed to a synchronization addition circuit 13 and a chroma encoder circuit 14 via D/A converter circuits 9a-9c. A synchronizing signal is given to all the circuits. The circuit 13 provides an output of a Y signal with vertical synchronizing signal and horizontal synchronizing signal are added thereto. The circuit 14 provides an output of a modulation color for the color difference signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a non-interlaced image output from a personal computer (hereinafter referred to as a personal computer) or the like into an interlaced image, and a television (hereinafter referred to as a television or TV).
The present invention relates to a scanning line conversion device when displaying on a display device such as.

[0002]

2. Description of the Related Art In recent years, the demand for personal computers has been rapidly growing all over the world. However, many of the personal computers that are becoming popular nowadays are purchased by businesses or individuals for business use. Therefore, diffusion to households will become the biggest issue in the future. In order to spread the personal computer in the home,
In addition to simplifying the operation and lowering the price, it is desirable to develop products that take into consideration family use. Recently, many personal computer manufacturers have released integrated personal computers with consideration of operability. These product groups include personal computers, displays, hard disks, floppy disks, CD-
Since the ROM and the like are integrated, the user does not have to connect the devices to each other. Also,
Each company is trying to improve the operability of the personal computer by devising the initial installation software (software for menu display, operation explanation, etc.).

However, the above-mentioned integrated personal computer is targeted at individuals, not at home (family). Similar to a conventional personal computer, the integrated personal computer allows a user to operate a keyboard or a mouse in front of a display of about 15 inches to enjoy a CD-ROM, a game, or the like. On the other hand, in the product development targeting the home (family), it is necessary to display the personal computer screen on a large display so that the detailed image or sound of the personal computer can be viewed by the whole family. Regarding operation, instead of using a conventional keyboard and mouse, operate a personal computer from a remote location using a wireless remote controller etc. used for home appliances such as audio-visual equipment (hereinafter referred to as AV equipment). You need to be able to.

The development of a display monitor for home use has the following problems. Generally, when a display for a personal computer is used as a display device, the price of the display is about four times that of a TV of the same size. This price difference (price) becomes a serious problem when the personal computer is popularized for home use. On the other hand, there is a method of displaying the output (display image) of a personal computer on a conventional home television screen. At that time, the display screen of the personal computer is sequentially scanned (hereinafter referred to as non-interlaced scanning), while the display of the television is interlaced scanning, so the image data sent by non-interlaced scanning (hereinafter, It is necessary to convert a non-interlaced image) into an interlaced scanning image (hereinafter referred to as an interlaced image). In that case,
Flicker occurs on the TV screen, resulting in a very unsightly image. Hereinafter, a screen display method for a personal computer and a television, a factor causing flicker, and a conventional scanning line conversion device equipped with a flicker removing circuit will be described.

First, a screen display method (screen display mode) of a personal computer will be briefly described. There are multiple modes for the screen display mode of a personal computer. Among them, the VGA standard which is often used will be briefly described. According to the VGA standard, the number of effective images on one line is 640.
The number of effective scanning lines in one frame is 480 lines. Further, the above image is displayed on the display in a non-interlaced manner. Note that there is no clear regulation regarding the frame frequency. (It is often output at a frame frequency of about 60 Hz.) Next, a screen display method (screen display mode) of the television will be described. IT
U-R Recommendation BT. According to 601 (system 525), the number of effective pixels in the horizontal direction of the television screen is 720 pixels (13.
The number of effective scanning lines in one frame is 486 when sampling at 5 MHz. Further, the television is displayed on the display as an interlaced image having a field frequency of 59.94 Hz. Therefore, when VGA output from a personal computer is simply converted into an interlaced image and displayed on a television screen, flicker occurs and the image becomes very unsightly.

Next, the process of generating flicker that occurs when converting a non-interlaced image to an interlaced image will be briefly described with reference to FIGS.
FIG. 18 is a diagram showing the characteristics of the spatial frequency of the non-interlaced image, showing the case where the number of scanning lines is 525 and the frame frequency is 60 Hz. In the figure, the horizontal axis shows the spatial frequency in the time axis direction, and the vertical axis shows the spatial frequency in the vertical direction. In the case of a non-interlaced image, the interval is 60 Hz in the time axis direction and 525 in the vertical direction.
The characteristics on the spatial frequency of the non-interlaced image (hereinafter, referred to as frequency spectrum) appear repeatedly at the line intervals. (See Fig. 18)

FIG. 19 is a diagram showing the spatial frequency characteristics of an interlaced image. More specifically, it shows the spatial frequency characteristics (frequency spectrum) when a non-interlaced image having the frequency spectrum shown in FIG. 18 is converted into an interlaced image. ing. (Field frequency 60H
z, interlaced image with 525 scanning lines) In the figure, the horizontal axis represents the spatial frequency in the time axis direction, and the vertical axis represents the spatial frequency in the vertical direction. The flicker that occurs when converting a non-interlaced image to an interlaced image is
This occurs because the high frequency component in the vertical direction folds back to the low frequency component in the vertical direction when viewed from the time axis direction. The hatched portion in the figure corresponds to a vertical high-frequency component turnover portion (flicker component) when viewed from the time axis direction.

FIG. 20 is a diagram showing a two-dimensional frequency characteristic of an interlaced image. In the figure, the horizontal axis represents the horizontal spatial frequency, and the vertical axis represents the vertical spatial frequency. Note that the hatched portion in the figure is the above-described vertical aliasing component (flicker component) on a two-dimensional frequency. Therefore, flicker can be eliminated by suppressing the high frequency component in the vertical direction.

FIG. 21 is a block diagram of a conventional scanning line conversion device. In this conventional example, a case where a signal based on the VGA standard is converted into an NTSC standard image will be described. In the figure, 1a to 1c are input terminals for VGA signals (R, G, and B signals based on the VGA standard), 2 are input terminals for synchronizing signals of VGA signals, and 3a to 3c are digital video signals for the input analog video signals. An analog / digital conversion circuit (hereinafter, referred to as an A / D conversion circuit or A / D) for converting into 4 is a V input from an input terminal 2.
A first synchronization detection circuit 5 for detecting a vertical synchronization signal and a horizontal synchronization signal from the synchronization signal of the GA signal, and a first synchronization detection circuit 5 for generating a clock based on the synchronization signal output from the first synchronization detection circuit 4. PLL circuits 6a to 6c are first vertical low-pass filters (hereinafter referred to as first VLPFs) for extracting vertical low-pass components of the input digital video signal, and 7a to 7c are first. It is a frame memory that stores digital video signals output from the VLPFs 6a to 6c.

Reference numeral 8 is a first memory control circuit for generating digital video signal write and read control signals to the line memories 23a and 23b in the first VLPFs 6a to 6c and the frame memories 7a to 7c, and 9
Reference numerals a to 9c are digital / analog conversion circuits (hereinafter, referred to as D / A conversion circuits or D / A) 10 for converting digital video signals output from the frame memories 7a to 7c into analog video signals. A matrix circuit for converting the R, G, and B signals into a luminance signal (hereinafter, referred to as Y signal) and two color difference signals (hereinafter, referred to as RY signal and BY signal), 11 Is a second PLL circuit which generates a clock based on the sync signal output from the second sync detection circuit 12, and 12 is a vertical sync signal and a horizontal sync signal from the TV-side sync signal input from the input terminal 16. It is a second synchronization detection circuit for detecting the like.

Reference numeral 13 is a synchronization addition circuit for adding a vertical synchronization signal and a horizontal synchronization signal to the Y signal output from the matrix circuit 10, and 14 is two color difference signals (R-Y signals) output from the matrix circuit 10. And BY signal)
Is a chroma encoder circuit for converting a modulated color signal (hereinafter referred to as a C signal), 15a and 15b are output terminals for Y and C signals, and 16 is an input terminal for a sync signal on the TV side.

FIG. 22 is a block diagram of a conventional first VLPF disclosed in, for example, Japanese Patent Laid-Open No. 7-95490. In the figure, 20 is a digital video signal input terminal, 21 is a memory control signal input terminal output from the first memory control circuit 8, 22 is a digital video signal output terminal, and 23a and 23b are input digital video signals. A line memory for delaying the signal by one line, 24a and 24b are multiplier circuits for multiplying the input digital video signal by 0.25, and 25 is 0.5 for the input digital video signal.
Is a multiplication circuit for multiplying by, and 26 is an addition circuit. FIG. 23 is a diagram showing frequency characteristics of the first VLPF shown in FIG. In the figure, the horizontal axis represents the vertical spatial frequency, and the vertical axis represents the amplitude characteristic.

The operation of the conventional scanning line conversion apparatus will be described below with reference to FIGS. In this conventional example, VG
A case of converting a non-interlaced image input based on the A standard into an interlaced image and outputting the interlaced image will be described. The R, G, and B signals input via the input terminals 1a to 1c are converted into digital video signals by the A / D conversion circuits 3a to 3c. On the other hand, the sync signal of the VGA signal input through the input terminal 2 is separated into the vertical sync signal and the horizontal sync signal by the first sync detection circuit 4. The horizontal sync signal separated by the first sync detection circuit 4 is the first PL.
It is input to the L circuit 5. The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronizing signal. The clock generated in the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the first memory control circuit 8. Note that the vertical synchronization signal and the horizontal synchronization signal detected by the first synchronization detection circuit 4 are also input to the first memory control circuit 8.

The first memory control circuit 8 uses the horizontal sync signal of the VGA signal output from the first sync detection circuit 4 to use the line memories 23a and 23b in the first VLPF 6.
A digital video signal write / read control signal is generated. For example, the line memories 23a, 2
When a FIFO (first in first out) memory is used for 3b, a line address reset signal at the time of writing and reading, a writing and reading enable signal (ENABL signal), and a writing and reading clock from the first memory control circuit 8. The signal is output. The first memory control circuit 8 also generates a write control signal of a digital video signal to the frame memories 7a to 7c using the vertical synchronizing signal and the horizontal synchronizing signal output from the first synchronization detecting circuit 4. In addition,
A specific control method for the frame memories 7a to 7c will be described later. Further, in the present conventional example, the FIFO memory is used as the line memories 23a and 23b in the first VLPF 6.

The R, G, and B signals converted into digital video signals by the A / D conversion circuits 3a to 3c are the first VL.
It is input to the PFs 6a to 6c. The operation of the first VLPF 6 will be described below with reference to FIG. The digital video signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. Line memory 2
At 3a, the input digital video signal is delayed by one line and output. The digital video signal output from the line memory 23a is applied to the multiplication circuit 25 and the line memory 23.
b. The line memory 23b delays the input digital video signal by one line and outputs the digital video signal, like the line memory 23a. The output of the line memory 23b is input to the multiplication circuit 24b.

The digital video signals input to the multiplication circuits 24a and 24b are multiplied by 0.25 and output. (Specifically, the data is output after being shifted by 2 bits.)
The digital video signal input to the multiplication circuit 25 is multiplied by 0.5 and output. (Specifically, the data is shifted by 1 bit and output.) Multiplier circuits 24a, 24
4b and the output of the multiplication circuit 25 are added by the addition circuit 26, the high frequency component in the vertical direction is removed, and the result is output to the frame memory 7 via the output terminal 22. The frequency characteristics of the first VLPF 6 are shown in FIG. The line memories 23 a and 23 b are connected to the first terminal via the input terminal 21.
Based on the data write control signal and the data read control signal output from the memory control circuit 8, the writing and reading of the digital video signal into the memory are controlled.

The digital video signal from which the vertical high frequency components have been removed by the first VLPFs 6a to 6c is the frame memory 7a.
To 7c. The operation of writing the digital video signal in the frame memory 7 will be described below.
The first memory control circuit 8 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal at a field frequency of 60 Hz. Specifically, when writing to the frame memory 7, a digital video signal input in a frame structure is converted into a field structure and written.

Hereinafter, a method of generating a data write control signal to the frame memory 7 output from the first memory control circuit 8 will be described. First, when a vertical synchronization signal is input from the first synchronization detection circuit 4, the first memory control circuit 8 sets a field of a digital video signal to be written to the frame memory 7 next. When the field setting result is the first field, a control signal for writing only odd lines to the frame memory 7 is generated, and when the field setting result is the second field, a control signal for writing only even lines to the frame memory 7 is generated. Occur. In addition,
The control is performed by discriminating the even / odd lines by using the horizontal sync signal output from the first sync detection circuit 4. At this time, in the conventional example, the frame memory 7 is connected to the VGA.
Control is performed so that only the effective video signal portion of the signal is written.

The non-interlaced digital video signal input to the frame memories 7a to 7c is a field structure digital video signal (interlaced structure digital video signal) based on the write control signal output from the first memory control circuit 8. And are stored in the frame memories 7a to 7c. In this conventional example, the frame memory 7 is composed of two field memories for the first field and the second field. Therefore, when writing the non-interlaced digital video signal into the frame memory 7, the field memory used is switched for each field. At this time, the field memory switching control signal is also output from the first memory control circuit 8 based on the field determination result.

On the other hand, the T input through the input terminal 16
The V-side sync signal is detected by the second sync detection circuit 12 as a vertical sync signal and a horizontal sync signal. At this time, the field discrimination is also performed by the second synchronization detection circuit 12.
The second PLL circuit 11 generates a reference clock on the television side with reference to the horizontal sync signal detected by the second sync detection circuit 12. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the first memory control circuit 8. The vertical sync signal, the horizontal sync signal, and the field determination result detected by the second sync detection circuit 12 are also input to the first memory control circuit 8.

In the first memory control circuit 8, a read control signal for reading the interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal on the television side and the field discrimination result. (Field switching signal, data read address, read control signal, etc.) are generated. The frame memories 7a to 7c output interlace-structured digital video signals based on the read control signal output from the first memory control circuit 8.

The interlaced structure digital video signals read from the frame memories 7a to 7c are input to the D / A conversion circuits 9a to 9c. D / A conversion circuit 9a-
At 9c, the input digital video signal having an interlaced structure is converted into an analog video signal having an interlaced structure. R output from the D / A conversion circuits 9a to 9c,
The G and B signals are the Y signal and two color difference signals (R-Y signal and B-Y signal) in the matrix circuit 10.
Is converted to The Y signal output from the matrix circuit 10 is output through the output terminal 15a after the vertical synchronization signal and the horizontal synchronization signal are added by the synchronization adding circuit 13. The synchronization adding circuit 13 is the second synchronization detecting circuit 12
A sync signal is generated and added to the Y signal on the basis of the vertical sync signal, the horizontal sync signal, and the field discrimination result output from the above.

Further, the two color difference signals (RY signal and BY signal) are converted into a modulated color signal (C signal) by the chroma encoder circuit 14 and output through the output terminal 15b. The second synchronization detection circuit 12 is used for chroma encoding (when converting two color difference signals into modulated color signals).
The two color difference signals are modulated based on the vertical synchronization signal, the horizontal synchronization signal, and the field discrimination result output from the above. The modulated color signal (C signal) subjected to the modulation is output terminal 1
It is output via 5b.

[0024]

Since the conventional scanning line conversion apparatus is configured as described above, the flicker that occurs when converting a non-interlaced image to an interlaced image can be removed, but the frequency band in the vertical direction is reduced. The vertical resolution is reduced due to the limitation. In other words, the flicker component removed by the conventional scanning line conversion device includes the vertical resolution component, and the vertical resolution is reduced by simply limiting the vertical band, and particularly fine characters on the display can be read. There are problems such as not being.

Further, as described above, when converting a non-interlaced image into an interlaced image, a reduction in resolution cannot be avoided. Therefore, when trying to read fine characters, the enlargement function is required. Conventionally, as the method of the enlargement function, a method of simply interpolating the average value of the video signal of the second field by using the video signals of the two adjacent upper and lower lines in the first field, or the video signal of the second field as the first Techniques such as interpolation with the same video signal as the field have been adopted. However, in the case of enlargement in which the video signal of the second field is interpolated from the video signals of the upper and lower two lines adjacent to each other in the first field by the average value interpolation, the video signal of the first field is the original signal itself, which is clear. In contrast to the video, the video signal of the second field is a blurry video compared to the video of the first field because the video signal of the second field is an average value interpolation of the upper and lower two lines of the video signal of the first field. Therefore, when the first field image and the second field image created as described above are displayed as an interlaced image, it looks as if the entire screen is flicker, which is visually unsightly. Further, when the video signal of the second field is interpolated with the same video signal as the video signal of the first field, there is no difference in clarity of the image between the first field video and the second field video, There is a problem that flicker occurs at the edge of the image.

The present invention has been made in order to solve the above problems, and visually reduces flicker, suppresses a decrease in resolution in the vertical direction, and incorporates a unique enlargement function on the display. It is an object of the present invention to obtain a scanning line conversion device which can read fine characters and the like.

[0027]

In a scanning line conversion apparatus according to the present invention, a scanning line conversion apparatus for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units is used. First frequency separating means for separating a vertical high band component and a vertical low band component of the interlaced image, and a vertical high band-horizontal high band component and a vertical high band-horizontal low band from the vertical high band component of the non-interlaced image. Second frequency separating means for separating the component, first direct current detecting means for detecting the horizontal direct current component of the input non-interlaced image, and the vertical direction based on the output of the first direct current detecting means. A first amplitude converting means for converting the amplitude of the high frequency-horizontal low frequency component, a vertical low frequency component separated by the first frequency separating means and the second frequency separation A vertical high-range / horizontal high-range component and an adding means for adding the output of the first amplitude converting means, wherein the first amplitude converting means includes the vertical high-range / horizontal low-range component. When the direct current is detected by the first direct current detecting means when converting the amplitude of the above, at least the inverse characteristic of the vertical high-frequency / horizontal low-frequency component is given and output, and the adding means is added. It is configured to generate a 1-field unit interlaced image by thinning out a predetermined line from the 1-frame unit non-interlaced image output.

Further, in a scanning line conversion device for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, a vertical high frequency component and a vertical low frequency component of the input non-interlaced image are separated. First frequency separating means, first direct current detecting means for detecting a direct current component in the horizontal direction of the input non-interlaced image, and the vertical high frequency component of the vertical high frequency component based on the output of the first direct current detecting means. A second amplitude converting means for converting the amplitude; and an adding means for adding the vertical low-frequency component separated by the first frequency separating means and the output of the second amplitude converting means. When converting the amplitude of the vertical high-frequency component by the amplitude conversion means, at least an inverse characteristic of the vertical high-frequency component is given when direct current is detected by the first direct-current detection means. Together configured to force, but be configured to generate an interlaced image of one field unit by thinning out predetermined line from non-interlaced image of one frame which is outputted from said adding means.

When detecting the horizontal DC component of the input non-interlaced image, the amplitude of the vertical high frequency-horizontal high frequency component separated by the second frequency separating means is compared with a predetermined value, The first DC detecting means is controlled so as to detect the DC component when the amplitude is less than a predetermined value.

Further, in a scanning line conversion device for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, screen enlargement position information generating means for generating screen enlargement position information when the screen is enlarged, Vertical direction interpolation means for interpolating pixels in the vertical direction based on the screen vertical expansion position information output from the screen expansion position information generating means, and horizontal direction based on the screen horizontal expansion position information output from the screen expansion position information generating means. Fields for forming an interlaced image in 1-field units by thinning a predetermined line from the non-interlaced image in 1-frame units in which the pixels in the vertical direction are interpolated by at least the vertical-direction interpolating means. It has an image generation means, and the vertical direction is calculated by the vertical direction interpolation means. When interpolating the pixel, on adjacent, or after the interpolation by the pixel below, and constitutes to remove limits the band of the vertical flicker component.

Further, the horizontal interpolation means for interpolating pixels in the horizontal direction based on the screen horizontal expansion position information output from the screen expansion position information generating means is arranged at the subsequent stage of the field image generating means. Is.

Further, when the vertical interpolation means interpolates the pixels in the vertical direction based on the screen vertical enlargement position information output from the screen enlargement position information generating means, after interpolating the adjacent upper or lower pixels. The flicker removal is performed by limiting the band in the vertical direction only for the luminance signal, and the flicker removal is not performed for the color difference signal.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION In a scanning line conversion apparatus according to an embodiment of the present invention, when a non-interlaced image input in 1-frame units is converted into an interlaced image in 1-field units, first frequency separation is performed. The vertical high frequency component and the vertical low frequency component of the non-interlaced image input by the means are separated. Next, the second high frequency component separates the vertical high band-horizontal high band component and the vertical high band-horizontal low band component from the separated vertical high band component. Further, the first DC component detecting means detects the horizontal DC component from the input non-interlaced image. Based on the DC component detection information, the first amplitude converting means switches the amplitude conversion characteristic applied to the vertical high band-horizontal low band component. When converting the amplitude of the vertical high-range / horizontal low-range component in the first amplitude converting means, at least the inverse characteristic of the vertical high-range / horizontal low-range component is detected when direct current is detected by the direct-current detecting means. And output. Then, the vertical low-frequency component separated by the first frequency separation means, the vertical high-horizontal high-frequency component separated by the second frequency separation means, and the first
The outputs of the amplitude conversion means are added. An interlaced image in 1-field units is generated by thinning a predetermined line from the non-interlaced image in 1-frame units in which the added flicker component is removed.

When converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, first, the vertical high-frequency component and the vertical low-frequency component of the non-interlaced image input by the first frequency separation means are converted. Separate the components. Next, the first DC detecting means detects the horizontal DC component of the input non-interlaced image. Based on the output of the first DC detecting means, the second amplitude converting means switches the amplitude converting characteristic applied to the vertical high frequency component. When converting the amplitude of the vertical high frequency component in the second amplitude converting means, at least an inverse characteristic of the vertical high frequency component is given and output when direct current is detected by the direct current detecting means. Then, the vertical low frequency component separated by the first frequency separating means and the output of the second amplitude converting means are added. An interlaced image in 1-field units is generated by thinning out predetermined lines from the non-interlaced image in 1-frame units output from the adding means.

Further, when the horizontal DC component of the input non-interlaced image is detected, the amplitude of the vertical high band-horizontal high band component separated by the second frequency separating means is compared with a predetermined value. . The first DC detecting means determines that the horizontal DC component is detected when the amplitude is less than a predetermined value.

When converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, screen enlargement position information generating means generates screen enlargement position information when the screen is enlarged. Based on the screen vertical expansion position information output from the screen expansion position information generating means, the vertical direction interpolation means interpolates pixels in the vertical direction. Further, the horizontal direction interpolation means interpolates the pixels in the horizontal direction based on the screen horizontal enlargement position information output from the screen enlargement position information generation means. Then, at least in the vertical direction interpolation means, a predetermined line is thinned out from the non-interlaced image of one frame unit in which the pixels in the vertical direction are interpolated to form an interlaced image of one field unit. When the vertical direction interpolation means interpolates the vertical direction pixel, after interpolating the adjacent upper or lower pixel, the vertical direction band is limited to remove the flicker component and output.

Further, after converting a non-interlaced image in 1-frame units into an interlaced image in 1-field units, horizontal pixels are interpolated based on the screen horizontal enlargement position information output from the screen enlargement position information generating means. .

Further, when the vertical direction interpolation means interpolates a pixel in the vertical direction based on the screen vertical enlargement position information output from the screen enlargement position information generation means, the interpolation pixel is formed by the adjacent upper or lower pixel. To generate. After that, flicker removal is performed by limiting the vertical band only for the luminance signal.

The present invention will be specifically described below with reference to the drawings showing the embodiments thereof. Embodiment 1 FIG. 1 is a block diagram of a scanning line conversion apparatus according to a first embodiment of the present invention. In the first embodiment as well, the signal based on the VGA standard is converted into the N
A case of converting to a TSC standard image will be described. In the figure, 1a to 1c are input terminals for VGA signals (R, G, and B signals based on the VGA standard), 2 are input terminals for synchronizing signals of VGA signals, and 3a to 3c are matrix circuits 10.
A / D conversion circuit for converting a luminance signal (Y signal) and an analog video signal converted into two color difference signals into a digital video signal by 4 is a VGA input from an input terminal 2.
A first synchronization detection circuit 5 for detecting a vertical synchronization signal and a horizontal synchronization signal from the synchronization signal of the signal, and a first PLL 5 for generating a clock based on the synchronization signal output from the first synchronization detection circuit 4. Circuits 7a to 7c are luminance signals (Y signals) output from the first flicker removing circuit 31, A /
It is a frame memory that stores two color difference signals (R-Y signal and B-Y signal) output from the D conversion circuits 3b and 3c.

Reference numerals 9a to 9c are D / A conversion circuits for converting the digital video signals output from the frame memories 7a to 7c into analog video signals. Two color difference signals (RY
Signal, and a matrix circuit for converting into a BY signal),
Reference numeral 11 is a second PLL that generates a clock based on the TV-side synchronization signal output from the second synchronization detection circuit 12.
The second circuit 12 detects a vertical synchronizing signal, a horizontal synchronizing signal, etc. from the TV side synchronizing signal inputted from the input terminal 16.
It is a synchronization detection circuit.

Reference numeral 13 is a synchronization addition circuit for adding a vertical synchronization signal and a horizontal synchronization signal to the Y signal output from the D / A conversion circuit 9a, and 14 is a color difference between the two colors output from the D / A conversion circuits 9b and 9c. Chroma encoder circuit for converting signals (RY signals and BY signals) into modulated color signals (C signals), 15a and 15b are output terminals for Y signals and C signals, and 16 is an input terminal for synchronization signals Is.

Reference numerals 30a and 30b denote band limiting filters (hereinafter referred to as LPFs) for limiting the horizontal signal bands of the RY and BY signals output from the matrix circuit 10, and 31 is input. A first flicker removing circuit for removing a flicker component in the Y signal, 32 is a line memory 23a, 23b in the first flicker removing circuit 31,
The line memory 43 and the frame memories 7a to 7
It is a second memory control circuit for writing a digital video signal to c and outputting a read control signal.

FIG. 2 is a block diagram of the first flicker removing circuit 31 in FIG. In the figure, 6 is a first VLPF for extracting a vertical low-frequency component of a digital video signal (Y signal), 40 is a Y signal input terminal, and 41 is a memory control signal output from the second memory control circuit 32. Input terminal, 42 is output terminal of Y signal, 43 is input Y
A line memory delays the signal by one line, and a subtraction circuit 44 subtracts the vertical low-frequency component output from the first VLPF 6 from the one-line delayed Y signal output from the line memory 43. The vertical high frequency component of the Y signal is separated by subtracting the output of the first VLPF 6 from the output of the line memory 43. 46 and 51 are registers,
Reference numerals 50 and 52 are addition circuits, 47 is a subtraction circuit, and 49 is a limiter. Reference numeral 48 is a first DC detection circuit (hereinafter, referred to as a first DC detection circuit) that detects a DC component in the horizontal direction from the input vertical high frequency-horizontal high frequency component, and 45 is a Y signal. It is a first horizontal low-pass filter (hereinafter, referred to as a first HLPF) for extracting the vertical high-frequency-horizontal low-pass component of the above.

FIG. 3 is a block diagram of the first HLPF 45 in FIG. In the figure, reference numeral 60 denotes an input terminal for a vertical high frequency component of a digital video signal (Y signal), and 61.
Is an output terminal for the vertical high-range / horizontal low-range components of the Y signal, 62
a and 62b are the vertical high frequency components of the input Y signal
Clock delay registers 63a and 63b are multiplier circuits for multiplying the input vertical high-frequency component of the Y signal by 0.25, and 64 is a multiplier for multiplying the vertical high-frequency component of the input Y signal by 0.5. A multiplication circuit, and 65 is an addition circuit. FIG. 4 is a diagram for explaining the operation of the scanning line conversion apparatus according to the first embodiment of the present invention. The figure shows the characteristics (frequency spectrum) on the two-dimensional frequency of the first embodiment. In the figure, the horizontal axis represents the horizontal spatial frequency,
The vertical axis represents the spatial frequency in the vertical direction.

The concept of the first embodiment will be briefly described below. As described in the conventional example, the vertical high-frequency component shown by hatching in FIG. 20 includes the resolution component in the vertical direction in addition to the flicker component. In the conventional scanning line conversion apparatus, in order to remove the flicker component, all vertical high frequency components including the resolution component in the vertical direction are removed. As a result, the resolution in the vertical direction is lowered, and there is a problem in that it is difficult to read small characters on the display.

In general, flicker generated in a large area is visually more noticeable than flicker generated in a small area. That is, flicker occurring in a fine character portion or the like is not visually noticeable, whereas flicker occurring in a horizontal line portion of a figure or a table is visually noticeable.
When human eyes visually detect flicker, it is detected that flicker has occurred up to an image around the flicker, and it appears that flicker has occurred in a large area. The flicker also depends on the amplitude of the vertical high frequency component in addition to the flicker generation area. In other words, the small amplitude component of the vertical high-frequency component is not so visually noticeable even if flicker occurs, while the large amplitude component is visually very noticeable.

In the first embodiment, the vertical high frequency component-horizontal high frequency component, in which the flicker is visually inconspicuous, is separated from the vertical high frequency component which causes the large area flicker. Then, the vertical resolution is improved by adding the separated vertical high frequency-horizontal high frequency component to the image from which the vertical high frequency component has been removed. Further, as described above, the flicker component of small amplitude is not so noticeable visually, so the limiter 4
9 extracts only a small amplitude component in which flicker is inconspicuous from the vertical high frequency-horizontal low frequency component containing a large amount of flicker component,
The vertical resolution can be further improved by feeding back (adding) to the output image. Further, in the first embodiment, the first DC detection circuit 48 detects the horizontal DC component from the vertical high-range / horizontal high-range components, and determines the limiter shape (characteristic) of the limiter 49 depending on whether or not the DC component is detected. ) Is adjusted to adjust the feedback amount of the vertical high band-horizontal low band component to the output image, so that the flicker component that cannot be completely removed by the conventional scanning line conversion apparatus can be removed.

In the first embodiment, since the vertical resolution component in which flicker is visually inconspicuous is added to the output image by the above operation, the occurrence of flicker can be suppressed and the vertical resolution in the fine character portion can be improved. Even small characters can be recognized. FIG. 4 shows frequency characteristics on the two-dimensional frequency of the first embodiment. The shaded portion in the figure is the above vertical high frequency-horizontal low frequency component.

The operation of the scanning line conversion apparatus according to the first embodiment will be described below with reference to FIGS. 1 to 4 and 22. It should be noted that in the first embodiment also, as in the conventional example, the VGA is used.
A case will be described in which a non-interlaced image input based on the standard is converted into an interlaced image and output. The R, G, and B signals input via the input terminals 1a to 1c are the Y signal and the 2 signal in the matrix circuit 10.
It is converted into one color difference signal (RY signal and BY signal). The two color difference signals (the RY signal and the BY signal) output from the matrix circuit 10 are the LPF 30.
A and 30b limit the horizontal band to half. (Note that the color difference signal is visually inconspicuous as compared with the luminance signal (Y signal), so even if the signal band is limited to half, the image quality is hardly deteriorated.) The Y signal output from the matrix circuit 10 and the LPFs 30a and 30b. Output from R-
The Y and BY signals are converted into digital video signals (digital signals) by the A / D conversion circuits 3a to 3c. At this time, the signal band of the two color difference signals is L as described above.
Since it is limited to half of the Y signal at PFs 30a and 30b,
It is assumed that the sampling clock at the time of A / D conversion is set to half the sampling clock of the Y signal to convert it into a digital video signal.

On the other hand, VG input through the input terminal 2
The first synchronization detection circuit 4 detects a vertical synchronization signal and a horizontal synchronization signal of the A signal synchronization signal. The horizontal synchronization signal detected by the first synchronization detection circuit 4 is supplied to the first PLL circuit 5
Is input to The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronizing signal. The clock generated in the first PLL circuit 5 is the A / D conversion circuits 3a to 3c and the first flicker removing circuit 3
It is input to the first and second memory control circuits 32. At that time, as described above, the clock used for processing the two color difference signals is frequency-divided to half the frequency of the clock used for processing the Y signal and output. The vertical sync signal and the horizontal sync signal detected by the first sync detection circuit 4 are also input to the second memory control circuit 32.

In the second memory control circuit 32, the line memory 2 in the first flicker removing circuit 31 is used by using the horizontal sync signal of the VGA signal output from the first sync detection circuit 4.
3a, 23b, and a write control signal and a read control signal for the digital video signal to the line memory 43 are generated. For example, the line memories 23a, 23
b and the line memory 43 in the FIFO as in the conventional example.
In the case of using a memory, the second memory control circuit 32 outputs a line address reset signal at the time of writing and reading, a writing and reading enable signal (EN
ABL signal), and write and read clock signals are output. In addition, the second memory control circuit 32
Then, by using the vertical synchronizing signal and the horizontal synchronizing signal output from the first synchronization detecting circuit 4, the frame memories 7a ...
A writing control signal of a digital video signal to 7c is also generated. The specific control method of the frame memories 7a to 7c will be described later.

The Y signal converted into the digital video signal by the A / D conversion circuit 3a is input to the first flicker removing circuit 31. Hereinafter, the operation of the first flicker removing circuit 31 will be described with reference to FIG. The Y signal input via the input terminal 40 is supplied to the first VLPF 6 and the line memory 43.
Is input to The operation of the first VLPF 6 will be described with reference to FIG. The Y signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input Y signal by one line and outputs it. The Y signal output from the line memory 23a is input to the multiplication circuit 25 and the line memory 23b. In the line memory 23b, the line memory 23
Similarly to a, the input Y signal is delayed by one line and output. The output of the line memory 23b is input to the multiplication circuit 24b. The line memories 23a and 23b are controlled using the data write and read control signals output from the second memory control circuit 32 via the input terminal 21.

The Y signal input to the multiplication circuits 24a and 24b is multiplied by 0.25 and output. Also, the multiplication circuit 2
The Y signal input to 5 is multiplied by 0.5 and output.
The outputs of the multiplying circuits 24a and 24b and the multiplying circuit 25 are added by the adding circuit 26, the vertical high frequency components are removed, and the output is output from the first VLPF 6 via the output terminal 22. On the other hand, the Y signal input to the line memory 43 is delayed by one line and output. The line memory 43 is controlled using the data write and read control signals output from the second memory control circuit 32 via the input terminal 41.

In the subtraction circuit 44, the first VLPF is output from the Y signal delayed by one line output from the line memory 43.
By subtracting the vertical low-frequency component of the Y signal output from 6, the vertical high-frequency component of the Y signal is separated. (In the line memory 43, the input Y signal and the first VLPF 6
The Y signal is delayed by one line in order to match the phase (group delay) with the vertical low-frequency component that is output. ) Subtraction circuit 44
Is output to the first HLPF 45 and the register 46. The operation of the first HLPF 45 will be described below with reference to FIG.

The vertical high frequency component of the Y signal input through the input terminal 60 is stored in the register 62a and the multiplication circuit 6.
3a. The vertical high frequency component of the Y signal delayed by one clock in the register 62a is input to the register 62b and the multiplication circuit 64. In addition, 1 in register 62b
The vertical high frequency component of the clock-delayed Y signal is multiplied by the multiplication circuit 6.
It is input to 3b. The vertical high frequency components of the Y signal input to the multiplication circuits 63a and 63b are multiplied by 0.25 and output. Similarly, the vertical high frequency component of the Y signal input to the multiplication circuit 64 is multiplied by 0.5 and output. Multiplication circuit 6
The outputs of 3a, 63b, and 64 are added by an adder circuit 65 to remove the horizontal high-frequency component (vertical high-frequency component of Y signal-horizontal high-frequency component) and output via the output terminal 61. The registers 62a and 62b in the first HLPF 45,
A clock is supplied from the first PLL circuit 5 to the registers 46 and 51 in the flicker removing circuit 31.

The vertical high band-horizontal low band components of the Y signal separated by the first HLPF 45 are input to the limiter circuit 49 and the subtraction circuit 47. Subtraction circuit 47
Then, the vertical high frequency component-horizontal low frequency component of the Y signal output from the first HLPF 45 is subtracted from the vertical high frequency component of the Y signal delayed by one clock in the register 46 to obtain the vertical high frequency component of the Y signal- Outputs horizontal high frequency components. (In the register 46, the vertical high-frequency component of the Y signal and the first HLPF 45
The vertical high frequency component of the Y signal is delayed by one clock in order to match the phase with the vertical high frequency component-horizontal low frequency component of the output Y signal. ) The output of the subtraction circuit 47 is input to the first DC detection circuit 48 and the addition circuit 50.

In the first DC detection circuit 48, the subtraction circuit 4
The horizontal direct current component (DC component) of the Y signal is detected from the vertical high frequency component-horizontal high frequency component of the Y signal output from 7.
The operation of the first DC detection circuit 48 according to the first embodiment will be briefly described below. First DC detection circuit 48
First, the vertical DC component in the horizontal direction is detected by comparing the vertical high frequency component-horizontal high frequency component of the input Y signal with a predetermined value. Specifically, the amplitude of the vertical high band-horizontal high band component of the input Y signal is set to YHH.
Then, for example, when YHH ≦ a and YHH ≧ −a, it is determined that the DC component is detected. (A is a positive real number)
As a result of performing simulation with a set to about 3, good results were obtained. (Note that the simulation was performed with the amplitude of YHH being -127 or more and 128 or less.)

The limiter 49 limits the amplitude of the vertical high band-horizontal low band component of the input Y signal and outputs it. 6 and 7 show an example of the input / output characteristics of the limiter 49. As shown in FIGS. 6 and 7, the limiter 49 switches the limiter shape (characteristic) based on the DC detection information output from the first DC detection circuit 48. Specifically, when the direct-current component is detected by the first DC detection circuit 48, in the first embodiment, the limiter having the characteristics shown in FIG. 6 is used to further reduce the flicker component in the Y signal. The details will be described later. When the DC component is not detected, in the first embodiment, the limiter having the characteristics shown in FIG. 7 limits and outputs the amplitude value of the vertical high band-horizontal low band component of the Y signal. The output of the limiter 49 is input to the adder circuit 50. The adder circuit 50 adds the output of the limiter 49 and the output of the subtractor circuit 47. The output of the adder circuit 50 is input to the adder circuit 52. The adder circuit 52 adds the output of the register 51 and the output of the adder circuit 50. Hereinafter, the limiter 4 having the characteristics shown in FIG. 6 and FIG.
9 will be described with reference to FIGS. 5, 8 and 9.

FIG. 5 is a diagram showing the residual flicker component contained in the first VLPF output signal. The hatched portion in the figure is the residual flicker component. As described above, the flicker that occurs in a large area is significantly more visible than the flicker that occurs in a small area. In other words, while flicker that occurs in small text parts is not very noticeable visually,
Flicker that occurs in a horizontal line portion of a figure or a table is very noticeable visually. The flicker also depends on the amplitude of the vertical high frequency component in addition to the flicker generation area. That is, even though flicker occurs in the small high-frequency component of the vertical high-frequency component, the user is not very visually concerned about the large-amplitude component.

Therefore, in the first embodiment, the residual flicker component is suppressed by switching the shape (characteristic) of the limiter 49 in accordance with the amplitude of the vertical high band-horizontal high band component of the input Y signal. Hereinafter, FIG. 8 and FIG.
The effect of the limiter 49 will be described with reference to. FIG. 8 is a diagram for explaining the operation of the limiter 49 when a Y signal having a DC component in the horizontal direction and a high-frequency component with a large amplitude in the vertical direction is input as seen in the horizontal line portion of the table. . FIG. 9 is a diagram for explaining the operation of the limiter 49 when a Y signal having no direct current component in the horizontal direction, which is seen in fine characters on the display, is input.

The operation of the limiter 49 when a Y signal having a large amplitude component in the vertical direction including a direct current component in the horizontal direction is input will be described below with reference to FIG. Y in FIG.
The input waveform of the signal, the output of the first VLPF 6, and the first
The output of the flicker removing circuit 31 is shown. The output of the subtraction circuit 44 is shown in FIG. The output of the limiter 49 is shown in FIG. The first flicker removing circuit 31 shown in FIG.
When a step waveform in the vertical direction as shown in (1) is input, the first VLPF 6 removes the vertical high frequency component. that time,
Since the Y signal input as described above is a DC component in the horizontal direction and a step waveform having a high-frequency component with a large amplitude in the vertical direction, it is caused by the residual flicker component (see FIG. 5) at the rising portion of the step. Flicker occurs. (As mentioned above, large-amplitude flicker is visually annoying.)

FIG. 6B shows the output waveform of the vertical high frequency component separated by the first VLPF 6. In the first flicker removing circuit 31 of the first embodiment, when the Y signal containing the horizontal DC component as described above is input, the limiter 49 selects the limiter shape as shown in FIG. A limiter 49 having a limiter shape as shown in FIG.
When the vertical high frequency component shown in FIG. 2 is input, an output as shown in FIG. By adding the output of the limiter 49 to the vertical low frequency components by the adding circuits 50 and 52, the rising edge becomes smoother than the output of the first VLPF 6. As a result, the residual flicker component can be completely removed visually. That is, by inputting the vertical high frequency component of the Y signal containing the horizontal DC component to the limiter 49 having the inverse characteristic as shown in FIG. 6, and adding the output to the vertical low frequency component of the Y signal, Since the flicker component that cannot be completely removed by the first VLPF 6 can be removed almost completely, a good image can be obtained.

On the other hand, the operation of the limiter 49 when a Y signal containing no horizontal DC component is input will be described with reference to FIG. FIG. 9A shows the input waveform of the Y signal, the first VL.
The output of the PF 6 and the output of the first flicker removing circuit 31 are shown. The output of the subtraction circuit 44 is shown in FIG. The output of the limiter 49 is shown in FIG. When a vertical step waveform as shown in FIG. 9A is input to the first flicker removing circuit 31, the first high frequency component is removed by the first VLPF 6. At that time, the above-mentioned residual flicker component is generated at the rising portion of the step as described above, but since the direct current component is not included in the horizontal direction as described above, the flicker is not visually noticeable.

FIG. 7B shows the output waveform of the vertical high frequency component separated by the first VLPF 6. In the first flicker removing circuit 31 of the first embodiment, the limiter 4 is activated when the Y signal that does not include the DC component is input in the horizontal direction as described above.
For 9, the limiter shape as shown in FIG. 7 is selected. Figure 7
The limiter 49 having a limiter shape as shown in FIG.
When the vertical high frequency component shown in (b) is input, an output as shown in (c) of the figure is obtained. The limiter 49
Of the first VLP as shown in (a) of FIG.
A sharper rising edge than the output of F6 is obtained. As a result, the resolution in the vertical direction is improved. That is, the vertical high frequency component of the Y signal that does not include the direct current component in the horizontal direction is input to the limiter 49 having the characteristics shown in FIG. 7, and its output is added to the vertical low frequency component of the Y signal to obtain Since the resolution in the direction can be improved, finer characters can be identified.

The Y signal from which the flicker component has been removed by the first flicker removing circuit 31 and the A / D conversion circuits 3b, 3
The two color difference signals (R-Y signal and BY signal) output from c are input to the frame memories 7a to 7c. The operation of writing the digital video signal in the frame memory 7 will be described below. The second memory control circuit 32 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal at a field frequency of 60 Hz. Specifically, when writing to the frame memory 7, a digital video signal input in a frame structure is converted into a field structure and written.

A method of generating a data write control signal for the frame memory 7 output from the second memory control circuit 32 will be described below. First, when the vertical synchronization signal is input from the first synchronization detection circuit 4, the second memory control circuit 32 next sets the field to be written in the frame memory 7. When the field setting result is the first field, a control signal for writing odd lines to the frame memory 7 is generated, and when the field setting result is the second field, a control signal for writing even lines to the frame memory 7 is generated. . In the control, the even / odd lines are discriminated using the horizontal sync signal output from the first sync detection circuit 4 to generate the control signal. At this time, in the first embodiment, the frame memory 7 is used as in the case of the conventional example.
Is controlled so that only the effective video signal portion of the VGA signal is written.

The non-interlaced digital video signal input to the frame memories 7a to 7c is a field structure digital video signal (interlaced structure digital video signal) based on the write control signal output from the second memory control circuit 32. And are stored in the frame memories 7a to 7c. In addition, the first embodiment
In this case, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field as in the conventional example. Therefore, the second memory control circuit 32 generates a switching control signal for switching the two field memories based on the field determination result in order to write the digital video signal converted into the interlaced structure into the frame memory 7. Specifically, the data of the odd lines is written to the field memory for the first field, and the data of the even lines is written to the field memory of the second field. Further, in the second memory control circuit 32, a vertical control signal for detecting a data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 is detected by the first synchronization detection circuit 4. It is generated based on the sync signal and the horizontal sync signal.

On the other hand, T input through the input terminal 16
The V-side sync signal is detected by the second sync detection circuit 12 as a vertical sync signal and a horizontal sync signal. At this time, the field discrimination is also performed by the second synchronization detection circuit 12.
The second PLL circuit 11 generates a reference clock on the television side with reference to the horizontal sync signal detected by the second sync detection circuit 12. At this time, the frequency of the sampling clock of the color difference signal is divided into half the frequency of the sampling clock of the Y signal. The clock generated in the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the second memory control circuit 32. The vertical sync signal, the horizontal sync signal, and the field determination result detected by the second sync detection circuit 12 are also input to the second memory control circuit 32.

The second memory control circuit 32 reads the interlaced image stored in the frame memory 7 on the basis of the vertical synchronizing signal, the horizontal synchronizing signal, and the field discrimination result (a reading control signal (the above field). Memory switching signals, data read addresses, read control signals, etc.). The frame memories 7a to 7c output interlaced digital video signals based on the read control signal output from the second memory control circuit 32.

The interlaced digital video signals read from the frame memories 7a to 7c are input to the D / A conversion circuits 9a to 9c. D / A conversion circuit 9a-
At 9c, the input digital video signal having an interlaced structure is converted into an analog video signal having an interlaced structure. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronization signal and the horizontal synchronization signal are added by the synchronization adding circuit 13. The synchronizing circuit 13 generates a synchronizing signal based on the vertical synchronizing signal, the horizontal synchronizing signal, and the result of the field discrimination output from the second synchronizing detecting circuit 12, and adds it to the Y signal.

The two color difference signals (RY signal and BY signal) output from the D / A conversion circuits 9b and 9c are converted into modulated color signals (C signals) by the chroma encoder circuit 14 and output. It is output via the terminal 15b. During chroma encoding (when converting two color difference signals into modulated color signals), two color difference signals are output based on the vertical sync signal, the horizontal sync signal, and the field discrimination result output from the second sync detection circuit 12. Modulate the signal.

In the first embodiment, the VGA signal input in the state of the R, G, and B signals is previously input in the matrix circuit 10 as the Y signal and the two color difference signals (RY signal and BY signal). Signal) and then signal processing is performed. This is for two reasons.

One is due to the flicker detection characteristics of the human eye. This is because human vision is very sensitive to flicker generated in the Y signal, but is not very sensitive to flicker generated in the color difference signal. As a result of performing flicker removal on the two color difference signals by computer simulation based on the above algorithm, almost no effect was found in flicker removal as compared with the case where flicker removal was not performed. On the other hand, in the image from which the flicker has been removed, the vertical resolution of the color difference signal is noticeably reduced.

As for the image (video) input in the state of the R, G, and B signals, as shown in the conventional example, the flicker removal is not performed on all the image data of the R, G, and B signals. Top Detectable flicker cannot be removed. Therefore, in the first embodiment, the input image data (R,
G and B signals) in the matrix circuit 10 as Y signals, and two color difference signals (RY signals and BY signals).
After the conversion, the flicker removing circuit 31 is provided only in the signal processing system of the Y signal to remove the flicker component. As a result, since flicker removal is not performed for the color difference signal in which the flicker component is visually inconspicuous, the number of flicker removal circuits 31 can be reduced from three to one as compared with the conventional scanning line conversion device. Further, since the flicker is not removed for the color difference signal in which the flicker is inconspicuous, it is possible to sufficiently secure the resolution component in the vertical direction and minimize the decrease in the resolution of the output image.

The second is due to the visual characteristics of the human color difference signal. This is because human vision is sensitive to changes in the Y signal, but is not very sensitive to changes in the color difference signals. That is, even if the horizontal signal band of the two color difference signals (RY signal and BY signal) is half of the Y signal, the difference (color signal band difference) is detected by human eyes. Can not do. Therefore, in the first embodiment, the two color difference signals output from the matrix circuit 10 are limited in half to the horizontal signal band by using the LPFs 30a and 30b. And LPF
The two color difference signals output from 30a and 30b are A / D
The frequency of the sampling clock when converting into a digital video signal (digital signal) by the conversion circuits 3b and 3c is half the frequency of the sampling clock of the Y signal.
Therefore, the number of data of color difference signals per frame can be halved as compared with the conventional example, so that the memory capacity of the frame memories 7b and 7c can be halved and the circuit scale can be reduced. is there. Further, since the clock frequency of the processing system of the two color difference signals can be halved, there is an effect that power consumption can be suppressed when the scanning line conversion device or the flicker removing circuit 31 is formed into an LSI.

As described above, the scanning line conversion apparatus according to the first embodiment extracts the vertical high frequency component-horizontal high frequency component from which the flicker is visually inconspicuous from the vertical high frequency component and outputs the original signal (output image).
In addition to the feedback, the vertical high-range / horizontal low-range components including the noticeable flicker component are also suppressed and fed back by the limiter in which the limiter shape (characteristic) is switched based on the DC detection information. Therefore, flicker that is visually noticeable can be sufficiently suppressed and the vertical resolution can be improved. Therefore, it is possible to reduce flicker that occurs in the horizontal line portion of the table and the like, and it is also possible to recognize fine characters and the like on the display. As a result of confirming the effect of the scanning line conversion method by computer simulation, the resolution in the vertical direction was improved and the identification of fine characters was also improved as compared with the conventional example. In addition, the flicker that occurs in the horizontal line portion of the table can be almost completely removed by adopting the scanning line conversion method.

Further, the first flicker removing circuit 31 shown in the first embodiment can be realized by simply adding a simple circuit to the conventional first VLPF 6, and without significantly increasing the circuit scale. There is an effect that a good output image can be obtained.

Embodiment 2 Next, a second embodiment of the present invention will be described. The scanning line conversion apparatus according to the second embodiment differs from the first embodiment only in the configuration and operation of the first flicker removing circuit 31 shown in FIG. Therefore, only the detailed configuration and operation of the first flicker removing circuit 31 will be described, and the description of the same parts as those in the first embodiment will be omitted.

FIG. 10 is a block diagram of the first flicker removing circuit according to the second embodiment of the present invention. In addition,
In the figure, those having the same symbols as those in the first embodiment have the same configuration and operation, and therefore detailed description thereof will be omitted. In the figure, 70 is a second DC detection circuit for detecting a horizontal DC component from the Y signal. Further, FIG. 11 is a block configuration diagram of the second DC detection circuit 70 in the second embodiment of the present invention. In the figure, 80 is a Y signal input terminal, 81 is a Y signal output terminal, 82 is a subtraction circuit, 83 is an average value circuit, 84 is a delay circuit, and 85 is a comparison circuit.

Next, the concept of the second embodiment will be briefly described. In the second embodiment, the vertical resolution component included in the vertical high frequency component of the video signal is extracted and is fed back (added) to the output image to improve the vertical resolution. Specifically, the flicker component is suppressed while switching the shape (characteristic) of the limiter applied to the vertical high-frequency component of the video signal according to whether the input video signal has a DC component in the horizontal direction. The resolution component is returned to the output image to improve the vertical resolution.

Next, the operation of the first flicker removing circuit 31 of the second embodiment will be described with reference to FIGS. 1, 10 and 11. The Y signal converted into the digital video signal by the A / D conversion circuit 3 a is input to the first flicker removing circuit 31. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. Since the configuration and operation of the first VLPF 6 are the same as those of the first embodiment, detailed description of the operation will be omitted.

The vertical low frequency components separated by the first VLPF 6 are input to the subtraction circuit 44 and the addition circuit 52.
On the other hand, the input Y signal is delayed by one line in the line memory 43, and the subtraction circuit 44 and the second DC detection circuit 7
Input to 0. The subtraction circuit 44 subtracts the vertical low frequency component of the Y signal output from the first VLPF 6 from the Y signal output from the line memory 43 and outputs the vertical high frequency component of the Y signal. The vertical high frequency component of the Y signal output from the subtraction circuit 44 is input to the limiter 49.

The second DC detection circuit 70 detects a horizontal DC component (DC component) from the Y signal delayed by one line output from the line memory 43. Hereinafter, FIG.
The operation of the second DC detection circuit 70 according to the second embodiment will be briefly described with reference to FIG. The Y signal input via the input terminal 80 is supplied to the average value circuit 83 and the delay circuit 8
4 is input. The average value circuit 83 obtains the average of two sampling points before and after, that is, five points, and outputs the averaged value from the subtraction circuit 82.
To enter. However, the average value circuit 83 is not limited to this. On the other hand, the Y signal input to the delay circuit 84 is output in the same phase as the output of the average value circuit 83. The subtraction circuit 82 subtracts the output of the average value circuit 83 from the Y signal output from the delay circuit 84, and outputs an error signal of the Y signal. The error signal of the Y signal output from the subtraction circuit 82 is input to a comparison circuit 85. The comparator circuit 85 detects the DC component in the horizontal direction by comparing the input error signal of the Y signal with a predetermined value. Specifically, when the amplitude of the error signal of the input Y signal is YE, for example, when YE ≦ a and YE ≧ −a, it is determined that the DC component is detected. (A is a positive real number)

In the limiter 49, the second DC detection circuit 70
The limiter shape (characteristic) is switched based on the output DC component detection information, and the amplitude of the vertical high frequency component of the input Y signal is limited and output. The characteristics (see FIGS. 6 and 7), configuration, and operation of the limiter 49 are the same as those in the first embodiment, and detailed description of the operation will be omitted.

The adder circuit 52 adds the vertical low-frequency component of the Y signal output from the first VLPF 6 and the output of the limiter 49. The Y signal from which the flicker component has been removed by the flicker removing circuit 31 and the two color difference signals (RY and BY signals) output from the A / D conversion circuits 3b and 3c are not stored in the frame memories 7a to 7c. The interlaced structure is converted to the interlaced structure and output.

Flicker removing circuit 3 shown in the second embodiment.
1 is a conventional first VLPF 6 and a limiter 49 and a second D
It can be realized only by adding the C detection circuit 70,
There is an effect that a good output image can be obtained without extremely increasing the circuit scale, and a residual flicker component that could not be removed by the conventional first VLPF 6 can be removed.

Third Embodiment FIG. 12 is a block diagram of a scanning line conversion apparatus according to a third embodiment of the present invention. In addition, also in the third embodiment, the VGA is used as in the conventional example.
A case of converting a signal based on the standard into an NTSC standard image will be described. In the figure, 1a to 1c are input terminals for VGA signals (R, G, and B signals based on the VGA standard), 2 is input terminals for synchronizing signals of VGA signals, and 3a to 3c.
Is a luminance signal (Y signal) in the matrix circuit 10, and 2
A / D conversion circuit for converting an analog video signal converted into one color difference signal into a digital video signal, 4 is an input terminal 2
A first sync detecting circuit 5 for detecting a vertical sync signal and a horizontal sync signal from a VGA signal input from the first sync signal generating circuit 5, and a first sync detecting circuit 5 for generating a clock based on the sync signal output from the first sync detecting circuit 4. PLL circuit, 7a-7c is the second
In the frame memory for storing the luminance signal (Y signal) output from the flicker removing circuit 91 and the two color difference signals (RY signal and BY signal) output from the A / D conversion circuits 3b and 3c. is there.

Reference numerals 9a to 9c are horizontal interpolation circuits 93a to 93c.
D / A conversion circuit for converting the digital video signal output from the digital video signal into an analog video signal, 10 is input R, G,
And B signal, Y signal, and two color difference signals (R-
A matrix circuit 11 for converting into a Y signal and a BY signal), and a TV output from the second synchronization detection circuit 12.
Second P that generates a clock based on the side synchronization signal
The LL circuit, 12 is a second sync detection circuit for detecting a vertical sync signal and a horizontal sync signal from the sync signal on the TV side input from the input terminal 16.

Reference numeral 13 is a synchronization addition circuit for adding a vertical synchronization signal and a horizontal synchronization signal to the Y signal output from the D / A conversion circuit 9a, and 14 is a difference between two colors output from the D / A conversion circuits 9b and 9c. Chroma encoder circuit for converting signals (RY signals and BY signals) into modulated color signals (C signals), 15a and 15b are output terminals for Y signals and C signals, and 16 is an input terminal for synchronization signals Is.

Reference numerals 30a and 30b denote band limiting filters (hereinafter referred to as LPFs) for limiting the horizontal signal bands of the RY and BY signals output from the matrix circuit 10, and 91 is input. A second flicker removing circuit for removing a flicker component in the Y signal or for interpolating the Y signal in the vertical direction. Reference numeral 92 denotes the second flicker removing circuit 91.
Inside line memories 115a and 115b, line memory 4
3 and a third memory control circuit for outputting a digital video signal to the frame memories 7a to 7c and outputting a read control signal. Reference numeral 92 further outputs screen enlargement position information to the frame memories 7a to 7c in the enlargement display mode. Reference numerals 93a to 93c are horizontal interpolation circuits. Reference numeral 90 is an input terminal for a normal / enlargement mode switching signal and screen enlargement position information.

FIG. 13 is a block diagram of the second flicker removing circuit 91 in FIG. In the figure, 101
Is a second VLPF for extracting the vertical low-frequency component of the digital video signal (Y signal) or interpolating the Y signal in the vertical direction,
40 is an input terminal for the Y signal, 41 is an input terminal for the memory control signal output from the third memory control circuit 92, 100
Is an input terminal for the normal / enlarged display mode switching signal output from the third memory control circuit 92, 42a is an output terminal for the first field video signal of the Y signal, and 42b is an output terminal for the second field video signal of the Y signal. , 43 is a line memory that delays the input Y signal by one line, and 44 is a second V signal from the Y signal that is delayed by one line from the line memory 43.
A subtraction circuit for subtracting the vertical low-frequency component output from the LPF 101. The vertical high frequency component of the Y signal is separated by subtracting the output of the second VLPF 101 from the output of the line memory 43. 46 and 51 are registers,
Reference numerals 50 and 52 are addition circuits, 47 is a subtraction circuit, and 49 is a limiter. Reference numeral 48 is a first DC that detects a direct current component in the horizontal direction from the input vertical high band-horizontal high band component.
The detection circuit 45 is a first HLPF for extracting the vertical high band-horizontal low band of the Y signal. Reference numeral 102 denotes a selector that switches the video signal output to the output terminals 42a and 42b according to the normal / enlarged display mode switching signal.

FIG. 14 shows the second VLPF1 in FIG.
It is a block diagram of 01. In the figure, 110 is an input terminal for a digital video signal (Y signal), 111 is an input terminal for a memory control signal output from the third memory control circuit 92, 112 is an output terminal for a Y signal in the normal display mode, and 113 is Output terminal of second field video signal of Y signal in enlarged display mode, 114 output terminal of first field video signal of Y signal in enlarged display mode, 115a and 115b delay input Y signal by one line Line memories, 116a to 116c are multiplication circuits for multiplying the input video signal by 0.25, 117 are multiplication circuits for multiplying the input video signal by 0.5, 11
8 to 122 are adder circuits.

FIG. 15 shows the horizontal interpolation circuit 93 shown in FIG.
FIG. 3 is a block diagram of the configuration of FIG. In the figure, 130 is an input terminal of a digital video signal (Y signal), 131 is an output terminal of a Y signal, 132 is an input terminal of a switching signal for alternately switching an original image and an interpolation image, and 133 is a normal / enlarged display mode switching signal. Input terminals, 134 and 135 are registers, 136 is an adder circuit, 137 is a multiplier circuit that multiplies the input video signal by 0.5, 138 is a selector that switches between an interpolation pixel and an input pixel in the enlarged display mode, 13
Reference numeral 9 denotes a selector for switching between the video signal in the normal display mode and the video signal in the enlarged display mode by the normal / enlarged display mode switching signal.

Next, the concept of the third embodiment will be briefly described. In the first embodiment, the flicker is sufficiently corrected by extracting vertical high-horizontal components and vertical high-horizontal low-frequency components having a small amplitude, in which flicker is visually less noticeable than vertical high-frequency components, and feeding back to the output image. While suppressing it, the vertical resolution has been improved. However, the scanning line conversion apparatus according to the first embodiment can improve the resolution in the vertical direction as compared with the conventional scanning line conversion apparatus, but it requires an enlargement function when reading characters using a very fine font. The third embodiment has an object to make it possible to read fine characters and the like on the display by incorporating an original enlargement function as an auxiliary function in the scanning line conversion apparatus of the first embodiment.

The enlargement function of the scanning line conversion apparatus according to the third embodiment will be described. As described above, as the conventional enlargement function method, the video signal of the second field is simply interpolated using the video signals of the two adjacent upper and lower lines in the first field, or the video signal of the second field. Is interpolated with the same video signal as in the first field. However, the video signal of the second field is
In the case of enlargement which is made by interpolating the average value from the video signals of the two adjacent upper and lower lines in the field, the video signal of the first field is the original signal itself and thus is a clear video, while the video signal of the second field is The first video signal is an interpolation of the average values of the upper and lower two lines of the first field video signal.
The image becomes blurry compared to the field image. Therefore, when the first field image and the second field image created as described above are displayed as an interlaced image, the entire screen appears to have flicker and is visually unsightly. Further, when the video signal of the second field is interpolated with the same video signal as the video signal of the first field, there is no difference in clarity of the image between the first field video and the second field video, There is a problem that flicker occurs at the edge of the image.

The outline of the enlargement method of the scanning line conversion apparatus according to the third embodiment will be described below with reference to the flowchart shown in FIG. When the enlarged display mode is selected in the scanning line conversion apparatus of the third embodiment, the screen enlarged position is first detected. Then, based on the screen enlargement position information, the video signal is vertically interpolated from the head line of the screen enlargement position to generate a vertically interpolated image of one frame. In the vertical direction interpolation, the video signal of the second field is the same as the video signal of the first field. Next, the 1-frame vertically interpolated image is passed through a 3-tap vertical low-pass filter to remove flicker, and a 1-frame vertically interpolated image from which flicker has been removed is generated.

A method of generating a vertically interpolated image for one frame and flicker removal will be described below with reference to FIG. First, the video signal of the second field is interpolated with the adjacent original signals as shown in the figure. After the interpolation, the flicker component is removed using the data of three adjacent lines. That is, the input video signal of the ( _{n-1) th} line is an _-1 ,
When the video signal of the n-th line is a _n and the video signal of the n + 1-th line is a _{n + 1} , the video signal of the n-th line of the first field in the enlarged display mode is (3a _n + a
_n-1) / 4, the n-th line of the video signal of the second field becomes _{(a n + 1 + 3a n} ) / 4.

Next, the flicker-removed one-frame vertical interpolation image generated by the above procedure is horizontally interpolated from the first pixel of the screen enlargement position based on the screen enlargement position information. Interpolation in the horizontal direction is performed by interpolating average values of adjacent original pixels. Since the magnifying function of the third embodiment is configured as described above, the problem that occurs in the conventional magnifying function as described above does not occur, flicker can be sufficiently suppressed, and a good magnified image can be obtained. Be done.

The operation of the scanning line conversion apparatus according to the third embodiment of the present invention will be described below with reference to FIGS. In addition,
In the third embodiment, the configurations and operations of the second flicker removing circuit 91 and the third memory control circuit 92, and the presence / absence of the horizontal interpolation circuit 93 are different from those of the scanning line conversion apparatus of the first embodiment. Since the circuit operation of is the same, detailed description of the operation is omitted.

Also in the third embodiment, a case will be described in which a non-interlaced image input based on the VGA standard is converted into an interlaced image and output as in the conventional example. The R, G, and B signals input via the input terminals 1a to 1c are converted by the matrix circuit 10 into a Y signal and two color difference signals. The two color difference signals output from the matrix circuit 10 are LPFs 30a,
At 30b, the horizontal band is limited to half. Y signal output from matrix circuit 10 and LPF 30
The two color difference signals output from a and 30b are converted into digital video signals by A / D conversion circuits 3a to 3c. At this time, the two color difference signals are converted into digital video signals with a sampling clock that is half the Y signal.

On the other hand, the VG input through the input terminal 2
As for the sync signal of the A signal, the vertical sync signal and the horizontal sync signal are detected by the first sync detection circuit 4. First PLL
The circuit 5 uses V as a reference based on the detected horizontal synchronizing signal.
Generate a reference clock on the GA side. First PLL circuit 5
The clock generated in the above is the A / D conversion circuits 3a to 3c,
It is input to the second flicker removing circuit 91 and the third memory control circuit 92. At this time, as described above, the clocks for the two color difference signals are frequency-divided and output at half the frequency of the clock for the Y signal. In addition, the first synchronization detection circuit 4
The vertical sync signal and horizontal sync signal detected in
Is also input to the memory control circuit 92.

In the third memory control circuit 92, the normal / enlargement mode switching signal input from the input terminal 90 and the horizontal synchronizing signal of the VGA signal output from the first synchronizing detection circuit 4 are used to output the second signal. It generates a digital video signal write / read control signal for the line memories 115a and 115b and the line memory 43 in the flicker removal circuit 91, and switching control signals for the selectors 102 and 139. In the third embodiment, as in the first embodiment, the line memories 105a, 105b,
The line memory 43 is configured by using a FIFO memory. Therefore, from the third memory control circuit 92, the line address reset signal at the time of writing and reading, the writing and reading enable signal (ENAB
L signal), and write and read clocks are output to the second flicker removal circuit 91. Also, the third
In the memory control circuit 92, the normal / enlargement mode switching signal input from the input terminal 90, the vertical synchronization signal output from the first synchronization detection circuit 4, and the horizontal synchronization signal are used to send the data to the frame memories 7a to 7c. A writing control signal for the digital video signal is also generated.

The Y signal converted into the digital video signal by the A / D conversion circuit 3a is input to the second flicker removing circuit 91. The operation of the second flicker removing circuit 91 will be described below with reference to FIG. The Y signal input via the input terminal 40 is input to the second VLPF 101 and the line memory 43. Second VLPF1 using FIG.
The operation of 01 will be described. The Y signal input via the input terminal 110 is applied to the multiplication circuit 116a and the line memory 1
15a is input. The line memory 115a delays the input Y signal by one line and outputs it. Line memory 1
The Y signal output from 15a is applied to the multiplication circuits 116b and 11b.
7 and the line memory 115b. Similarly to the line memory 115a, the line memory 115b delays the input Y signal by one line and outputs the delayed Y signal. The output of the line memory 115b is input to the multiplication circuit 116c. The line memories 115a and 115b are controlled by using the data write and read control signals input from the third memory control circuit 92 via the input terminal 111.

The Y signal input to the multiplication circuits 116a to 116c is multiplied by 0.25 and output. The Y signal input to the multiplication circuit 117 is multiplied by 0.5 and output. The outputs of the multiplication circuits 116a and 116b are the addition circuit 1
It is added in 18 and is output to the adding circuits 120 and 121. Similarly, the outputs of the multiplication circuits 116b and 116c are added by the addition circuit 119 and output to the addition circuits 120 and 122. In the adder circuit 120, the adder circuits 118 and 1
The outputs of 19 are added, the vertical high frequency component of the Y signal is removed, and the signal is output via the output terminal 112. Output terminal 1
The signal output from 12 is Y in the normal display mode.
It is a signal and is equal to the output of the first VLPF in the first embodiment. In the adder circuit 121, the outputs of the adder circuit 118 and the multiplier circuit 117 are added and output to the selector 102 via the output terminal 113. Similarly, the adder circuit 122
Then, the outputs of the adding circuit 119 and the multiplying circuit 117 are added and output to the selector 102 via the output terminal 114. As described above, the signal output from the output terminal 114 is the Y signal written in the first field memory of the frame memory 7a in the enlarged display mode, and the signal output from the output terminal 113 is the frame memory in the enlarged display mode. Y written in the second field memory 7a
Signal.

On the other hand, the Y signal input to the line memory 43 is delayed by one line and output. The line memory 43 is controlled by using the data write and read control signals output from the third memory control circuit 92 via the input terminal 41.

The subtraction circuit 44 outputs the second VLPF from the Y signal delayed by one line output from the line memory 43.
By subtracting the vertical low-frequency component of the Y signal output from 101, the vertical high-frequency component of the Y signal is separated. (Note that
In the line memory 43, the input Y signal and the second VLP
The Y signal is delayed by one line in order to match the phase with the vertical low-frequency component output from F101. ) The output of the subtraction circuit 44 is input to the first HLPF 45 and the register 46.

The vertical high band-horizontal low band component of the Y signal separated by the first HLPF 45 is input to the limiter circuit 49 and the subtraction circuit 47. Subtraction circuit 47
Then, the vertical high frequency component-horizontal low frequency component of the Y signal output from the first HLPF 45 is subtracted from the vertical high frequency component of the Y signal delayed by one clock in the register 46 to obtain the vertical high frequency component of the Y signal- Outputs horizontal high frequency components. (In the register 46, the vertical high-frequency component of the Y signal and the first HLPF 45
The vertical high frequency component of the Y signal is delayed by one clock in order to match the phase with the vertical high frequency component-horizontal low frequency component of the output Y signal. ) The output of the subtraction circuit 47 is input to the first DC detection circuit 48 and the addition circuit 50.

In the first DC detection circuit 48, the subtraction circuit 4
The horizontal direct current component (DC component) of the Y signal is detected from the vertical high frequency component-horizontal high frequency component of the Y signal output from 7.
The operation of the first DC detection circuit 48 is the same as that described in the first embodiment, and will not be repeated here.

The limiter 49 limits and outputs the amplitude of the vertical high band-horizontal low band component of the input Y signal based on the direct current detection information of the first DC detection circuit 48.
Specifically, as in the first embodiment, when the direct current component is detected in the first DC detection circuit 48, the limiter shape (characteristic) as shown in FIG. 6, and when the direct current component is not detected, Is Y using the limiter shape as shown in FIG.
Limits the amplitude of the vertical high-horizontal low-pass component of the signal.

The adder circuit 50 adds the outputs of the subtractor circuit 47 and the limiter circuit 49. The adder circuit 52 adds the outputs of the register 51 and the adder circuit 50. The output of the adder circuit 52 is input to the selector 102.

In the selector 102, the output of the adder circuit 52 (Y signal in the normal display mode) and the output of the second VLPF 101 input via the output terminals 113 and 114 (Y signal in the enlarged display mode) are input terminal 10.
The output is switched based on the normal / enlarged display mode switching signal input via 0. The output of the selector 102 is input to the frame memory 7a via the output terminals 42a and 42b. The video signal of the first field is output from the output terminal 42a, and the video signal of the second field is output from the output terminal 42b.

The second flicker removing circuit 91 removes the flicker component, or the Y signal in which the image is vertically interpolated, and the A / D conversion circuits 3b and 3c output 2
The one color difference signal (RY signal and BY signal) is output to the frame memories 7a to 7c. The operation of writing the digital video signal in the frame memory 7 will be described below.

The third memory control circuit 92 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal at a field frequency of 60 Hz. Specifically, when writing to the frame memory 7, a digital video signal input in a frame structure is converted into a field structure and written.
Taking the Y signal as an example, the Y signal of the first field output from the output terminal 42a of the second flicker removal circuit 91 is transferred to the first field memory of the frame memory 7a and the second field output from the output terminal 42b. The Y signal of is written in the second field memory of the frame memory 7a.

A method of generating a data write control signal for the frame memory 7 output from the third memory control circuit 92 will be described below. First, when the vertical synchronization signal is input from the first synchronization detection circuit 4, the normal / normal input from the input terminal 90 is input to the third memory control circuit 92.
The display mode is detected using the enlarged display mode switching signal. Since the data write control signal differs between the normal display mode and the enlarged display mode, the operation in each case will be described.

The case of the normal display mode will be described.
When the normal display mode is detected, the third memory control circuit 92 sets a field to be written in the frame memory 7 next and outputs a signal indicating the normal display mode to the second flicker removing circuit 91. To do. When the field setting result is the first field, a control signal for writing the odd line to the first field memory of the frame memory 7 is generated, and when the second field is set, the even line is set to the first field memory of the frame memory 7. A control signal for writing to the two-field memory is generated. Specifically, in the case of the Y signal, if the field result is the first field, the output terminal 42 of the second flicker removing circuit 91
A signal for writing the output of a to the first field memory of the frame memory 7a and the output of the output terminal 42b of the second flicker removing circuit 91 to the second field memory of the frame memory 7a is generated if the field result is the second field. To do. In the control, the horizontal sync signal output from the first sync detection circuit 4 is used to discriminate even / odd lines to generate the control signal. At that time, the third embodiment
Then, similarly to the case of the first embodiment, control is performed so that only the effective video signal portion of the VGA signal is written in the frame memory 7.

The non-interlaced digital video signal input to the frame memories 7a to 7c is a field structure digital video signal (interlaced structure digital video signal) based on the write control signal output from the third memory control circuit 92. ) And stored in the frame memories 7a to 7c. In the third embodiment, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field as in the conventional example. Therefore, in the third memory control circuit 92, in order to write the digital video signal converted into the interlaced structure into the frame memory 7, the switching control signal of the two field memories is generated based on the field discrimination result. Also,
In the third memory control circuit 92, the data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 is detected by the first synchronization detection circuit 4 in the vertical synchronization. It is generated based on the signal and the horizontal sync signal.

On the other hand, the T input through the input terminal 16
The V-side sync signal is detected by the second sync detection circuit 12 as a vertical sync signal and a horizontal sync signal. At this time, the field discrimination is also performed by the second synchronization detection circuit 12.
The second PLL circuit 11 generates a reference clock on the television side with reference to the horizontal sync signal detected by the second sync detection circuit 12. At this time, the frequency of the sampling clock of the color difference signal is divided into half the frequency of the sampling clock of the Y signal as in the first embodiment. Second P
The clock generated by the LL circuit 11 is input to the D / A conversion circuits 9a-9c and the third memory control circuit 92. The vertical sync signal, the horizontal sync signal, and the field determination result detected by the second sync detection circuit 12 are also input to the third memory control circuit 92.

In the third memory control circuit 92, a read control signal for reading the interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the field discrimination result (the field Memory switching signals, data read addresses, read control signals, etc.). The frame memories 7a to 7c output interlaced digital video signals based on the read control signal output from the third memory control circuit 92.

The interlaced structure digital video signals read from the frame memories 7a to 7c are input to the horizontal interpolation circuits 93a to 93c. The operation of the horizontal interpolation circuit 93 in the normal display mode will be described below with reference to FIG. The video signal input via the input terminal 130 is input to the selector 139. The selector 139 outputs the input video signal according to the normal display mode signal input from the input terminal 133.

The interlaced structure digital video signals output from the horizontal interpolation circuits 93a to 93c are converted into interlaced analog video signals by the D / A conversion circuits 9a to 9c. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronization signal and the horizontal synchronization signal are added by the synchronization adding circuit 13. The sync addition circuit 13 generates a vertical sync signal output from the second sync detection circuit 12, a horizontal sync signal, and a sync signal based on the field discrimination result, and adds the sync signal to the Y signal.

Further, the two color difference signals (RY signal and BY signal) output from the D / A conversion circuits 9b and 9c are converted into modulated color signals (C signals) by the chroma encoder circuit 14 and output. It is output via the terminal 15b. During chroma encoding (when converting two color difference signals into modulated color signals), two color difference signals are output based on the vertical sync signal, the horizontal sync signal, and the field discrimination result output from the second sync detection circuit 12. Modulate the signal.

Next, the case of the enlarged display mode will be described. When the enlarged display mode is detected, the third memory control circuit 92 sets the screen enlargement range on the basis of the screen enlargement position information input from the input terminal 90, and causes the second flicker removal circuit 91 to set the normal / normal state. The enlarged display mode switching signal (enlarged display mode signal) is output. In the second flicker removing circuit 91, when the enlarged display mode signal is input, the Y signals interpolated in the vertical direction of the first field and the second field output from the second VLPF 101 are output to the output terminals 42a and 42b. Is output via.

When the enlarged display mode is detected, the third memory control circuit 92 generates a control signal for writing the video signal in the first field and the second field in the frame memory 7. In the case of the Y signal, the output of the output terminal 42a of the second flicker removing circuit 91 is output to the first field memory of the frame memory 7a and the output terminal 42a.
A control signal for simultaneously writing the output of b into the second field memory of the frame memory 7a is generated. Also, 2
In the case of one color difference signal, the data of the same line is written in the first field memory and the second field memory in the frame memories 7b and 7c.

Specifically, first, the vertical sync signal and horizontal sync signal detected by the first sync detection circuit 4 are used to detect the start line of the image at the time of enlargement and the position of the start pixel in the horizontal direction. To do. Then, a control signal for writing data belonging to the screen expansion range to the frame memory 7 is generated based on the detected start line and the position of the start pixel in the horizontal direction. As a result, in the normal display mode, the video signals are alternately written in the first field memory and the second field memory in the frame memory 7, whereas in the enlarged display mode, the video signals in the frame memory 7 are simultaneously written. The video signal is written in the 1st field memory and the 2nd field memory. In the third embodiment, regarding the Y signal in which the flicker component is conspicuous, the second
The video signals of the respective fields output from the flicker removing circuit 91 are written in the frame memory 7a, and for the two color difference signals in which the flicker is inconspicuous, the video signals of the same line are written in the field memories in the frame memories 7b and 7c. By writing in the memory, the circuit scale is reduced in the enlarged display mode.

Furthermore, in the third memory control circuit 92,
A vertical synchronization signal input from the second synchronization detection circuit 12,
Generates a read control signal (a switching signal of the field memory, a read address of the data, a read control signal, etc.) for reading the interlaced image stored in the frame memory 7 based on the horizontal synchronization signal and the result of field discrimination. To do. Frame memories 7a-7
In c, the interlaced structure digital video signal is output based on the read control signal output from the third memory control circuit 92. In the enlarged display mode, the interlaced structure digital video signal is read at half the frequency in the normal display mode.

The interlaced structure digital video signals read from the frame memories 7a to 7c are input to the horizontal interpolation circuits 93a to 93c. The operation of the horizontal interpolation circuit 93 in the enlarged display mode will be described below with reference to FIG. The video signal input via the input terminal 130 is input to the register 134 and the adder circuit 136. Register 1
The video signal delayed by one clock in 34 is registered in the register 135.
And to the selector 138. Also, register 1
The video signal delayed by one clock at 35 is added by an adder circuit 136.
Is input to The adder circuit 136 adds the video signal input through the input terminal 130 and the output of the register 135 and outputs the result. The multiplication circuit 137 multiplies the output of the register 135 by 0.5 and outputs the result. The output of the multiplication circuit 137 is input to the selector 138. In the selector 138,
The output of the register 134 and the output of the multiplication circuit 137 are alternately switched by the switching signal input via the input terminal 132 and output to the selector 139. The output image of the register 134 is the original image, the output image of the multiplication circuit 137 is the average value interpolation image on both sides in the horizontal direction, and the output of the selector 138 is the image in the enlarged display mode. Selector 1
At 39, the output of the selector 138 is selected by the enlarged display mode signal input through the input terminal 133. The output of the selector 139 is output to the D / A conversion circuits 9a to 9c via the output terminal 131.

The interlaced structure digital video signals output from the horizontal interpolation circuits 93a to 93c are converted into interlaced analog video signals by the D / A conversion circuits 9a to 9c. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronization signal and the horizontal synchronization signal are added by the synchronization adding circuit 13. The sync addition circuit 13 generates a vertical sync signal output from the second sync detection circuit 12, a horizontal sync signal, and a sync signal based on the field discrimination result, and adds the sync signal to the Y signal.

The two color difference signals (RY signal and BY signal) output from the D / A conversion circuits 9b and 9c are converted into modulated color signals (C signals) by the chroma encoder circuit 14 and output. It is output via the terminal 15b. During chroma encoding (when converting two color difference signals into modulated color signals), two color difference signals are output based on the vertical sync signal, the horizontal sync signal, and the field discrimination result output from the second sync detection circuit 12. Modulate the signal.

As described above, the scanning line conversion apparatus according to the third embodiment is capable of performing the second interpolation when interpolating the vertical pixels of the Y signal.
The field signal is interpolated with the same video signal as in the first field, and then the flicker component is removed and output by limiting the band in the vertical direction with a 3-tap vertical low-pass filter. It is possible to suppress the deterioration of the resolution and the occurrence of flicker, which are problems in (3), as much as possible, and it is possible to obtain a visually excellent screen.
Since flicker is less noticeable in the two color difference signals than in the Y signal, interpolation in the vertical direction is sufficient by interpolating the video signal of the second field with the same video signal as that of the first field. Since the flicker removing circuit 91 is unnecessary, the circuit scale can be reduced. Further, since the interpolation in the horizontal direction is performed after the non-interlaced image is converted into the interlaced image, the interpolation processing can be performed at half the normal frequency, and the power consumption can be suppressed to a low level when integrated into an LSI. Although the average value interpolation of adjacent pixels is adopted as the horizontal interpolation, the present invention is not limited to this, and the same effect can be obtained even if the repeated interpolation of the previous pixel on the same line is adopted. Furthermore, the method of controlling writing to the frame memory 7 in the normal display mode is not limited to that shown in the first to third embodiments. For example, as in the case of the enlarged display mode, the field memory in the frame memory 7 is switched so that the odd line of the video signal of one frame is the first field memory in the frame memory 7 and the even line is the second field memory. Even if it is controlled to write in, the same effect can be obtained. Further, the configuration of the flicker removing circuit at the time of enlargement is shown in FIG.
However, the present invention is not limited to that shown in FIG.
Alternatively, the same effect can be obtained with the circuit configuration as shown in the second embodiment.

In the first to third embodiments, the shape of the limiter 49 (see FIGS. 6 and 7) is switched depending on the DC component and other components, but the present invention is not limited to this, and the first D
A plurality of DC detection levels for the C detection circuit 48 are prepared, and the limiter 4 is selected according to the plurality of detection levels.
The shape of 9 may be changed.

In the first and third embodiments, the horizontal DC component is detected by using the vertical high band-horizontal high band component of the Y signal output from the subtraction circuit 47, but the present invention is not limited to this. For example, Y output from the subtraction circuit 44
It goes without saying that the same effect can be obtained even if the horizontal DC component is detected from the vertical high frequency component of the signal or the horizontal DC component is directly detected from the input Y signal. In addition, in the first and third embodiments, the limiter 49 suppresses the amplitude of the vertical high-frequency / horizontal low-frequency component input from the first HLPF 45. The amplitude of the high-frequency and low-frequency components may be increased and fed back to the output image, in which case the vertical resolution is further increased. Further, the limiter 49 has a plurality of amplitude conversion data, and the user or a personal computer or the like discriminates the pattern and switches the data (for example, when the resolution is required, it is set to double and flicker is eliminated). If it is desired to completely remove it, it is set to 0.5 times, and in other cases, it is set to 1.0), and the same effect is obtained.

In the above first to third embodiments, as an example of the non-interlaced image, a VG of a personal computer is used.
Although the operation of the scanning line conversion device has been described using the A signal, the present invention is not limited to this, and an image input in non-interlace (for example, DV which is currently under discussion in Europe).
B, non-interlaced images sent by digital broadcasting such as ATV, which is being standardized in the United States, and ISDB, which is being standardized in Japan, or images in other display modes of a personal computer. In the case of converting (1) to an interlaced image, the same effect can be obtained by removing the flicker component using the scanning line conversion device and outputting the flicker component.

In the first to third embodiments, the R, G, and B signals are converted into the Y signal by the matrix circuit 10.
And the flicker component of the Y signal is removed after conversion into the two color difference signals (R-Y signal and BY signal), but the present invention is not limited to this, and the flicker component included in the R, G, and B signals is not limited to this. May be removed by the flicker removing circuit 31 and output. Also, RY signal and B-
The flicker component may be removed from the Y signal by the flicker removing circuit 31. Further, when removing the flicker component in the color difference signal, the characteristics or the configuration of the flicker removing circuit 31 may be changed from the case of removing the flicker component in the luminance signal. Further, it goes without saying that the characteristics or configuration of the flicker removing circuit 31 may be changed for each color difference signal.

In the first to third embodiments, it is possible to output an image without fine characters, or an image from which high-frequency components in the vertical direction are removed as shown in the conventional example when the viewing distance is long. Alternatively, the scanning line conversion device may be configured. In the first to third embodiments, the matrix circuit 10 converts the luminance signal (Y signal) into two color difference signals (RY signal and BY signal), but the present invention is not limited to this. , A luminance signal (Y signal) and two color signals (U and V signals), or a luminance signal (Y
It is needless to say that the same effect can be obtained even if the flicker component is removed from the Y signal after the conversion into the interlaced image after the conversion into the other signals. Also, 2
Scanning line conversion may be performed after converting one color difference signal into a modulated color signal.

In the first to third embodiments, the horizontal low-pass filter and the vertical low-pass filter are configured as shown in FIG. 3 and FIG. 22, respectively. , The shape and type of the filter (FIR filter, IIR filter, etc.), frequency characteristics, etc. are not limited to these. Further, in the first to third embodiments, the vertical high pass filter is configured by subtracting the output of the vertical low pass filter from the input signal, but the present invention is not limited to this. For example, the vertical high-pass filter and the vertical low-pass filter are separately configured, or the vertical high-pass component is separated using the vertical high-pass filter, and then the vertical high-pass component is subtracted from the input signal. By doing so, a vertical low pass filter may be configured. Similarly, a horizontal low pass filter,
And the horizontal high-pass filter separately, or the horizontal high-pass component is separated using the horizontal high-pass filter, and then the horizontal high-pass component is subtracted from the input signal to obtain the horizontal low-pass filter. You may comprise.

[0136]

Since the present invention is configured as described above, it has the following effects.

When converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, first, the vertical high-frequency component and the vertical low-frequency component of the non-interlaced image input by the first frequency separation means are converted. To separate. Next, the second high frequency component separates the vertical high band-horizontal high band component and the vertical high band-horizontal low band component from the separated vertical high band component. Further, the first DC component detecting means detects the horizontal DC component from the input non-interlaced image. Based on the DC component detection information, the first amplitude converting means switches the amplitude conversion characteristic applied to the vertical high band-horizontal low band component. For images with horizontal lines such as a table where horizontal dc components are detected and where flicker is very noticeable visually,
Since the output is output in addition to the first amplitude converting means having the amplitude characteristic of the inverse characteristic with respect to the vertical high band-horizontal low band component, the occurrence of flicker due to the residual flicker component shown in FIG. 5 can be suppressed. For an image having a vertical resolution component other than the DC component, the vertical resolution is extracted from the vertical high band-horizontal low band component and output by the first amplitude converting means. The resolution can be improved. Further, the second frequency separating means separates a vertical high-horizontal low-frequency component in which flicker is conspicuous and a vertical high-horizontal high-frequency component in which flicker is relatively inconspicuous, with respect to the vertical high-horizontal low-frequency component. As a result, flicker is suppressed or the resolution is improved by the first amplitude converting means, and the vertical high-frequency-horizontal high-frequency component, which is the resolution component, is returned to the original signal as it is, so further improvement in resolution can be expected.

In addition, it can be realized by simply adding a simple circuit to the conventional scanning line conversion apparatus, and it is possible to suppress the occurrence of flicker without extremely increasing the circuit scale and improve the vertical resolution. Therefore, a good output image can be obtained.

When converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, first, the vertical high-frequency component and the vertical low-frequency component of the non-interlaced image input by the first frequency separating means are converted. Separate the components. Next, the first DC detecting means detects the horizontal DC component of the input non-interlaced image. Based on the output of the first DC detecting means, the second amplitude converting means switches the amplitude converting characteristic applied to the vertical high frequency component. For images with horizontal lines such as a table where horizontal DC components are detected and where flicker is very noticeable visually, the vertical high frequency component has an inverse amplitude characteristic. Since the output is output in addition to the first amplitude converting means, it is possible to suppress the occurrence of flicker due to the residual flicker component shown in FIG.
For an image having a resolution component in the vertical direction other than the DC component, the above-mentioned vertical high frequency band-in the first amplitude conversion means.
Since the resolution component in the vertical direction is extracted and output from the horizontal low-frequency component, the resolution in the vertical direction can be improved.

In addition, it can be realized by simply adding a simple circuit to the conventional scanning line conversion device, and the occurrence of flicker can be suppressed without extremely increasing the circuit scale. Further, there is an effect that the resolution in the vertical direction can be improved and a good output image can be obtained. Further, even if compared with the scanning line conversion apparatus according to the first aspect of the present invention, it is possible to suppress the occurrence of flicker with a simple circuit configuration and improve the resolution in the vertical direction.

Further, when the horizontal DC component of the input non-interlaced image is detected, the amplitude of the vertical high frequency-horizontal high frequency component separated by the second frequency separation means is compared with a predetermined value. . Since the first DC detecting means determines that the DC component is detected when the amplitude is less than the predetermined value, the DC component can be reliably detected with a very simple circuit configuration.

When converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, screen enlargement position information generating means generates screen enlargement position information when the screen is enlarged. Based on the screen vertical expansion position information output from the screen expansion position information generating means, the vertical direction interpolation means interpolates pixels in the vertical direction. Further, the horizontal direction interpolation means interpolates the pixels in the horizontal direction based on the screen horizontal enlargement position information output from the screen enlargement position information generation means. When the vertical pixel is interpolated by the vertical direction interpolating means, the vertical band is limited and the flicker component is removed and output after interpolating with the adjacent upper or lower pixel. It is possible to minimize the deterioration of resolution and the occurrence of flicker, which are problems, and it is possible to obtain a visually excellent screen.

In addition, it can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, and the circuit scale is slightly increased as compared with the conventional enlargement circuit, so that the flicker is suppressed. An enlarged image can be obtained.

Since the non-interlaced image in 1-frame units is converted into the interlaced image in 1-field units, the pixels in the horizontal direction are interpolated based on the screen horizontal enlargement position information output from the screen enlargement position information generating means. As compared with the case where the interpolation process is performed in the state of the non-interlaced image, the interpolation process can be performed at half the frequency, and the power consumption can be suppressed to be small when the LSI is used.

Further, when the vertical direction interpolation means interpolates the pixels in the vertical direction based on the screen vertical enlargement position information output from the screen enlargement position information generating means, the interpolation pixel at the adjacent upper or lower pixel is used. To generate. After that, flicker removal is performed by limiting the vertical band only for the luminance signal and no flicker removal circuit is provided for the color difference signal. Therefore, the circuit scale can be reduced to about 1/3 and the visual expansion is good. Images can be obtained.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of a scanning line conversion apparatus that is Embodiment 1 of the present invention.

FIG. 2 is a block diagram of a first flicker removing circuit 31 in FIG. 1;

FIG. 3 is a block diagram of a first HLPF 45 in FIG.

FIG. 4 is a diagram for explaining the operation of the scanning line conversion device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a residual flicker component included in a first VLPF output signal.

FIG. 6 is a diagram showing input / output characteristics of the limiter according to the first embodiment of the present invention.

FIG. 7 is a diagram showing input / output characteristics of the limiter according to the first embodiment of the present invention.

FIG. 8 is a diagram showing the effect of the limiter according to the first embodiment of the present invention.

FIG. 9 is a diagram showing the effect of the limiter according to the first embodiment of the present invention.

FIG. 10 is a block configuration diagram of a first flicker removing circuit that is Embodiment 2 of the present invention.

FIG. 11 is a second DC according to the second embodiment of the present invention.
3 is a block diagram of a detection circuit 70. FIG.

FIG. 12 is a block configuration diagram of a scanning line conversion apparatus which is Embodiment 3 of the present invention.

FIG. 13 is a block configuration diagram of a second flicker removal circuit in FIG.

14 is a block diagram of the second VLPF 101 in FIG.

FIG. 15 is a block configuration diagram of a horizontal interpolation circuit 93 in the third embodiment of the present invention.

FIG. 16 is a flowchart showing a vertical interpolation method.

FIG. 17 is a diagram showing a method of generating a video signal of a first field and a video signal of a second field by interpolation in the vertical direction.

FIG. 18 is a diagram showing a spatial frequency characteristic of a non-interlaced image.

FIG. 19 is a diagram showing a spatial frequency characteristic of an interlaced image.

FIG. 20 is a diagram showing a two-dimensional frequency characteristic of an interlaced image.

FIG. 21 is a block diagram of a conventional scanning line conversion device.

FIG. 22 is a block configuration diagram of a first VLPF.

FIG. 23 is a diagram showing frequency characteristics of the first VLPF shown in FIG. 22.

[Explanation of symbols]

6 1st VLPF, 7 frame memory, 23 line memory, 24 multiplication circuit, 25 multiplication circuit, 26 addition circuit, 31 flicker removal circuit, 32 second memory control circuit, 43 line memory, 44 subtraction circuit, 45
First HLPF, 46 register, 47 subtraction circuit,
48 first DC detection circuit, 49 limiter, 50 addition circuit, 51 register, 52 addition circuit, 62 register, 63 multiplication circuit, 64 multiplication circuit, 65 addition circuit, 70 second DC detection circuit, 82 subtraction circuit, 83
Average value circuit, 84 delay circuit, 85 comparison circuit, 91
2nd flicker removal circuit, 92 3rd memory control circuit, 93 horizontal interpolation circuit, 101 2nd VLPF, 1
02 selector, 115 line memory, 116 multiplication circuit, 117 multiplication circuit, 118 addition circuit, 119 addition circuit, 120 addition circuit, 121 addition circuit, 122
Adder circuit, 134 register, 135 register, 13
6 adder circuit, 137 multiplier circuit, 138 selector,
139 Selector.

Claims (6)

[Claims] 1. A scanning line conversion device for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, wherein a vertical high frequency component and a vertical low frequency component of the input non-interlaced image are separated. A first frequency separation means for separating the vertical high frequency component from the vertical high frequency component of the non-interlaced image into a vertical high frequency region-horizontal high frequency region component and a vertical high frequency region-horizontal low frequency region component; A first direct current detecting means for detecting a direct current component in the horizontal direction of the non-interlaced image to be reproduced, and a first direct current detecting means for converting the amplitude of the vertical high band-horizontal low band component based on the output of the first direct current detecting means. The amplitude converting means, the vertical low-frequency component separated by the first frequency separating means, the vertical high-horizontal high-frequency component separating by the second frequency separating means, and the first Of the amplitude converting means, and when the first amplitude converting means converts the amplitude of the vertical high-range / horizontal low-range component, the first DC detecting means detects a direct current. In such a case, at least the inverse characteristic of the vertical high-frequency / horizontal low-frequency component is given and outputted, and a predetermined line is thinned out from the non-interlaced image of one frame unit outputted from the adding means. The scanning line conversion device is characterized in that it is configured to generate an interlaced image in units of one field. 2. A scanning line conversion device for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, wherein a vertical high-frequency component and a vertical low-frequency component of the input non-interlaced image are separated. And a first frequency separating means for detecting the direct current component in the horizontal direction of the input non-interlaced image.
DC detecting means, second amplitude converting means for converting the amplitude of the vertical high frequency component based on the output of the first direct current detecting means, and vertical low frequency component separated by the first frequency separating means. And an adding means for adding the outputs of the second amplitude converting means, and when the amplitude of the vertical high frequency component is converted by the second amplitude converting means, the direct current is detected by the first direct current detecting means. In this case, at least the inverse characteristic of the vertical high frequency component is given and outputted, and a predetermined line is thinned out from the non-interlaced image of one frame unit outputted from the adding means to make one field unit. And a scanning line conversion device configured to generate an interlaced image. 3. When detecting a horizontal DC component of the input non-interlaced image, the amplitude of the vertical high frequency-horizontal high frequency component separated by the second frequency separation means is compared with a predetermined value. 2. The scanning line conversion apparatus according to claim 1, wherein the first DC detecting means is controlled so as to detect the DC component when the amplitude is less than a predetermined value. 4. A scanning line conversion device for converting a non-interlaced image input in 1-frame units into an interlaced image in 1-field units, and screen enlarging position information generating means for generating screen enlarging position information when enlarging the screen,
Vertical direction interpolation means for interpolating vertical pixels based on the screen vertical expansion position information output from the screen expansion position information generating means, and horizontal based on the screen horizontal expansion position information output from the screen expansion position information generating means. An interlaced image for each field is formed by thinning a predetermined line from a horizontal interpolating means for interpolating pixels in the direction and at least a non-interlaced image for each frame in which vertical pixels are interpolated by the vertical interpolating means. A field image generating unit is provided, and when the vertical direction interpolation unit interpolates the vertical direction pixel, the vertical band is limited and the flicker component is removed after interpolating the adjacent upper or lower pixel. A scanning line conversion device having the above-mentioned configuration. 5. The horizontal interpolation means for interpolating pixels in the horizontal direction based on the screen horizontal enlargement position information output from the screen enlargement position information generating means is arranged at the subsequent stage of the field image generating means. The scanning line conversion device according to claim 4, wherein: 6. The vertical direction interpolation means interpolates pixels in the vertical direction based on the screen vertical expansion position information output from the screen expansion position information generation means, and interpolates at adjacent upper or lower pixels. 5. The scanning line conversion apparatus according to claim 4, wherein after that, only the luminance signal is subjected to flicker removal by limiting the band in the vertical direction, and the chrominance signal is not removed.