JP3213682B2 - Scanning line conversion device and flicker removal device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a non-interlaced image output from a personal computer (hereinafter referred to as a personal computer) or the like into an interlaced image and converts the image into a television (hereinafter referred to as a television or a TV). The present invention relates to a scanning line conversion device for displaying on a display device.

[0002]

2. Description of the Related Art In recent years, demand for personal computers has been growing rapidly in various countries around the world. However, many of the personal computers that are now in widespread use are purchased by companies or individuals for business use. Therefore, in the future, the spread to homes will be the biggest issue. In order to spread personal computers at home,
There is a demand for product development that takes into account family use in addition to simplified operation and cost reduction. Recently, many personal computer manufacturers have released integrated PCs that take operability into account. These products include personal computers, displays, hard disks, floppy disks, CD-
By integrating the ROM and the like into a single unit, the user does not need to connect the devices. Also,
Each company is trying to improve the operability of personal computers by devising the initial installation software (software such as menu display and operation explanation).

[0003] However, the integrated personal computers of each company are aimed at individuals, not at home (family). The above-mentioned integrated personal computer is operated in the same manner as a conventional personal computer by a user operating a keyboard or a mouse in front of a display of about 15 inches in a CD-RO.
M or a game. On the other hand, in product development targeting the home (family), it is necessary to display a personal computer screen on a large display in order for the whole family to view fine images or sounds of the personal computer. For operation, instead of using a conventional keyboard and mouse, a personal computer can be operated from a remote place using a wireless remote controller or the like used for home appliances such as audio visual equipment (hereinafter, referred to as AV equipment). I need to be able to do it.

[0004] The development of a display monitor for home use has the following problems. Generally, when a display for a personal computer is used as a display device, the price of the display is about four times that of a television of the same size. This price difference (price) poses a serious problem in disseminating personal computers for home use. On the other hand, there is a method of displaying the output (display image) of a personal computer on a conventional home television screen. At this time, the display screen of the personal computer is sequentially scanned (hereinafter referred to as non-interlaced scanning), whereas the display of the television is interlaced scanning. It is necessary to convert a non-interlaced image into an interlaced scan image (hereinafter, referred to as an interlaced image). In that case,
Flickers occur on the TV screen, resulting in very unsightly images. Hereinafter, a method of displaying a screen of a personal computer and a television, causes of flicker, and a conventional scanning line conversion device including a flicker removing circuit will be described.

First, a screen display method (screen display mode) of a personal computer will be briefly described. There are a plurality of screen display modes of the personal computer. Among them, a frequently used VGA standard will be briefly described. In the VGA standard, the number of effective images per line is 64
The number of effective scanning lines in one frame is defined as 480 lines with 0 pixels. The image is displayed on the display in a non-interlaced manner. Note that there is no clear definition regarding the frame frequency. (It is often output at a frame frequency of about 60 Hz.) Next, a screen display method (screen display mode) of the television will be described. ITU-R Recommendation BT. 601 (system 5
According to 25), the number of effective pixels in the horizontal direction of the TV screen is 7
20 pixels (at the time of 13.5 MHz sampling), the number of effective scanning lines in one frame is 486 lines. Also,
The television is displayed on the display as an interlaced image having a field frequency of 59.94 Hz. Therefore, when the VGA output from the personal computer is simply converted into an interlaced image and displayed on a television screen, flicker occurs and the image becomes very unsightly.

Next, a process of generating flicker which occurs when a non-interlaced image is converted to an interlaced image will be briefly described with reference to FIGS.
FIG. 15 is a diagram showing the spatial frequency characteristics of a non-interlaced image. In other words, the characteristics on the spatial frequency of the non-interlaced image in the case of 525 scanning lines and a frame frequency of 60 Hz (hereinafter, referred to as a frequency spectrum). Is shown. In the figure, the horizontal axis represents the spatial frequency in the time axis direction, and the vertical axis represents the spatial frequency in the vertical direction. In the case of a non-interlaced image, the frequency spectrum repeatedly appears at an interval of 60 Hz in the time axis direction and at an interval of 525 lines in the vertical direction. (See Fig. 15)

[0007] Figure 16 is a diagram showing the spatial frequency characteristics of the interlaced image, so to speak, the space at the time of converting the non-interlaced image field frequency 60 Hz, the 525 scanning lines of an interlaced image having the frequency spectrum shown in FIG. 15 The graph shows frequency characteristics (frequency spectrum). In the figure, the horizontal axis represents the spatial frequency in the time axis direction, and the vertical axis represents the spatial frequency in the vertical direction. Flicker that occurs when a non-interlaced image is converted to an interlaced image occurs because a high-frequency component in the vertical direction returns to a low-frequency component in the vertical direction when viewed from the time axis direction. The hatched portion in the figure corresponds to a folded portion (flicker component) of a high frequency component in the vertical direction when viewed from the time axis direction.

FIG. 17 is a diagram showing characteristics (frequency spectrum) on the two-dimensional frequency of the interlaced image shown in FIG. In the figure, the horizontal axis is the horizontal spatial frequency,
The vertical axis indicates the spatial frequency in the vertical direction. Note that, in the figure, the shaded portion is the above-described vertical aliasing component (flicker component) on a two-dimensional frequency. Therefore, flicker can be eliminated by suppressing the high frequency component in the vertical direction.

FIG. 18 is a block diagram of a conventional scanning line converter. In this conventional example, a case where a VGA signal based on the VGA standard is converted into an NTSC signal will be described. In the figure, reference numerals 1a to 1c denote input terminals for VGA signals (R, G, B signals based on the VGA standard), 2 denotes input terminals for VGA signal synchronization signals, and 3a to 3c denote input analog video signals as digital video signals. A / D conversion circuit (hereinafter referred to as an A / D conversion circuit or A / D) 4 is a VG input from an input terminal 2
A first synchronization detection circuit for detecting a vertical synchronization signal and a horizontal synchronization signal from the synchronization signal of the A signal, and a first synchronization detection circuit for generating a clock based on a synchronization signal output from the first synchronization detection circuit. PLL circuits 6a to 6c extract a first low frequency component of the input digital video signal in a vertical direction.
And a vertical memory low-pass filter (hereinafter referred to as a first VLPF) 7a to 7c are frame memories for storing digital video signals output from the first VLPFs 6a to 6c.

Reference numeral 8 denotes a line memory for the line memories 23a to 23b in the first VLPFs 6a to 6c (the structure of the first VLPF 6 is shown in FIG. 19 but will be described later in detail) and to the frame memories 7a to 7c. A first memory control circuit 9a to 9c for generating a digital video signal write / read control signal is provided with a digital / analog conversion circuit (hereinafter, referred to as a digital / analog conversion circuit) for converting a digital video signal output from the frame memories 7a to 7c into an analog video signal. D / A conversion circuit or D / A.) 10 denotes the input R, G and B signals as a luminance signal (hereinafter referred to as Y signal) and two color difference signals (hereinafter referred to as RY). Matrix circuit for converting the signal into a signal and a BY signal.)
Reference numeral 11 denotes a second PLL circuit that generates a clock based on a synchronization signal output from the second synchronization detection circuit 12;
Reference numeral 2 denotes a second synchronization detection circuit that detects a vertical synchronization signal, a horizontal synchronization signal, and the like from a TV-side synchronization signal input from the input terminal 16.

Reference numeral 13 denotes a synchronization adding circuit for adding a vertical synchronizing signal and a horizontal synchronizing signal to the Y signal output from the matrix circuit 10, and 14 denotes two color difference signals (RY signals, RY signals, And BY signal)
Are converted into a modulated color signal (hereinafter, referred to as a C signal), 15a and 15b are output terminals for a Y signal and a C signal, and 16 is an input terminal for a synchronization signal on the TV side.

FIG. 19 is a block diagram of the first VLPF 6 of the related art. In the figure, reference numeral 20 denotes an input terminal of a digital video signal, 21 denotes an input terminal of a memory control signal output from the first memory control circuit 8, 22 denotes output terminals of digital video signals, and 23a and 23b denote input digital signals. A line memory that delays a video signal by one line,
24a and 24b are multiplication circuits for multiplying the input digital video signal by 0.25, 25 is a multiplication circuit for multiplying the input digital video signal by 0.5, and 26 is an addition circuit. FIG. 20 is a diagram illustrating a frequency characteristic of the first VLPF 6. In the figure, the horizontal axis represents the spatial frequency in the vertical direction, and the vertical axis represents the amplitude characteristics.

The operation of the conventional scanning line converter will be described below with reference to FIGS. In this conventional example, VG
A case where a non-interlaced image input based on the A standard is converted into an interlaced image and output will be described. The R, G, and B signals input via the input terminals 1a to 1c are converted into digital signals by A / D conversion circuits 3a to 3c. On the other hand, the synchronization signal of the VGA signal input via the input terminal 2 is separated into a vertical synchronization signal and a horizontal synchronization signal by the first synchronization detection circuit 4. The first of the same period
Horizontal synchronizing signal separated by the detection circuit 4 is input to the first PLL circuit 5. The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronization signal. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the first memory control circuit 8. Note that the vertical synchronization signal and the horizontal synchronization signal detected by the first synchronization detection circuit 4 are also input to the first memory control circuit 8.

The first memory control circuit 8 uses the horizontal synchronization signal of the VGA signal output from the first synchronization detection circuit 4 to use the line memories 23a and 23a in the first VLPF 6
3b to generate a digital video signal write control signal and a read control signal. For example, when FIFO (first-in first-out) memories are used for the line memories 23a and 23b, the first memory control circuit 8 outputs a line address reset signal for writing and reading, a write and read enable signal (ENABL signal). ), And write and read clock signals are output. The first memory control circuit 8 uses the vertical synchronizing signal and the horizontal synchronizing signal output from the first synchronizing
7c are also generated. A specific control method of the frame memories 7a to 7c will be described later. In the conventional example, the FIFO memory is used as the line memories 23a and 23b in the first VLPF 6.

The R, G, and B signals converted into digital signals by the A / D conversion circuits 3a to 3c are converted into first VLPF signals.
6a to 6c. Hereinafter, the first method will be described with reference to FIG.
The operation of the VLPF 6 will be described. The digital video signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input digital video signal by one line and outputs it. The digital video signal output from the line memory 23a is input to the multiplication circuit 25 and the line memory 23b. In the line memory 23b, the line memory 23a
And outputs the input digital video signal with one line delay. The output of the line memory 23b is a multiplication circuit 2
4b.

The digital video signals input to the multiplication circuits 24a and 24b are multiplied by 0.25 and output.
(Specifically, the data is shifted by two bits and output.) The digital video signal input to the multiplication circuit 25 is output after being multiplied by 0.5. (Specifically, the data is shifted by one bit and output.) The outputs of the multiplication circuits 24a and 24b and the multiplication circuit 25 are added to the addition circuit 26.
And the high-frequency component in the vertical direction is removed.
2 to the frame memory 7. Note that FIG.
0 shows the frequency characteristics of the first VLPF 6. The line memories 23a and 23b are connected to the input terminals 21.
Based on the data write control signal and the data read control signal output from the first memory control circuit 8 via the first memory control circuit 8, the digital video signal is written into and read out from the memory based on the data read control signal.

The digital video signals from which high-frequency components in the vertical direction have been removed by the first VLPFs 6a to 6c are input to frame memories 7a to 7c. Hereinafter, the operation of writing the digital video signal into the frame memory 7 will be described. The first memory control circuit 8 outputs a control signal to the frame memory 7 for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal having a field frequency of 60 Hz. Specifically, the frame memory 7
A digital video signal input in a frame structure is converted into a field structure and written when writing to the device.

Hereinafter, a method of generating a data write control signal to the frame memory 7 output from the first memory control circuit 8 will be described. First, when a vertical synchronization signal is input from the first synchronization detection circuit 4, the first memory control circuit 8 sets a field of a digital video signal to be written to the frame memory 7 next. If the field setting result is the first field, a control signal for writing only odd lines to the frame memory 7 is generated. If the field setting result is the second field, a control signal for writing only even lines to the frame memory 7 is generated. appear. The above control is performed by using the horizontal synchronization signal output from the first synchronization detection circuit 4 to determine the even / odd lines. At this time, in this conventional example, control is performed such that only the effective video signal portion of the VGA signal is written into the frame memory 7.

The non-interlaced digital video signals input to the frame memories 7a to 7c are digital video signals having a field structure (digital video signals having an interlaced structure) based on the write control signal output from the first memory control circuit 8. And stored in the frame memories 7a to 7c. In this conventional example, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field. Therefore, when write the digital video signal of the non-interlaced structure to the frame memory 7, switching the field memory to be used for each field alternately. At that time, cut conversion EShin No. field memory are also output from the first memory control circuit 8 based on the field determination result.

On the other hand, T input through the input terminal 16
The vertical synchronization signal and the horizontal synchronization signal of the V-side synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. In the second PLL circuit 11, the second synchronization detection circuit 1
A reference clock on the television side is generated based on the horizontal synchronization signal detected in step 2. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the first memory control circuit 8. Note that the vertical synchronization signal, the horizontal synchronization signal, and the field determination result detected by the second synchronization detection circuit 12 are also input to the first memory control circuit 8.

In the first memory control circuit 8, a read control signal for reading an interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the field discrimination result on the television side. (A switching signal for the field memory, a data read address, a read control signal, etc.). In the frame memories 7a to 7c, the first memory control circuit 8
A digital video signal having an interlaced structure is read from the memory based on the read control signal output from the memory.

The interlaced digital video signals read from the frame memories 7a to 7c are input to D / A conversion circuits 9a to 9c. D / A conversion circuits 9a to
In step 9c, the input interlaced digital video signal is converted into an interlaced analog video signal. R output from the D / A conversion circuits 9a to 9c,
The G and B signals are converted by the matrix circuit 10 into a Y signal and two color difference signals (RY signal and BY signal).
Is converted to The Y signal output from the matrix circuit 10 is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronizing circuit 13. Note that the synchronization adding circuit 13 is a second synchronization detecting circuit 12.
A synchronization signal is generated based on a vertical synchronization signal, a horizontal synchronization signal, and a field discrimination result, which are output, and added to the Y signal.

The two color difference signals (RY signal and BY signal) are converted into a modulated color signal (C signal) by the chroma encoder circuit 14 and output via an output terminal 15b. At the time of chroma encoding (when two color difference signals are converted into modulated color signals), two chroma signals are output from the second sync detection circuit 12 based on the vertical sync signal, the horizontal sync signal, and the field determination result. Modulate the color difference signal. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

[0024]

Since the conventional scanning line conversion apparatus is configured as described above, flicker generated when converting a non-interlaced image to an interlaced image can be removed, but the frequency band in the vertical direction is reduced. Due to the limitation, the resolution in the vertical direction deteriorates. That is, the flicker component removed by the conventional scanning line conversion device includes a high-frequency component in the vertical direction, and simply limiting the band in the vertical direction lowers the vertical resolution. Problems such as the inability to read characters and the like arise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a scanning line conversion apparatus capable of visually reducing flicker and suppressing a decrease in vertical resolution. And

[0026]

According to a first aspect of the present invention, there is provided a scanning line conversion apparatus for converting a non-interlaced image input in units of one frame into an interlaced image in units of one field. Vertical low frequency component, vertical high frequency-horizontal low frequency component, and vertical
Separating means for separating and outputting a high-frequency component and a horizontal high-frequency component ;
Vertical high-frequency output from the separation unit - a first amplitude limiting means for limiting the amplitude of the horizontal low-frequency component, said separating means
Vertical low frequency component and vertical high frequency-horizontal high frequency component
And an adding means for adding the output of the first amplitude limiting means. The interlaced image of one field unit is obtained by thinning out a predetermined line from the non-interlaced image of one frame unit output from the adding means. It constitutes.

According to a second aspect of the present invention, there is provided a scanning line conversion apparatus according to the first aspect, wherein the separation means is inputted.
Separates and outputs vertical low-frequency components from non-interlaced images.
The first non-interruptable frequency separating means.
Output from the first frequency separating means from the race image
Subtracts the above vertical low frequency component and outputs the vertical high frequency component
A first subtraction means for outputting the output from the first subtraction means.
Vertical high-horizontal high frequency component from the vertical high frequency component
A second frequency separating means for outputting the separated frequency signal;
From the vertical high frequency component output from the calculating means,
The vertical height-horizontal height output from the frequency separation means of
Output a vertical high-horizontal low-pass component by subtracting
And two subtraction means .

[0028]

According to a third aspect of the present invention, a scanning line conversion apparatus separates a high-frequency component in the horizontal direction from a non-interlaced image input in the first or second aspect.
And the absolute value of the amplitude of the separated horizontal high-frequency component
A comparing means for comparing with a predetermined value and outputting a comparison result;
The amplitude limiting value of the first amplitude limiting means is calculated by the comparing means.
Configuration to switch based on the comparison result output
Used when the absolute value of the amplitude is equal to or less than the predetermined value.
The absolute value of the amplitude is equal to the predetermined value.
If it is larger than the value, it will be smaller than the above amplitude limit value
The first amplitude limiting means is configured to be controlled .

According to a fourth aspect of the present invention, there is provided a scanning line conversion device comprising: a vertical high frequency separation means for separating a vertical high frequency component from a non-interlaced image input in the first or second aspect; The horizontal high-frequency component of the vertical high-frequency component output from the high-frequency separation means is separated, and
Absolute value of the amplitude of the vertical high-frequency component in the horizontal direction
Has a comparing means for comparing the value with a predetermined value and outputting a comparison result,
The amplitude limiting value of the first amplitude limiting means is compared with the comparing means.
Is switched based on the comparison result output
Used when the absolute value of the amplitude is equal to or less than the predetermined value.
The absolute value of the amplitude is
It becomes smaller than the above amplitude limit value when it is larger than the fixed value
Thus, the first amplitude limiting means is configured to be controlled .

[0031]

[0032]

[0033]

Further, the scanning line conversion apparatus according to claim 5 of the present invention converts a non-interlaced image inputted in one frame unit into an interlaced image in one field unit in a horizontal direction from the inputted non-interlaced image. Third frequency separating means for separating the low-frequency component and the high-frequency component from each other, and first flicker removing means for removing the flicker component from the horizontal low-frequency component output from the third frequency separating means; A second method for removing flicker components from horizontal high-frequency components output from the third frequency separating means;
Flicker removing means, an adding means for adding the output of the first flicker removing means and the output of the second flicker removing means, and a predetermined line from a non-interlaced image of one frame unit output from the adding means. Interlacing conversion means for forming an interlaced image in units of one field by thinning out, and when removing a flicker component from the input non-interlaced image, suppressing the high-frequency component in the vertical direction by the first flicker removing means The degree is set to be greater than the degree of suppression of the high frequency component in the vertical direction by the second flicker removing means.

Further, the scanning line conversion apparatus according to claim 6 of the present invention converts a non-interlaced image input in units of one frame into an interlaced image in units of one field in a vertical direction from the input non-interlaced image. A fourth frequency separating means for separating a low-frequency component and a high-frequency component from each other, comparing the absolute value of the amplitude of the high-frequency component in the horizontal direction of the input non-interlace signal with a predetermined value, and outputting a comparison result Means, second amplitude limiting means for limiting the amplitude of the high-frequency component in the vertical direction output from the fourth frequency separating means, and low-frequency component in the vertical direction output from the fourth frequency separating means. And an adder for adding the output of the second amplitude limiter, and switching the amplitude limit value of the second amplitude limiter based on the comparison result output from the comparator. As well as so that control is to configured to generate an interlaced image of one field unit by thinning out predetermined line from non-interlaced image of one frame which is outputted from said adding means.

In a scanning line conversion apparatus according to a seventh aspect of the present invention, in the sixth aspect , the comparing means includes the comparing means for converting the high frequency component in the horizontal direction of the vertical high frequency component output by the fourth frequency separating means. Separated and configured to compare the absolute value of the amplitude of the separated high-frequency component in the horizontal direction with a predetermined value, the amplitude limit value used when the absolute value of the amplitude is equal to or less than the predetermined value, The second amplitude limiter is controlled so as to be smaller than the amplitude limit value when the absolute value of the amplitude is larger than the predetermined value.

[0037]

Further, the scanning line converting apparatus according to claim 8 of the present invention, in the scanning line converting apparatus for converting a non-interlaced image to an interlaced image of one field unit is input frame by frame, the non-interlaced input Separating means for separating and outputting a vertical low frequency component and a vertical high frequency-horizontal high frequency component from an image, and amplitude converting means for converting the amplitude of the vertical high frequency-horizontal high frequency component output from the separating means And an adding means for adding the vertical low-frequency component output from the separating means and the output from the amplitude converting means, wherein a predetermined line is thinned out from the non-interlaced image of one frame unit output from the adding means. This constitutes an interlaced image on a field-by-field basis.

Further, the claims of the present invention9Flicker removal
The device removes the input non-interlaced video signal.
This occurs when converting to an interlaced video signal and displaying it.
Which removes flickering from the input video signal.
Vertical low frequency component, vertical high frequency-horizontal low frequency component, vertical high frequency
Separating means for separating and outputting the horizontal high-frequency component;
Amplitude of vertical high-horizontal low-frequency component output from separation means
From the first amplitude limiting means for limiting the
A vertical low-frequency component and a vertical high-frequency component that is applied;
Adding means for adding the output of the first amplitude limiting means.
Have Claims10Flicker removal
Claims:9In the above, the separation means is input
The vertical low-frequency component from the non-interlaced image
First frequency separating means for outputting, and input non-in
From the taresure image, the first frequency
The above vertical low frequency component is subtracted to produce a vertical high frequency component.
First subtraction means for applying the force, and an output from the first subtraction means.
Vertical high-horizontal high frequency component from the vertical high frequency component
A second frequency separating means for separating and outputting the signal;
From the vertical high frequency component output from the calculating means,
The vertical height-horizontal height output from the frequency separation means of
Output a vertical high-horizontal low-pass component by subtracting
2 subtraction means. In addition,
Request11The flicker removing device according to the claim9Or a contract
Request10High frequency component in the horizontal direction from the input video signal at
To separate the amplitude of the separated high-frequency component in the horizontal direction.
There is a comparison unit that compares the pair value with a predetermined value and outputs the comparison result.
Then, the amplitude limit value of the first amplitude limiter is set in the comparison
Switching based on the comparison result output from the stage
It is configured. Claims12Pretend pertaining to
Claims:9Or claims10Enter at
Vertical high-frequency separation unit that separates vertical high-frequency components from force video signals
And a vertical high frequency component output from the vertical high frequency separating means.
The high frequency component in the horizontal direction is separated by
The absolute value of the amplitude of the high-frequency component in the horizontal direction of the
And comparing means for comparing and outputting a comparison result.
The amplitude limiting value of the amplitude limiting means is output from the comparing means.
Switching based on the comparison result.
The above used when the absolute value of the amplitude is equal to or less than the predetermined value.
The amplitude limit value is such that the absolute value of the amplitude is greater than the predetermined value.
Threshold value so that it becomes smaller than the amplitude limit value
1 to control the first amplitude limiting means.
You. Claims13The flicker removal device according to
Non-interlaced video signals
Flicker that occurs when converting and displaying video signals
When removing, the low frequency components and high frequencies in the horizontal direction
A third frequency separating means for separating a frequency component;
From the horizontal low-frequency component output from the frequency separation means
First flicker removing means for removing flicker;
High-frequency component in the horizontal direction output from the frequency separation means 3
A second flicker removing means for further removing flicker;
The output of the first flicker removing means and the second flicker removal
Means for adding the output of the means
When removing flicker more, the first flicker removing means
The degree of suppression of the high frequency component in the vertical direction by the step
Greater than the degree of suppression of high frequency components in the vertical direction by the power removal means
It is configured so as to be set well. Claims
14The flicker elimination device according to
-Converts a race video signal to an interlace video signal
When removing flicker that occurs when displaying
The second one separates the low frequency component and high frequency component in the vertical direction from the image signal.
4 frequency separating means, and a high frequency band in the horizontal direction of the input video signal.
Compares the absolute value of the component amplitude with a predetermined value and outputs the comparison result
Output from the comparing means and the fourth frequency separating means.
A second amplitude limiter for limiting the amplitude of the high frequency component in the vertical direction
And the vertical frequency output from the fourth frequency separating means.
Adder for adding the low-frequency component and the output of the second amplitude limiting means
And an amplitude limit value of the second amplitude limiting means.
Switching based on the comparison result output from the comparing means
It is configured as follows. ClaimsFifteenPertaining to
Claims:14In the above comparison means
With the vertical high frequency component output by the fourth frequency separating means.
Minute high-frequency component in the horizontal direction, and
The absolute value of the amplitude of the high-frequency component in the direction is compared with a predetermined value.
Is what it does. Claims16Pertaining to flicker
Claims:14The absolute value of the above amplitude
The amplitude limit value used when the value is equal to or less than the predetermined value,
When the absolute value of the amplitude is larger than the predetermined value,
The second amplitude limiting means so as to be smaller than the width limiting value.
Is controlled. Claims17Pretend pertaining to
The non-interlaced video that is input
When converting a signal to an interlaced video signal for display
It removes flicker that occurs, and
Vertical high frequency component and vertical high frequency component-horizontal high frequency component
Separating means for outputting as output, and output from the separating means.
Amplitude conversion means for converting the amplitude of a vertical high-frequency component
And the vertical low-frequency component output from the separating means and the vibration
Having an adding means for adding the output of the width converting means.
You.

[0040]

In the scanning line conversion apparatus according to the first aspect of the present invention, when a non-interlaced image input in units of one frame is converted into an interlaced image in units of one field, first, a non-interlaced image input first is used.
Vertical low frequency component, vertical high frequency-horizontal low frequency component, vertical high frequency
-Output separately from the horizontal high frequency component . Next, the amplitude of the separated vertical high band-horizontal low band component is limited by using a first amplitude limiting unit. And vertical low frequency component and vertical
A high-horizontal high-frequency component and the vertical-high-horizontal low-frequency component subjected to the amplitude limitation output from the first amplitude limiting means are added, and the added flicker component is removed for each frame. A predetermined line is thinned out from the non-interlaced image of (1) to generate an interlaced image in units of one field.

According to a second aspect of the present invention, there is provided a scanning line conversion apparatus, wherein:
Non-interlace input by the frequency separation means 1
The vertical low frequency component is separated from the image and output, and the first subtraction
In the step, from the input non-interlaced image,
The vertical low frequency component output from the frequency separation means
By performing the subtraction, the vertical high frequency component is output, and the second
The wave number separating means outputs the signal from the first subtracting means.
The vertical high-frequency component is separated from the vertical high-frequency component
And output from the first subtraction means by the second subtraction means.
The second frequency separation from the applied vertical high frequency component
Subtract the vertical high-horizontal component output from the means
By doing so, a vertical high-frequency component and a horizontal low-frequency component are output.

[0042]

According to a third aspect of the present invention, in the scanning line conversion apparatus according to the first or second aspect, first, a high-frequency component in the horizontal direction is separated from a non-interlaced image input first , and the separation is performed. Horizontal high-frequency component
Is compared with a predetermined value, and a comparison result is output.
Then, the amplitude limit value of the first amplitude limiter is set to the above-mentioned ratio.
Switching based on the comparison result output from the comparison means
You. At this time, when the absolute value of the amplitude is equal to or less than the predetermined value.
The absolute value of the amplitude is
Smaller than the above amplitude limit value when it is larger than the predetermined value
To become .

Further, in the scanning line conversion apparatus according to a fourth aspect of the present invention, in the first or second aspect, first, a vertical high frequency component is separated from a non-interlaced image input first. Also output from the vertical high-frequency separation means
The horizontal high-frequency component of the vertical high-frequency component
The amplitude of the horizontal high frequency component of the separated vertical high frequency component
The absolute value is compared with a predetermined value and a comparison result is output. And above
The amplitude limiting value of the first amplitude limiting means is calculated by the comparing means.
Switching is performed based on the comparison result output. On this occasion,
Used when the absolute value of the amplitude is equal to or less than the predetermined value.
The amplitude limit value is such that the absolute value of the amplitude is greater than the predetermined value.
Make it smaller than the above amplitude limit value when it is large
You.

[0045]

[0046]

[0047]

In the scanning line conversion apparatus according to the fifth aspect of the present invention, when converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, the non-interlaced image input first Separate the low-frequency component and the high-frequency component in the horizontal direction.
Next, a flicker component is removed from the separated low-frequency component in the horizontal direction by using a first flicker removing unit. Similarly, a flicker component is removed from the separated high-frequency component in the horizontal direction by using a second flicker removing unit. Then, the adding means adds the horizontal low-frequency component from which the flicker component has been removed by the first flicker removing means and the horizontal high-frequency component from which the flicker component has been removed by the second flicker removing means. Then, a predetermined line is thinned out from the non-interlaced image of one frame unit output from the adding means to generate an interlaced image of one field unit. At this time, the degree of suppression of the high frequency component in the vertical direction by the first flicker removing means is set to be larger than the degree of suppression of the high frequency component in the vertical direction by the second flicker removing means.

In the scanning line conversion apparatus according to the sixth aspect of the present invention, when converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, the first input non-interlaced image is used. The low frequency component and the high frequency component in the more vertical direction are separated.
The absolute value of the amplitude of the high frequency component in the horizontal direction of the input non-interlace signal is compared with a predetermined value. Next, the amplitude of the separated high frequency component in the vertical direction is limited by the second amplitude limiting means. Then, the vertical low-frequency component separated by the adding means is added to the output of the second amplitude limiting means. In addition, control is performed so that the amplitude limit value of the second amplitude limiter is switched based on the result of the comparison, and a predetermined line is thinned out in one-field units from one-frame non-interlaced images output from the adder. Generate an interlaced image.

According to a seventh aspect of the present invention, in the scanning line conversion apparatus according to the sixth aspect , the high frequency component in the horizontal direction of the vertical high frequency component outputted by the fourth frequency separating means is separated. The absolute value of the amplitude of the separated high-frequency component in the horizontal direction is compared with a predetermined value. Then, the amplitude limit value used when the absolute value of the amplitude is equal to or smaller than the predetermined value is controlled to be smaller than the amplitude limit value when the absolute value of the amplitude is larger than the predetermined value.

[0051]

[0052]

In the scanning line conversion apparatus according to the eighth aspect of the present invention, when converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, the non-interlaced image input first The vertical low-frequency component and the vertical high-frequency component are separated and output. Then, the amplitude of the vertical high-frequency component is converted. Then, the separated vertical low-frequency component and the output of the amplitude converting means are added by an adding means. Then, a predetermined line is thinned out from the non-interlaced image of one frame unit output from the adding means to generate an interlaced image of one field unit.

[0054]

【Example】

Embodiment 1 FIG. FIG. 1 is a block diagram of a scanning line conversion apparatus according to the first embodiment of the present invention. Note that also in the first embodiment,
A VGA signal based on the VGA standard is converted to NTS
The case of converting to a C signal (interlace signal) will be described. In the figure, reference numerals 1a to 1c denote VGA signals (VG
R, G, B signal input terminals based on A standard), 2 is VG
An input terminal of a synchronization signal of the A signal, 3a to 3c are an A / D conversion circuit for converting a luminance signal (Y signal) in the matrix circuit 10 and an analog video signal converted into two color difference signals into a digital video signal, Is a first synchronization detection circuit for detecting a vertical synchronization signal and a horizontal synchronization signal from the synchronization signal of the VGA signal input from the input terminal 2, and 5 is based on the synchronization signal output from the first synchronization detection circuit 4. The first PLL circuits 7a to 7c for generating clocks are a luminance signal (Y signal) output from the flicker removing circuit 31, and two color difference signals (RY) output from the A / D conversion circuits 3b and 3c. Signal and a BY signal).

Reference numerals 9a to 9c denote D / A conversion circuits for converting digital video signals output from the frame memories 7a to 7c into analog video signals, and 10 denotes input R, G, B.
A matrix circuit 11 for converting the signal into a Y signal and two color difference signals (RY signal and BY signal); A second PLL circuit for generating a clock, 1
Reference numeral 2 denotes a second synchronization detection circuit that detects a vertical synchronization signal, a horizontal synchronization signal, and the like from a TV-side synchronization signal input from the input terminal 16.

Reference numeral 13 denotes a synchronization adding circuit for adding a vertical synchronizing signal and a horizontal synchronizing signal to the Y signal output from the D / A conversion circuit 9a, and 14 denotes two color difference signals output from the D / A conversion circuits 9b and 9c. (RY signal and BY signal
Signal) to a modulated color signal (C signal), 15a and 15b are output terminals for a Y signal and a C signal, respectively, and 16 is an input terminal for a synchronizing signal on the TV side.

Reference numerals 30a and 30b denote band-limiting filters (hereinafter, referred to as LPFs) for restricting horizontal signal bands of the RY signal and the BY signal output from the matrix circuit 10, respectively. A flicker elimination circuit 32 for eliminating a flicker component in the Y signal includes line memories 23a and 23b in the flicker elimination circuit 31;
43 (the configuration of the flicker removal circuit 31 is shown in FIG. 2 but will be described later in detail), and the frame memory 7
and a second memory control circuit for outputting a digital video signal write / read control signal to / from a to 7c.
The first VLPF 6 in the flicker removal circuit 31 is
As in the conventional example, it is assumed that the configuration is as shown in FIG.

FIG. 2 shows a flicker removing circuit 31 in FIG.
FIG. 3 is a block diagram of the configuration of FIG. In the figure, reference numeral 6 denotes a first VLPF for extracting a low-frequency component of a digital video signal (Y signal) in the vertical direction; 40, an input terminal of the Y signal; 41, a memory control output from the second memory control circuit 32; Signal input terminal, 42 is a Y signal output terminal, 43 is the input Y
A line memory 44 for delaying the signal by one line, and a subtraction circuit 44 for subtracting the vertical low frequency component output from the first VLPF 6 from the Y signal delayed by one line output from the line memory 43, are provided. By subtracting the output of the first VLPF 6 from the output of the line memory 43, the vertical high frequency component of the input Y signal is separated. Reference numeral 45 denotes a first horizontal high-pass filter (hereinafter, referred to as a first HHPF) that separates a horizontal high-frequency component from a vertical high-frequency component output from the subtraction circuit 44. The register 47 is an addition circuit.

FIG. 3 is a block diagram of the first HHPF 45 in FIG. In the figure, reference numeral 50 denotes an input terminal for a digital video signal (a vertical high-frequency component of a Y signal);
51 is an output terminal, 52a and 52b are registers for delaying the input high-frequency component of the Y signal in the vertical direction by one clock, and 53a and 53b are -0. Multiplication circuit for multiplying 25, 5
4 is 0 in the vertical high-frequency component of the input Y signal.
A multiplication circuit for multiplying 5 and an addition circuit 55 are provided. FIG. 4 is a diagram for explaining the basic concept of the flicker removal circuit 31 according to the first embodiment of the present invention. FIG.
2 shows a characteristic (frequency spectrum) on a two-dimensional frequency. In the figure, the horizontal axis represents the spatial frequency in the horizontal direction, and the vertical axis represents the spatial frequency in the vertical direction.

Hereinafter, the concept of the first embodiment will be briefly described. As described in the conventional example, the vertical high-frequency component indicated by hatching in FIG. 17 includes a vertical resolution component in addition to the flicker component. In the conventional scanning line conversion device, since the vertical high frequency component is also removed together with the flicker component, the resolution in the vertical direction is reduced, and there has been a problem that fine characters on a display cannot be read.

The concept of the first embodiment will be described below with reference to FIG. Generally, flicker occurring in a large area is much more visually noticeable than flicker occurring in a small area. That is,
Flicker generated in a fine character portion or the like is not visually noticeable, whereas flicker generated in a horizontal line portion of a diagram or a table is visually noticeable. When human eyes visually detect flicker, it is detected that flicker has occurred up to an image around the flicker, and it appears that flicker has occurred in a large area.

In the first embodiment, a vertical resolution component in which the flicker is visually inconspicuous is separated from the vertical high-frequency component which is a factor for generating the large area flicker. Then, the vertical resolution component is improved by adding the separated vertical resolution component to the image from which the vertical high frequency component has been removed. The above operation adds a vertical resolution component in which visual flicker is inconspicuous to the output image, so that the occurrence of flicker can be suppressed, and the vertical resolution in fine character portions is improved, so that fine characters can be recognized. it can. FIG. 4 shows frequency characteristics on a two-dimensional frequency of the first embodiment. In the figure, the hatched portion is the flicker component that is very noticeable visually. In the first embodiment, as shown in FIG. 4, a horizontal high-frequency component that is visually inconspicuous of flicker is separated from the separated vertical high-frequency component, and the separated horizontal high-frequency component is output to an output image. The feedback (addition) improves the resolution in the vertical direction.

The operation of the scanning line conversion apparatus according to the first embodiment will be described below with reference to FIGS. 1 to 4 and FIG. In addition,
Also in the first embodiment, a case will be described in which a non-interlaced image input based on the VGA standard is converted into an interlaced image and output as in the conventional example. The R, G, and B signals input through the input terminals 1a to 1c are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10. Two color difference signals (R-
YF and BY signals) are supplied to LPFs 30a and 30
At 0b, the horizontal band is limited to half. (Because the color difference signal is less noticeable than the luminance signal (Y signal), the image quality hardly deteriorates even if the signal band is limited to half.) The Y signal output from the matrix circuit 10 and the LPFs 30a and 30b RY output from
And BY signals are converted into digital video signals (digital signals) by A / D conversion circuits 3a to 3c. At this time, the signal band of the two color difference signals is LP as described above.
Since the signal is limited to half of the Y signal in F30a and F30b, the sampling clock at the time of A / D conversion is set to half of the sampling clock of the Y signal and converted to a digital video signal.

On the other hand, the VG input through the input terminal 2
The vertical synchronization signal and the horizontal synchronization signal are detected by the first synchronization detection circuit 4 from the synchronization signal of the A signal. The horizontal synchronization signal detected by the first synchronization detection circuit 4 is supplied to a first PLL circuit 5
Is input to The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronization signal. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the second memory control circuit 32. At that time, as described above, the clock used for processing the two color difference signals is frequency-divided and output to half the frequency of the clock used for processing the Y signal. The vertical synchronization signal and the horizontal synchronization signal detected by the first synchronization detection circuit 4 are also input to the second memory control circuit 32.

The second memory control circuit 32 uses the horizontal synchronizing signal of the VGA signal output from the first synchronizing detecting circuit 4 to use the line memory 23a in the flicker removing circuit 31.
23b and a digital video signal write control signal and a read control signal for the line memory 43 are generated. For example, when the line memories 23a to 23b and the line memory 43 are configured using FIFO memories as in the conventional example, the second memory control circuit 32 outputs a line address reset signal for writing and reading, a writing and reading operation. Enable signal (ENABL signal),
Also, write and read clock signals are output. The second memory control circuit 32 also generates a control signal for writing a digital video signal to the frame memories 7a to 7c using the vertical synchronization signal and the horizontal synchronization signal output from the first synchronization detection circuit 4. A specific control method of the frame memories 7a to 7c will be described later.

The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31.
Hereinafter, the operation of the flicker removal circuit 31 will be described with reference to FIG. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. Here, the operation of the first VLPF 6 will be described with reference to FIG. The Y signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input Y signal by one line and outputs it. The Y signal output from the line memory 23a is input to the multiplication circuit 25 and the line memory 23b. In the line memory 23b, similarly to the line memory 23a, the input Y signal is delayed by one line and output. The output of the line memory 23b is input to the multiplication circuit 24b. The line memories 23a and 23b are controlled by using the data write and read control signals output from the second memory control circuit 32 via the input terminal 21.

The Y signals input to the multiplying circuits 24a and 24b are each multiplied by 0.25 and output. The Y signal input to the multiplication circuit 25 is multiplied by 0.5 and output. The outputs of the multiplying circuits 24a and 24b and the multiplying circuit 25 are added by the adding circuit 26 to remove high-frequency components in the vertical direction, and are output from the first VLPF 6 via the output terminal 22. On the other hand, the Y signal input to the line memory 43 shown in FIG. 2 is output after being delayed by one line. The line memory 43 is controlled by:
The operation is performed using the data write and read control signals output from the second memory control circuit 32 via the input terminal 41.

In the subtraction circuit 44, the first VLP is obtained from the Y signal delayed by one line output from the line memory 43.
The vertical high frequency component of the Y signal is separated by subtracting the vertical low frequency component of the Y signal output from F6.
(In the line memory 43, the Y signal is delayed by one line in order to match the phase of the input Y signal with the vertical low-frequency component output from the first VLPF 6.) The output of the subtraction circuit 44 The signal is input to the first HHPF 45.
Hereinafter, the operation of the first HHPF 45 will be described with reference to FIG.

The vertical high frequency component of the Y signal input via the input terminal 50 is supplied to the register 52a and the multiplication circuit 5
3a. The vertical high frequency component of the Y signal delayed by one clock in the register 52a is input to the register 52b and the multiplier 54. The vertical high frequency component of the Y signal delayed by one clock in the register 52b is added to the multiplication circuit 53.
b. The vertical high frequency component of the Y signal input to the multiplication circuits 53 a and 53 b is multiplied by −0.25 and output to the addition circuit 55. Similarly, the vertical high frequency component of the Y signal input to the multiplication circuit 54 is multiplied by 0.5 and
5 is input. In the addition circuit 55, the multiplication circuits 53a,
The vertical high frequency components of the Y signal output from 3b and 54 are added to separate a high frequency component in the horizontal direction (vertical high frequency component-horizontal high frequency component of the Y signal). The vertical high band-horizontal high band component of the Y signal separated by the adding circuit 55 is output via the output terminal 51. The registers 52a and 52b in the first HHPF 45 and the flicker removal circuit 31
The clock is supplied from the first PLL circuit 5 to the register 46 inside.

The vertical high-horizontal high-frequency component of the Y signal separated by the first HHPF 45 is input to the adding circuit 47.
On the other hand, the vertical low frequency component of the Y signal output from the first VLPF 6 is delayed by one clock in the register 46 and input to the adding circuit 47. (In the register 46, the vertical low-frequency component of the Y signal output from the first VLPF 6 and the first
In order to match the phase with the vertical high-frequency component of the Y signal output from the HHPF 45, the vertical low-frequency component of the Y signal is delayed by one clock. ) The adding circuit 47 adds the output of the first HHPF 45 and the output of the register 46.

The Y signal from which the flicker component has been removed by the flicker removing circuit 31, and the A / D conversion circuits 3b and 3
Two color difference signals (RY signal and BY signal) output from c are input to the frame memories 7a to 7c. Hereinafter, the operation of writing the digital video signal into the frame memory 7 will be described. The second memory control circuit 32 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal at a field frequency of 60 Hz. Specifically, a digital video signal input in a frame structure at the time of writing to the frame memory 7 is converted into a field structure and written.

Hereinafter, a method of generating a data write control signal to the frame memory 7 output from the second memory control circuit 32 will be described. First, when a vertical synchronization signal is input from the first synchronization detection circuit 4, the second memory control circuit 32 sets a field to be written to the frame memory 7 next. When the field setting result is the first field, a control signal for writing odd lines to the frame memory 7 is generated, and when the field setting result is the second field, a control signal for writing even lines to the frame memory 7 is generated. . The above control uses the horizontal synchronization signal output from the first synchronization detection circuit 4 to determine the even / odd line and generate the control signal. that time,
In the first embodiment, the frame memory 7 is used in the same manner as in the conventional example.
Is controlled so that only the effective video signal portion of the VGA signal is written.

The non-interlaced digital video signals input to the frame memories 7a to 7c are converted into field-structured digital video signals (interlaced digital video signals) based on the write control signal output from the second memory control circuit 32. ) And stored in the frame memories 7a to 7c. Example 1
In this case, as in the conventional example, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field. Therefore, in the second memory control circuit 32, to write the digital video signal converted into interlaced structure to the frame memory 7, a cut conversion No. EShin of the two field memories generated based on the field determination result . Further, in the second memory control circuit 32, a data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 is detected by the first synchronization detection circuit 4. Generated based on the vertical and horizontal synchronization signals.

On the other hand, the T input through the input terminal 16
The vertical synchronization signal and the horizontal synchronization signal of the V-side synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. The second PLL circuit 11 generates a television-side reference clock based on the horizontal synchronization signal detected by the second synchronization detection circuit 12. At this time, the frequency of the sampling clock of the color difference signal is divided to half the frequency of the sampling clock of the Y signal. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the second memory control circuit 32. The vertical synchronization signal, the horizontal synchronization signal, and the field determination result detected by the second synchronization detection circuit 12 are also input to the second memory control circuit 32.

The second memory control circuit 32 reads out the interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the result of field discrimination. Memory switching signal, data read address, read control signal, etc.). In the frame memories 7a to 7c, digital video signals having an interlaced structure are read from the memories based on the read control signals output from the second memory control circuit 32.

The digital video signals of the interlaced structure read from the frame memories 7a to 7c are D / A
The signals are input to the conversion circuits 9a to 9c. D / A conversion circuit 9a
In 9c, the input interlaced digital video signal is converted into an interlaced analog video signal. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronization adding circuit 13. It should be noted that the synchronization adding circuit 13 includes the second synchronization detecting circuit 1
A synchronization signal is generated based on a vertical synchronization signal, a horizontal synchronization signal, and a field discrimination result output from 2, and added to the Y signal.

The two color difference signals (RY signal and BY signal) output from the D / A conversion circuits 9b to 9c are converted into modulated color signals (C signals) by the chroma encoder circuit 14 and output. Output via the terminal 15b. At the time of chroma encoding (when two color difference signals are converted into modulated color signals), two chroma signals are output from the second sync detection circuit 12 based on the vertical sync signal, the horizontal sync signal, and the field determination result. Modulate the color difference signal. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

In the first embodiment, the VGA signal input in the state of the R, G, B signals is converted into a Y signal and two color difference signals (RY signal and BY signal) in the matrix circuit 10 in advance. After that, the signal processing is performed. This is for the following two reasons.

The first reason is due to the flicker detection characteristics of the human eye. Human vision detects the flicker occurring in the Y signal very sensitively, but is less sensitive to the flicker occurring in the color difference signal. As a result of performing flicker removal on the two color difference signals by computer simulation based on the above algorithm, almost no effect was obtained with respect to flicker removal as compared with a case where flicker removal was not performed. On the other hand, in the image from which flicker has been removed, the vertical resolution of the color difference signal is significantly reduced.

As for the image (video) input in the state of the R, G, B signals, as shown in the conventional example,
Unless flicker removal is performed on all image data of the G and B signals, visually detectable flicker cannot be removed. Therefore, in the first embodiment, after the input image data (R, G, B signals) are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10, Y
A flicker removing circuit 31 is provided only in the signal processing system of the signal to remove flicker components. As a result, flicker removal is not performed on a color difference signal in which a flicker component is visually inconspicuous, so that the number of flicker removal circuits 31 can be reduced from three to one as compared with a conventional scanning line conversion device. In addition, since the flicker is not removed from the color difference signal in which flicker is not noticeable, a sufficient resolution component in the vertical direction can be ensured, so that a reduction in the resolution of the output image can be minimized.

The second reason is due to the visual characteristics of the human to the color difference signal. This is because human vision is sensitive to changes in the Y signal, but not so sensitive to changes in the color difference signal. That is, the above 2
Even if the horizontal signal band of two color difference signals (RY signal and BY signal) is half of the Y signal, the difference (color signal band difference) cannot be detected by human eyes. Therefore, in the first embodiment, the two color difference signals output from the matrix circuit 10 are converted into the LPFs 30a and 30b.
To limit the horizontal signal band to half. When the two color difference signals output from the LPFs 30a and 30b are converted into digital signals (digital video signals) by the A / D conversion circuits 3b and 3c, the frequency of the sampling clock is half the frequency of the sampling clock of the Y signal. Do. Therefore, since the number of data of the color difference signal per one frame can be halved as compared with the conventional example, can be reduced to half the memory capacity of the frame memory 7b and 7c, it is possible to reduce the circuit scale effective. Further, since the clock frequency of the processing system for the two color difference signals can be halved, when the scanning line converter or the flicker removing circuit 31 is formed into an LSI,
There is an effect that power consumption can be suppressed .

Since the scanning line conversion device of the first embodiment is configured as described above, a horizontal high-frequency component in which flicker is not visually noticeable is extracted from a vertical high-frequency component.
By feeding back (adding) to the output image (vertical low-frequency component), the resolution in the vertical direction can be improved, and flicker can be sufficiently suppressed visually. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the scanning line conversion method by computer simulation,
Although flicker of a small area slightly occurred in a diagonal line portion of a character (a position at a viewing distance of about 1H), the resolution in the vertical direction was improved, and the identification of fine characters was also improved as compared with the conventional example. The detected small area flicker was not detected from a position about 3H away from the screen.

Further, the flicker elimination circuit 31 shown in the first embodiment can be realized only by adding a simple circuit to the first VLPF 6 of the related art, and is excellent without greatly increasing the circuit scale. There is an effect that an output image can be obtained.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to FIGS. 1, 3 to 6, and FIG. FIG. 5 is a block diagram of the flicker removal circuit 31 of the scanning line conversion device according to the second embodiment of the present invention. In the drawings, components denoted by the same reference numerals as those in the first embodiment have the same configuration and operation, and thus detailed description is omitted. Reference numeral 60 denotes a register, 61 denotes a subtraction circuit, and 62 denotes an amplitude limiting circuit (hereinafter, referred to as an amplitude limiting circuit).
Described as a limiter circuit or a limiter. ) And 63 are addition circuits. FIG. 6 is a diagram illustrating input / output characteristics of the limiter 62 according to the second embodiment. In the figure, the horizontal axis is input,
The vertical axis corresponds to the output. The input / output characteristics of the limiter 62 are not limited to those shown in FIG.

Next, the concept of the second embodiment will be briefly described. In the first embodiment, as shown in FIG. 4, the horizontal high-frequency component in which flicker is visually inconspicuous is extracted from the vertical high-frequency component, and is fed back (added) to the output image to sufficiently suppress the flicker. The direction resolution has been improved. The purpose of the second embodiment is to suppress the occurrence of flicker and further increase the resolution in the vertical direction. In the second embodiment, a vertical resolution component is further extracted from a horizontal low-frequency component in a vertical high-frequency component indicated by hatching in FIG. 4 and fed back (added) to an output image.
By doing so, the resolution in the vertical direction is improved. Specifically, the flicker detected by human eyes depends on the amplitude of the high frequency component in the vertical direction in addition to the flicker occurrence area described in the first embodiment. That is, even if flicker occurs, a small amplitude component of a high-frequency component in the vertical direction is not visually noticeable (cannot be detected).

In the second embodiment, the vertical resolution component in which flicker is not visually noticeable is separated according to the amplitude of the high frequency component in the vertical direction. Then, the vertical resolution component is improved by adding the separated vertical resolution component to the image from which the vertical high frequency component has been removed. The above operation adds a vertical resolution component in which visual flicker is inconspicuous to the output image, thereby improving the vertical resolution particularly in fine character portions, suppressing occurrence of flicker, and recognizing fine characters. be able to. In the second embodiment, the resolution component in the vertical direction is separated and output from the hatched area in the figure in which the high frequency component in the vertical direction and the low frequency component in the horizontal direction on the two-dimensional frequency shown in FIG. The case of returning to an image will be described. Therefore,
In the second embodiment, the vertical resolution component is extracted from the vertical high band-horizontal low band component removed in the first embodiment and is fed back (added) to the output image, thereby further increasing the vertical resolution. Can be improved.

Hereinafter, the operation of the scanning line conversion device according to the second embodiment of the present invention will be described with reference to FIGS. 1, 3 to 6, and 19. In the second embodiment, only the configuration of the flicker removing circuit 31 is different, and the other circuit operations are the same. Also in the second embodiment, a case will be described in which a non-interlaced image input based on the VGA standard is converted into an interlaced image and output as in the conventional example. The R, G, and B signals input via the input terminals 1a to 1c are converted by the matrix circuit 10 into a Y signal and two color difference signals. The two color difference signals output from the matrix circuit 10 are L
The horizontal band is limited to half by the PFs 30a and 30b. A Y signal output from the matrix circuit 10,
The two color difference signals output from the LPFs 30a and 30b are converted into digital video signals by A / D conversion circuits 3a to 3c. At this time, the two color difference signals are Y
The signal is converted into a digital video signal by a half sampling clock of the signal.

On the other hand, VG input via input terminal 2
The vertical synchronization signal and the horizontal synchronization signal are detected by the first synchronization detection circuit 4 from the synchronization signal of the A signal. In the first PLL circuit 5, VG is determined based on the detected horizontal synchronizing signal.
A side reference clock is generated. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the second memory control circuit 32. that time,
As described above, the two clocks for the color difference signal are frequency-divided to half the frequency of the clock for the Y signal and output.

The second memory control circuit 32 uses the horizontal synchronizing signal of the VGA signal output from the first synchronizing detection circuit 4 to control the line memory 23a in the flicker removing circuit 31.
23b and a digital video signal write control signal and a read control signal for the line memory 43 are generated. In the second embodiment, as in the first embodiment, the line memories 23a to 23b and the line memory 43 are
It is assumed to be configured using an IFO memory. Therefore, from the second memory control circuit 32, a line address reset signal at the time of writing and reading, a write and read enable signal (ENABL signal), and a write and read clock are output to the flicker removal circuit 31. The second memory control circuit 32 also generates a control signal for writing a digital video signal to the frame memories 7a to 7c using the vertical synchronization signal and the horizontal synchronization signal output from the first synchronization detection circuit 4.

The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker elimination circuit 31.
The operation of the flicker removal circuit 31 will be described below with reference to FIGS. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. FIG. 19 shows a block diagram of the first VLPF 6. The detailed operation of the first VLPF 6 is described in the first embodiment.
Therefore, the description is omitted. On the other hand, the Y signal input to the line memory 43 is output after being delayed by one line.

The subtraction circuit 44 subtracts the vertical low-frequency component of the Y signal output from the first VLPF 6 from the Y signal delayed by one line in the line memory 43, and separates the vertical high-frequency component of the Y signal. . The output of the subtraction circuit 44 is input to the first HHPF 45 and the register 60. FIG. 3 shows a block diagram of the first HHPF 45. The detailed operation of the first HHPF 45 is the same as that of the first embodiment, and a description thereof will be omitted. On the other hand, the vertical high frequency component of the Y signal input to the register 60 is output after being delayed by one clock. The subtraction circuit 61 subtracts the vertical high-frequency component of the Y signal output from the first HHPF 45 from the vertical high frequency component of the Y signal delayed by one clock in the register 60. The vertical high band-horizontal low band component (vertical high band-horizontal low band data) of the Y signal output from the subtraction circuit 61 is input to a limiter 62.

The limiter 62 limits the amplitude of the vertical high band-horizontal low band component of the input Y signal and outputs it. FIG.
(A) shows the input / output characteristics of the limiter 62. Limiter 6
The vertical-high-horizontal-low-frequency component of the Y signal, the amplitude of which is limited by 2, is added to the vertical-high-horizontal-high-frequency component of the Y signal output from the first HHPF 45 by the adding circuit 63. The output of the addition circuit 63 (the resolution component in the vertical direction) is
At 7, it is added to the vertical low frequency component of the Y signal output from the register 46 and output. In the second embodiment, the limiter 62 separates small amplitude components (vertical resolution components) in which flicker is inconspicuous from the vertical high band-horizontal low band components of the Y signal. In the second embodiment, the vertical resolution is improved by feeding back (adding) the vertical high resolution component separated by the first HHPF 45 and the limiter 62 to the output image (vertical low frequency component). (In the case of Example 2, the result of computer simulation
The amplitude of the high frequency component in the vertical direction of the Y signal is -127 to 128
When the maximum value of the amplitude limit value was set to about ± 10 to ± 20, good results were obtained. ) Note that the first HH
A first PLL to PF45, registers 46 and 60
It is assumed that a clock is supplied from the circuit 5.

The Y signal from which the flicker component has been removed by the flicker removing circuit 31, and the A / D converting circuits 3b and 3
c are output from the frame memory 7
a to 7c. Note that the writing and reading of the digital video signal to and from the frame memory 7 are the same as in the first embodiment, and a detailed description of the operation will be omitted. The second memory control circuit 32 converts a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal having a field frequency of 60 Hz.
Write data to

In the second memory control circuit 32, when writing data to the frame memory 7, first, a field to be written to the frame memory 7 based on the vertical synchronization signal output from the first synchronization detection circuit 4 Set. When the field setting result is the first field, a control signal is generated so as to write odd lines to the frame memory 7 when the field setting result is the second field.
The control signal for line switching is generated by determining the even / odd line using the horizontal synchronization signal output from the first synchronization detection circuit 4.

The non-interlaced digital video signal input to the frame memories 7a to 7c is converted into a field-structured digital video signal based on the write control signal output from the second memory control circuit 32. 7c. In addition,
In the second embodiment, as in the first embodiment, it is assumed that the frame memory 7 includes two field memories for the first field and the second field. The second memory control circuit 32 sends a data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 in the first memory control circuit 32.
Is generated based on the vertical synchronization signal and the horizontal synchronization signal detected by the synchronization detection circuit 4.

On the other hand, the T input through the input terminal 16
The vertical synchronization signal and the horizontal synchronization signal of the V-side synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. The second PLL circuit 11 generates a television-side reference clock based on the horizontal synchronization signal detected by the second synchronization detection circuit 12. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the second memory control circuit 32. In the second memory control circuit 32, a read control signal (switching of the field memory) for reading an interlaced image stored in the frame memory 7 based on the vertical synchronization signal, the horizontal synchronization signal, and the field determination result. Signal, data read address, read control signal, etc.). In the frame memories 7a to 7c, digital video signals having an interlaced structure are read from the memories based on the read control signals output from the second memory control circuit 32.

The digital video signals of the interlaced structure read from the frame memories 7a to 7c are D / A
The conversion circuits 9a to 9c convert the signals into analog video signals having an interlaced structure. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronization adding circuit 13. The synchronization adding circuit 13 outputs a vertical synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal output from the second synchronization detection circuit 12.
The sync signal is generated based on the result of the field discrimination and added to the Y signal. Also, D / A conversion circuits 9b to 9c
The two color difference signals output from the color conversion circuit 14 are converted into a modulated color signal (C signal) by the chroma encoder circuit 14 and output from the output terminal 15.
b. At the time of chroma encoding, two color difference signals are modulated based on a vertical synchronization signal, a horizontal synchronization signal, and a field determination result output from the second synchronization detection circuit 12. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

In the second embodiment, the VGA signal input in the state of the R, G, and B signals is
, A Y signal and two color difference signals (R
The signal processing is performed after the conversion into the -Y signal and the BY signal).

In the second embodiment, similarly to the first embodiment, the input R, G, and B signals are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10.
After the conversion, the flicker removal circuit 31 removes the flicker component only from the Y signal, and does not remove the flicker component from the color difference signal in which the flicker component is visually inconspicuous. Thus, the number of flicker removing circuits 31 can be reduced from three to one.
In addition, since flicker is not removed from a color difference signal in which flicker is not conspicuous, a sufficient resolution component in the vertical direction can be secured, and a reduction in resolution of an output image can be minimized.

In the second embodiment, as in the first embodiment, two color difference signals output from the matrix circuit 10 are converted to LP signals.
F30a and 30b limit the horizontal signal band to half. The outputs of the LPFs 30a and 30b are A
The frequency of the sampling clock at the time of conversion into a digital video signal by the / D conversion circuits 3b and 3c is set to half the frequency of the sampling clock of the Y signal. Therefore,
Since the number of data of the color difference signal per frame can be halved as compared with the conventional example, the frame memory 7b
And 7c can be halved in memory capacity, and the circuit size can be reduced.

Since the scanning line conversion apparatus of the second embodiment is configured as described above, the horizontal high-frequency component and the horizontal low-frequency component in which flicker is less visually noticeable than the vertical high-frequency component. By extracting the small amplitude component and feeding back (adding) it to the output image (vertical high frequency component), the resolution in the vertical direction can be improved, and the flicker can be sufficiently suppressed visually. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the above scanning line conversion method by computer simulation, a small area flicker occurred in a diagonal line portion of a character or the like (at a position at a viewing distance of about 1H). Discrimination was further improved as compared with the conventional example. (The resolution was further improved compared to Example 1.) The detected small area flicker was not detected from a position about 3H away from the screen.

In the second embodiment, the shape (characteristics) of the limiter 62 has been described as being shown in FIG. 6A. However, the present invention is not limited to this, and the configuration as shown in FIG. May be adopted. As a result of comparison by the computer simulations those limiter shape shown in FIGS. 6 (b) those of the limiter shape shown in FIG. 6 (a),
In the case of the same amplitude limit value (the maximum amplitude value output from the limiter 62), the limiter shape shown in FIG. 6B slightly improved the resolution.

In the second embodiment, the limiter 62
When the amplitude limit value is increased, the vertical resolution is improved, but the amount of flicker is increased. Therefore, it goes without saying that a plurality of types of the shape of the limiter 62 may be prepared, and the amplitude limit value of the limiter 62 may be switched according to the viewing distance or the type of the output image.
The setting of the limiter shape may be manually input by the user, or may be set by recognizing the character size on the personal computer side.

Further, the flicker elimination circuit 31 shown in the second embodiment can be realized only by adding a simple circuit to the conventional first VLPF 6, and a good output can be obtained without extremely increasing the circuit scale. There is an effect that an image can be obtained.

Embodiment 3 FIG. The scanning line converter according to the third embodiment is different from the first and second embodiments only in the configuration and operation of the flicker removing circuit 31 shown in FIG. Therefore,
Only the detailed configuration and operation of the flicker elimination circuit 31 will be described, and the description of the same parts as those in the first or second embodiment will be omitted.

FIG. 7 is a block diagram of the flicker removing circuit 31 of the scanning line conversion device according to the third embodiment. In addition,
In the figure, the same symbols as those of the first or second embodiment are attached.
Since the things are the same configuration and operation and detailed description thereof will be omitted. Reference numeral 70 denotes a second vertical low-pass filter (hereinafter, referred to as a second VLPF). FIG. 8 shows FIG.
2 is a block diagram of a second VLPF 70 in FIG.
In the figure, components having the same reference numerals as those of the embodiment and the conventional example have the same configuration and operation, and thus detailed description is omitted. 71a and 71b are multiplication circuits for multiplying the input data by 0.2, and 72 is a multiplication circuit for multiplying the input data by 0.6. FIG. 9 shows the second VLPF 7 in FIG.
It is a figure showing the frequency characteristic of 0. In the figure, the horizontal axis represents the spatial frequency in the vertical direction, and the vertical axis represents the amplitude characteristics. FIG. 10 is a diagram for explaining the basic concept of the flicker removal circuit 31 of the scanning line conversion device according to the third embodiment of the present invention.
FIG. 12 shows an area on a two-dimensional frequency in the third embodiment. In the figure, the horizontal axis represents the spatial frequency in the horizontal direction, and the vertical axis represents the spatial frequency in the vertical direction.

Next, the concept of the third embodiment will be briefly described. In the third embodiment, the data of the horizontal high-frequency component in which flicker is inconspicuous visually (denoted as area 2 in FIG. 10) and the data of the horizontal low-frequency component in which flicker is noticeable (denoted as area 1 in FIG. 10) are used. By changing the shape of the filter applied in the vertical direction in order to eliminate the noise, the occurrence of visually noticeable flicker is suppressed and the resolution in the vertical direction is improved.

In the third embodiment, a filter having a low degree of suppression of high-frequency components in the vertical direction is used for a high-frequency component in the horizontal direction in which flicker is not visually noticeable due to the above operation (see FIG. 9).
To remove flicker components (high-frequency components in the vertical direction), and to remove low-frequency components in the horizontal direction in which flicker is noticeable, using a filter (see FIG. 20) having a high degree of suppression of high-frequency components in the vertical direction Since the component (high-frequency component in the vertical direction) is removed, the flicker component can be almost certainly removed from the output image, and the resolution in the vertical direction can be improved.

Next, the operation of the flicker removing circuit 31 according to the third embodiment will be described with reference to FIGS. 3, 7 to 10, and 19 to 20. The Y signal converted to a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. The Y signal input via the input terminal 40 is input to the first HHPF 45 and the register 46. In addition,
FIG. 3 shows a block diagram of the first HHPF 45. The operation of the first HHPF 45 is the same as that of the first embodiment, and a detailed description thereof will be omitted.

The horizontal high frequency component separated by the first HHPF 45 is input to the subtraction circuit 44 and the second VLPF 70. On the other hand, the input Y signal is
The clock is delayed and input to the subtraction circuit 44. In the subtraction circuit 44, the first signal from the Y signal output from the register
The horizontal high frequency component of the Y signal output from the HHPF 45 is subtracted to separate the horizontal low frequency component of the Y signal. The horizontal low-frequency component of the Y signal separated by the subtraction circuit 44 is equal to the first V
Input to LPF6. The high-frequency component in the horizontal direction of the Y signal input to the second VLPF 70 is suppressed in the vertical direction. Hereinafter, the operation of the second VLPF 70 will be described with reference to FIG.

The horizontal high-frequency component of the Y signal input via the input terminal 20 is supplied to the multiplication circuit 71a and the line memory 2
3a. The line memory 23a delays the input high-frequency component of the Y signal by one line and outputs the delayed signal. The horizontal high frequency component of the Y signal output from the line memory 23a is input to the multiplication circuit 72 and the line memory 23b. In the line memory 23b, similarly to the line memory 23a, the horizontal high frequency component of the input Y signal is delayed by one line and output. The output of the line memory 23b is a multiplication circuit 7
1b. The line memories 23a and 23a
The control of 3b is performed by using the data write and read control signals output from the second memory control circuit 32 via the input terminal 21.

The horizontal high frequency component of the Y signal input to the multiplying circuits 71a and 71b is multiplied by 0.2 and output.
The high frequency component of the Y signal input to the multiplication circuit 72 is multiplied by 0.6 and output. Multiplication circuits 71a and 7
1b and the output of the multiplying circuit 72 are added by the adding circuit 26, the high-frequency component in the vertical direction is suppressed, and the result is output from the second VLPF 70 via the output terminal 22. FIG. 9 shows the second
3 shows the frequency characteristics of the VLPF 70 of FIG. As shown in the figure,
The frequency characteristic of the second VLPF 70 is the vertical high band (525 /
The amplitude suppression degree (around 2 lines) is the first VL shown in FIG.
It is smaller than the amplitude suppression degree of PF6.

On the other hand, the horizontal low-frequency component of the Y signal input to the first VLPF 6 is output after removing the vertical high-frequency component. Since the operation of the first VLPF 6 is the same as that of the first embodiment, detailed description of the operation is omitted. Also, the first and second VLPFs 6 and the line memory 23a in 70
It is assumed that the control of writing and reading of data into and 23b is performed based on a control signal output from the second memory control circuit 32 via the input terminal 41 as in the first embodiment.

In the adder circuit 47, the horizontal low-frequency component of the Y signal from the first VLPF 6 from which the flicker component has been removed and the horizontal high-frequency component of the Y signal from the second VLPF 70 from which the flicker component has been removed. The components are added to generate a Y signal from which a flicker component has been removed. The Y signal from which the flicker component has been removed by the flicker removing circuit 31,
The two color difference signals (RY signal and BY signal) output from the D conversion circuits 3b and 3c are converted and output from the non-interlaced structure to the interlaced structure in the frame memories 7a to 7c.

Since the scanning line conversion apparatus of the third embodiment is configured as described above, a horizontal high-frequency component in which visual flicker is not noticeable and a horizontal low-frequency component in which visual flicker is noticeable are used. By changing the characteristics of the vertical low-pass filter that removes flicker components, the generation of flicker is sufficiently suppressed, and the resolution in the vertical direction is increased, so that it is possible to identify fine characters and the like. As for the characteristics of the above filter , a filter having a characteristic of high suppression of the vertical high frequency component is used to remove the flicker component with respect to the horizontal low frequency component in which the flicker is visually noticeable. For the band component, a filter having a characteristic with a low degree of suppression of the vertical high band component is used in order to secure the resolution in the vertical direction.

The first and second VLPFs 6 for eliminating flicker from the horizontal low-frequency component and the horizontal high-frequency component
The circuit configurations 70 and 70 are not limited to those shown in FIGS. 19 and 8, and may be configured using a non-linear processing circuit including amplitude limiting means such as a limiter circuit as shown in the second embodiment. In this case, the characteristics of the flicker elimination circuit used for the low-frequency components in the horizontal direction are larger than those of the flicker elimination circuit used for the high-frequency components in the horizontal direction. It is configured to suppress the occurrence of flicker.

In the third embodiment, the case where the image is divided into two bands of a low-frequency component in the horizontal direction and a high-frequency component in the horizontal direction has been described. However, the present invention is not limited to this. The same effect can be obtained if the image is divided into a plurality of areas on the dimensional frequency plane, and a flicker removing circuit is provided for each area to remove the flicker component and to extract the vertical resolution component. For example, horizontal low, horizontal mid, and horizontal high
It is needless to say that the same effect can be achieved by dividing the frequency band into two bands and providing a flicker removing circuit for each component to remove the flicker component and also extract the vertical resolution component.

As a result of confirming the effect of the above scanning line conversion method by computer simulation, in the first embodiment, a small area of flicker occurred slightly in a diagonal line portion such as a character (a position at a viewing distance of about 1H). It can be completely removed, the resolution in the vertical direction is improved, and the recognition of fine characters is improved as compared with the conventional example.

Further, the flicker removing circuit 31 shown in the third embodiment includes the first VLPF 6 of the related art and the first VLPF 6 of the related art.
By combining and processing the second VLPF 70 having substantially the same configuration as that of No. 6, flicker can be removed with a simple circuit configuration, and an advantageous effect that a good output image can be obtained without extremely increasing the circuit scale is obtained. is there.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. The scanning line converter in the fourth embodiment differs from the first, second, and third embodiments only in the configuration and operation of the flicker removing circuit 31 shown in FIG. Therefore, only the detailed configuration and operation of the flicker removal circuit 31 will be described,
The description of the same parts as in the above embodiment is omitted.

FIG. 11 is a block diagram of the flicker removing circuit 31 of the scanning line converter according to the fourth embodiment. In the figure, 80 and 81 are addition circuits, 82 is a subtraction circuit,
83 is a low-pass high-pass separation filter .

Next, the concept of the fourth embodiment will be briefly described. In the fourth embodiment, as described in the second embodiment, a vertical resolution component included in a vertical high-frequency component of a video signal is extracted and fed back (added) to an output image to improve the vertical resolution. Measure. More specifically, as described in the second embodiment, the flicker detected by the human eye depends on the amplitude of the high frequency component in the vertical direction. That is, flicker is not visually noticeable for the small amplitude component of the high frequency component in the vertical direction. Therefore, in the fourth embodiment, a vertical resolution component in which flicker is not visually noticeable is separated according to the vertical high-frequency component amplitude. And
The vertical resolution is improved by adding the separated vertical resolution component to the output image from which the vertical high frequency component has been removed.

Since the above operation adds a vertical resolution component in which visual flicker is not noticeable to the output image, the vertical resolution particularly in a fine character portion can be improved, and the occurrence of flicker can be suppressed. Can also be recognized. In the fourth embodiment, the second embodiment is used.
Although the circuit size is smaller than that of the second embodiment, the amplitude limit value of the limiter 62 needs to be set to a value slightly larger than that in the second embodiment.

Next, the operation of the flicker removing circuit 31 of the fourth embodiment will be described with reference to FIG. The Y signal converted to a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. Y input via the input terminal 40
The signal is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input Y signal by one line and outputs it. The Y signal output from the line memory 23a is supplied to the multiplication circuit 25 and the line memory 23.
b. In the line memory 23b, similarly to the line memory 23a, the input Y signal is delayed by one line and output. The output of the line memory 23b is a multiplication circuit 24
b. Note that the line memories 23a and 23
The control of b is performed using the data write and read control signals output from the second memory control circuit 32 via the input terminal 41.

The Y signals input to the multiplication circuits 24a and 24b are multiplied by 0.25 and output. The Y signal input to the multiplication circuit 25 is multiplied by 0.5 and output. The outputs of the multiplication circuits 24a and 24b are
0 is added. Then, the outputs of the addition circuit 80 and the multiplication circuit 25 are added by the addition circuit 81, and the vertical low-frequency component (vertical low-frequency component) of the Y signal is separated. Similarly,
In the subtraction circuit 82, the addition circuit 8
The output of 0 is subtracted, and the vertical high-frequency component (vertical high-frequency component) of the Y signal is separated. The high-frequency component in the vertical direction of the Y signal output from the subtraction circuit 82 is input to the limiter 62. Note that the low-pass high-pass separation filter 8 in the fourth embodiment
3 is a line memory 23a, 23b, a multiplication circuit 24a,
24b, 25, addition circuits 80, 81, and subtraction circuit 8
2 is comprised.

The limiter 62 limits the amplitude of the vertical high frequency component of the input Y signal and outputs the resultant signal. FIG. 6B shows an example of the input / output characteristics of the limiter 62 according to the fourth embodiment. The vertical high-frequency component of the Y signal, the amplitude of which is limited by the limiter 62, is added to the vertical low-frequency component of the Y signal by the adding circuit 47 and output. In the fourth embodiment, the limiter 62 controls the Y
A small amplitude component (vertical luminosity component) in which flicker is inconspicuous is separated from a vertical high frequency component of the signal. Then, the vertical resolution component separated by the limiter 62 is fed back (added) to the output image (vertical low frequency component) to improve the vertical resolution.

As a result of the computer simulation, in the case of the fourth embodiment, when the amplitude of the high-frequency component in the vertical direction of the Y signal is -127 to 128, the maximum value of the amplitude limit value is set to about ± 10 to ± 20. Then, good results were obtained. Control of the line memories 23a and 23b is as follows.
The data write and read control signals output from the second memory control circuit 32 via the input terminal 41 are assumed to be used. The Y signal from which the flicker component has been removed by the flicker removal circuit 31, and the two color difference signals (RY) output from the A / D conversion circuits 3b and 3c.
Signals and BY signals) are stored in the frame memories 7a to 7c.
Is converted from a non-interlaced structure to an interlaced structure and output.

Since the scanning line conversion apparatus according to the fourth embodiment is configured as described above, the Y line in which flicker is visually inconspicuous.
The resolution in the vertical direction can be improved by separating the small-amplitude component in the vertical high-frequency component of the signal and feeding it back (adding) to the output image (vertical low-frequency component). be able to. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the above scanning line conversion method by computer simulation, a small area flicker occurred in a diagonal line portion of a character or the like (at a position at a viewing distance of about 1H). The discrimination was also improved compared to the conventional example. The detected small area flicker was not detected from a position about 3H away from the screen.

Further, the flicker removing circuit 31 shown in the fourth embodiment can remove flicker with a simple circuit configuration by adding a subtraction circuit 82, an addition circuit 47, and a limiter 62 to the conventional first VLPF 6. There is an effect that a good output image can be obtained without extremely increasing the circuit scale.

Further, Y shown in Embodiment 1 and Embodiment 2
Off to separate the high-frequency components and low-frequency component in the vertical direction of the signal
When the filter is configured as the low-pass / high-pass separation filter 83 shown in FIG. 11 according to the fourth embodiment, the line memory 43 can be omitted and the circuit scale can be reduced.

Embodiment 5 FIG. The scanning line conversion apparatus according to the fifth embodiment is different from the first, second, third, and fourth embodiments only in the configuration and operation of the flicker removing circuit 31 illustrated in FIG. Therefore, only the detailed configuration and operation of the flicker elimination circuit 31 will be described, and description of the same parts as those in the above embodiment will be omitted.

FIG. 12 is a block diagram of the flicker removing circuit 31 of the scanning line conversion device according to the fifth embodiment. In the figure, 90 is a DC detection circuit for extracting a DC component in the horizontal direction from the input vertical high frequency component in the vertical direction, 91 is a limiter, and 92 is an amplitude conversion circuit. FIG. 13 is a diagram illustrating the input / output characteristics of the limiter 91 according to the fifth embodiment of the present invention. In FIG. 13, the horizontal axis represents input and the vertical axis represents output. Similarly, FIG. 14 shows one of the input / output characteristics of the amplitude conversion circuit 92.
Examples have been shown. In the figure, the horizontal axis represents input and the vertical axis represents output.

Next, the concept of the fifth embodiment will be briefly described. In the fifth embodiment, as described in the second embodiment, a vertical resolution component is further extracted from a horizontal low-pass component in a vertical high-pass component indicated by hatching in FIG.
The resolution in the vertical direction is improved by feedback (addition) to the output image. Specifically, the flicker detected by human eyes in the horizontal direction depends on the amplitude of the high frequency component in the vertical direction, in addition to the flicker occurrence area described in the first embodiment. In other words, even if flicker occurs, a small amplitude component of a high-frequency component in the vertical direction is not visually noticeable. In the second embodiment, the limiter 62 controls the vertical high frequency range.
From the horizontal low-frequency component, a small-amplitude component with no noticeable flicker was extracted and fed back (added) to the output image (vertical low-frequency component).

In the second embodiment, when the maximum amplitude value output from the limiter 62 is increased, the resolution in the vertical direction is improved. However, since the flicker of a large area occurs in a horizontal line portion of the table, the output maximum amplitude of the limiter 62 is sufficiently increased. I couldn't take it. In the fifth embodiment, the DC component in the horizontal direction is detected from the input Y signal, and the limiter shape (characteristic) is switched between the DC component in the horizontal direction and another component to improve the resolution in the vertical direction.

Further, by suppressing the output amplitude of the high frequency component in the horizontal direction output from the first HHPF 45 by the amplitude conversion circuit 92, flicker generated in the oblique line portion can be eliminated. (Incidentally, when the amplitude of the above components is increased, the occurrence of flicker slightly increases, but the vertical resolution slightly increases.)

Next, the operation of the flicker removing circuit 31 according to the fifth embodiment will be described with reference to FIGS. The Y signal converted to a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. FIG. 19 shows a block diagram of the first VLPF 6. Since the detailed operation of the first VLPF 6 is the same as that of the first embodiment, the description is omitted. On the other hand, the Y signal input to the line memory 43 is output after being delayed by one line.

The subtraction circuit 44 subtracts the vertical low-frequency component of the Y signal output from the first VLPF 6 from the Y signal delayed by one line in the line memory 43, and separates the vertical high-frequency component of the Y signal. . The output of the subtraction circuit 44 is the first H
It is input to the HPF 45 and the register 60. The first HHPF 45 is shown in the block diagram of FIG. On the other hand, the vertical high frequency component of the Y signal input to the register 60 is output after being delayed by one clock. The subtraction circuit 61 subtracts the vertical high-frequency component of the Y signal output from the first HHPF 45 from the vertical high frequency component of the Y signal delayed by one clock in the register 60. The vertical high band-horizontal low band component of the Y signal output from the subtraction circuit 61 is input to a limiter 91.

The output of the first HHPF 45 is input to the DC detection circuit 90. In the DC detection circuit 90 , the first
A DC component (DC component) is detected from the vertical high-frequency component of the Y signal output from the HHPF 45 of FIG. Less than,
The operation of the DC detection circuit 90 according to the fifth embodiment will be briefly described. First, the DC detection circuit 90 separates the DC component in the horizontal direction by comparing the amplitude of the vertical high band-horizontal high band component of the input Y signal with a predetermined value. Specifically, when the amplitude of the vertical high band-horizontal high band component of the input Y signal is YHH, for example, if YHH ≦ α and YHH ≧ −α, it is determined that a DC component has been detected. (Α is a positive real number) Note that α is 1-3
A good result was obtained as a result of performing a simulation with the setting at about. (A simulation was performed with an amplitude of YHH of -127 or more and 128 or less.)

The limiter 91 limits the amplitude of the vertical high band-horizontal low band component of the input Y signal and outputs it. FIG.
As shown in FIG. 3, the limiter 91 switches the limiter shape (characteristic) based on the input DC detection information. Specifically, when a DC component is detected by the DC detection circuit 90,
In the fifth embodiment, the limiter 91 outputs 0. If the DC component is not detected, the amplitude value of the vertical high band-horizontal low band component of the input Y signal is limited according to the characteristics shown in FIG. The vertical high band-horizontal low band component of the Y signal whose amplitude is limited by the limiter 91 is input to the addition circuit 63.

On the other hand, the vertical high-frequency component of the Y signal output from the first HHPF 45 is input to the amplitude conversion circuit 92. In the fifth embodiment, as shown in FIG.
The amplitude of the vertical high-frequency component of the Y signal output from the HHPF 45 is increased by a factor of 0.5. (Note that the characteristic of the amplitude conversion circuit 92 is a linear conversion in the fifth embodiment, but may be a non-linear conversion.) The output of the amplitude conversion circuit 92 is input to the addition circuit 63. The addition circuit 63 adds the output of the amplitude conversion circuit 92 and the output of the limiter 91. The output of the addition circuit 63 (the resolution component in the vertical direction) is
At 7, it is added to the vertical low frequency component of the Y signal output from the register 46 and output.

In the fifth embodiment, the limiter 91
A small amplitude component ( resolution component in the vertical direction) in which flicker is inconspicuous is separated from a vertical high band-horizontal low band component of the Y signal.
In the fifth embodiment, the first HHPF 45 and the limiter 9
The vertical resolution is improved by feeding back (adding) the high resolution component in the vertical direction separated by 1 to the output image (low frequency component in the vertical direction). In the case of the fifth embodiment, since the DC component of the visually noticeable flicker is output as the amplitude value 0 by the limiter 91,
Since the maximum value of the amplitude limit value of the limiter 91 can be set to be larger than that in the case of the second embodiment, the resolution in the vertical direction can be further improved. Also, the first H
Since the amplitude of the vertical high band-horizontal high band component of the Y signal output from the HPF 45 is reduced by the amplitude conversion circuit 92 and output, it is generated in the oblique line portion such as the character described in the second embodiment. Small area flicker can also be removed.

The first HHPF 45 and the register 4
Clocks are supplied to 6 and 60 from the first PLL circuit 5. The line memories 23a and 23b and the line memory 43 in the first VLPF 6 are controlled by the second memory control circuit 3 via the input terminal 41.
2 is performed by using the data write and read control signals output from the second data. Flicker removal circuit 3
1, the Y signal from which the flicker component has been removed, and A / D
The two color difference signals (RY signal and BY signal) output from the conversion circuits 3b and 3c are converted and output from the non-interlaced structure to the interlaced structure in the frame memories 7a to 7c.

Since the scanning line conversion device of the fifth embodiment is configured as described above, the Y line in which flicker is not visually noticeable is noticeable.
By separating small amplitude components in the vertical high-frequency component of the signal and feeding it back (adding) to the output image (vertical low-frequency component), the resolution in the vertical direction can be improved, and the flicker is also visually sufficient. Can be suppressed. Therefore, there is an effect that fine characters and the like on the display can be recognized. In addition, the first H
Since the output amplitude of the HPF 45 is reduced, flicker of a small area, which has occurred in an oblique line portion of a character or the like, can be suppressed, and the resolution in the vertical direction is improved, and the identification of a fine character is further improved as compared with the conventional example. improves.

Further, the flicker removing circuit 31 shown in the fifth embodiment can remove flicker with a simple circuit configuration by adding a simple circuit to the conventional first VLPF 6, thereby significantly increasing the circuit scale. There is an effect that a good output image can be obtained without any. The DC component in the horizontal direction of the Y signal is detected by the DC detection circuit 90, and the shape (characteristic) of the limiter 91 is switched based on the DC detection result. By reducing the feedback amount of the low-frequency component, the feedback amount of the vertical high-frequency component and the horizontal low-frequency component can be increased with respect to components other than the direct current component, so that the resolution component in the vertical direction can be further improved.

Further, the line memory 43 can be omitted by employing the configuration of the filter for separating the high-frequency component and the low-frequency component in the vertical direction of the Y signal shown in the fifth embodiment shown in FIG. 11 shown in the fourth embodiment. This has the effect of reducing the circuit scale. In the fifth embodiment, the shape of the limiter 91 is switched between the DC component and the other components. However, the present invention is not limited to this. A plurality of types of DC detection levels are prepared in the DC detection circuit 90, and the plurality of types of detection are prepared. The configuration of the limiter 91 may be changed according to the level.

In the fifth embodiment, when the DC component is detected by the DC detection circuit 90 , when the amplitude of the vertical high band-horizontal high band component of the input Y signal is YHH, YHH ≦
When α and YHH ≧ −α, it was determined that the DC component was detected. However, a DC component (DC component) is obtained from the vertical high-frequency component of the Y signal output from the first HHPF 45.
, The DC detection circuit 90 first detects the amplitude (YHH) of the vertical high-horizontal high frequency component of the Y signal input first.
Is compared with a predetermined value (α), and the above YHH
If the absolute value of is less than α, it may be determined that a DC component has been detected. In the fifth embodiment, the DC detection circuit 90
Is described as a logic circuit, but the present invention is not limited to this, and a DC component may be detected using a microcomputer or the like. At this time, as described above, the algorithm for detecting the DC component is set to YHH
In the case of <α and YHH> −α, the same effect is obtained even if a DC component is detected. Here, α is a positive real number.

In the fifth embodiment, the first HHPF 45
Although the DC component of the Y signal is detected using the output of the Y signal, the present invention is not limited to this. For example, the DC component is detected from the vertical high frequency component of the Y signal output from the subtraction circuit 44, or the input Y signal is detected. Needless to say, the same effect can be obtained by directly detecting the DC component. Further, in the fifth embodiment, the case where the amplitude of the data of the vertical high frequency-horizontal high frequency component input from the first HHPF 45 is suppressed by the amplitude conversion circuit 92 has been described. The amplitude may be increased and fed back (added) to the output image, in which case the vertical resolution further increases. Further, the amplitude conversion circuit 92 has a plurality of amplitude conversion data, and the user or a personal computer or the like discriminates a picture and switches it (for example, when the resolution is required, it is set to double, If it is desired to completely remove flicker, it is set to 0.5 times, and in other cases, it is set to 1.0), and the same effect can be obtained.

[0148] Further, implementing the D C detection circuit 90 shown in Example 5 Example 2 flicker removing circuit 3 or in Examples 4,
The same effect can be obtained even if the limiter 63 is provided in the switch 1 so as to switch the characteristics of the limiter 63 based on the detection result of the horizontal DC component (or the DC component of the high-frequency component in the vertical direction) of the input signal.

Embodiment 6 FIG. In addition, the above-mentioned Examples 1 to 5
In the above, the operation of the scanning line conversion device was described using a VGA signal of a personal computer as an embodiment of a non-interlaced image. However, the present invention is not limited to this, and non-interlaced images (for example, standards are currently being discussed in Europe) Non-interlaced images transmitted by digital broadcasting such as DVB, ATV which is being standardized in the United States, or ISDB which is being standardized in Japan, or images in other display modes of personal computers. ) Is converted to an interlaced image, the same effect can be obtained by removing the flicker component using the scanning line conversion device and outputting the image.

In the first embodiment, the matrix circuit 10 converts the R, G, and B signals into a Y signal and two color difference signals (R-G
After the conversion into the Y signal and the BY signal), only the flicker component of the Y signal is removed, but the present invention is not limited thereto.
The flicker components included in the R, G, and B signals may be removed by the flicker removal circuit 31 and output. Further, the flicker component may be removed from the RY signal and the BY signal by the flicker removing circuit 31. In addition, when the flicker component in the color difference signal is removed, the characteristic or configuration of the flicker removal circuit 31 may be changed from the case where the flicker component in the luminance signal is removed. Needless to say, the characteristics or configuration of the flicker removal circuit 31 may be changed for each color difference signal.

Embodiment 7 FIG. In the first to fifth embodiments, when the image without fine characters or the viewing distance is long, the scanning line conversion is performed so as to output the image from which the high-frequency component in the vertical direction has been removed as shown in the conventional example. The device may be configured. In the first to fifth embodiments, the luminance signal (Y signal) and the two color difference signals (R-
Y signal and BY signal), but the present invention is not limited thereto. For example, a luminance signal (Y signal) and two color signals (U and V signals), or a luminance signal (Y signal), and Needless to say, the same effect can be obtained even if the flicker component is removed from the Y signal after the conversion into another color signal and the conversion into an interlaced image is performed. Alternatively, the scanning line conversion may be performed after converting the two color difference signals into modulated color signals.

In the first to fifth embodiments, the horizontal high-pass filter or the vertical low-pass filter is used.
The filter was configured as shown in FIGS. 3, 8, 11, and 19, but the configuration of the filter (the number of taps, the shape of the filter ,
And type (FIR filter , IIR filter, etc.))
The frequency characteristics and the like are not limited to this. In Examples 1 to 5, the high-pass filter in the vertical direction was used.
The filter is configured by subtracting the output of the vertical low-pass filter from the input signal, but is not limited to this. For example, the vertical high-pass filter, and vertical low-pass Fi
The separately configured filter, or vertical highpass fill
After separating the vertical high-pass component using a filter , the vertical high-pass component is subtracted from the input signal to obtain a vertical low-pass filter.
A filter may be configured. Similarly, a horizontal high-pass filter and a horizontal low-pass filter are separately configured, or a horizontal low-pass component is separated using a horizontal low-pass filter , and then the horizontal low-pass component is separated from an input signal. A horizontal high-pass filter may be configured by subtracting the components. In addition,
In the above-described first to seventh embodiments, the non-input
The case of interlaced images has been described, but it is not limited to this.
Not something. For example, a non-interlaced image
Convert to an interlaced image without flicker removal and transfer
The transmitted or reproduced flicker is also the same as in the first to seventh embodiments.
The same effect can be obtained by using the flicker removing circuit shown.
Specifically, the input interlaced image is stored in a memory
A non-
If reconstructed into an interlaced image,
The flicker removal circuit shown impairs vertical resolution more than necessary
No flicker generation in interlaced images
Minutes can be removed.

[0153]

Since the present invention is configured as described above, it has the following effects.

The scanning line converter according to claim 1 of the present invention
According to this, the vertical high-horizontal low-frequency component (which is a factor that generates large-area flicker) in which visual flicker is conspicuous is suppressed, and the vertical resolution in which visual flicker is further inconspicuous is further reduced. Since the component (vertical high-frequency component) is extracted and fed back (added) to the output image, the vertical resolution in the fine character portion is improved, the occurrence of flicker can be suppressed, and the fine character can be removed. There is an effect that can be recognized.

[0155] Further , the visual component is visually recognized from the high frequency component in the vertical direction.
Horizontal high frequency component and horizontal low frequency with inconspicuous liquor
Output image (vertical low-frequency component) by extracting small amplitude components from components
The vertical solution by adding feedback to
Image quality can be improved, and flicker is also visible.
Can be suppressed sufficiently. Therefore, on the display
There is an effect that fine characters and the like can be recognized. In addition, this can be realized by simply adding a simple circuit to the conventional scanning line conversion device, suppressing the occurrence of flicker and improving the vertical resolution without significantly increasing the circuit scale. Thus, there is an effect that a good output image can be obtained.

Further, according to the scanning line converter of the second aspect of the present invention , the vertical low frequency component and the vertical high frequency
-Horizontal low frequency component and vertical high frequency component-Separate horizontal high frequency component
Can be output.

[0157]

[0158]

[0159]

Further, according to the scanning line conversion device of the third aspect of the present invention, a horizontal line portion of a table or the like which is visually noticeable for flicker can be detected from the input non-interlaced image. Therefore, with respect to small-amplitude components of the horizontal high-frequency component in a prominent visual flicker (such as the horizontal part of the table) it is possible to suppress the occurrence of flicker by suppressing vertical resolution component, a small high-frequency component Regarding the vertical resolution component other than the amplitude component (such as fine characters) , the amplitude limit value of the first amplitude limiter can be increased, so that the vertical resolution is further improved. There is an effect that can be.

Further, the present invention can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, and it is possible to suppress the occurrence of flicker without significantly increasing the circuit scale, and to reduce the vertical resolution. Is improved, and there is an effect that a good output image can be obtained. In addition, detection of small amplitude components (such as the horizontal lines in the table) of the high-frequency components described above.
Since the shape of the first amplitude limiting means is switched on the basis of the output result , the small amplitude component of the high-frequency component in which the flicker is conspicuous visually is displayed.
For the horizontal line part in the table, the flicker component can be sufficiently suppressed by reducing the feedback amount (addition amount), and other than the small amplitude component of the high frequency component.
The feedback amount (addition amount) can be increased for components (such as fine characters) , so that the resolution component in the vertical direction can be further improved.

Further, according to the scanning line conversion device of the fourth aspect of the present invention, a horizontal line portion of a table or the like which is visually noticeable for flicker can be detected from the vertical high frequency component. Therefore, the high-frequency component in the horizontal direction where flicker is conspicuous visually
With respect to small-amplitude components (such as the horizontal part of the table) it is possible to suppress the occurrence of flicker by suppressing vertical resolution component, small non-amplitude component (fine print of the high frequency component
The effect of Regarding vertical resolution component can be improved further in the vertical resolution since it is possible to amplitude limit value larger at the first amplitude limiting means etc.). In addition, the small-amplitude component of the high-frequency component is
The high frequency component is compared with the case of claim 3 because the minute is detected.
The storage capacity of the storage means for matching the phase of the detection information of the small amplitude component (horizontal line portion of the table, etc.) with the above vertical high-range and horizontal low-range component can be reduced, and the circuit scale can be reduced. There is.

Further, the present invention can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, and it is possible to suppress the occurrence of flicker without significantly increasing the circuit scale, and to reduce the vertical direction. There is an effect that the resolution can be improved and a good output image can be obtained. In addition, detection of small amplitude components (such as the horizontal lines in the table) of the high-frequency components described above.
Since the shape of the first amplitude limiting means is switched on the basis of the output result, the small amplitude component of the high-frequency component in which the flicker is conspicuous visually is displayed.
For the horizontal line part in the table, the flicker component can be sufficiently suppressed by reducing the feedback amount (addition amount), and other than the small amplitude component of the high frequency component.
The feedback amount (addition amount) can be increased for components (such as fine characters) , so that the resolution component in the vertical direction can be further improved.

[0164]

[0165]

[0166]

According to the scanning line conversion apparatus of the fifth aspect of the present invention, when a non-interlaced image input in units of one frame is converted into an interlaced image in units of one field, a non-interlaced image input first is input. The horizontal low frequency component and high frequency component are separated from the interlaced image.
Next, a flicker component is removed from the separated low-frequency component in the horizontal direction by using a first flicker removing unit. Similarly, a flicker component is removed from the separated high-frequency component in the horizontal direction by using a second flicker removing unit. Then, the adding means adds the horizontal low-frequency component from which the flicker component has been removed by the first flicker removing means and the horizontal high-frequency component from which the flicker component has been removed by the second flicker removing means. Then, a predetermined line is thinned out from the non-interlaced image of one frame unit output from the adding means to form an interlaced image of one field unit. In this case, the degree of suppression of the high frequency component in the vertical direction by the first flicker removing means is set to be larger than the degree of suppression of the high frequency component in the vertical direction by the second flicker removing means. The characteristics of the vertical low-pass filter that removes the flicker component are switched between the horizontal high-frequency component in which the flicker is not noticeable and the horizontal low-frequency component in which the flicker is visually noticeable, so that the occurrence of flicker is sufficiently suppressed. Since the resolution in the vertical direction is increased, there is an effect that fine characters can be identified.

As a result of confirming the effect of the scanning line conversion method by computer simulation, it was found that flicker could be almost completely removed, the resolution in the vertical direction was improved, and the identification of fine characters was improved as compared with the conventional example. In addition, it can be realized by simply adding a simple circuit to the conventional scanning line conversion device, and it is possible to suppress the occurrence of flicker and improve the resolution in the vertical direction without extremely increasing the circuit scale. Thus, there is an effect that a good output image can be obtained.

[0169] Further, the small-amplitude components in accordance according to the scanning line converting apparatus of claim 6, it is possible to suppress visually sufficiently flickering, vertical high in component inconspicuous visual flicker of the present invention Is separated and fed back (added) to an output image (vertical low-frequency component), whereby the resolution in the vertical direction can be improved.

Further, the present invention can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, so that flicker can be suppressed without significantly increasing the circuit scale, and the vertical resolution can be reduced. Can be improved and a good output image can be obtained.

[0171] Further, according to the scanning line converting apparatus according to claim 7 of the present invention, it can be detected from the non-interlaced image visually very flicker is input to such horizontal portion such as a table, however. In addition, the suppression of the vertical resolution component of the small amplitude component of the horizontal high-frequency component (horizontal line in the table) where the flicker is conspicuous visually can suppress the occurrence of flicker, and the small high-frequency component can be suppressed. As for the vertical resolution components other than the amplitude components (such as fine characters), the amplitude limit value of the second amplitude limiter can be increased, so that the resolution in the vertical direction can be further improved.

Further, the present invention can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, and it is possible to suppress the occurrence of flicker without significantly increasing the circuit scale, and to reduce the vertical resolution. Can be improved and a good output image can be obtained. Also,
Since the shape of the second amplitude limiting means is switched based on the detection result of the small amplitude component of the high frequency component, the feedback amount (addition amount) is reduced for the small amplitude component of the high frequency component where flicker is conspicuous visually. Small amplitude of high frequency component
Feedback amount (addition amount) for components other than components
Can be increased, and the resolution component in the vertical direction can be further improved.

[0173]

[0174]

[0175]

[0176] Further, according to the scanning line converting apparatus according to claim 8 of the present invention, it is possible to suppress the flicker of a small area can be confirmed slightly generated in the oblique line portion such as characters, improved vertical resolution Also, there is an effect that the identification of fine characters is further improved as compared with the conventional example.

Further, the present invention can be realized only by adding a simple circuit to the conventional scanning line conversion apparatus, and it is possible to suppress the occurrence of flicker without significantly increasing the circuit scale, and to reduce the vertical resolution. Is improved, and there is an effect that a good output image can be obtained. According to the flicker removing device according to the ninth to seventeenth aspects of the present invention, it is possible to suppress the occurrence of flickering without using the above-described scanning line converting device without increasing the circuit scale extremely. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a scanning line conversion apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a flicker removing circuit in FIG. 1;

FIG. 3 is a block diagram of a first HHPF in FIG. 2;

FIG. 4 is a diagram for explaining a basic concept of a flicker removal circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a flicker removing circuit of the scanning line conversion device according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating input / output characteristics of a limiter according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a flicker removal circuit of a scanning line conversion apparatus according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a second VLPF in FIG. 7;

9 is a diagram illustrating a frequency characteristic of a second VLPF in FIG. 8;

FIG. 10 is a diagram for explaining a basic concept of a flicker removal circuit according to a third embodiment of the present invention.

FIG. 11 is a block diagram illustrating a flicker removal circuit of a scanning line conversion apparatus according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a flicker removal circuit of a scanning line conversion device according to a fifth embodiment of the present invention.

FIG. 13 is a diagram illustrating input / output characteristics of a limiter according to a fifth embodiment of the present invention.

FIG. 14 is a diagram illustrating input / output characteristics of an amplitude conversion circuit according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a spatial frequency characteristic of a non-interlaced image.

FIG. 16 is a diagram showing a spatial frequency characteristic of an interlaced image.

17 is a diagram showing characteristics of the interlaced image shown in FIG. 16 on a two-dimensional frequency.

FIG. 18 is a block diagram of a conventional scanning line conversion device.

FIG. 19 is a block diagram of a first conventional VLPF.

FIG. 20 is a diagram showing frequency characteristics of a first conventional VLPF.

[Explanation of symbols]

6 first VLPF, 7 frame memory, 10 matrix circuit, 23 line memory, 24 multiplication circuit, 2
5 Multiplication circuit, 26 addition circuit, 30 LPF, 31
Flicker removal circuit, 32 Second memory control circuit, 43
Line memory, 44 subtraction circuit, 45 first HHP
F, 46 registers, 47 addition circuits, 52 registers, 53 multiplication circuits, 54 multiplication circuits, 55 addition circuits, 60 registers, 61 subtraction circuits, 62 limiters, 63 addition circuits, 70 second VLPFs, 71 multiplication circuits, 72 multiplications Circuit, 80 addition circuit, 81 addition circuit, 82 subtraction circuit, 83 low-pass high-pass separation filter ,
90 DC detection circuit, 91 limiter, 92 amplitude conversion circuit.

Continuation of the front page (56) References JP-A-3-220990 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 7/01

Claims (17)

(57) [Claims] 1. A scanning line conversion apparatus for converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, comprising: a vertical low-frequency component and a vertical high-frequency-horizontal lower than an input non-interlaced image. Separation means for separating and outputting the band component and the vertical high band-horizontal high band component; and first amplitude limiting means for limiting the amplitude of the vertical high band-horizontal low band component output from the separation unit. A vertical low band component and a vertical high band-horizontal high band component output from the separation unit and an output of the first amplitude limiting unit, and an output unit that outputs the output. By thinning out a predetermined line from a non-interlaced image of one frame unit,
A scanning line conversion device for forming an interlaced image in field units. 2. The first frequency separating means for separating and outputting a vertical low-frequency component from an input non-interlaced image, and the first frequency separating means from an input non-interlaced image. First subtraction means for subtracting the output vertical low frequency component from the output signal to output a vertical high frequency component; and a vertical high frequency-horizontal high frequency range from the vertical high frequency component output from the first subtraction means. A second frequency separating means for separating and outputting a component; and a vertical high-frequency-horizontal height output from the second frequency separating means from the vertical high-frequency component output from the first subtracting means. 2. The scanning line conversion device according to claim 1, further comprising second subtraction means for subtracting the band component and outputting a vertical high band-horizontal low band component. 3. A comparing means for separating a high frequency component in the horizontal direction from the input non-interlaced image, comparing the absolute value of the amplitude of the separated high frequency component in the horizontal direction with a predetermined value, and outputting a comparison result. The amplitude limit value of the first amplitude limit means is switched based on the comparison result output from the comparison means, and the amplitude limit value is used when the absolute value of the amplitude is equal to or less than the predetermined value. 3. The control device according to claim 1, wherein the first limiter controls the first limiter so that an amplitude limit value is smaller than the amplitude limit value when the absolute value of the amplitude is larger than the predetermined value. Scanning line converter. 4. A vertical high-frequency separation means for separating a vertical high-frequency component from an input non-interlaced image, and a horizontal high-frequency component of the vertical high-frequency component output from the vertical high-frequency separation means. Comparing means for comparing the absolute value of the amplitude of the horizontal high-frequency component of the separated vertical high-frequency component with a predetermined value and outputting a comparison result; and setting the amplitude limit value of the first amplitude limiting means to Switching is performed based on the comparison result output from the comparing means, and the amplitude limit value used when the absolute value of the amplitude is equal to or less than the predetermined value is such that the absolute value of the amplitude is larger than the predetermined value. 3. The scanning line conversion device according to claim 1, wherein the first amplitude limiter is controlled to be smaller than the amplitude limit value at the time. 5. A scanning line conversion apparatus for converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, wherein a low-frequency component and a high-frequency component in the horizontal direction are separated from the input non-interlaced image. A third flicker removing means for removing a flicker component from a horizontal low-frequency component output from the third frequency separating means, and a third flicker removing means output from the third frequency separating means. A second flicker removing unit for removing a flicker component from a high frequency component in a horizontal direction, an adding unit for adding an output of the first flicker removing unit and an output of the second flicker removing unit, By thinning out a predetermined line from the output non-interlaced image of one frame unit, 1
Interlaced image conversion means for forming an interlaced image in field units, wherein when the flicker component is removed from the input non-interlaced image, the degree of suppression of the high frequency component in the vertical direction by the first flicker removal means is determined by A scanning line conversion device configured to set the degree of suppression of the high frequency component in the vertical direction to be greater than the degree of suppression by the flicker removing means. 6. A scanning line conversion apparatus for converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, wherein a low-frequency component and a high-frequency component in the vertical direction are separated from the input non-interlaced image. Fourth frequency separating means for comparing the absolute value of the amplitude of the high frequency component in the horizontal direction of the input non-interlace signal with a predetermined value, and outputting a comparison result; Second amplitude limiting means for limiting the amplitude of the high frequency component in the vertical direction outputted from the second frequency limiting means, and the low frequency component in the vertical direction outputted from the fourth frequency separating means and the output of the second amplitude limiting means. And an adder for adding a value to the second amplitude limiter, and controlling the amplitude limit value of the second amplitude limiter to be switched based on the comparison result output from the comparator. The addition means scanning line conversion apparatus characterized by constituting the interlaced image of one field unit by thinning out predetermined line from non-interlaced picture of one frame output from. 7. The comparing means separates the horizontal high-frequency component of the vertical high-frequency component output by the fourth frequency separating means, and outputs the absolute value of the amplitude of the separated horizontal high-frequency component. Is configured to be compared with a predetermined value, and the amplitude limit value used when the absolute value of the amplitude is equal to or less than the predetermined value is larger than the amplitude limit value when the absolute value of the amplitude is larger than the predetermined value. 7. The scanning line conversion device according to claim 6, wherein the second amplitude limiter is controlled so that the amplitude is also reduced. 8. A scanning line conversion apparatus for converting a non-interlaced image input in units of one frame into an interlaced image in units of one field, wherein a vertical low-frequency component and a vertical high-frequency-horizontal height are higher than the input non-interlaced image. Separating means for separating and outputting the band component; amplitude converting means for converting the amplitude of the vertical high band-horizontal high band component outputted from the separating means; and a vertical low band component outputted from the separating means. An adding means for adding the output of the first amplitude converting means, wherein 1 is obtained by thinning out a predetermined line from the non-interlaced image of one frame unit output from the adding means.
A scanning line conversion device for forming an interlaced image in field units. 9. A flicker eliminator for converting an input non-interlaced video signal into an interlaced video signal and removing flicker generated when displaying the same, comprising: a vertical low-frequency component and a vertical high-frequency component from an input video signal. Separating means for separating and outputting the horizontal low frequency component and the vertical high frequency-horizontal high frequency component; and a first amplitude limit for limiting the amplitude of the vertical high frequency-horizontal low frequency component output from the separating means. Means for adding flicker and vertical low frequency component and vertical high frequency-horizontal high frequency component output from the separating means and the output of the first amplitude limiting means. apparatus. 10. A first frequency separating means for separating and outputting a vertical low-frequency component from an input non-interlaced image, and a first frequency separating means for separating the input non-interlaced image from the input non-interlaced image. First subtraction means for subtracting the output vertical low frequency component from the output signal to output a vertical high frequency component; and a vertical high frequency-horizontal high frequency range from the vertical high frequency component output from the first subtraction means. A second frequency separating means for separating and outputting a component; and a vertical high-frequency-horizontal height output from the second frequency separating means from the vertical high-frequency component output from the first subtracting means. 10. The flicker removing device according to claim 9, further comprising second subtraction means for subtracting the band component and outputting a vertical high band-horizontal low band component. 11. A comparing means for separating a horizontal high-frequency component from an input video signal, comparing the absolute value of the amplitude of the separated horizontal high-frequency component with a predetermined value, and outputting a comparison result, claim 9 or claim, characterized in that configuring the amplitude limit value of the first amplitude limiting means so as to switch on the basis of the comparison result output from the comparing means 10
The flicker removing device as described in the above. 12. A vertical high-frequency separation means for separating a vertical high-frequency component from an input video signal, and a horizontal high-frequency component of the vertical high-frequency component output from the vertical high-frequency separation means,
Comparing the absolute value of the amplitude of the horizontal high-frequency component of the separated vertical high-frequency component with a predetermined value and outputting a comparison result; and comparing the amplitude limit value of the first amplitude limit means with the comparison value. Means for switching based on the comparison result output from the means, wherein the amplitude limit value used when the absolute value of the amplitude is equal to or less than the predetermined value is determined when the absolute value of the amplitude is larger than the predetermined value. of the amplitude limit value flicker removing apparatus according to claim 9 or claim 10, wherein the controller controls the first amplitude limiting means to be smaller than. 13. A flicker elimination device for converting an input non-interlaced video signal into an interlaced video signal and removing flicker generated when the input video signal is displayed. A third flicker removing unit for removing flicker from horizontal low-frequency components output from the third frequency separating unit, and an output from the third frequency separating unit. A second flicker removing unit for removing flicker from a horizontal high-frequency component to be obtained; and an adding unit for adding an output of the first flicker removing unit and an output of the second flicker removing unit. When removing flicker from the video signal, the degree of suppression of the high frequency component in the vertical direction by the first flicker removing means is
A flicker eliminator characterized in that the degree of suppression of a vertical high-frequency component by a second flicker eliminator is set to be larger than the degree of suppression. 14. A flicker eliminator for removing a flicker generated when an input non-interlaced video signal is converted into an interlaced video signal and displayed, wherein a low frequency component and a high frequency component in a vertical direction from the input video signal are provided. Fourth frequency separating means for comparing the absolute value of the amplitude of the high frequency component in the horizontal direction of the input video signal with a predetermined value, and outputting the comparison result; and output from the fourth frequency separating means. Second amplitude limiting means for limiting the amplitude of the high frequency component in the vertical direction, and addition for adding the low frequency component in the vertical direction output from the fourth frequency separating means and the output of the second amplitude limiting means. Means for controlling the switching of the amplitude limiting value of the second amplitude limiting means based on the comparison result output from the comparing means. 15. The comparing means separates the horizontal high-frequency component of the vertical high-frequency component output by the fourth frequency separating means, and outputs the absolute value of the amplitude of the separated horizontal high-frequency component. 15. The flicker removing device according to claim 14 , wherein the flicker is compared with a predetermined value. 16. The amplitude limit value used when the absolute value of the amplitude is equal to or smaller than the predetermined value is smaller than the amplitude limit value when the absolute value of the amplitude is larger than the predetermined value. 15. The flicker removing device according to claim 14, wherein the second amplitude limiting means is controlled. 17. A flicker eliminator for converting an input non-interlaced video signal into an interlaced video signal and removing flicker generated when displaying the same, wherein a vertical low-frequency component and a vertical high-frequency-horizontal component of the input video signal are reduced. Separating means for separating and outputting the high-frequency component; amplitude converting means for converting the amplitude of the vertical high-frequency component output from the separating means; and a vertical low-frequency component output from the separating means. A flicker removing device, comprising: an adder for adding an output of the amplitude converter.