JPH09191377A - Line memory controller and image data processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the line memory controller outputting delayed data with low power consumption by providing a read control means or the like selecting plural line memories according to the write sequence and reading plural output signals with a prescribed delay from each line memory respectively. SOLUTION: When write reset signal is received, a write selector control circuit 5 or the like is reset and image data received serially to a data input node in a clock timing of a received write clock signal are stored in a memory cell located at a prescribed address according to address sequence and image data by one line are stored in a memory array. On the other hand, when a read reset signal is received, a read selector control circuit 6 or the like is reset and image data stored in a memory cell at a prescribed address are read according to the address sequence at a clock timing of a received read clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line memory control device for obtaining delay data from a plurality of line memories, and is used as a line memory for image processing in, for example, a digital copying machine, a laser beam printer, a facsimile machine or the like. And a line memory controller suitable for obtaining a delayed data sequence.

[0002]

2. Description of the Related Art Conventionally, in image processing apparatuses such as digital copiers, laser beam printers, and facsimile machines that handle image data, a large amount of image data for one page is stored as a storage means for temporarily storing the image data. It was usual to use a line memory that stores image data for one line instead of the page memory having the storage capacity.

Generally, these image processing apparatuses generally perform various data processing such as contour enhancement, dither processing and resolution compensation on the image data digitized and stored in the storage means. Such data processing generally requires not only the image data of the line to be subjected to the data processing but also the image data of the lines before and after the line, so that the image data delayed by the line unit is usually required. Met.

FIG. 6 shows a conventional configuration in which a line memory is used as a storage means in order to obtain image data delayed in units of lines as described above. In FIG. 6, reference numerals 1 to 4 are line memories for storing image data in units of first to fourth lines, and here, as an example, a first-in first-out type memory (hereinafter referred to as a FIFO memory) is shown. Reference numeral 9 denotes an external write control signal line, which is a write clock signal (WCK) and a write reset signal (WRE).
SB) to write the data of the external data input signal line Dn to the line memories 1 to 4. An external read control signal line 10 transmits a read clock signal (RCK) and a read reset signal (RRESB), and performs an operation of reading the data of the line memories 1 to 4 to the external data output signal lines of Qn1 to Qn4. It is for doing. Dn is an external data input signal line, and Qn1 to Qn4 are external data output signal lines.

Next, the operation of the image data storage means configured as described above will be described for each state shown in FIG. 7 (j). First, in the initial state, all the FIFO memories 1
In Nos. 4 to 4, neither write operation nor read operation is performed. Next, in step 1 after the write reset operation (WRESB = “L”), one line of data (A) from the external data input signal line Dn is written in the FIFO memory 1.

Next, a reset 1 operation (RRESB = "
In step 2 after L ″), the data (A) written in step 1 is read from the FIFO memory 1 to the external data output signal line Qn1, and the data (A) is written in the FIFO memory 2. Input signal line Dn
The data (B) for one line is written in the FIFO memory 1.

Next, in step 3 after the reset 2 operation,
The data (B) written in step 2 is read from the FIFO memory 1 to the external data output signal line Qn1, and the data (B) is written to the FIFO memory 2. Further, the data (A) written in step 2 is read from the FIFO memory 2 to the external data output signal line Qn2,
In addition, the data (A) is written in the FIFO memory 3. Further, the data (C) for one line of the external data input signal line Dn is written in the FIFO memory 1.

Next, in step 4 after the reset 3 operation,
The data (C) written in step 3 is read from the FIFO memory 1 to the external data output signal line Qn1, and the data (C) is written to the FIFO memory 2. Further, the data (B) written in step 3 is read from the FIFO memory 2 to the external data output signal line Qn2,
Further, the data (B) is written in the FIFO memory 3. Further, the data (A) written in step 3 is stored in the FIFO.
From the memory 3, the external data output signal line Qn3 is read, and the data (A) is written in the FIFO memory 4. Further, data (D) for one line of the external data input signal line Dn is written in the FIFO memory 1.

Next, in step 5 after the reset 4 operation,
The data (D) written in step 4 is read from the FIFO memory 1 to the external data output signal line Qn1, and the data (D) is written to the FIFO memory 2. Further, the data (C) written in step 4 is read from the FIFO memory 2 to the external data output signal line Qn2,
In addition, the data (C) is written in the FIFO memory 3. Further, the data (B) written in step 4 is stored in the FIFO.
The data (B) is read from the memory 3 to the external data output signal line Qn3, and the data (B) is written to the FIFO memory 4. Further, the data (A) written in step 4 is set to F
The data is read from the IFO memory 4 to the external data output signal line Qn4. Further, data (E) for one line of the external data input signal line Dn is written in the FIFO memory 1. The operation after step 6 is the same as that of step 5, and the description thereof is omitted.

[0010]

As described above, in the conventional image data storage means, the data read from the line memory is written into the other line memory to delay the delayed data string. Because I am getting
It was necessary for all line memories to perform write operations. Further, the power consumed for this purpose also increases as the number of line memories increases, and when a large number of line memories are required, this reduction of power consumption has been an important issue. An object of the present invention is to solve the above problems, and an object of the present invention is to obtain a line memory control device that outputs delayed data with low power consumption.

[0011]

In a line memory control device of the present invention, write control means for controlling the operation and order of writing an external data input signal to a plurality of line memories, and the plurality of line memories according to the write order. And a read control means for reading a plurality of output signals from each line memory with a predetermined delay from each other.

Further, the write control means receives the write selector control circuit connected to the external write control signal line and the external read control signal line, the output signal of the write selector control circuit and the external data input signal as input, and outputs a plurality of signals. The write control circuit is configured to output a signal to the line memory, and the read control means includes a read selector control circuit connected to the external read control signal line and the external write control signal line, and an output signal of the read selector control circuit. The read selector circuit receives the output signals of the plurality of line memories and outputs the external data output signal.

Further, in the above structure, a plurality of line memories are constituted by FIFO memories.

A plurality of line memories for temporarily storing image data for each unit, a data input signal line to which image data is serially input, a data output signal line of the same number as the plurality of line memories, and an image. Write control means for selecting the plurality of line memories sequentially and cyclically for each data unit and writing image data input to the selected line memory via the data input signal line, To sequentially and cyclically select the plurality of line memories according to the order of writing to the line memory, and to output a plurality of image data having a predetermined delay to the plurality of data output signal lines. The reading control means is provided.

Further, in the above configuration, the write control means controls the write selector for outputting the write decode selection signal for sequentially and cyclically selecting the plurality of line memories each time the image data for each unit is read. Circuit and a write decode selection signal from the write selector control circuit, and selects image data input via a data input signal line based on the received write decode select signal from the plurality of line memories. And a write selector circuit for transmitting the data via a data input line corresponding to a data input node of any one of the line memories.

The read control means outputs a read decode select signal for sequentially and cyclically selecting the plurality of line memories each time image data for each unit is read, and a read selector control circuit, Receiving the read decode select signal from the read selector control circuit, outputting the image data read from each of the plurality of line memories via the corresponding data output line based on the received read decode signal, and outputting the plurality of data. And a read selector circuit for selectively outputting to the signal line.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numerals 1 to 4 denote first to fourth line memories for storing image data in line units, respectively. , Each of which uses a FIFO memory capable of simultaneously writing and reading data without the need to specify an address, and includes a data input node, a data output node, a write reset signal input node, and a write A clock signal input node, a read reset signal input node, a read clock signal input node, and a memory array that stores image data for one line and has a number of memory cells corresponding to the image data for one line are provided. And works as follows.

First, the FIFO memories 1 to 4 can be written and read by signals (not shown). Next, when a write reset signal that means reset (“L” level in the first embodiment) is input to the write reset signal input node, the write state (write control circuit 14 and write selector control circuit in FIG. 4) is input. 5) is reset, and the image data serially input to the data input node at the clock timing of the write clock signal input to the write clock signal input node is sequentially stored in the memory cells located at the predetermined address according to the predetermined address order. The image data for one line is stored in the memory array.

On the other hand, when a read reset signal that means reset (“L” level in the first embodiment) is input to the read reset signal input node,
The read state (the read control circuit 18 and the read selector control circuit 6 in FIG. 4) is reset, and the read clock signal input to the read clock signal input node is sequentially located at a predetermined address in a predetermined address order according to the clock timing of the read clock signal. The image data stored in the memory cell is serially read to the data output node.

Then, the first to fourth line memories 1
Each of the FIFO memories constituting the parts 4 to 4 has the same structure as in the first embodiment.
Then, the configuration is as shown in FIG. In FIG. 4, reference numeral 16 denotes a memory cell selected by a write decode signal and capable of writing data (data rewriting), and a memory cell selected by a read decode signal and having data read out corresponds to at least one line of image data. The memory array has a number of memory cells, and is composed of, for example, an arbitrary number m words × an arbitrary number n bits.

Reference numeral 15 is a clock of the write clock signal (WCK) which is reset based on the write control circuit 14 which receives the write reset signal (WRESB) input to the write reset signal input node and which is input to the write clock signal input node. 1 based on timing
A write decoder that outputs a write decode signal that is shifted up by each address to the memory array 16 and is composed of, for example, a counter. Further, the write decoder 15 is set to automatically return to the first address when the memory array reaches m words.

Reference numeral 17 is reset based on the read control circuit 18 which receives the read reset signal (RRESB) input to the read reset signal input node, and is the clock of the read clock signal (RCK) input to the read clock signal input node. 1 based on timing
A read decoder that outputs a read decode signal that is shifted up by each address to the memory array 16 is used to select the memory cells of the memory array 16 in the same order as the memory cells of the memory array 16 are selected by the write decoder 15. It is selected, and is configured by, for example, a counter. further,
The read decoder 17 is set to automatically return to the first address when the memory array has reached m words.

Reference numeral 14 is reset based on the write reset signal (WRESB) input to the write reset signal input node, and based on the clock timing of the write clock signal (WCK) input to the write clock signal input node. Image data input to the memory cell of the memory array selected by the write decoder 15, and the write decoder 15
Is a write control circuit for controlling the.

Reference numeral 18 is reset based on the read reset signal (RRESB) input to the read reset signal input node, and the read decoder is based on the clock timing of the read clock signal (RCK) input to the read clock signal input node. A read control circuit that takes in the image data read from the memory cell of the memory array 16 selected by 17, outputs the taken image data to the data output signal line Q1n, and controls the read decoder 17.

Returning to FIG. 1, 9 is the FIFO memory 1 described above.
Write clock signal (WCK) and write reset signal (WRESB) used to execute the operation of writing the image data input to the data input nodes 4 to 4.
Is a write control signal line for transmitting to the write reset signal input node and the write clock signal input node of the first to fourth line memories 1 to 4, respectively.

The write reset signal (WRES
In the configuration of the present invention, B) is a signal that means reset of the write control circuit 14, the write selector control circuit 5, and the read selector control circuit 6 of the FIFO memories 1 to 4 before the data writing is started. It will be.

Reference numeral 10 denotes a read clock signal (RCK) used to execute an operation of reading the image data temporarily stored in the first to fourth line memories 1 to 4 to a data output node, and the FIFO memory 1 described above. 4 is a read control signal line for transmitting a read reset signal (RRESB) that means reset of the read control circuit 18, read selector control circuit 6, and write selector control circuit 5.

The read reset signal (RRES
B) resets the read selector that selects the FIFO memory to be read before reading one line of image data, resets the read decoder in the FIFO memory to start reading new data, and further This is a signal for resetting the write selector for performing new writing when the line reading is completed.

Dn is a data input signal line for transmitting input image data, and Qn1 to Qn4 are the FIFOs.
The first to fourth data output signal lines for transmitting the image data read from the memories 1 to 4, the first data output signal line Qn1 transmits the image data of the current line, and the second data output signal line Qn1 transmits the image data of the current line. The data output signal line Qn2 is 1 of the current line.
The third data output signal line Qn3 transmits the image data delayed by the line, and the third data output signal line Qn3 transmits the image data delayed by two lines of the current line and the fourth data output signal line Qn4.
Is for transmitting image data delayed by three lines of the current line.

Reference numeral 5 denotes a write clock signal (WCK) and a write reset signal (WRESB) transmitted through the write control signal line 9 and the read control signal line 10.
In response to the read clock signal (RCK) and the read reset signal (RRESB) transmitted in step S1, the image data for one line of the image data for each line of the image data based on the received signals. Every time the data is read, the first to fourth line memories 1 to 4 are sequentially and circulated, that is, the first → second → third → third → fourth → first
A write selector control circuit that outputs a write decode selection signal for selection as shown by → has the configuration shown in FIG. 3 in the first embodiment.

In FIG. 3, 11a is a write clock signal (WC) transmitted through the write control signal line 9.
K) and the write reset signal (WRESB) to reset the counter 12a.

The reference numeral 13a receives the read clock signal (RCK) and the read reset signal (RRESB) transmitted through the read control signal line 10, generates a clock signal, and inputs the signal as the clock of the counter 12a. , Each time the reading of the FIFO memory is completed, the count of the counter 12a is advanced.

Numeral 12a is reset by a reset signal from the reset signal generator 11a, counts based on the clock signal from the count clock signal generator 13a, and the write decode select signal is applied to the write selector control line S1. The output counter increments the count each time the image data is read from the first to fourth line memories 1 to 4. In the first embodiment, 2 bits are used as the write decode selection signal. For example, the count value (corresponding to the output value) 00 is the count value 0 in the first line memory 1 described above.
1 is set to select the second line memory 2, the count value 10 is set to select the third line memory 3, and the count value 11 is set to select the fourth line memory 4.

Returning to FIG. 1, numeral 7 receives the write decode select signal from the write selector control circuit 5 via the write selector control line S1, and based on the received write decode signal, the data input signal line Dn. Image data input via the data input line D corresponding to a data input node of any one of the first to fourth line memories 1 to 4 selected.
In the first embodiment, for example, in the write selector circuit for transmitting via 1n to D4n, an input node connected to the data input signal line Dn and the data input lines D1n to D1n.
First to fourth output nodes connected corresponding to D4n, a control node connected to the write selector control line S1, and corresponding first to fourth output nodes, respectively. The first to the third nodes, which are provided between the input node and the corresponding output node and make the input node and the corresponding output node conductive or non-conductive based on the decode selection signal input to the control node. And a fourth switching means.

By the write selector control circuit 5 and the write selector circuit 7, the data input signal line D is applied to the first to fourth line memories 1 to 4.
The operation and order of writing the image data input via n are controlled, that is, the first to fourth line memories 1 to 4 are sequentially and cyclically selected for each line of the image data. Write control means for writing the image data input via the data input signal line Dn into the selected line memory.

Reference numeral 6 denotes a write clock signal (WCK) and a write reset signal (WRESB) transmitted through the write control signal line 9 and the read control signal line 10.
In response to the read clock signal (RCK) and the read reset signal (RRESB) transmitted in step S1, the image data for one line of the image data for each line of the image data based on the received signals. Every time the data is read, the first to fourth line memories 1 to 4 are sequentially and circulated, that is, the first → second → third → third → fourth → first
A read selector control circuit for outputting a read decode selection signal for selection as shown by → has the configuration shown in FIG. 5 in the first embodiment.

In FIG. 5, 11b is a write clock signal (WC) transmitted through the write control signal line 9.
K), a write reset signal (WRESB), a read clock signal (RCK) transmitted through the read control signal line 10, and a read reset signal (RRES).
B) and a reset signal generator for resetting the counter 12b.

Reference numeral 13b receives the read clock signal (RCK) and the read reset signal (RRESB) transmitted through the read control signal line 10, and the received read reset signal (RRESB) means reset. It is a count clock signal generator that outputs a clock signal in synchronization with (RCK).

12b is reset by a reset signal from the reset signal generator 11b, counts based on the clock signal from the count clock signal generator 13b, and outputs a read decode select signal to the read selector control line S2. The output counter increments the count each time the image data is read from the first to fourth line memories 1 to 4, and in the first embodiment, 2 bits are used as the read decode selection signal. The count value (corresponding to the output value) 00 is the first state, the count value 01 is the second state, the count value 10 is the third state, and the count value 11 is the fourth state. It is set to be selected.

Returning to FIG. 1, reference numeral 8 receives the read decode selection signal from the read selector control circuit 6 via the read selector control line S2, and based on the received read decode signal, the first to fourth portions. Corresponding data output lines Q1n to
The read selector circuit selectively outputs the image data read via Q4n to the first to fourth data output signal lines Qn1 to Qn4.

In the first embodiment, the read selector circuit 8 has the first line to the first data output signal line Qn1 when the decode signal indicates the first state (eg, step 6 in FIG. 2). The image data read from the memory 1, the image data read from the fourth line memory 4 to the second data output signal line Qn2, the third line memory 3 to the third data output signal line Qn3. The image data read from the image data read from the second line memory 2 is transmitted to the fourth data output signal line Qn4, and the first data output signal is output when the second state is indicated. The image data read from the second line memory 2 to the line Qn1, the image data read from the first line memory 1 to the second data output signal line Qn2, the third data output signal The image data read from the fourth line memory 4 is transmitted to the line Qn3, and the image data read from the third line memory 3 is transmitted to the fourth data output signal line Qn4. First when showing
Image data read from the third line memory 3 to the second data output signal line Qn1 of the second data output signal line Qn1.
The image data read from the second line memory 2 is input to n2, the image data read from the first line memory 1 to the third data output signal line Qn3, and the image data read to the fourth data output signal line Qn4. The image data read from the fourth line memory 4 is transmitted, and when the fourth state is indicated, the image data read from the fourth line memory 4 is transferred to the first data output signal line Qn1. The image data read from the third line memory 3 is output to the second data output signal line Qn2, and the image data read from the second line memory 2 is output to the third data output signal line Qn3. The image data read from the first line memory 1 is transmitted to the respective data output signal lines Qn4.

That is, the first data output signal line Qn1 for each line of image data is 1st → 2nd → 3rd → 4th →
The image data read from the first to fourth line memories 1 to 4 in the order from the first to the ... Is transmitted as the image data of the current line, and is transmitted to the second data output signal line Qn2. The first data output signal line Qn1 is delayed by one line of the image data, and is cycled in the order of 1st → 2nd → 3rd → 4th → 1st → ... Or the image data read from the fourth line memories 1 to 4 is transmitted as image data delayed by one line of the current line, and the third data output signal line Qn is transmitted.
3 to the image data 2 from the first data output signal line Qn1.
The line is delayed by the first line and the first line
The second → the third → the fourth → the first → ...
Or the image data read from the fourth line memories 1 to 4 is transmitted as image data delayed by two lines of the current line, and the first data output signal line Qn1 is transmitted to the fourth data output signal line Qn4. After being delayed by three lines of image data, the first → second → for each line of image data.
The image data read out from the first to fourth line memories 1 to 4 in the order of third->fourth->first-> is transferred as image data delayed by three lines of the current line. It functions to let you.

For example, the first to fourth line memories 1 to 4 are provided corresponding to the respective first to fourth line memories 1 to 4 and are connected to the data output lines Q1n to Q4n connected to the output nodes of the corresponding line memories. To fourth input nodes, first to fourth output nodes connected to the data output signal lines Qn1 to Qn4, a control node connected to the read selector control line S2, and the first to fourth input nodes. The fourth output node is provided corresponding to each of the first to fourth input nodes and the corresponding output node, and based on the read decode selection signal input to the control node, A conductive state is established between an input node selected from the first to fourth input nodes and a corresponding output node, and an output node corresponding to a non-selected input node Those having a non-conducting state and forming first through fourth switching means between.

The read selector control circuit 6 and the read selector circuit 8 select the first to fourth line memories 1 to 4 in accordance with the order of writing to the first to fourth line memories 1 to 4. And
A plurality of image data having mutually predetermined delays are obtained as outputs, that is, the data output signal lines Qn1 to Qn4.
The image data is sequentially delayed by one line, and the first to fourth line memories 1 to 4 are sequentially and cyclically selected for each line of the image data, and the selected line memory is selected. It constitutes a read control means for outputting the image data read from the data output signal lines Qn1 to Qn4.

Next, the operation of the image data processing apparatus configured as described above will be described for each operation state with reference to FIG. 2 showing the operation timing. [Initial State] In the initial state, all the line memories 1 to 4 are in an initial state, for example, all the memory cells are in an undefined state, and the write reset signal (WRES
B) and the read reset signal (RRESB) do not output a signal indicating reset, so that neither the write operation nor the read operation is performed.

Similarly, the write reset signal (WRES
B) and the read reset signal (RRESB) do not output the signal indicating reset, the write selector control circuit 5 and the read selector control circuit 6 also do not output the decode selection signal, and the write selector circuit 7 receives the data input line. The read selector circuit 8 sets the data output signal lines Qn1 to D1n to D4n in the high impedance state.
~ Qn4 is in a high impedance state.

[Step 1] As shown in FIG. 2B, when the write reset signal (WRESB) means reset, that is, when the write reset signal (WRESB) becomes "L" level, the write reset state is set. That is, the first line memory 1 is reset to the write state, the write selector control circuit 5 outputs the write decode selection signal consisting of “00”, and the write selector circuit 7 outputs the data input signal line Dn and the The input node of the first line memory 1 is made conductive, and the data input signal line Dn and the second to fourth line memories 2 to 4 are made non-conductive.

Therefore, the image data (A) appearing on the data input signal line Dn (see (c) of FIG. 2) is first synchronized with the clock of the write clock signal (WCK) shown in (a) of FIG. Are stored in the first line memory 1 according to a predetermined address order. The image data (A) indicates the image data on the first line, and the first line is determined by the number of clocks of the write clock signal (WCK) for one line.
Will be written in the line memory 1.

In addition, the second to fourth line memories 2 to
In No. 4, since the input node of each of them is set to the non-conduction state with the data input signal line Dn by the write selector circuit 7, the image data is not written.

Further, a read reset signal (RRES
Since B) does not output a signal that means reset,
The read selector control circuit 6 does not output the decode selection signal either, and the read selector circuit 8 outputs the data output signal line Qn.
1 to Qn4 are in a high impedance state. In short, in this step 1, the operation of writing the image data (A) in the first line memory 1 is performed.

[Step 2] At the timing when the writing of the image data (A) into the first line memory 1 is completed, the read reset signal (RRESB) means reset, as shown in (e) of FIG. That is, when the level becomes "L", the read reset state (reset 1) is set.

That is, the write selector control circuit 5 outputs a write decode select signal consisting of "01", and the write selector circuit 7 outputs the data input signal line D.
n and the input node of the second line memory 2 are made conductive, and the data input signal line Dn and the first, third and fourth line memories 1, 3 and 4 are made non-conductive, and a read selector control circuit A read decode select signal consisting of "00" is output from 6, and the read selector circuit 8
The first state, that is, the first data output signal line Qn1 and the output node of the first line memory 1, the second data output signal line Qn2 and the output node of the fourth line memory 4, 3 data output signal line Qn3 and the output node of the third line memory 3 are connected to the fourth data output signal line Qn.
4 and the output node of the second line memory 2 are brought into conduction with each other.

Therefore, the image data (B) appearing on the data input signal line Dn (see (c) of FIG. 2) is synchronized with the clock of the write clock signal (WCK) shown in (a) of FIG. Are taken into the line memory 2 and are stored in the second line memory 2 according to a predetermined address order. The image data (B) shows the image data in the second line, and the second line is determined by the number of clocks of the write clock signal (WCK) for one line.
Will be written into the line memory 2.

Since the input nodes of the first, third and fourth line memories 1, 3 and 4 are not electrically connected to the data input signal line Dn by the write selector circuit 7, the image data ( B) is not written.

On the other hand, the first line memory 1 is stored in the first line memory 1 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. 2A is read out to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in FIG. As shown in (f), the read image data (A) passes through the first data output line Q1n and the read selector circuit 8 and the first data output signal line Q.
It will be output to n1.

The second to fourth line memories 2 to
4 is also reset to the read state when the read reset signal (RRESB) means reset,
Since the storage state is still in the initial state at the time of reading, the image data is not output to the second to fourth data output signal lines Qn2 to Qn4.

In short, in this step 2, the image data (B) is written in the second line memory 2, and the image data (A) stored in the first line memory 1 is stored in the first line memory 1. The operation of reading to the data output signal line Qn1 is performed.

[Step 3] Timing at which writing of the image data (B) into the second line memory 2 is completed, that is, the first data output signal line Qn of the image data (A).
At the timing when reading from 1 ends, as shown in (e) of FIG.
When B) means reset, that is, when it goes to "L" level, the read reset state (reset 2) is entered.

That is, the write selector control circuit 5 outputs a write decode select signal consisting of "10", and the write selector circuit 7 outputs the data input signal line D.
n and the input node of the third line memory 3 are in a conductive state, and the data input signal line Dn and the first, second and fourth line memories 1, 2 and 4 are in a non-conductive state, and a read selector control circuit A read decode select signal consisting of "01" is output from 6, and the read selector circuit 8
The second state, that is, the first data output signal line Qn1 and the output node of the second line memory 2, the second data output signal line Qn2 and the output node of the first line memory 1, 3 data output signal line Qn3 and the output node of the fourth line memory 4 are connected to the fourth data output signal line Qn.
4 and the output node of the third line memory 3 are brought into conduction with each other.

Therefore, the image data (C) appearing on the data input signal line Dn (see (c) of FIG. 2) is synchronized with the clock of the write clock signal (WCK) shown in (a) of FIG. Are stored in the third line memory 3 according to a predetermined address order. The image data (C) shows the image data in the third line, and the image data (C) is the third data depending on the number of clocks of the write clock signal (WCK) for one line.
Will be written in the line memory 3.

Further, the input nodes of the first, second and fourth line memories 1, 2 and 4 are made non-conductive with the data input signal line Dn by the write selector circuit 7, so that the image data ( C) is not written.

On the other hand, the first line memory 1 is reset to the read state when the read reset signal (RRESB) means reset, that is, when the read reset signal (RRESB) is at the “L” level, the first line memory 1 is stored in the first line memory 1. 2A is read out to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in FIG. (G), the read image data (A) passes through the first data output line Q1n and the read selector circuit 8 to the second data output signal line Q.
It will be output to n2.

The second line memory 2 is also stored in the second line memory 2 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. Image data (B) is read to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in (d) of FIG. (F), the read image data (B) passes through the second data output line Q2n and the read selector circuit 8 and the first data output signal line Q.
It will be output to n1.

Incidentally, the third and fourth line memories 3, 4
Also, when the read reset signal (RRESB) means reset, it is reset to the read state, but since the storage state is still the initial state at the time of read, the third and fourth data output signal lines Qn3, Not output to Qn4.

In short, in this step 3, the image data (C) is written in the third line memory 3, and the image data (A) stored in the first line memory 1 is stored in the second line memory 3. The image data (B) read out to the data output signal line Qn2 and stored in the second line memory 2 is read out to the first data output signal line Qn1.

[Step 4] Timing at which the writing of the image data (C) to the third line memory 3 is completed, that is, the first and second data output signal lines Qn1 of the image data (A) and (B). , At the timing when the reading from Qn2 ends, the read reset signal (RRESB) means reset as shown in (e) of FIG. 2, that is, when it becomes the “L” level, the read reset state (reset 3) is set. Become.

That is, the write selector control circuit 5 outputs a write decode select signal consisting of "11", and the write selector circuit 7 outputs the data input signal line D.
n and the input node of the fourth line memory 4 are brought into conduction, the data input signal line Dn and the first to third line memories 1 to 3 are brought out of conduction, and the read selector control circuit 6 outputs “10”. And the read selector circuit 8 outputs the read data to the third state, that is, the first data output signal line Qn1 and the output node of the third line memory 3 to the second data. The output signal line Qn2 and the output node of the second line memory 2, the third data output signal line Qn3 and the output node of the first line memory 1, and the fourth data output signal line Qn4 and the fourth data output signal line Qn4.
The output node of the line memory 4 of FIG.

Therefore, the image data (D) appearing on the data input signal line Dn (see (c) of FIG. 2) is synchronized with the clock of the write clock signal (WCK) shown in (a) of FIG. Are stored in the fourth line memory 4 according to a predetermined address order. The image data (D) indicates the image data in the fourth line, and the image data (D) corresponds to the fourth line depending on the number of clocks of the write clock signal (WCK) for one line.
Will be written in the line memory 4.

Further, the first to third line memories 1 to 1
In No. 3, since the input node of each of them is set to the non-conduction state with the data input signal line Dn by the write selector circuit 7, the image data (D) is not written.

On the other hand, the first line memory 1 is reset to the read state when the read reset signal (RRESB) means reset, that is, when the read reset signal (RRESB) is at the “L” level, the first line memory 1 is stored in the first line memory 1. 2A is read out to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in FIG. (H), the read image data (A) passes through the first data output line Q1n and the read selector circuit 8 and the third data output signal line Q.
It will be output to n3.

The second line memory 2 is also stored in the second line memory 2 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. Image data (B) is read to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in (d) of FIG. (G), the read image data (B) passes through the second data output line Q2n and the read selector circuit 8 and the second data output signal line Q.
It will be output to n2.

Furthermore, the third line memory 3 is also stored in the third line memory 3 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. Image data (C) is read to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in (d) of FIG. (F), the read image data (C) passes through the third data output line Q3n and the read selector circuit 8 and the first data output signal line Q.
It will be output to n1.

In the fourth line memory 4 as well, if the read reset signal (RRESB) means reset,
Although it is reset to the reading state, the memory state is still in the initial state at the time of reading, so that the image data is not output to the fourth data output signal line Qn4.

In short, in step 4, the image data (D) is written in the fourth line memory 4, and the image data (A) stored in the first line memory 1 is stored in the third line memory 4. The image data (B) read out to the data output signal line Qn3 and stored in the second line memory 2 is read out to the second data output signal line Qn2 and stored in the third line memory 3. The operation of reading the data (C) to the first data output signal line Qn1 is performed.

[Step 5] Timing at which the writing of the image data (D) to the fourth line memory 4 is completed, that is, the first to the third of the image data (A) to (C).
At the timing when the reading from the data output signal lines Qn1 to Qn3 ends, the read reset signal (RRESB) means reset as shown in (e) of FIG. The state (reset 4) is entered.

That is, the write decode select signal consisting of "00" is output from the write selector control circuit 5, and the write selector circuit 7 inputs the data input signal line Dn and the first line memory 1 as in step 1. The node is made conductive, the data input signal line Dn and the second to fourth line memories 2 to 4 are made non-conductive, and the read selector control circuit 6 outputs a read decode select signal consisting of "11". Then, the read selector circuit 8 sets the fourth state, that is, the first data output signal line Qn1 and the output node of the fourth line memory 4 to the second data output signal line Qn2 and the third line memory. 3 output node to the third data output signal line Qn3
The output node of the line memory 2 and the fourth data output signal line Qn4 are brought into conduction with the first line memory 1.

Therefore, the image data (E) appearing on the data input signal line Dn (see (c) of FIG. 2) is first synchronized with the clock of the write clock signal (WCK) shown in (a) of FIG. Are stored in the first line memory 1 according to a predetermined address order. The image data (E) shows the image data in the fifth line, and the first line is determined by the number of clocks of the write clock signal (WCK) for one line.
Will be written in the line memory 1.

Also, the second to fourth line memories 2 to 2
In No. 4, since the input node of each of them is made non-conductive with the data input signal line Dn by the write selector circuit 7, the image data (E) is not written.

On the other hand, the first line memory 1 is stored in the first line memory 1 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. 2A is read out to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in FIG. (I), the read image data (A) passes through the first data output line Q1n and the read selector circuit 8 and the fourth data output signal line Q.
It will be output to n4.

The second line memory 2 is also stored in the second line memory 2 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. Image data (B) is read to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in (d) of FIG. (H), the read image data (B) passes through the second data output line Q2n and the read selector circuit 8 and the third data output signal line Q.
It will be output to n3.

Further, the third line memory 3 is also stored in the third line memory 3 because it is reset to the read state when the read reset signal (RRESB) is reset, that is, when it goes to "L" level. Image data (C) is read to the output node according to the same predetermined address order as the address order written in synchronization with the clock of the read clock signal (RCK) shown in (d) of FIG. (G), the read image data (C) passes through the third data output line Q3n and the read selector circuit 8 and the second data output signal line Q.
It will be output to n2.

Furthermore, in the fourth line memory 4, the read reset signal (RRESB) means reset,
In other words, when it becomes the “L” level, it is reset to the read state, so that the image data (D) stored in the fourth line memory 4 becomes the read clock signal (RCK) shown in FIG. The read image data (D) is read out to the output node according to a predetermined address order that is the same as the address order written in synchronization with the clock, and the read image data (D) is output as the first data output, as shown in (f) of FIG. It is output to the first data output signal line Qn1 via the line Q1n and the read selector circuit 8.

In summary, in step 5, the image data (E) is rewritten to the image data (A) in the first line memory 1 and the image data (E) is stored in the first line memory 1. The previously stored image data (A) is read to the fourth data output signal line Qn4, and the image data (B) stored in the second line memory 2 is read to the third data output signal line Qn3. Issued,
The image data (C) stored in the third line memory 3 is read out to the second data output signal line Qn2, and the image data (D) stored in the fourth line memory 4 is output as the first data. The operation of reading to the signal line Qn1 is performed.

[Step 6] Timing at which the writing of the image data (E) to the first line memory 1 is completed, that is, the first to fourth of the image data (A) to (D).
When the read from the data output signal lines Qn1 to Qn4 is completed, the read reset signal (RRESB) means reset as shown in (e) of FIG. The state (reset 5) is entered.

That is, the write decode selection signal consisting of "01" is output from the write selector control circuit 5, and the write selector circuit 7 inputs the data input signal line Dn and the second line memory 2 as in step 2. The node and the data input signal line Dn and the first,
The third and fourth line memories 1, 3 and 4 are brought into a non-conduction state, the read selector control circuit 6 outputs a read decode select signal consisting of “00”, and the read selector circuit 8 performs the step 2 Similarly, the first state is set.

As a result, as in step 2, in this step 6, the image data (F) is rewritten to the image data (B) in the second line memory 2 and the first line memory 1 is also executed. The image data (E) stored in the first data output signal line Qn1 is read out, and the image data (B) stored before the image data (F) in the second line memory 2 is stored in the fourth data output signal line Qn1. Data output signal line Q
The image data (C) read to n4 and stored in the third line memory 3 is read to the third data output signal line Qn3 and stored in the fourth line memory 4 (D). Is read out to the second data output signal line Qn2. Thereafter, the same operations as those in Step 3, Step 4, and Step 5 are repeatedly performed, and the image data for each line transmitted through the data input signal line Dn is stored in the first to fourth line memories 1 to 4 in a predetermined manner. Is written in any one of the line memories selected according to the write order, and the remaining three unselected line memories are not subjected to the write operation, and are stored in the first to fourth line memories 1 to 4. The image data is read to the first to fourth data output signal lines Qn1 to Qn4 according to a predetermined reading order, and the image data of the current line is read to the first data output signal line Qn1.
Image data delayed by one line of the current line is input to the second data output signal line Qn2, and image data delayed by two lines of the current line is output to the third data output signal line Qn3. Image data delayed by 3 lines of the current line will appear on the data output signal line Qn4.

In the first embodiment, the first
Although the fourth line memories 1 to 4 are FIFO memories, they may be configured by using an ordinary SRAM or DRAM. In this case, the write selector control circuit 5, the write selector circuit 7, and the read selector control described above may be used. The same effect can be obtained by combining with the addressing means composed of the circuit 6 and the read selector circuit 8, and even if it is composed of a sequential access memory or a LIFO (Last in First Out). The effect of.

[0088]

Since the line memory control device of the present invention is constructed as described above, it has the following effects.

Write control means for controlling the operation and order of writing the external data input signal to the plurality of line memories, the plurality of line memories are selected according to the write order, and each line memory has a predetermined delay from each other. In addition, since the read control means for reading out a plurality of output signals is provided, the write operation to each line memory is required only once, and the power consumption associated with the write operation can be significantly reduced.

The write control means receives the write selector control circuit connected to the external write control signal line and the external read control signal line, the output signal of the write selector control circuit, and the external data input signal as inputs.
The read control means is composed of a write selector circuit that outputs signals to a plurality of line memories, and the read control means is a read selector control circuit connected to the external read control signal line and the external write control signal line, and the output of the read selector control circuit. Since it is composed of a read selector circuit that receives signals and output signals of the plurality of line memories and outputs external data output signals, the power consumption can be reduced with a simple configuration.

Further, since the plurality of line memories are constituted by the FIFO memories, it is not necessary to provide any addressing means, and the constitution can be simplified.

Further, a plurality of line memories for temporarily storing the image data for each unit, a data input signal line for serially inputting the image data, and a data output signal line of the same number as the plurality of line memories. And write control means for selecting the plurality of line memories sequentially and cyclically for each unit of image data, and writing the image data input through the data input signal line into the selected line memory. According to the order of writing to the plurality of line memories, the plurality of line memories are sequentially and cyclically selected, and a plurality of image data having a predetermined delay from each other are output to the plurality of data output signal lines. And an image data processing device having a read control means for outputting the image data. Can.

Further, the write control means outputs a write decode select signal for sequentially and cyclically selecting the plurality of line memories each time the image data for each unit is read, and a write selector control circuit, Image data input via the data input signal line based on the received write decode selection signal from the write selector control circuit is selected from among the plurality of line memories selected above. Since it is provided with a write selector circuit which transmits via a data input line corresponding to a data input node of one line memory, it is possible to obtain an image data processing device of low power consumption with a simple configuration.

The read control means outputs a read decode select signal for sequentially and cyclically selecting the plurality of line memories each time image data for each unit is read, and a read selector control circuit for outputting the read decode select signals. Receiving the read decode select signal from the read selector control circuit, outputting the image data read from each of the plurality of line memories via the corresponding data output line based on the received read decode signal, and outputting the plurality of data. Since it is provided with a read selector circuit for selectively outputting to the signal line, it is possible to obtain an image data processing device with a simple configuration and low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a line memory control device and a line memory according to an embodiment of the present invention.

FIG. 2 is a timing waveform chart of the line memory control device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a write selector control circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a FIFO memory as an example of a line memory according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a read selector control circuit according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional image data storage means and line memory.

FIG. 7 is a timing waveform chart of a conventional image data storage means.

[Explanation of symbols]

 1-4 line memory (FIFO memory) 5 write selector control circuit 6 read selector control circuit 7 write selector circuit 8 read selector circuit 9 external write control signal line 10 external read control signal line 11a reset signal generator 11b reset signal generator 12 Counter 13a Count clock signal generator 13b Count clock signal generator 14 Write control circuit 15 Write decoder 16 Memory array 17 Read decoder 18 Read control circuit Dn External data input signal lines Qn1 to Qn4 External data output signal line WCK Write clock signal WRESB Write Reset signal RCK Read clock signal RRESB Read reset signal S1 Write selector control line S2 Read selector control line D1n- 4n data input signal lines Q1n~Q4n data output signal line

Claims (6)

[Claims] 1. A write control means for controlling an operation and a sequence of writing an external data input signal to a plurality of line memories, selecting the plurality of line memories according to the write order, and delaying a predetermined delay from each line memory. A line memory control device having a read control means for reading out a plurality of output signals by having a read signal. 2. The write control means receives a write selector control circuit connected to the external write control signal line and the external read control signal line, an output signal of the write selector control circuit, and an external data input signal, And a read selector control circuit connected to the external read control signal line and the external write control signal line, and an output signal of the read selector control circuit. 2. The line memory control device according to claim 1, further comprising a read selector circuit that receives the output signals of the plurality of line memories and outputs the external data output signal. 3. The line memory control device according to claim 1, wherein the plurality of line memories are FIFO memories. 4. A plurality of line memories for temporarily storing image data for each unit, a data input signal line for serially inputting image data, a data output signal line of the same number as the plurality of line memories, and an image. Write control means for sequentially and cyclically selecting the plurality of line memories for each data unit and writing image data input to the selected line memory via the data input signal line, The plurality of line memories are sequentially and cyclically selected in accordance with the writing order to the line memory, and a plurality of image data having a predetermined delay is output to the plurality of data output signal lines. Image data processing apparatus including a reading control unit for reading. 5. A write selector control circuit which outputs a write decode select signal for sequentially and cyclically selecting the plurality of line memories each time the write control means reads image data for each unit, and Image data input via the data input signal line based on the received write decode selection signal from the write selector control circuit is selected from among the plurality of line memories selected above. 5. The image data processing device according to claim 4, further comprising a write selector circuit which transmits the data via a data input line corresponding to a data input node of one line memory. 6. A read selector control circuit which outputs a read decode select signal for sequentially and cyclically selecting the plurality of line memories each time the read control means reads image data for each unit, and Receiving the read decode select signal from the read selector control circuit, outputting the image data read from each of the plurality of line memories via the corresponding data output line based on the received read decode signal, and outputting the plurality of data. The image data processing device according to claim 4 or 5, further comprising a read selector circuit that selectively outputs to a signal line.