JPH09191298A - Data receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the circuit by storing once received data to a data storage means and allowing a DSP(digital signal processor) to detect a symbol identification point and to recover a bit clock based on a sum result of a synchronization adder means. SOLUTION: A detector 23 detects a reception signal Sa and an A/D converter 24 applies over-sampling to I, Q signals and the result is stored once in a memory 25. A synchronization adder section 26 applies synchronization addition arithmetic operation to the digitized I, Q signals and a symbol identification point detection section 27 detects a maximum value of the arithmetic operation result and a data decoding section 29 decodes data of the symbol identification point stored in the memory. A clock phase correction section 28 detects a phase shift based on information from the symbol identification point detection section 27 to recover a bit clock. The synchronization adder section 26, the generating by the symbol identification point detection section 27, the clock phase correction section 28 and the decoding section 29 is conducted by digital signal software processing to make the circuit scale small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device for digital communication, and more particularly to a device for reproducing a bit clock with a device having a small circuit scale.

[0002]

2. Description of the Related Art A data receiving device can obtain information from a received signal by establishing frame synchronization with a transmitting side. In order to establish this frame synchronization, the data receiving device first regenerates a bit clock that is in phase synchronization with the symbol identification point of the received signal, and then uses this bit clock to generate a signal at the symbol identification point of the received signal. To detect the sync word contained in the received signal,
You have acquired frame synchronization.

As shown in FIG. 19, a conventional data receiving apparatus which performs such an operation detects a received signal Sa by a free-running clock, a detecting means 3, an oscillator 1 for generating the free-running clock, and a frequency divider. 2, a clock extraction means 4 for extracting a reference bit clock from the output of the detection means 3, and a digital PLL (Phase Locked Loop) means 5 for suppressing the jitter amount of the reference bit clock.
And an A / D conversion means 8 for analog-digital converting the output of the detection means 3 using the reproduced bit clock output from the digital PLL means 5 as a sampling clock.
A data decoding means 9 for decoding data from the received signal digitized by the A / D conversion means 8; and a frame synchronization means for extracting a synchronization word from the decoded data to obtain frame synchronization and generating a timer reset signal. Ten
And the reproduced bit clock output from the digital PLL means 5 is used as a timer clock, the frame synchronization is maintained by the timer reset signal output from the frame synchronization means 10, and a timing signal synchronized with the frame is generated for the receiving device. Frame synchronization timing generating means
11 and are provided.

Further, the digital PLL means 5 is output from the variable frequency dividing means 6 for varying the frequency division ratio of the free-running clock according to the control signal, the reference clock output from the clock extracting means 4 and the variable frequency dividing means 6. And a phase ratio comparison means 7 for comparing the phase with the clock and outputting a control signal for setting the variable frequency division ratio to the variable frequency division means 6.

The operation of this device will be described.

First, the clock reproducing operation in this apparatus will be described. FIG. 20 is a timing example schematically showing the timing of clock reproduction. Clock extraction means 4
Extracts from the output of the detection means 3 a reference clock that is synchronized with the bit clock (clock that is in phase synchronization with the symbol identification point). However, the reference clock has jitter due to Rayleigh fading on the line, noise generated by the radio section of the receiving device, and the like. The digital PLL means 5 minimizes this jitter component and reproduces the bit clock.

Next, the receiving operation and the frame synchronizing operation will be described. The A / D conversion means 8 converts the received signal into a digital signal at the symbol identification point in accordance with the reproduced bit clock phase-synchronized with the symbol identification point, and the data decoding circuit 9 converts the converted digital signal. Get the decrypted data.

FIG. 21 shows a frame configuration example showing the configuration of decoded data. As shown in the figure, the decoded data is composed of a data part and a sync word part which is known data, and the data is periodically received by this frame structure. The data receiving device acquires frame synchronization by taking the bit correlation with the synchronization word from the received signal Sa.

FIG. 22 is a timing chart showing a timing example of the frame synchronization timing signal. When the frame synchronization means 10 detects the acquisition of the frame synchronization, it sends a timer reset signal to the frame synchronization timing generation means 11. Frame synchronization timing generation means 11
Has a timer of the same cycle as the TDMA frame, and starts a timer count operation in synchronization with the TDMA frame by a timer reset signal. Then, a frame synchronization timing signal is generated according to the count value of this timer.

[0010]

However, the conventional data receiving apparatus requires a dedicated circuit such as the clock extracting means 4 and the digital PLL means 5 for reproducing the bit clock, which increases the circuit scale. Moreover, since the clock extraction means 4 handles analog signals, there is a problem in that the circuit becomes complicated in configuring the receiving device.

At the time of pulling in the initial synchronization, the reference clock and the variable frequency dividing means 6 of the digital PLL means 5 are also included.
If the phases of and are deviated by a value close to π, there is a problem that it takes time to pull in the synchronization.

The present invention solves the above-mentioned problems of the prior art, and the bit clock can be regenerated by a simple mechanism and by a digital signal processing with a small amount of calculation, and the initial synchronization can be performed at high speed. An object of the present invention is to provide a retractable data receiving device.

[0013]

Therefore, in the data receiving apparatus of the present invention, the received signal is oversampled at a sampling frequency N times the symbol rate (N is an integer),
A / D conversion means for digitizing the sample value, and A / D
A data storage means for storing the D-converted digital signal is provided, and the sample values read from the data storage means are synchronously added over M symbol intervals (M is an integer) at each symbol interval, and the symbol identification is performed from the result. A point is detected, the clock is corrected from the deviation of the symbol identification point to generate a reproduction bit clock, and a timing signal synchronized with the TDMA frame is generated based on the decoded synchronization word.

This device has a simple configuration and is a DSP.
The bit clock can be reproduced by digital signal processing using (Digital Signal Processor) or the like. At this time, since the received data is temporarily stored in the data storage means, even if the digital signal processing time exceeds the reception slot time, the processing can be performed in time series after the data is stored.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a data receiving apparatus for recovering a bit clock from a received signal, decoding the data, and generating a frame synchronization timing signal. N times (N
A / D conversion means for oversampling at a sampling frequency of
Data accumulating means for storing the A / D converted digital signal, and sample values read from the data accumulating means are synchronously added over M symbol intervals (M is an integer) at each symbol interval, and N synchronous addition results are obtained. , A symbol identification point detecting means for detecting a symbol identification point from the synchronous addition result obtained by the synchronous adding means, and a data decoding means for performing data decoding at the symbol identification point detected by the symbol identification point detecting means. And a clock correction means for detecting a difference between the symbol identification points detected for different reception slots and correcting the clock based on the difference to generate a reproduction bit clock, and a frame based on the decoded synchronization word. A timing control means for acquiring synchronization and generating a timing signal synchronized with the TDMA frame is provided. Apparatus and clock extraction means comprise, phase comparing means in the digital PLL unit is not required, the configuration is simplified. Also, the bit clock can be reproduced by digital signal processing using a DSP or the like. At this time, since the data storage means for temporarily storing the received data is provided, even if the combined processing time of the synchronous addition processing, the symbol identification point detection processing, the clock phase correction processing, and the data decoding processing exceeds the reception slot time, These functions can be processed in a time series by the batch processing of accumulation.

According to a second aspect of the present invention, the clock correcting means is configured to variably divide the frequency of the free-running bit clock based on the difference to generate a regenerated bit clock. The regenerated bit clock is input to a necessary part of the timing control means or the data receiving device.

According to a third aspect of the present invention, the clock correction means corrects the initial value of the frame synchronization timer operating at Nt times the bit rate based on the difference. In this case, the variable frequency dividing means is also unnecessary, and the circuit scale can be reduced. Also, PLL
Since the phase comparison operation in the means is not required, the initial synchronization pull-in can be performed at high speed.

According to a fourth aspect of the present invention, when the synchronous addition means sets the number of symbols in the reception slot to L, L> M
The sample value is configured to be synchronously added over the M symbol section having the relationship of, and it is possible to reduce the amount of calculation in the synchronous addition process when using the DSP, and to achieve low power consumption. You can

According to a fifth aspect of the present invention, the synchronous addition means has three sample points including the symbol identification point detected based on the result of the previous synchronous addition over the M symbol interval and the sample points before and after the symbol identification point. The symbol identification point detecting means detects the symbol identification points from the three points, and the amount of calculation in the synchronous addition processing when using the DSP can be reduced. Therefore, low power consumption can be achieved.

According to a sixth aspect of the present invention, the data accumulating means has three sample points including the symbol identification point detected based on the result of the previous synchronous addition over the M symbol section and the sample points before and after the symbol identification point. Is configured to store the sample value of, and the capacity of the data storage means can be significantly reduced.

According to a seventh aspect of the present invention, the intermittent clock is supplied to the A / D converting means in response to the timing signal synchronized with the TDMA frame generated from the timing controlling means and supplying the free-running clock only during the slot receiving period. Since the generation means is provided, the A / D conversion means can be operated intermittently to achieve low power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) As shown in FIG. 1, the data receiving apparatus of the first embodiment generates a detecting means 23 for detecting the received signal Sa by a free-running clock and a free-running clock thereof. A / D for digitizing the I and Q signals output from the oscillator 21, the frequency divider 22, and the detecting means 23 by using a free-running clock at a sampling frequency N times the symbol rate (N is an integer). Conversion means 24
And a data storage means 25 for storing the A / D-converted digital signal, and a sample value of one symbol section oversampled at N times the symbol rate over M symbol sections (M is an integer) at every symbol interval. Synchronous addition means 26 to obtain N synchronous addition results, symbol identification point detection means 27 for detecting symbol identification points based on the synchronous addition results of the synchronous addition means 26, and symbol identification point detection means 27. Data decoding means 29 for performing data decoding at the detected symbol identification point, frame synchronization means 30 for extracting a synchronization word from the decoded data, acquiring frame synchronization and generating a timer reset signal, and symbol identification point detection means 27. Based on the obtained symbol identification point information, the phase shift from the base station is detected, and the phase of the free-running bit clock is corrected to synchronize with the base station. And a frame synchronization timing generating means for generating a timing signal synchronized with the TDMA frame by using the reproduced bit clock as an operation clock.
31.

Next, the operation of this data receiving apparatus will be described. First, the data storage means 25, the synchronous addition means 26,
The operations of the symbol identification point detecting means 27 and the data decoding means 29 will be described.

FIG. 2 is a diagram schematically showing symbol waveforms of I and Q signals after detection. For ease of explanation, here, the sampling rate N of the A / D conversion means 24 is used.
Will be assumed to be 10 and the number of synchronous addition symbols will be M symbols. As shown in FIG. 2, the A / D conversion means 24 performs analog-digital conversion on the detected I and Q signals at a sampling rate 10 times the symbol rate.

The synchronous adding means 26 is a digitized I
And the Q signal are subjected to the synchronous addition operation by the following equation 1.

A ₀ = Σ (I _j0 ² + Q _j0 ² ) A ₁ = Σ (I _j1 ² + Q _j1 ² ) ‥‥‥‥‥‥‥‥ A ₉ = Σ (I _j9 ² + Q _j9 ² ) (Equation 1 (However, Σ is added from j = 0 to M−1) The ten results of A _{0 to} A ₉ obtained by the synchronous addition operation become a waveform having a peak as shown in the example of FIG. .
In FIG. 3, A ₅ indicates the maximum value, and at this time, the symbol identification point detecting means 27 determines that the symbol identification point number is 5.

On the other hand, as shown in FIG. 4, the data storage means 25 has a two-sided memory capable of storing the reception data I and Q digitized by the A / D conversion means 24 at the same timing. doing. This memory can store data for the number of symbols of one reception slot, which is L symbols or more. Here, for ease of explanation, the size of the memory is set to a size capable of storing data for L symbols, and the address is shown in decimal.

The data storage means 25 stores the received data based on the reception timing generated by the frame synchronization timing generation means 31. One symbol of received data is stored over 10 words in the memory. If the symbol identification point detecting means 27 determines that the sample number Ns = 5 is the symbol identification point, the data of the sample number Ns = 5 from the memory, that is, the address 005,0015,0.
The values of 025, ... Are transferred to the data decoding means 29, and the data is decoded.

Next, the operation of the clock phase correction means 28 will be described. The clock phase correcting means 28, as shown in FIG. 5, is a variable frequency dividing means 44 for variably dividing the free-running bit clock.
And 1TDMA delay means 41 for delaying the symbol identification point information output from the symbol identification point detecting means 27 by 1 TDMA frame and outputting the symbol identification point information of the previous slot and the current slot output from the 1TDMA delay means 41. Phase shift detection means 42 for detecting a phase shift by comparing with the symbol identification point information, and variable frequency division ratio control means for controlling the frequency division ratio of the variable frequency division means 44 based on the detected phase shift.
43 and.

FIG. 6 is an explanatory diagram for explaining the operation of the clock phase correction means 28. In FIG. 6, an example of a case where the symbol identification point number (which symbol identification point corresponds to the sample number Ns) obtained by the symbol identification point determination for each reception slot changes to 5, 5, 6, and 6. Is shown. At this time, the phase shift detecting means 42 detects 0, +1, 0
Is output. The variable frequency division ratio control means 42 sets the variable frequency division ratio based on the differential signal obtained from the phase shift detection means 42. Assuming that the normal frequency division ratio is 1 / L, when the difference signal is 0, frequency division is performed at 1 / L, and when it is +1 as shown in FIG. 7, only once in M symbols 1 / L + 1. Divide by. Similarly, when it is -1, frequency division is performed by 1 / L-1 to reproduce the bit clock.

Further, FIG. 8 shows the synchronous addition means of this device.
26 shows an example of processing timing when the symbol identification point means 27, the clock phase correction means 28 and the data decoding means 29 are realized by software processing using one DSP. The frame synchronization timing generation means 31 generates a reception slot timing signal in synchronization with the timing of the reception slot, and the data storage means 25 stores data based on this timing. The DSP performs synchronous addition processing using data for M symbols of the accumulated data, and then performs symbol identification point detection processing. Next, the clock phase correction processing is performed from the obtained symbol identification point information, and the data of the symbol identification point is read from the data storage means 25 and the data decoding processing is performed.

FIG. 8 shows a case where the processing time of synchronous addition processing, symbol identification point detection processing, clock phase correction processing and data decoding processing exceeds the reception slot time. By storing the received data in the means 25, it is possible to perform processing by utilizing the idle time other than the receiving slot.

Further, M can be synchronously added with the number of symbols (L) for one reception slot at the maximum, but M <L can be set in order to reduce the amount of calculation. Generally M
The larger the value of, the more accurately the identification point can be detected, but when the value exceeds a certain value, the accuracy hardly increases. Therefore, the amount of calculation can be reduced by optimizing M.

The operations of the frame synchronizing means 30 and the frame synchronizing timing generating means 31 of this apparatus are the same as those of the conventional apparatus.

As described above, in the data receiving apparatus of the first embodiment, the symbol identification point is detected from the synchronous addition result obtained by the synchronous addition means 26, and the clock phase correction means 28 detects the time-divided intervals. The phase shift is detected from the shift of the symbol identification points, the frequency division ratio of the variable frequency dividing means 44 is controlled according to this phase shift, and the bit clock is reproduced.

Therefore, the clock extracting means and the phase comparing means in the digital PLL means, which are provided in the conventional device, are not required, and the circuit structure can be simplified. Also, D
The bit clock can be regenerated by digital signal processing such as SP. In this case, since the data accumulating means 25 for temporarily storing the received data is provided, synchronous addition processing, symbol identification point detection processing, clock phase correction processing,
Even when the total processing time of the data decoding processing and the data decoding processing exceeds the reception slot time, the DSP can perform these functions in time series by the collective storage processing.

(Second Embodiment) The data receiving apparatus of the second embodiment can reduce the amount of calculation in the synchronous addition of samples. This apparatus, as shown in FIG. 9, performs a synchronous addition by narrowing the synchronous addition to three samples.
It has. Other configurations are the same as the device of the first embodiment (FIG. 1).

The synchronous addition means 36 of this apparatus has a total of 3 samples of the symbol identification points detected by the synchronous addition of the immediately preceding M symbol periods and the samples of the sampling points before and after that.
Synchronous addition is performed for one sample over the M symbol period, and the symbol identification point detecting means 37 determines the sample position of the sample having the maximum value among the synchronous addition results of these three samples as the symbol identification point. Then, the synchronous addition means 36 next performs synchronous addition of three samples for M symbols in total of the sample point determined as the symbol identification point and the sample points before and after it.

FIG. 10 shows the result of the synchronous addition means 36 performing the synchronous addition of three samples. The middle value K of the three samples is the symbol identification point determined by the result of synchronous addition of the previous reception slot. FIG. 7A shows an example in which the same symbol identification point K as that detected in the immediately preceding M symbol is determined as the symbol identification point of the current slot. In this case, the variable frequency division in the clock phase correction means 28 is performed. Means 44
Performs frequency division at a normal frequency division ratio of 1 / L.
FIGS. 9B and 9C are examples in which a point different from the symbol identification point K detected in the immediately preceding M symbol is determined as the symbol identification point of the current slot, and FIGS. Further, in FIG. 7C, K + after one sample is detected as a symbol identification point. (B) In the case of the figure, K
Immediately after the − is detected, the frequency division is performed only once at a frequency division ratio of 1 / (L−1), and in the case of FIG. Division is performed at the division ratio. Other operations are the same as those of the data receiving apparatus of the first embodiment.

This device can reduce the amount of synchronous addition processing in the DSP processing timing chart of FIG. 8 in a transmission environment with a small phase shift, and when it is realized using a DSP, the operation clock of the DSP is It can be dropped and low power consumption can be realized.

(Third Embodiment) As shown in FIG. 11, the data receiving apparatus according to the third embodiment has a data storage means.
35 accumulates data for 3 samples including the symbol identification point and the points before and after it. The other configuration is the same as that of the device of the second embodiment (FIG. 9).

The data structure of the data storage means 35 of this apparatus is shown in FIG. This figure shows the case where the position of the symbol identification point is the sample number Ns = 5. That is, sample number Ns = 5 and one sample before and after that (Ns = 4,
In addition to 6), 3 samples are stored in the data storage means 35.

This data receiving device can significantly reduce the capacity of the data storage means 35 as compared with the data receiving device of the second embodiment, and is compared with the data receiving device of the second embodiment. And can be realized with a smaller circuit scale. Further, this memory reduction effect becomes greater as the oversampling rate N increases.

(Fourth Embodiment) As shown in FIG. 13, the data receiving apparatus according to the fourth embodiment has an A / D conversion means.
An operation clock generation means 50 for generating an operation clock given to 24 is provided. Other configurations are the same as the device of the first embodiment (FIG. 1).

The operation clock generation means 50 includes a frequency divider.
The free-running clock generated by 22 and the data reception timing signal generated by the frame synchronization timing generating means 31 are input. The operation clock generation means 50 uses the A of those signals.
ND is taken to generate an operation clock, and the operation clock is output to the A / D conversion means 24. Therefore, the A of this device
As shown in FIG. 14, the / D conversion means 24 is supplied with a clock only at the timing of receiving a slot, performs an A / D conversion operation only during this time, and stores the converted reception data in the data storage means 25. Therefore, lower power consumption can be achieved as compared with the data receiving device of the first embodiment.

In addition to the A / D conversion means, for example, the detection means 23 is also controlled in the same manner, and is operated only when the slot is received, whereby the power consumption can be further reduced.

(Fifth Embodiment) As shown in FIG. 15, the data receiving apparatus of the fifth embodiment has a frame synchronization timing generating means 61 instead of the clock phase correcting means.
Initial value control means for directly correcting the initial value of the timer
Has 60. Further, the frame synchronization timing generation means 61 is provided with a timer for managing a TDMA frame, which operates with a free-running clock Nt times the bit clock. Other configurations are the same as those of the data receiving apparatus (FIG. 1) of the first embodiment.

As shown in FIG. 16, the timer initial value control means 60 delays the symbol identification point information output from the symbol identification point detection means 27 by 1 TDMA frame and outputs the delayed 1 TDMA delay means 67 and 1 TDMA delay means. Phase shift detecting means 65 for detecting the phase shift by comparing the symbol identification point information of the previous slot and the symbol identification point information of the current slot output from 67, and the frame synchronization timing generating means based on the detected phase shift. A timer initial value setting means 66 for controlling the initial value of the timer 61 is provided.

The operation of this device will be described with reference to FIGS. For ease of explanation, it is assumed in FIG. 17 that the received I and Q signals are oversampled at 10 times the symbol rate (N = 10). The operation clock of the timer is also operated at 10 times the symbol rate (Nt = 10). Note that N and Nt do not necessarily have to match, but by setting N = Nt, the detection result of the clock phase shift becomes the same as the jitter amount of the clock correction, and the control becomes the easiest.

In FIG. 17, the symbol identification point detecting means 27 is
Based on the result of synchronous addition, the symbol identification points are set to 5, 5 ,,
It shows the case of judging as 6, 6, .... Phase shift detection means 65 of the timer initial value control means 60, based on this result,
0, +1, 0, ... Is output as the difference from the previous reception slot.

Assuming that the frame synchronization timer of the frame synchronization timing generation means 61 counts with a count number of T for one TDMA frame, the timer initial value setting means 66 outputs T, T + 1, T, .... At this time, the frame synchronization timer changes the initial value according to the output of the timer initial value setting means 66, and performs the counting operation shown in FIG. As a result, the count by the frame synchronization timer is synchronized with the TDMA frame.

Other operations are the same as those of the data receiving apparatus of the first embodiment.

This device can regenerate the bit clock by digital signal processing without the need for the clock extracting means and the phase comparing means of the digital PLL means in the conventional device. Further, in this device, the variable frequency dividing means in the device of the first embodiment can also be eliminated, so that a circuit scale smaller than that of the first embodiment can be realized. In addition, in this device, P
Since the phase comparison operation in the LL means is not required, the initial synchronization pull-in can be performed at high speed.

[0055]

As can be seen from the above description, the data receiving apparatus of the present invention has the following effects.

(1) In the data receiving apparatus of the present invention, the synchronous addition means detects the symbol identification point based on the result of the synchronous addition, and the clock phase correction means detects the deviation of the symbol identification points in the time distant section. The phase shift is detected, and the frequency division ratio of the variable frequency dividing means is controlled based on the detected phase shift to reproduce the bit clock. Therefore, unlike the conventional device, the clock extraction means and the phase comparison means in the digital PLL means are not required, and the bit clock can be reproduced by digital signal processing such as DSP. Moreover, since the data storage means for temporarily storing the received data is provided, even when the combined processing of the synchronous addition processing, the symbol identification point detection processing, the clock phase correction processing and the data decoding processing exceeds the reception slot time,
These functions can be processed in a time-series manner by the collective storage processing that sequentially processes after the storage of data.

(2) In addition, in the device in which the number of samples for synchronous addition is narrowed down to 3 and the symbol identification point is detected from the sample, the amount of synchronous addition processing in the DSP processing can be reduced, and when the DSP is used. It is possible to realize low power consumption.

(3) Further, in the device in which the number of samples stored in the data accumulating means is reduced to three, the capacity of the data accumulating means can be greatly reduced and a smaller circuit scale can be realized.

(4) Further, in the device in which the clock is supplied to the A / D conversion means only during the slot reception section and the operation of the A / D conversion means is performed only during the slot reception section,
By this intermittent operation, power consumption can be reduced.

(5) Further, in the device in which the operation clock of the frame synchronization timer is operated at N times the bit rate and the initial value of this timer is corrected based on the phase shift of the symbol identification point, the variable frequency dividing means is also unnecessary. Therefore, it is possible to realize a smaller circuit scale. Further, the initial synchronization pull-in can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data receiving device according to a first embodiment,

FIG. 2 is an explanatory diagram explaining an operation of a synchronous addition unit of the data receiving apparatus of the first embodiment,

FIG. 3 is an explanatory view explaining the operation of a symbol identification point detecting means of the data receiving apparatus of the first embodiment,

FIG. 4 is an explanatory diagram illustrating a configuration of data storage means of the data receiving device according to the first embodiment;

FIG. 5 is a block diagram showing a configuration of clock phase correction means of the data receiving apparatus according to the first embodiment.

FIG. 6 is an explanatory view explaining the operation of the clock phase correction means of the data receiving apparatus of the first embodiment,

FIG. 7 is an explanatory diagram illustrating the operation of the variable frequency dividing means of the data receiving device according to the first embodiment;

FIG. 8 is an explanatory diagram illustrating processing timing of the data receiving device according to the first embodiment;

FIG. 9 is a block diagram showing a configuration of a data receiving device according to a second embodiment,

FIG. 10 is an explanatory diagram explaining the operation of the synchronous addition means of the data receiving device according to the second embodiment;

FIG. 11 is a block diagram showing a configuration of a data receiving device according to a third embodiment,

FIG. 12 is an explanatory diagram illustrating a configuration of data storage means of the data receiving device according to the third embodiment;

FIG. 13 is a block diagram showing a configuration of a data receiving device according to a fourth embodiment,

FIG. 14 is an explanatory diagram explaining an operation of the data receiving device according to the fourth embodiment;

FIG. 15 is a block diagram showing a configuration of a data receiving device according to a fifth embodiment,

FIG. 16 is a block diagram showing the configuration of timer initial value setting means of the data receiving device according to the fifth embodiment;

FIG. 17 is an explanatory diagram explaining an operation of the data receiving device according to the fifth embodiment;

FIG. 18 is an explanatory diagram explaining the operation of the frame synchronization timer of the data receiving device according to the fifth embodiment;

FIG. 19 is a block diagram showing a configuration of a conventional data receiving device,

FIG. 20 is a timing chart for explaining the operation of the bit clock recovery unit of the conventional data receiving device,

FIG. 21 is an explanatory diagram illustrating a frame structure of received data;

FIG. 22 is a timing chart illustrating generation of a frame synchronization timing signal of a conventional data receiving device.

[Explanation of symbols]

 1, 21, oscillator 2, 22 frequency divider 3 23 detector 4 clock extraction circuit 5 digital PLL 6 variable frequency divider 7 phase comparator 8, 24 A / D converter 9, 29 data decoding unit 10, 30 frame synchronization Section 11, 31 Frame synchronization timing generation section 25 Memory 26 M symbol squared envelope synchronization addition section 27, 37 Symbol identification point detection section Envelope 28 Clock phase correction section 35 3 sample memory 36 M symbol 3 sample squared envelope synchronization Adder 41 1-frame delay 42 Phase shift detector 43 Variable frequency division ratio controller 44 Variable frequency divider 50 Clock generator 60 Timer initial value setting controller 65 Phase shift detector 66 Timer initial value setting controller 67 1 frame Delay part

Claims (7)

[Claims] 1. A bit clock is recovered from a received signal,
In a data receiving device for decoding data and generating a frame synchronization timing signal, A / D conversion means for oversampling the received signal at a sampling frequency N times (N is an integer) the symbol rate and digitizing the sample value. , A data storage means for storing the A / D-converted digital signal, and a sample value read from the data storage means are synchronously added over M symbol intervals (M is an integer) for each symbol interval, and N number of synchronizations are performed. Synchronous addition means for obtaining an addition result, symbol identification point detection means for detecting a symbol identification point from the synchronous addition result obtained by the synchronous addition means, and data decoding by the symbol identification point detected by the symbol identification point detection means. The difference between the data decoding means to be performed and the symbol identification points detected for different receiving slots is detected. By correcting a clock based on the difference acquired clock correction means for generating a reproduction bit clock, the frame synchronization based on the decoded sync word, T
A data receiving apparatus, comprising: a timing control unit that generates a timing signal synchronized with a DMA frame. 2. The data receiving apparatus according to claim 1, wherein the clock correction means variably divides the frequency of the free-running bit clock based on the difference to generate a regenerated bit clock. 3. The data receiving apparatus according to claim 1, wherein the clock correction means corrects an initial value of a frame synchronization timer operating at Nt times a bit rate based on the difference. 4. The synchronous addition means synchronously adds the sample values over an M symbol section having a relationship of L> M, where L is the number of symbols in the reception slot. 3. The data receiving device according to item 3. 5. The synchronous addition means performs synchronous addition for three samples including a symbol identification point detected based on the result of the previous synchronous addition over the M symbol section and sample points before and after the symbol identification point, 5. The data receiving apparatus according to claim 1, wherein the symbol identification point detecting means detects a symbol identification point from among the three points. 6. The data accumulating means stores sample values for three samples including a symbol identification point detected based on the result of the synchronous addition over the previous M symbol section and sample points before and after the symbol identification point. The data receiving device according to claim 5, wherein 7. Receiving a timing signal synchronized with the TDMA frame generated from the timing control means,
2. The data receiving apparatus according to claim 1, wherein the A / D converting means is provided with an intermittent clock generating means for supplying a free-running clock only during a slot receiving period.