JPH09191167A - Chip component and its manufacturing method - Google Patents

Chip component and its manufacturing method

Info

Publication number
JPH09191167A
JPH09191167A JP273996A JP273996A JPH09191167A JP H09191167 A JPH09191167 A JP H09191167A JP 273996 A JP273996 A JP 273996A JP 273996 A JP273996 A JP 273996A JP H09191167 A JPH09191167 A JP H09191167A
Authority
JP
Japan
Prior art keywords
substrate
terminal electrode
forming
hole
chip component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP273996A
Other languages
Japanese (ja)
Other versions
JP2768655B2 (en
Inventor
Sukeo Kai
貮夫 甲斐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanwa Denki Seisakusho KK
Original Assignee
Sanwa Denki Seisakusho KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanwa Denki Seisakusho KK filed Critical Sanwa Denki Seisakusho KK
Priority to JP8002739A priority Critical patent/JP2768655B2/en
Publication of JPH09191167A publication Critical patent/JPH09191167A/en
Application granted granted Critical
Publication of JP2768655B2 publication Critical patent/JP2768655B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

PROBLEM TO BE SOLVED: To form required conductor pattern and terminal electrodes at the same time to reduce the production cost by patterning a conductor film on the inner faces of terminal electrode forming holes, together with a conductor film on a substrate to form specified conductor pattern including the terminal electrodes of a chip component. SOLUTION: An insulative substrate 1 such as glass substrate is selected. Terminal electrode forming holes 2 and via-hole forming holes are formed through the substrate in the same stem. A conductor film is formed on the front and back faces of the substrate 1 and inner faces of the holes by the Cu plating etc. A photoresist film is applied to the entire surface by electrodeposition. A photo mask is patterned to form spiral conductor patterns 7 on both sides of the substrate as well as via-holes 3' and terminal electrodes 6. A protective film is printed on other part than the electrodes 6. Finally individual chip components are separated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、回路基板上に表
面実装されるチップ部品およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component surface-mounted on a circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より、回路基板に表面実装される例
えばチップ抵抗などは、絶縁性の基板に対して複数チッ
プ分の各種電極パターンを形成し、これを列単位に一次
分割し、その分割面に側面電極を印刷し、焼成した後、
個別のチップ形状に二次分割し、さらに、端子電極部分
をメッキすることによって製造されている。また、例え
ばモールドタイプのチップインダクタは、基板上に別体
としての巻線をマウントし、全体を樹脂外装して製造さ
れ、積層タイプのチップインダクタは、フェライトのグ
リーンシートを利用して、導電体と磁性体を交互に積層
印刷し、焼成することによって製造されている。
2. Description of the Related Art Conventionally, for example, for a chip resistor or the like mounted on a circuit board, various electrode patterns for a plurality of chips are formed on an insulating substrate, and these are firstly divided into columns and divided. After printing the side electrode on the surface and firing it,
It is manufactured by subdividing into individual chip shapes and further plating the terminal electrode portions. Also, for example, a mold type chip inductor is manufactured by mounting a winding as a separate body on a substrate and covering the whole with a resin, and a multilayer type chip inductor is manufactured by using a ferrite green sheet to form a conductor. It is manufactured by alternately laminating and printing magnetic materials and firing.

【0003】また、別体のコイルをマウントしたり積層
印刷を行わない平面型のインダクタンス素子としては、
絶縁基板上にスパイラル状の導電体パターンを形成した
ものもあった。図18はこのような従来技術による平面
型インダクタンス素子をチップ形状にした場合の例を示
す。図18において基板上にはスパイラル状の導電体パ
ターン13が形成され、その外周端は一方の端子電極1
8に接続され、内周端はエアブリッジ17を介して他方
の端子電極18に接続される。このように導電体膜をス
パイラル状にパターン化してチップインダクタを構成す
る際の工程は次のようになる。まず、図19に示すよう
に、基板10の上面にレジスト膜11をパターン化し、
図20に示すように全体に導電体膜12を蒸着し、レジ
スト膜11をリフトオフすることによってスパイラル状
の導電体パターン13を形成する。続いて、図22に示
すようにレジスト膜14をパターン化し、その表面に給
電層15をスパッタリングし、さらに図23に示すよう
にエアブリッジを形成すべき箇所以外をレジスト膜16
で被い、メッキを行うことによってエアブリッジ17を
形成する。その後、図24に示すようにイオンミリング
法でレジスト膜14を除去し、図25に示すように、基
板から各チップを切断し、その端部に端子電極18を形
成する。
[0003] Further, as a planar inductance element in which a separate coil is not mounted or lamination printing is not performed,
In some cases, a spiral conductive pattern was formed on an insulating substrate. FIG. 18 shows an example of a case where such a conventional planar inductance element is formed into a chip shape. In FIG. 18, a spiral conductor pattern 13 is formed on the substrate, and the outer peripheral end of the spiral conductor pattern 13 is one of the terminal electrodes 1.
8 is connected to the other terminal electrode 18 via an air bridge 17. The steps of forming the chip inductor by patterning the conductor film in a spiral shape as described above are as follows. First, as shown in FIG. 19, a resist film 11 is patterned on the upper surface of the substrate 10,
As shown in FIG. 20, a conductor film 12 is vapor-deposited on the entire surface, and the resist film 11 is lifted off to form a spiral conductor pattern 13. Subsequently, the resist film 14 is patterned as shown in FIG. 22, the power feeding layer 15 is sputtered on the surface thereof, and the resist film 16 is formed at portions other than the portion where the air bridge is to be formed as shown in FIG.
To form an air bridge 17 by plating. After that, the resist film 14 is removed by the ion milling method as shown in FIG. 24, each chip is cut from the substrate as shown in FIG. 25, and the terminal electrode 18 is formed at the end thereof.

【0004】[0004]

【発明が解決しようとする課題】ところが、上述した従
来のチップ部品では、いずれのタイプであっても、基板
からチップ状の区画を切り離してから側面の端子電極を
個別に形成しなければならなかった。また、厚膜印刷に
よる積層型チップインダクタのようなチップ部品は多層
の導電体パターンを形成するので、その製造工数が多く
なる問題があり、また、図18に示したようにエアブリ
ッジを形成するものではエアブリッジを形成するための
レジスト膜を特殊な工程で除去しなければならず、全体
に製造工程が複雑となる。
However, in the above-mentioned conventional chip components, the terminal electrodes on the side surfaces must be formed individually after separating the chip-shaped sections from the substrate, regardless of the type. Was. In addition, since a chip component such as a multilayer chip inductor formed by thick film printing forms a multi-layered conductor pattern, there is a problem that the number of manufacturing steps increases, and an air bridge is formed as shown in FIG. However, the resist film for forming the air bridge must be removed in a special process, which complicates the manufacturing process as a whole.

【0005】この発明の目的は、チップ部品に要する導
電体パターンと端子電極とを実質上同時に形成できるよ
うにして、上述の問題を解消したチップ部品およびその
製造方法を提供することにある。
An object of the present invention is to provide a chip part and a method of manufacturing the same which can solve the above problems by forming a conductor pattern required for a chip part and a terminal electrode substantially at the same time.

【0006】また、この発明の他の目的は、従来のエア
ブリッジなどを用いることなく、実質的に単層の導電体
パターンによってチップ部品に必要な導電体パターンを
形成できるようにして、上述の問題を解消したチップ部
品およびその製造方法を提供することにある。
Another object of the present invention is to enable formation of a conductor pattern required for a chip component by a conductor pattern of substantially a single layer without using a conventional air bridge or the like. It is an object to provide a chip component and a method for manufacturing the same that solve the problem.

【0007】また、この発明の他の目的は、対向する端
部に複数の端子電極が設けられ、基板の表裏面にそれぞ
れ複数の端子電極から延びる導電体パターンが設けられ
た、従来技術では得られなかった小型でかつ多機能なチ
ップ部品およびその製造方法を提供することにある。
Another object of the present invention is obtained in the prior art in which a plurality of terminal electrodes are provided at opposite ends and conductive patterns extending from the plurality of terminal electrodes are provided on the front and back surfaces of the substrate, respectively. An object of the present invention is to provide a small-sized and multifunctional chip component that has not been achieved and a manufacturing method thereof.

【0008】[0008]

【課題を解決するための手段】この発明のチップ部品の
製造方法は、所定の導電体パターンと端子電極とを同時
に形成可能とするために、請求項1に記載の通り、絶縁
性の基板、または絶縁板に導電体膜を予め形成した基板
に、内面の一部がチップ部品の端子電極の一部となる端
子電極形成用孔を形成する工程と、前記基板上および前
記端子電極形成孔の内面に導電体膜をメッキ法により形
成する工程と、前記基板上の導電体膜または前記基板上
の導電体膜とともに前記端子電極形成用孔内面の導電体
膜をエッチング法によりパターン化してチップ部品の端
子電極を含む所定の導電体パターンを形成する工程と、
前記チップ部品の端子電極が形成されていない部分を通
る前記基板上の位置にスリットまたは溝を形成して、チ
ップ部品を前記基板から分離する工程とからなる。
According to the method of manufacturing a chip component of the present invention, in order to be able to form a predetermined conductor pattern and a terminal electrode at the same time, an insulating substrate, Alternatively, a step of forming a terminal electrode forming hole in which a part of the inner surface is a part of a terminal electrode of a chip component is formed on a substrate on which an insulating plate is preformed with a conductor film, and on the substrate and the terminal electrode forming hole. A step of forming a conductor film on an inner surface by a plating method, and a conductor film on the substrate or a conductor film on the inner surface of the terminal electrode forming hole together with the conductor film on the substrate are patterned by an etching method to form a chip component Forming a predetermined conductor pattern including the terminal electrodes of
Forming a slit or a groove at a position on the substrate passing through a portion of the chip component where no terminal electrode is formed, and separating the chip component from the substrate.

【0009】請求項1に係るチップ部品の製造方法で
は、基板に端子電極形成用孔が予め形成され、その端子
電極形成用孔の内面にメッキ法により導電体膜が形成さ
れ、エッチング法により基板上の導電体膜または基板上
の導電体膜とともに端子電極形成用孔内面の導電体膜が
パターン化され、その後、端子電極が形成されていない
部分で基板からチップ部品が分離されるため、必要な導
電体パターンと端子電極とが同時に形成され、且つチッ
プ部品として分離される前に端子電極が形成されるため
製造コストが大幅に削減される。
In the method of manufacturing a chip component according to the first aspect of the present invention, the terminal electrode forming hole is formed in the substrate in advance, the conductor film is formed on the inner surface of the terminal electrode forming hole by the plating method, and the substrate is formed by the etching method. Necessary because the conductor film on the inner surface of the terminal electrode formation hole is patterned together with the conductor film on the top or the conductor film on the substrate, and then the chip component is separated from the substrate at the portion where the terminal electrode is not formed. Since the conductive pattern and the terminal electrode are simultaneously formed, and the terminal electrode is formed before being separated as a chip component, the manufacturing cost is significantly reduced.

【0010】また、この発明のチップ部品の製造方法
は、基板の表裏面に導電体パターンを形成するととも
に、両者の導通を容易に図るために、請求項2に記載の
通り、絶縁性の基板、または絶縁板に導電体膜を予め形
成した基板に、内面の一部がチップ部品の端子電極の一
部となる端子電極形成用孔およびチップ部品の形成領域
内にバイアホール用孔を形成する工程と、前記基板の表
裏面、前記端子電極形成用孔およびバイアホール用孔の
内面に導電体膜をメッキ法により形成する工程と、前記
基板の表裏面の導電体膜または前記基板の表裏面の導電
体膜とともに前記端子電極形成用孔の内面の導電体膜を
エッチング法によりパターン化してチップ部品の端子電
極を含む所定の導電体パターンを形成する工程と、前記
チップ部品の端子電極が形成されていない部分を通る前
記基板上の位置にスリットまたは溝を形成して、チップ
部品を前記基板から分離する工程とからなる。
Further, according to the method of manufacturing a chip component of the present invention, an insulating substrate is formed as described in claim 2 in order to form conductive patterns on the front and back surfaces of the substrate and to easily conduct the two. Or, in a substrate in which a conductor film is preliminarily formed on an insulating plate, a hole for forming a terminal electrode whose inner surface is a part of a terminal electrode of a chip component and a hole for a via hole are formed in a chip component forming region. A step of forming a conductor film on the front and back surfaces of the substrate, the inner surfaces of the terminal electrode forming holes and the via hole holes by a plating method, and a conductor film on the front and back surfaces of the substrate or the front and back surfaces of the substrate Forming a predetermined conductor pattern including the terminal electrodes of the chip component by patterning the conductor film on the inner surface of the terminal electrode forming hole with the conductor film of 1. by an etching method, and the terminal electrode of the chip component. Forming a slit or groove in the position on the substrate through the formed portions not, and a step of separating the chip components from the substrate.

【0011】この発明のチップ部品は、基板表裏面の導
電体パターン同士を導通させて、二層の導電体パターン
を用いるようにするため、請求項3に記載の通り、絶縁
基板にバイアホール用孔が形成され、絶縁基板の対向す
る端部に端子電極が形成され、前記バイアホール用孔内
に導電体膜が形成され、前記絶縁基板の表面の一方の端
子電極と前記バイアホール用孔内の導電体膜との間に所
定形状の導電体パターンが形成され、前記絶縁基板の裏
面の他方の端子電極と前記バイアホール用孔内の導電体
膜との間に所定形状の導電体パターンが形成されてな
る。
In the chip component of the present invention, the conductor patterns on the front and back surfaces of the substrate are electrically connected to each other so that the two-layer conductor pattern is used. A hole is formed, a terminal electrode is formed at opposite ends of the insulating substrate, a conductor film is formed in the via hole hole, and one terminal electrode on the surface of the insulating substrate and the via hole hole are formed. A conductor pattern of a predetermined shape is formed between the conductor film and the conductor film of a predetermined shape between the other terminal electrode on the back surface of the insulating substrate and the conductor film in the hole for the via hole. Formed.

【0012】請求項2に係るチップ部品の製造方法およ
び請求項3に係るチップ部品では、基板に端子電極形成
用孔およびバイアホール用孔が形成された後、メッキ法
により基板の表裏面、端子電極形成用孔およびバイアホ
ール用孔の内面に導電体膜が形成され、エッチング法に
より、基板表裏面の導電体膜または基板表裏面の導電体
膜とともに、端子電極形成用孔の内面の導電体膜がパタ
ーン化され、その後に基板からチップ部品が分離される
ため、基板表裏面の所定の導電体パターンと端子電極と
ともにバイアホールも同時に形成されることになり、基
板表裏面の導電体パターンが基板内を通って導通するチ
ップ部品を容易に製造できるようになる。
In the chip component manufacturing method according to claim 2 and the chip component according to claim 3, after the terminal electrode forming holes and the via hole are formed in the substrate, the front and back surfaces of the substrate and the terminals are plated by a plating method. A conductor film is formed on the inner surfaces of the hole for electrode formation and the via hole, and the conductor film on the inner surface of the terminal electrode formation hole is formed by the etching method together with the conductor film on the front and back surfaces of the substrate or the conductor film on the front and back surfaces of the substrate. Since the film is patterned, and then the chip component is separated from the substrate, a predetermined conductor pattern on the front and back surfaces of the substrate and via holes are simultaneously formed together with the terminal electrodes. It becomes possible to easily manufacture a chip component that conducts through the inside of the substrate.

【0013】また、この発明のチップ部品は、チップイ
ンダクタとして用いるようにするため、請求項4に記載
の通り、前記バイアホール用孔は前記基板の略中央に設
けられていて、前記所定形状の導電体パターンは、それ
ぞれ端子電極から前記バイアホール用孔内の導電体膜に
までスパイラル状に延びたものとする。
Further, in order to use the chip component of the present invention as a chip inductor, as described in claim 4, the hole for via hole is provided at substantially the center of the substrate and has the predetermined shape. Each of the conductor patterns spirally extends from the terminal electrode to the conductor film in the via hole.

【0014】請求項4に係るチップ部品では、基板の表
裏面にそれぞれ端子電極からバイアホールまでスパイラ
ル状の導電体パターンが形成されているため、対向する
端子電極間にインダクタが設けられることになり、従来
のような積層印刷によるものや、エアブリッジを設けた
ものとは異なり、基板表裏面の導電体パターンを用いた
チップインダクタが得られる。
In the chip component according to the fourth aspect, since the spiral conductor pattern is formed from the terminal electrode to the via hole on each of the front and back surfaces of the substrate, the inductor is provided between the opposing terminal electrodes. Unlike the conventional one using the laminated printing and the one using the air bridge, a chip inductor using the conductor pattern on the front and back surfaces of the substrate can be obtained.

【0015】また、この発明のチップ部品は、4つ以上
の端子電極を備えて、2つの層からなる導電体パターン
によって多機能なチップ部品を得るため、請求項5に記
載の通り、絶縁基板の対向する端部にそれぞれ複数の端
子電極が形成され、前記絶縁基板の表面に一方の端部の
複数の端子電極に接続された導電体パターンが形成さ
れ、前記絶縁基板の裏面に他方の端部の複数の端子電極
に接続された導電体パターンが形成されてなる。
Further, the chip component of the present invention has four or more terminal electrodes and obtains a multifunctional chip component by the conductor pattern composed of two layers. A plurality of terminal electrodes are formed on opposite ends of the insulating substrate, a conductor pattern connected to the plurality of terminal electrodes on one end is formed on the surface of the insulating substrate, and the other end is formed on the back surface of the insulating substrate. A conductor pattern connected to the plurality of terminal electrodes of the portion.

【0016】請求項5に係るチップ部品では、4つ以上
の端子電極から基板の表裏面に延びる導電体パターンに
よって、所定の機能を有するチップ部品として作用す
る。例えば、基板の対向する端部にそれぞれ2つの端子
電極を形成し、つづら折れ状の電極パターンを基板の表
裏面に形成すれば、基板の表裏面のつづら折れ状の電極
パターン同士が誘導結合して変圧器として作用すること
になる。
In the chip component according to the fifth aspect, the conductor pattern extending from the four or more terminal electrodes to the front and back surfaces of the substrate acts as a chip component having a predetermined function. For example, if two terminal electrodes are formed on opposite ends of the substrate and zigzag electrode patterns are formed on the front and back surfaces of the substrate, the zigzag electrode patterns on the front and back surfaces of the substrate are inductively coupled to each other. Will act as a transformer.

【0017】[0017]

【発明の実施の形態】この発明の第1の実施形態に係る
チップ部品およびその製造方法を図1〜図11を基に以
下に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A chip part and a method for manufacturing the same according to a first embodiment of the present invention will be described below with reference to FIGS.

【0018】図1は、絶縁性の基板に対し端子電極形成
用孔およびバイアホール用孔を形成した状態を示す部分
斜視図である。図1において、1は絶縁性の基板であ
り、この基板1に、互いに対向するコ字型の端子電極形
成用孔2を縦横に配列形成している。また、チップ部品
の形成領域内にバイアホール用孔3をそれぞれ形成して
いる。
FIG. 1 is a partial perspective view showing a state in which a terminal electrode forming hole and a via hole are formed in an insulating substrate. In FIG. 1, reference numeral 1 denotes an insulating substrate, on which U-shaped terminal electrode forming holes 2 facing each other are arranged vertically and horizontally. Also, via-holes 3 are formed in the chip component formation region.

【0019】図2は、図1に示した状態から基板の全面
に導電体膜をメッキし、フォトレジスト膜の塗布、露
光、現像の後、エッチングを行った状態を示す部分斜視
図である。図2において6はチップ部品の対向する両端
部に位置する端子電極であり、それぞれ5面に連続して
形成している。3′はバイアホール用孔(3)の内面に
導電体膜を形成して構成したバイアホールである。チッ
プ部品となる領域の表裏面には端子電極6からバイアホ
ール3′まで延びるスパイラル状の導電体パターン7を
形成している。
FIG. 2 is a partial perspective view showing a state in which a conductive film is plated on the entire surface of the substrate from the state shown in FIG. 1, a photoresist film is applied, exposed, developed, and then etched. In FIG. 2, reference numerals 6 denote terminal electrodes located at opposite ends of the chip component, each being formed continuously on five surfaces. 3 'is a via hole formed by forming a conductive film on the inner surface of the via hole (3). A spiral conductive pattern 7 extending from the terminal electrode 6 to the via hole 3 'is formed on the front and back surfaces of the region to be the chip component.

【0020】図3は、図2に示した状態から2点鎖線部
分を分断することによって基板1から分離した単一のチ
ップ部品の斜視図であり、図4は、図3に示したチップ
部品の上面図および底面図である。但し、図3および図
4では保護膜を省略している。このように端子電極6か
らバイアホール3′までスパイラル状に延びる導電体パ
ターン7を基板の表裏面にそれぞれ形成したことによ
り、対向する2つの端子電極6−6間に所定のインダク
タンスが生じることになる。
FIG. 3 is a perspective view of a single chip component separated from the substrate 1 by cutting off a two-dot chain line portion from the state shown in FIG. 2, and FIG. 4 is a perspective view of the chip component shown in FIG. 3A and 3B are a top view and a bottom view, respectively. However, the protective film is omitted in FIGS. 3 and 4. By forming the conductor patterns 7 extending spirally from the terminal electrodes 6 to the via holes 3 'on the front and back surfaces of the substrate, a predetermined inductance is generated between the two opposing terminal electrodes 6-6. Become.

【0021】次に、上記チップ部品の製造方法を図5〜
図11を参照して説明する。
Next, a method of manufacturing the above-mentioned chip component will be described with reference to FIGS.
This will be described with reference to FIG.

【0022】まず、図5に示すしょうに、例えばガラス
布・エポキシ系のガラス基材などの絶縁性基板1を選定
する。この基板1に対し図6に示すように端子電極形成
用孔2およびバイアホール用孔3をNCボール盤による
ミーリング加工やプレスマシンによるプレス加工によっ
て、同一工程で形成する。次に、図7に示すように例え
ば銅などの無電解メッキおよび電解メッキにより導電体
膜4を基板の表裏面および孔の内面に被着させる。続い
て図8に示すように、電着法によりフォトレジスト膜を
全体に塗布する。その後、フォトマクスを基板の両面に
重ねて散乱光により露光し、現像することによって、図
9に示すようにフォトマスクをパターン化する。続いて
導電体膜4をエッチングし、レジスト膜5を除去するこ
とによって図10に示すように基板の両面にスパイライ
ル状の導電体パターン7を形成するとともに、バイアホ
ール3′および端子電極6を形成する。その後、図11
に示すように保護膜8を端子電極6以外の部分に印刷す
る。最後に、図2において2点鎖線で示したように、端
子電極が形成されていない部分を通る位置で個別のチッ
プ部品を分離する。これは、Vカットマシン(スリッ
タ)により断面V形の溝を形成して分割するか、ダイシ
ングソーでダイシングすることによって行う。
First, as shown in FIG. 5, an insulating substrate 1 such as a glass cloth / epoxy glass substrate is selected. As shown in FIG. 6, a hole 2 for forming a terminal electrode and a hole 3 for a via hole are formed in the same substrate 1 by milling with an NC drilling machine or pressing with a press machine in the same step. Next, as shown in FIG. 7, the conductor film 4 is applied to the front and back surfaces of the substrate and the inner surfaces of the holes by electroless plating of copper or the like and electrolytic plating. Subsequently, as shown in FIG. 8, a photoresist film is applied to the entire surface by an electrodeposition method. Thereafter, a photomask is patterned on the both surfaces of the substrate by irradiating the photomask with scattered light and developing the photomask as shown in FIG. Subsequently, the conductor film 4 is etched and the resist film 5 is removed to form a spiral-shaped conductor pattern 7 on both surfaces of the substrate as shown in FIG. Form. Then, FIG.
The protective film 8 is printed on portions other than the terminal electrodes 6 as shown in FIG. Finally, as shown by a two-dot chain line in FIG. 2, individual chip components are separated at positions passing through portions where terminal electrodes are not formed. This is performed by forming a groove having a V-shaped cross section with a V-cut machine (slitter) and dividing the groove, or by dicing with a dicing saw.

【0023】尚、図5〜図11では絶縁性基板1を出発
材料とする例を示したが、例えば絶縁性基材に銅箔を張
り合わせた銅張積層基板を出発材料としても同様に製造
することができる。
Although FIGS. 5 to 11 show an example in which the insulating substrate 1 is used as a starting material, for example, a copper-clad laminated substrate in which an insulating base material is laminated with a copper foil is similarly used as a starting material. be able to.

【0024】次に、端子電極形成用孔の他の例を第2、
第3、第4および第5の実施形態として図12〜図15
を基に説明する。
Next, another example of the terminal electrode forming hole will be described in the second.
12 to 15 as the third, fourth and fifth embodiments.
This will be described based on FIG.

【0025】図12は第2の実施形態に係る端子電極形
成用孔の平面図である。図12において、2はそれぞれ
端子電極形成用孔であり、Aで示す領域がチップ部品の
形成領域である。このように隣接するチップ部品の端子
電極形成用孔を連続する孔として設けてもよい。
FIG. 12 is a plan view of a terminal electrode forming hole according to the second embodiment. In FIG. 12, reference numerals 2 denote terminal electrode forming holes, and a region indicated by A is a chip component forming region. In this manner, the terminal electrode forming holes of the adjacent chip components may be provided as continuous holes.

【0026】図13は第3の実施形態に係る端子電極形
成用孔の平面図である。端子電極が、対向する端面の3
面に導電体膜を形成したものである場合には、この図1
3に示すように、端子電極形成用孔2を略直線状に形成
して、2点鎖線で示すように、端子電極形成用孔2に直
交する方向にチップ部品を分離するようにしてもよい。
図13においてAで示す領域がチップ部品の形成領域で
あり、(A)は単一のチップ部品の形成領域毎に端子電
極形成用孔を設けた例、(B)は複数のチップ部品の形
成領域毎に端子電極形成用孔を設けた例である。
FIG. 13 is a plan view of the terminal electrode forming hole according to the third embodiment. The terminal electrode has 3
If a conductor film is formed on the surface,
As shown in FIG. 3, the terminal electrode forming hole 2 may be formed in a substantially linear shape, and the chip parts may be separated in a direction orthogonal to the terminal electrode forming hole 2 as shown by a chain double-dashed line. .
In FIG. 13, a region indicated by A is a chip component forming region, (A) is an example in which a terminal electrode forming hole is provided for each single chip component forming region, and (B) is forming a plurality of chip components. This is an example in which a hole for forming a terminal electrode is provided in each region.

【0027】図14は第4の実施形態に係る端子電極形
成用孔の平面図である。この例では、C字型の端子電極
形成用孔2を設けて、端子電極6を形成し、2点鎖線で
示す一箇所で分離する。
FIG. 14 is a plan view of the terminal electrode forming hole according to the fourth embodiment. In this example, a C-shaped terminal electrode forming hole 2 is provided to form a terminal electrode 6, which is separated at one location indicated by a two-dot chain line.

【0028】図15は第5の実施形態に係る端子電極形
成用孔の平面図である。この例では、端子電極形成用孔
2を形成するとともに、チップ部品形成領域の四隅にそ
れぞれ端子電極6a,6bを形成して4端子のチップ部
品を得る。
FIG. 15 is a plan view of the terminal electrode forming hole according to the fifth embodiment. In this example, the terminal electrode forming holes 2 are formed, and the terminal electrodes 6a and 6b are formed at the four corners of the chip component forming region, respectively, to obtain a four-terminal chip component.

【0029】次に、第6の実施形態に係るチップ部品の
外観斜視図を図16に示す。このチップ部品は図15に
示した状態から2点鎖線部分で基板から分離したもので
ある。このように基板1の四隅に端子電極6a,6bを
形成するとともに、基板表面に両端が一方の端子電極6
a,6aに接続されたつづら折り状の導電体パターン7
を形成し、基板1の裏面側にも両端が他の端子電極6
b,6bに接続されたつづら折り状の導電体パターンを
形成している。これにより端子電極6aと6b間が変圧
器等の変成器として作用する。
Next, FIG. 16 shows an external perspective view of the chip part according to the sixth embodiment. This chip component is separated from the substrate at the two-dot chain line portion from the state shown in FIG. As described above, the terminal electrodes 6a and 6b are formed at the four corners of the substrate 1, and both ends of the terminal electrodes 6a and 6b are formed on the substrate surface.
a, serpentine conductor pattern 7 connected to 6a
Are formed, and both terminal electrodes 6 are also provided on the back side of the substrate 1.
A serpentine conductor pattern connected to b and 6b is formed. Thereby, the space between the terminal electrodes 6a and 6b functions as a transformer such as a transformer.

【0030】次に第7の実施形態に係るチップ部品の構
成を外観斜視図として図17に示す。この例では、6つ
のバイアホール3′を基板1に形成していて、これらの
バイアホールによって分布定数回路を構成し、端子電極
6と一部のバイアホールとを基板の表面または裏面で接
続している。本願発明によれば、チップ部品に要する導
電体パターンとバイアホールおよび端子電極が実質上同
時に形成されるため、このようにして、複数のバイアホ
ールを用いた分布定数回路を組み込んだチップ部品も容
易に得られる。
Next, FIG. 17 is an external perspective view showing the configuration of the chip part according to the seventh embodiment. In this example, six via holes 3 'are formed in the substrate 1, a distributed constant circuit is formed by these via holes, and the terminal electrode 6 and a part of the via holes are connected on the front surface or the back surface of the substrate. ing. According to the present invention, the conductor pattern required for the chip component, the via hole, and the terminal electrode are formed substantially at the same time, and thus the chip component incorporating the distributed constant circuit using the plurality of via holes can be easily formed. Is obtained.

【0031】[0031]

【発明の効果】請求項1に記載の発明によれば、チップ
部品として必要な導電体パターンと端子電極とが同時に
形成され、且つチップ部品として分離される前に端子電
極が形成されるため製造コストが大幅に削減される。
According to the first aspect of the present invention, a conductor pattern and a terminal electrode required for a chip component are simultaneously formed, and the terminal electrode is formed before being separated as a chip component. Costs are greatly reduced.

【0032】請求項2および3に記載の発明によれば、
チップ部品として必要な導電体パターンとバイアホール
および端子電極が同時に形成され、且つチップ部品とし
て分離される前に端子電極が形成されるため、基板の表
裏面に導電体パターンを有するとともに、両導電体パタ
ーンが基板内を通って導通するチップ部品が容易に製造
できるようになる。
According to the invention described in claims 2 and 3,
Since the conductor pattern required for the chip component, the via hole and the terminal electrode are formed at the same time, and the terminal electrode is formed before being separated as the chip component, it has the conductor pattern on the front and back surfaces of the substrate, It becomes easy to manufacture a chip component in which the body pattern is conducted through the inside of the substrate.

【0033】請求項4に記載の発明によれば、基板の表
裏面にそれぞれ端子電極からバイアホールまでスパイラ
ル状の導電体パターンが形成されるため、従来のような
積層印刷やエアブリッジの形成が不要となり、チップイ
ンダクタが容易に得られる。
According to the invention described in claim 4, since spiral conductor patterns are formed from the terminal electrode to the via hole on the front and back surfaces of the substrate respectively, the conventional laminated printing and air bridge formation can be performed. It becomes unnecessary and the chip inductor can be easily obtained.

【0034】請求項5に記載に発明によれば、4つ以上
の端子電極から基板の表裏面に延びる導電体パターンに
よって、例えば変成器等の所定の機能を有するチップ部
品が容易に得られる。
According to the fifth aspect of the invention, a chip component having a predetermined function such as a transformer can be easily obtained by the conductor patterns extending from the four or more terminal electrodes to the front and back surfaces of the substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係るチップ部品の製造途中に
おける状態を示す部分斜視図である。
FIG. 1 is a partial perspective view showing a state in the course of manufacturing a chip component according to a first embodiment.

【図2】第1の実施形態に係るチップ部品の製造途中に
おける状態を示す部分斜視図である。
FIG. 2 is a partial perspective view showing a state during the manufacture of the chip component according to the first embodiment.

【図3】チップ部品の外観斜視図である。FIG. 3 is an external perspective view of a chip part.

【図4】チップ部品の上面図および底面図である。FIG. 4 is a top view and a bottom view of the chip component.

【図5】絶縁性基板の断面図である。FIG. 5 is a sectional view of an insulating substrate.

【図6】端子電極形成用孔およびバイアホール用孔形成
後の断面図である。
FIG. 6 is a cross-sectional view after forming a terminal electrode forming hole and a via hole.

【図7】導電体膜形成後の断面図である。FIG. 7 is a cross-sectional view after a conductor film is formed.

【図8】フォトレジスト膜形成後の断面図である。FIG. 8 is a sectional view after a photoresist film is formed.

【図9】フォトレジスト膜パターン化後の断面図であ
る。
FIG. 9 is a cross-sectional view after patterning the photoresist film.

【図10】導電体膜エッチング後の断面図である。FIG. 10 is a cross-sectional view after conductor film etching.

【図11】保護膜塗布後の断面図である。FIG. 11 is a cross-sectional view after a protective film is applied.

【図12】第2の実施形態に係る端子電極形成用孔の形
成例を示す平面図である。
FIG. 12 is a plan view showing an example of forming a terminal electrode forming hole according to a second embodiment.

【図13】第3の実施形態に係る端子電極形成用孔の形
成例を示す平面図である。
FIG. 13 is a plan view illustrating an example of forming a terminal electrode forming hole according to a third embodiment.

【図14】第4の実施形態に係る端子電極形成用孔の形
成例を示す平面図である。
FIG. 14 is a plan view showing an example of forming terminal electrode forming holes according to a fourth embodiment.

【図15】第5の実施形態に係る端子電極形成用孔の形
成例を示す平面図である。
FIG. 15 is a plan view showing an example of forming a terminal electrode forming hole according to the fifth embodiment.

【図16】第6の実施形態に係るチップ部品の外観斜視
図である。
FIG. 16 is an external perspective view of a chip component according to a sixth embodiment.

【図17】第7の実施形態に係るチップ部品の外観斜視
図である。
FIG. 17 is an external perspective view of a chip part according to a seventh embodiment.

【図18】従来技術によるチップインダクタの平面図で
ある。
FIG. 18 is a plan view of a conventional chip inductor.

【図19】基板上にレジスト膜をパターン化した状態の
断面図である。
FIG. 19 is a cross-sectional view showing a state where a resist film is patterned on a substrate.

【図20】導電体膜形成後の断面図である。FIG. 20 is a cross-sectional view after formation of a conductor film.

【図21】導電体パターン形成後の断面図である。FIG. 21 is a cross-sectional view after formation of a conductor pattern.

【図22】レジスト膜のパターン化および導電体膜形成
後の断面図である。
FIG. 22 is a cross-sectional view after patterning a resist film and forming a conductor film.

【図23】エアブリッジ形成後の断面図である。FIG. 23 is a cross-sectional view after formation of an air bridge.

【図24】レジスト膜除去後の断面図である。FIG. 24 is a cross-sectional view after removing the resist film.

【図25】端子電極形成後の断面図である。FIG. 25 is a cross-sectional view after forming a terminal electrode.

【符号の説明】[Explanation of symbols]

1−基板 2−端子電極形成用孔 3−バイアホール用孔 3′−バイアホール 4−導電体膜 5−フォトレジスト膜 6−端子電極 7−導電体パターン 8−保護膜 10−基板 11−レジスト膜 12−導電体膜 13−導電体パターン 14−レジスト膜 15−導電体膜 16−レジスト膜 17−導電体膜(エアブリッジ) 18−端子電極 Reference Signs List 1-substrate 2-hole for forming terminal electrode 3-hole for via hole 3'-via hole 4-conductor film 5-photoresist film 6-terminal electrode 7-conductor pattern 8-protective film 10-substrate 11-resist Film 12-conductor film 13-conductor pattern 14-resist film 15-conductor film 16-resist film 17-conductor film (air bridge) 18-terminal electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性の基板、または絶縁板に導電体膜
を予め形成した基板に、内面の一部がチップ部品の端子
電極の一部となる端子電極形成用孔を形成する工程と、 前記基板上および前記端子電極形成孔の内面に導電体膜
をメッキ法により形成する工程と、 前記基板上の導電体膜または前記基板上の導電体膜とと
もに前記端子電極形成用孔内面の導電体膜をエッチング
法によりパターン化してチップ部品の端子電極を含む所
定の導電体パターンを形成する工程と、 前記チップ部品の端子電極が形成されていない部分を通
る前記基板上の位置にスリットまたは溝を形成して、チ
ップ部品を前記基板から分離する工程とからなるチップ
部品の製造方法。
1. A step of forming a terminal electrode forming hole, a part of the inner surface of which is a part of a terminal electrode of a chip component, in an insulating substrate or a substrate in which a conductor film is formed in advance on an insulating plate, Forming a conductor film on the substrate and on the inner surface of the terminal electrode formation hole by a plating method, and a conductor film on the substrate or a conductor film on the inner surface of the terminal electrode formation hole together with the conductor film on the substrate Forming a predetermined conductor pattern including a terminal electrode of a chip component by patterning the film by an etching method, and forming a slit or groove at a position on the substrate passing through a portion where the terminal electrode of the chip component is not formed. A method of manufacturing a chip part, which comprises the step of forming the chip part and separating the chip part from the substrate.
【請求項2】 絶縁性の基板、または絶縁板に導電体膜
を予め形成した基板に、内面の一部がチップ部品の端子
電極の一部となる端子電極形成用孔およびチップ部品の
形成領域内にバイアホール用孔を形成する工程と、 前記基板の表裏面、前記端子電極形成用孔およびバイア
ホール用孔の内面に導電体膜をメッキ法により形成する
工程と、 前記基板の表裏面の導電体膜または前記基板の表裏面の
導電体膜とともに前記端子電極形成用孔の内面の導電体
膜をエッチング法によりパターン化してチップ部品の端
子電極を含む所定の導電体パターンを形成する工程と、 前記チップ部品の端子電極が形成されていない部分を通
る前記基板上の位置にスリットまたは溝を形成して、チ
ップ部品を前記基板から分離する工程とからなるチップ
部品の製造方法。
2. A terminal electrode forming hole and a chip component forming region, a part of the inner surface of which is a part of a terminal electrode of a chip component, on an insulating substrate or a substrate in which a conductor film is previously formed on an insulating plate. A step of forming a hole for a via hole therein, a step of forming a conductor film on the front and back surfaces of the substrate, an inner surface of the terminal electrode forming hole and a via hole hole by a plating method, and Forming a predetermined conductor pattern including a terminal electrode of a chip component by patterning the conductor film or the conductor films on the front and back surfaces of the substrate together with the conductor film on the inner surface of the terminal electrode forming hole by an etching method; And a step of separating the chip component from the substrate by forming a slit or groove at a position on the substrate that passes through a portion of the chip component where the terminal electrode is not formed. Law.
【請求項3】 絶縁基板にバイアホール用孔が形成さ
れ、絶縁基板の対向する端部に端子電極が形成され、前
記バイアホール用孔内に導電体膜が形成され、前記絶縁
基板の表面の一方の端子電極と前記バイアホール用孔内
の導電体膜との間に所定形状の導電体パターンが形成さ
れ、前記絶縁基板の裏面の他方の端子電極と前記バイア
ホール用孔内の導電体膜との間に所定形状の導電体パタ
ーンが形成されてなるチップ部品。
3. A via hole is formed in the insulating substrate, terminal electrodes are formed at opposite ends of the insulating substrate, a conductor film is formed in the via hole, and a surface of the insulating substrate is formed. A conductor pattern having a predetermined shape is formed between one terminal electrode and the conductor film in the via hole hole, and the other terminal electrode on the back surface of the insulating substrate and the conductor film in the via hole hole. A chip component in which a conductor pattern having a predetermined shape is formed between and.
【請求項4】 前記バイアホール用孔は前記基板の略中
央に設けられていて、前記所定形状の導電体パターン
は、それぞれ端子電極から前記バイアホール用孔内の導
電体膜にまでスパイラル状に延びたものである請求項3
に記載のチップ部品。
4. The via hole hole is provided substantially in the center of the substrate, and the conductor pattern of the predetermined shape is spirally formed from the terminal electrode to the conductor film in the via hole hole. It is an extended one.
The chip parts described in the above.
【請求項5】 絶縁基板の対向する端部にそれぞれ複数
の端子電極が形成され、前記絶縁基板の表面に一方の端
部の複数の端子電極に接続された導電体パターンが形成
され、前記絶縁基板の裏面に他方の端部の複数の端子電
極に接続された導電体パターンが形成されてなるチップ
部品。
5. A plurality of terminal electrodes are formed on opposite ends of an insulating substrate, and a conductor pattern connected to a plurality of terminal electrodes on one end is formed on a surface of the insulating substrate, the insulating substrate A chip component in which a conductor pattern connected to a plurality of terminal electrodes at the other end is formed on the back surface of a substrate.
JP8002739A 1996-01-11 1996-01-11 Manufacturing method of chip parts Expired - Fee Related JP2768655B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8002739A JP2768655B2 (en) 1996-01-11 1996-01-11 Manufacturing method of chip parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8002739A JP2768655B2 (en) 1996-01-11 1996-01-11 Manufacturing method of chip parts

Publications (2)

Publication Number Publication Date
JPH09191167A true JPH09191167A (en) 1997-07-22
JP2768655B2 JP2768655B2 (en) 1998-06-25

Family

ID=11537721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8002739A Expired - Fee Related JP2768655B2 (en) 1996-01-11 1996-01-11 Manufacturing method of chip parts

Country Status (1)

Country Link
JP (1) JP2768655B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065764A (en) * 2011-10-20 2013-04-24 阿尔卑斯绿色器件株式会社 Magnetic element and manufacturing method
JP2013183044A (en) * 2012-03-02 2013-09-12 Alps Green Devices Co Ltd Method for manufacturing magnetic element and magnetic element

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0346291A (en) * 1989-07-14 1991-02-27 Tanaka Kikinzoku Kogyo Kk Tie bar push-back type pin hole processed printed board
JPH0380509A (en) * 1989-08-23 1991-04-05 Murata Mfg Co Ltd Laminated transformer
JPH0537098A (en) * 1991-08-02 1993-02-12 Omron Corp Multi-cavity double-sided printed wiring board
JPH05145214A (en) * 1991-11-15 1993-06-11 Teac Corp Manufacture of circuit board device
JPH07106134A (en) * 1993-09-29 1995-04-21 Kyocera Corp Chip filter part
JPH07135114A (en) * 1993-11-11 1995-05-23 Yokogawa Electric Corp Multilayered printed coil and its manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0346291A (en) * 1989-07-14 1991-02-27 Tanaka Kikinzoku Kogyo Kk Tie bar push-back type pin hole processed printed board
JPH0380509A (en) * 1989-08-23 1991-04-05 Murata Mfg Co Ltd Laminated transformer
JPH0537098A (en) * 1991-08-02 1993-02-12 Omron Corp Multi-cavity double-sided printed wiring board
JPH05145214A (en) * 1991-11-15 1993-06-11 Teac Corp Manufacture of circuit board device
JPH07106134A (en) * 1993-09-29 1995-04-21 Kyocera Corp Chip filter part
JPH07135114A (en) * 1993-11-11 1995-05-23 Yokogawa Electric Corp Multilayered printed coil and its manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065764A (en) * 2011-10-20 2013-04-24 阿尔卑斯绿色器件株式会社 Magnetic element and manufacturing method
JP2013089876A (en) * 2011-10-20 2013-05-13 Alps Green Devices Co Ltd Magnetic element and method for manufacturing the same
TWI490894B (en) * 2011-10-20 2015-07-01 Alps Green Devices Co Ltd Method for manufacturing magnetic force components
JP2013183044A (en) * 2012-03-02 2013-09-12 Alps Green Devices Co Ltd Method for manufacturing magnetic element and magnetic element

Also Published As

Publication number Publication date
JP2768655B2 (en) 1998-06-25

Similar Documents

Publication Publication Date Title
CN1914699B (en) Method for manufacturing electronic component, parent board and electronic component
US5197170A (en) Method of producing an LC composite part and an LC network part
KR960015427B1 (en) Flat coil
US7338892B2 (en) Circuit carrier and manufacturing process thereof
JP2976049B2 (en) Multilayer electronic components
JP2002252117A (en) Laminated coil component and its manufacturing method
US7460000B2 (en) Chip inductor and method for manufacturing the same
JP2004127976A (en) Inductive element and its manufacturing method
JP2005159222A (en) Thin film common mode filter and thin film common mode filter array
KR20030073285A (en) A weak-magnetic field sensor using printed circuit board and its making method
JP3257532B2 (en) Method for manufacturing laminated electronic component and method for measuring characteristics thereof
KR900005314B1 (en) Bar code reading device method of producing mutlilayer printed-wiring board contaning metal core
JP2000173835A (en) Laminated electronic component and manufacture thereof
JP2768655B2 (en) Manufacturing method of chip parts
JP2004127966A (en) Inductive element and its manufacturing method
JPH08186024A (en) Multilayer inductor
JPH10208942A (en) Chip inductor incorporating magnetic core and its manufacture
JP2007012825A (en) Chip part and its manufacturing method
JP2660965B2 (en) Method for manufacturing at least two multilayer chip inductors
JPH11186040A (en) Laminated noise filter
JP3257531B2 (en) Multilayer electronic components
JP2000068149A (en) Laminated electronic component and manufacture therefor
JPH0917635A (en) Multilayer type electronic component and its manufacture
JP2000049058A (en) Manufacture of laminated electronic component
JPH09219324A (en) Coil component and its manufacture

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees