JPH09190959A - Resist pattern forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine contact hole (narrow space) pattern. SOLUTION: A positive type resist 12 is applied on a semiconductor substrate 11, and this positive resist 12 is partially exposed by using a mask 13. The positive resist 12 is developed and a pillar pattern 12a or a narrow space pattern is formed on the semiconductor substrate 11. Also, a negative resist 16 is applied on the semiconductor substrate 11, and a full surface exposure is performed. Thereafter, it is developed and only a pillar pattern 12a or a narrow space pattern is dissolved, and a fine contact hole pattern or a narrow space pattern is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine resist pattern on a semiconductor substrate.

[0002]

2. Description of the Related Art IC (Integrated Circuit)
The degree of high integration of (uit) has increased at a rate of 4 times in 3 years, and the miniaturization of elements is progressing. Therefore, it is required to fabricate the element on the semiconductor substrate by the microfabrication technique.

In the microfabrication technology, it is important to form patterns for element isolation, electrodes, contact holes, wirings, etc., with a photoresist as precisely as desired.

The photoresist is used as a mask material for etching and ion implantation for forming the above pattern. FIG. 18 schematically shows a conventional method for forming a resist pattern on a semiconductor substrate.

First, a resist is applied on a semiconductor substrate. Then, exposure is performed by a predetermined optical system to form an image on the resist. In addition, when the resist is a chemically amplified resist, if the resist is a normal resist (novolak-based resist) after the predetermined heat treatment, if the developing process is immediately performed, the latent image generated in the resist is generated. The image dissolves or remains and a resist pattern is formed.

After that, by performing etching or ion implantation using the resist as a mask, element isolation,
Patterns such as electrodes, contact holes, and wiring are formed with desired accuracy.

[0007] The chemically amplified resist is a resist having a property that an acid group is generated in the exposed portion and the exposed portion is solubilized or hardly dissolved when heat treatment is performed thereafter. Further, the ordinary resist is a resist having a property that an exposed portion is solubilized or hardly soluble.

In the photoresist, when the latent image formed on the resist is developed, the exposed portion is dissolved,
Alternatively, the type is roughly divided into two, depending on whether the unexposed portion is dissolved.

Generally, a resist having a high solubility in an exposed portion is called a positive resist, and a resist having a high solubility in an unexposed portion is called a negative resist.

As the developer, an aqueous solution type developer is widely used in order to improve the resolution, because it does not cause the pattern to swell during development. This is because the photoresist is generally made of an organic material.

[0011]

It is known that the resolution (R) of the photoresist pattern formed by the above method is generally expressed by the equation (1) (Rayleigh).
theory). R = k · (λ / NA) (1) where λ is the wavelength of light, NA is the lens numerical aperture, and k is a constant (generally 0.6 is used).

That is, it is found that shortening the wavelength and increasing the lens numerical aperture are effective for improving the resolution of the resist pattern. For example, i-line (wavelength 365n
m) When a stepper is used, the resolution (R) obtained from equation (1) is about 0.35 μm (λ = 365 nm, NA =
In the case of 0.63). However, it is known that the practical resolution of the i-line stepper varies depending on the type of resist pattern, as shown in Table 1.

[0013]

[Table 1]

That is, as shown in FIG. 19, the remaining resist itself such as the line & space pattern (a), the isolated line pattern (b) and the pillar pattern (c) becomes a pattern. In the case of the above, a practical resolution (0.35 μm) which is almost in agreement with the theoretical value obtained from the equation (1) can be obtained, while the contact hole pattern (d) and the narrow space pattern (e) are obtained. ), Etc., in which the dissolved portion of the resist becomes a pattern, a practical resolution (0.4 to 0.45 μm) worse than the theoretical value obtained from the equation (1).
m) is obtained.

Such a phenomenon also occurs in a g-line (436 nm) stepper, a KrF line (248 nm) stepper, and an ArF line (193 nm) stepper. The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to use a resist pattern in a case where a dissolved portion of a resist such as a contact hole pattern or a narrow space pattern is used as a pattern. It is an object of the present invention to provide a resist pattern forming method capable of improving the practical resolution of the pattern and coping with the miniaturization of the element.

[0016]

In order to achieve the above object, a method of forming a resist pattern according to the present invention comprises applying a positive type resist on a semiconductor substrate and using a mask to partially remove the positive type resist. After exposing, the positive resist is developed to form a first resist pattern on the semiconductor substrate, a negative resist is applied on the semiconductor substrate, and the entire first resist pattern and the negative resist are formed. Is exposed, the first resist pattern and the negative resist are developed, and only the first resist pattern is dissolved to form a second resist pattern on the semiconductor substrate. It is what is done.

The first resist pattern is a pillar pattern or an isolated line pattern, and the second resist pattern is a contact hole pattern or a narrow space pattern.

[0018]

DETAILED DESCRIPTION OF THE INVENTION A method of forming a resist pattern according to the present invention will be described in detail below with reference to the drawings. FIG. 1 schematically shows all steps of the method for forming a resist pattern of the present invention. Moreover, FIGS.
It shows each step of the method of forming a resist pattern of the present invention.

In the following, a case where a contact hole pattern is formed on a semiconductor substrate using an ordinary novolac photoresist will be described as an example. First, as shown in FIG. 2, a positive photoresist 12 is applied on the semiconductor substrate 11. Then, a pattern (pillar pattern) in which the contact hole pattern is reversed.
Light having a predetermined wavelength (for example, 500 nm or less) is applied to the resist 12 to expose the resist 12.

Reference numeral 15 is a shielding film. Further, the mask 13 may be provided with a phase shift film to improve the resolution. The term "contact hole pattern"
The "mask" is a pattern in which a shielding film is formed on a portion other than the contact hole portion so that light is applied only to the contact hole portion.

That is, in the case of using a positive type photoresist, if light is applied only to the contact hole portion and the resist portion is developed and dissolved, the contact hole pattern is formed by the conventional method. This is because it can be formed.

Therefore, the light 14 does not reach the portion forming the contact hole pattern due to the shielding film 15.
Next, as shown in FIG. 3, when a developing treatment with an alkaline solution is performed, a pillar pattern 12a is formed in a portion where a contact hole pattern is formed. Here, as shown in Table 1 above, the pillar pattern is a contact hole.
Practical resolution is better than Rupatan.

Next, as shown in FIG. 4, the semiconductor substrate 11
A negative photoresist 16 is applied on top. And
Light 14 having a predetermined wavelength (for example, 500 nm or less) is applied to the resists 12a and 16 to perform exposure. As a result, the positive photoresist (pillar pattern) 12a becomes soluble and the negative photoresist 16 becomes insoluble.

Next, as shown in FIG. 5, when a developing treatment with an alkaline solution is performed, a positive type photoresist (pillar) is formed.
Pattern) 12a is melted, contact hole pattern
Are formed.

Here, since the contact hole pattern has the same practical resolution as the pillar pattern shown in Table 1 above, the practical resolution of the contact hole pattern is improved. Therefore, it is possible to cope with the miniaturization of the device.

For example, as shown in Table 2, i-line (wavelength 3
When the stepper is used, the practical resolution of the contact hole pattern can be improved from about 0.45 μm to about 0.35 μm, and the practical resolution of the narrow space pattern is reduced from about 0.4 μm. It can be increased to about 0.35 μm.

[0027]

[Table 2]

Next, a case of forming a contact hole pattern on a semiconductor substrate using a chemically amplified photoresist will be described. First, as shown in FIG. 2, a positive photoresist 12 is applied on the semiconductor substrate 11. The photoresist 12 has a property that an acid group is generated in the exposed portion and the exposed portion is solubilized by heat treatment.

Using a mask 13 having a pattern (pillar pattern) obtained by inverting the contact hole pattern, a resist 14 is irradiated with light 14 having a predetermined wavelength (for example, 500 nm or less). To do.

An acid group is generated in the exposed portion of the resist 12, and heat treatment is performed thereafter to solubilize the exposed portion of the resist 12. Next, as shown in FIG. 3, when a developing treatment with an alkaline solution is performed, a pillar pattern 12a is formed in a portion where a contact hole pattern is formed.
Here, as shown in Table 1 above, the pillar pattern has a better practical resolution than the contact hole pattern.

Next, as shown in FIG. 4, the semiconductor substrate 11
A negative photoresist 16 is applied on top. This photoresist 16 has a property that an acid group is generated in the exposed portion and the exposed portion becomes insoluble when heat-treated.

Light 14 having a predetermined wavelength (for example, 500 nm or less) is applied to the resists 12a and 16 to perform exposure. An acid group is generated in the positive photoresist (pillar pattern) 12a, and heat treatment is performed thereafter to solubilize the resist 12a. In addition, the negative photoresist 16 has
When an acid group is generated and heat treatment is performed thereafter, the resist 16
Is insolubilized.

Next, as shown in FIG. 5, a developing treatment with an alkaline solution is carried out.
Pattern) 12a is melted, contact hole pattern
Are formed.

Since the contact hole pattern has the same practical resolution as that of the pillar pattern shown in Table 1 above, the practical resolution of the contact hole pattern is improved. Therefore, it is possible to cope with the miniaturization of the device.

In the above embodiment, the case where the contact hole pattern is formed has been described, but it goes without saying that the present invention can be applied to the case where a narrow space pattern is formed.

FIGS. 7 to 10 show the respective steps when the present invention is applied to the formation of a contact hole on the gate and the source / drain of a MOS transistor. In the following, a case of forming a contact hole pattern using a normal novolac photoresist will be described as an example.

First, as shown in FIG. 7, the semiconductor substrate 21
MO with gate 22 and source / drain 23 on top
An S transistor is formed. After that, the insulating film 24 is formed on the entire surface of the semiconductor substrate 21.

A positive photoresist 25 is applied on the insulating film 24. Then, using a mask having a pattern (pillar pattern) obtained by inverting the contact hole pattern, light having a predetermined wavelength (for example, 500 nm or less) is applied to the resist 25 to perform exposure.

After that, when a developing treatment with an alkaline solution is performed, a pillar pattern 25 is formed in a portion where a contact hole pattern is formed. Here, the pillar pattern
The screen 25 has a better practical resolution than the contact hole pattern.

Next, as shown in FIG. 8, a negative photoresist 26 is applied on the insulating film 24. Then, the resist 25 is irradiated with light having a predetermined wavelength (for example, 500 nm or less).
26, and exposure is performed. As a result, the positive type photoresist (pillar pattern) 25 becomes soluble and the negative type photoresist 26 becomes insoluble.

Next, as shown in FIG. 9, when a developing treatment with an alkaline solution is performed, a positive photoresist (pillar) is formed.
The pattern 25 is melted to form a contact hole pattern.

Since the contact hole pattern has the same practical resolution as that of the pillar pattern, the practical resolution of the contact hole pattern can be improved and the device can be improved. It is possible to cope with the miniaturization of.

Next, as shown in FIG. 10, after the insulating film 24 is etched using the photoresist 26 as a mask,
When the photoresist 26 is peeled off, a contact hole reaching the gate 22 and the source / drain 23 of the MOS transistor is formed.

The manufacturing method in this embodiment is
Not only when a contact hole reaching the gate source drain is formed, but also when a contact hole between the multilayer wiring is formed.
It can be applied to the formation of a trench, a trench capacitor of a DRAM, and the like.

According to the above-mentioned manufacturing method, a pillar pattern is formed by using a positive resist in the first exposure / development, and a negative resist is applied in the second exposure / development. Only the pattern is melted to form a contact hole pattern.

Therefore, the practical resolution of the contact hole pattern can be improved, and the device can be miniaturized. 11 to 17 show each step when the present invention is applied to the formation of the wiring groove in the damascene method.

In the following, a case will be described as an example where a wiring groove is formed using a normal novolac photoresist. First, as shown in FIG. 11, insulating films 32 and 33 are formed on the semiconductor substrate 31 by using the CVD method or the like.

Next, as shown in FIG. 12, a positive photoresist 34 is applied on the insulating film 33. And
Light having a predetermined wavelength (for example, 500 nm or less) is applied to the photoresist 34 using a mask having a pattern obtained by inverting the wiring groove pattern, and exposure is performed. After that, when development processing is performed with an alkaline solution, the photoresist (isolated line pattern) 34 remains in the portion where the wiring groove is formed.

Next, as shown in FIG. 13, a negative photoresist 35 is applied on the insulating film 33. Then, the resist 3 is irradiated with light having a predetermined wavelength (for example, 500 nm or less).
Exposure to 4, 35 and 35 is performed. As a result, the positive photoresist 34 becomes soluble and the negative photoresist 3
5 becomes insoluble.

Next, as shown in FIG. 14, when a developing treatment with an alkaline solution is performed, the positive photoresist 34 is dissolved and a wiring groove pattern is formed. Next, FIG.
As shown in FIG. 5, after the insulating film 33 is etched using the photoresist 35 as a mask, the photoresist 35 is peeled off, whereby the wiring groove 36 is formed in the insulating film 33.

Next, as shown in FIG. 16, a metal film (for example, an aluminum film) 37 that completely fills the wiring groove 36 is formed on the insulating film 33. Next, as shown in FIG.
When the metal film 37 is polished by the CMP (chemical mechanical polishing) method to leave the metal film only in the wiring groove, the wiring layer 38 is formed in the wiring groove.

The manufacturing method in this embodiment is
R not only when forming a wiring groove by the damascene method
It can be applied to the formation of narrow space pattern wiring using IE.

According to the above-mentioned manufacturing method, an isolated line pattern is formed by using a positive type resist in the first exposure / development, and a negative type resist is applied in the second exposure / development. Only the wiring is melted to form the wiring groove pattern. Therefore, the practical resolution of the wiring groove pattern can be improved, and the device can be miniaturized.

[0054]

As described above, according to the method of forming the resist pattern of the present invention, the following effects can be obtained. In the first exposure / development, a positive resist is used to form a pillar pattern or an isolated line pattern,
In the second exposure / development, a negative resist is applied, and both positive and negative resists are exposed to dissolve only the pillar pattern or the isolated line pattern, and the contact hole pattern is formed. Or a wiring groove pattern is formed. Therefore, the practical resolution of the contact hole pattern or the wiring groove pattern can be improved more than before.
It is possible to cope with miniaturization of elements.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing all steps of a method for forming a resist pattern according to the present invention.

FIG. 2 is a diagram showing one step of a method for forming a resist pattern of the present invention.

FIG. 3 is a diagram showing one step of a method of forming a resist pattern of the present invention.

FIG. 4 is a diagram showing one step of a method for forming a resist pattern of the present invention.

FIG. 5 is a diagram showing one step of a method for forming a resist pattern of the present invention.

FIG. 6 is a diagram showing one step of a method for forming a resist pattern of the present invention.

FIG. 7 is a diagram showing one step when the method of the present invention is applied to the formation of a contact hole pattern.

FIG. 8 is a diagram showing a step when the method of the present invention is applied to the formation of a contact hole pattern.

FIG. 9 is a diagram showing a step when the method of the present invention is applied to the formation of a contact hole pattern.

FIG. 10 is a diagram showing one step when the method of the present invention is applied to the formation of a contact hole pattern.

FIG. 11 is a diagram showing a step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 12 is a diagram showing a step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 13 is a diagram showing a step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 14 is a diagram showing a step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 15 is a diagram showing one step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 16 is a diagram showing one step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 17 is a diagram showing a step when the method of the present invention is applied to the formation of a wiring groove pattern.

FIG. 18 is a diagram schematically showing all the steps of a conventional resist pattern forming method.

FIG. 19 is a diagram showing types of resist patterns.

[Explanation of symbols]

 11, 21, 31: Semiconductor substrate, 12, 25, 34: Positive photoresist, 12a: Pillar pattern, 13: Mask, 14, 17: Light, 15: Shielding film, 16, 26, 35: Negative Type photoresist, 22: gate, 23: source / drain, 24, 32, 33: insulating film, 36: wiring groove, 37: metal film, 38: wiring layer.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/30 502R 515E

Claims (2)

[Claims] 1. A step of applying a positive resist on a semiconductor substrate, a step of partially exposing the positive resist using a mask, and a step of developing the positive resist to form a first resist on the semiconductor substrate. Forming a resist pattern, applying a negative resist on the semiconductor substrate, exposing the entire first resist pattern and the negative resist, the first resist pattern and the above A step of developing a negative resist and dissolving only the first resist pattern to form a second resist pattern on the semiconductor substrate. 2. The first resist pattern is a pillar pattern or an isolated line pattern, and the second resist pattern is a contact hole pattern or a narrow space pattern.
The method for forming a resist pattern according to claim 1, wherein the resist pattern is a pattern.