JP3492846B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention is particularly random a fine pattern is required, relates to the production how a semiconductor device using a photolithographic method.

[0002]

2. Description of the Related Art With the demand for high-speed integrated circuits, especially MO
The gate electrode length of SFET is being miniaturized at an accelerating rate, and it will be 0.15 μm to 0.1 μm in the near future devices.
It is expected that an integrated circuit using a MOSFET having a gate electrode length of about m will appear.

The technique of the photo-etching method corresponding to the miniaturization of the gate electrode has been dealt with by shortening the wavelength of the light source of the reduction exposure projection device for forming the resist pattern on the wafer. For example, in the 0.35 μm generation, 3
Using a wavelength of about 65 nm, 248 n at 0.25 μm
In the 0.2 μm generation, a wavelength of about 193 nm is about to be used.

However, when considering a gate electrode length of about 0.1 μm, it is difficult to realize this on the extension line of the current reduction exposure projection apparatus, and as an alternative technique, a pattern exposure technique using an electron beam. There is.

However, in the drawing method using the electron beam, the beam system cannot be so large as to project the entire desired pattern all at once. Therefore, each pattern is divided into a limited area and directly drawn, which causes a problem that the time required for the photo-etching process becomes very long.

To improve this problem, the character
A method called projection has been proposed. This method is a method in which a specific pattern that can be collectively projected by an electron beam is prepared in advance as an aperture, and only the area of this aperture pattern is collectively drawn, and the processing time is shortened.

FIG. 5 is a pattern plan view showing a drawing pattern in the character projection system.
In the figure, a region 501 is set as one unit, and this is sequentially and repeatedly drawn to form the entire pattern.

However, according to this character projection method, it is an effective means in a device in which a repeating pattern such as a memory cell is dominant, that is, a memory device, but is constituted by a random pattern such as a logic device. Not suitable for devices.

[0009]

BRIEF Problem to be Solved] The present invention in view of the circumstances described above, producing how a semiconductor device using an efficient photolithographic method for devices constituting a random fine pattern shape The purpose is to provide.

[0010]

The present invention is a character
・ Electron beam exposure by projection method and other
Photo-etching including formation of resist pattern in combination with exposure
A method for manufacturing a semiconductor device using an engraving process, comprising the steps of:
The pattern formed by the electron beam exposure in the true etching process.
There are several types of patterns, and the shapes of these patterns are
A rectangle whose short sides have the same length in all patterns
And the length of the long side is a predetermined basic dimension or
Is only an integral multiple of that and is formed by the electron beam exposure.
Pattern and the pattern formed by another exposure method.
The connection part with the turn is the rectangle formed by the electron beam exposure.
Overlap of any length in the long side direction of the shape pattern
The electron beam exposure that is finally formed by having
The length of the pattern formed by
It is characterized by being set.

[0011]

[0012]

1 is a pattern plan view of a semiconductor device according to an embodiment of the present invention. 11 to 18 in the figure
It is a pattern of a gate electrode of a MOS transistor formed on a semiconductor substrate. Although not shown, source and drain diffusion regions are formed in a predetermined region on the substrate with a gate electrode therebetween. Among the above gate electrodes, the patterns 12 to 16 are patterns having the finest line width (gate length) and are formed according to the resist formed by electron beam exposure. The other patterns 11, 17 and 18 and the patterns 21 to 23 of the contact portion connecting these patterns are formed according to the resist formed by the collective reduction projection exposure method.

The development processing of the resist is collectively performed after the above two types of exposure are completed. Therefore, a resist agent that is sensitive to both electron beam exposure and light exposure is used. For example, a chemically amplified negative resist composed of polyvinylphenol, a cross-linking agent and an acid generator, or a chemically amplified positive resist composed of polyvinylphenol, a dissolution inhibitor and an acid generator is used.

FIGS. 2A to 2E show F2-F2 of FIG.
FIG. 7 is a cross-sectional view showing the steps of forming a cross section along the line in order. First, as shown in FIG. 2A, after a SiO2 film 202 of about 10 nm is formed on a Si substrate 201 by, for example, a thermal oxidation method, a polycrystalline Si film 203 of about 200 nm is formed by, for example, a chemical vapor deposition method. accumulate. After that, a resist film 204 used in the photo-etching process is applied with a film thickness of, for example, about 500 nm. At this time, as the resist film 204, a negative resist suitable for both electron beam exposure and light exposure as described above is used.

The reason for applying the negative resist here is as follows.
The exposure area of one shot of electron beam exposure is a narrower area than that of light exposure, and the electron beam exposure forms a partially fine portion such as a gate electrode as a resist mask. is there. That is, it is considered that the burden of the exposure area due to the electron beam exposure is small.

Next, as shown in FIG. 2B, an exposed portion 204a is formed in a predetermined region of the resist film using an electron beam exposure apparatus. Further, FIG. 3 shows a plan view corresponding to FIG. 1 of the exposed portion at this stage. The pattern formed here has, for example, all the short sides of 0.1 μm and the long sides of 1 μm (indicated by A in the figure) or an integral multiple of 1 μm (indicated by n × A in the figure). The pattern is designed so that

After that, as shown in FIG.
nm (so-called i-line), 248 nm (KrF excimer laser), or 193 nm (ArF excimer laser)
An exposed portion 204b is formed in a predetermined region of the resist film 204 by collective reduction projection exposure using light having wavelengths such as the above. Figure 4
Shows a plan view corresponding to FIG. 1 of the exposed portion at this stage. This light exposure portion 204b allows the formation of other patterns 11, 17, 18 and the contact area patterns 21-23 connecting these patterns in addition to the electron beam exposure portion 204a for the patterns 12-16 in FIG. The resist pattern for exposure was exposed.

At a portion (for example, 401 in FIG. 4) where the pattern formed by the electron beam exposure and the pattern formed by the collective reduction exposure at this stage are connected to each other, a superposition matching the alignment accuracy of the exposure apparatus is performed. It is desirable to secure a margin. In addition, by setting the length of this overlap arbitrarily, the pattern with the finest line width that will be finally formed has the same dimension in the short side direction of the rectangle and has an arbitrary length in the long side direction. Can be formed.

After that, as shown in FIG. 2D, the resist film is developed after the above-mentioned two types of exposure to remove the unexposed region, and the development is performed as shown in FIG. 2E. Using the processed resist film 204 (204a, 204b) as a mask, for example, anisotropic etching is used to form the polycrystalline Si film 20.
3 is formed into a predetermined shape (11 and 12 in Fig. 1).

In this way, a partial fine pattern,
When the pattern of the other part which is not relatively fine is in the same layer and it is a random pattern, the desired pattern can be formed in a short time by performing different photo-etching methods on the same layer. .

Further, in this embodiment, when a plurality of types of MOSFETs are provided, a first gate electrode patterned by electron beam exposure on the same layer and a second gate electrode patterned by light exposure other than electron beam exposure. A gate electrode, and a contact portion extending from these gates is patterned by the light exposure, and the first gate electrode length is the finest in the pattern formed in the photo-etching process. It is characterized by having dimensions. Also, MOS
It is shown that the gate width of the FET can be appropriately adjusted within the range of overlap with the electron beam exposure in the light exposure.

The scope of application of the present invention is not limited to this, and can be similarly applied to other fine patterns other than MOSFETs, and the structure of the base to which the photo-etching process is applied is also limited to this. Not a thing. Further, even if the layers are not the same layer, a layer requiring a fine pattern may be subjected to a photolithography process of introducing a resist pattern by electron beam exposure to form a desired pattern.

Although the negative resist is shown as the resist to be used, the resist is not limited to this, and it is desirable to use a positive resist when forming a pattern such as a contact hole. For example, when forming a resist pattern of a fine contact hole and a contact hole of other random size, a positive resist is used, the former corresponds to electron beam exposure, and the latter corresponds to light exposure.

Further, in the above-described embodiment, the electron beam exposure is first performed, and then the collective reduction projection exposure is performed.
The order is not limited to this, and there is no problem even if the order is reversed.

[0025]

As described above, according to the present invention,
Since the pattern to which the electron beam drawing is applied can be constituted by a rectangle having a minimum dimension in the short side direction and a certain dimension in the long side direction, a plurality of types of MOSFETs can be formed.
Etc., even for repetitive irregular random patterns,
The character projection system can be applied, and a fine desired pattern can be formed in a short time.

In forming a fine random pattern, a pattern having the finest line width and a pattern other than that are formed by another photographic etching method, the former is an electron beam drawing, and the latter is a collective reduction projection exposure method. Form. In addition, at this time, all the patterns formed by electron beam drawing are formed in a rectangular shape, and the dimensions in the short side direction are all common, and the long side direction has a certain predetermined dimension and a predetermined dimension. Design the pattern so that it consists only of integral multiples of the dimensions.
This makes it possible to draw a random fine pattern in a short time in a semiconductor device such as an ASIC with few repeating patterns.

[Brief description of drawings]

FIG. 1 is a pattern plan view of a semiconductor device according to an embodiment of the present invention.

2A to 2E are cross-sectional views sequentially showing a step of forming a cross section taken along line 2F-2F in FIG.

FIG. 3 is a plan view corresponding to FIG. 1 showing an electron beam exposed portion.

FIG. 4 is a view showing a light-exposed portion in addition to an electron-beam-exposed portion.
The plan view corresponding to.

FIG. 5 is a pattern plan view showing a drawing pattern in the character projection system.

[Explanation of symbols]

11-18 ... Gate electrode of MOS transistor 12-23 ... Contact area 201 ... Si substrate 202 ... SiO2 film 203 ... Polycrystalline Si film 204 ... Resist film (negative resist) 204a ... Electron beam exposed area 204b ... light exposure area 401… Overlay patterns

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 7/20 521

Claims (4)

(57) [Claims] 1. A character projection system
Resist beam using both electron beam exposure and other exposure.
Of a semiconductor device using a photo-etching process including formation of turns
A manufacturing method, wherein the electron beam in the photo-etching process
There are multiple types of patterns formed by exposure.
Each pattern has a rectangular shape, and the length of its short side is
The same on all turns and the length of its long side
Is the specified basic size or an integral multiple of it.
The pattern formed by the electron beam exposure and other
The connection part with the pattern formed by the exposure method
In the long side direction of the rectangular pattern formed by electron beam exposure.
And having a margin of any length, the final
Pattern formed by the electron beam exposure formed on
Is characterized in that the length in the long side direction of is set arbitrarily
Manufacturing method of semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the shape of the pattern formed by the electron beam exposure is a rectangle, and the length of the short side of the pattern is the pattern formed in the photolithography process. It is characterized by having the finest dimension among them. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the resist agent of the resist pattern is a negative resist that is exposed to both electron beam exposure and light exposure, and the photoetching step is performed for both exposures. After that, the resist layer is developed to form the resist pattern, and the same layer is etched using the resist pattern as a mask. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the resist agent of the resist pattern is a positive resist that is exposed to both electron beam exposure and light exposure, and the photoetching step is performed to both exposures. After that, the resist layer is developed to form the resist pattern, and the same layer is etched using the resist pattern as a mask.