JPH09190530A - Method and device for processing data and data output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rotate data with a simple circuit configuration. SOLUTION: In registers 23-25 inputting and holding eight-bit data of the respective rows in respective kinds of 8×8 digital data and these eight registers, digital data held in the register is shifted by a one-bit unit and one-bit data shifted-out from the respective eight registers by the shift operation are read so as to be outputted to an output bus 22 so that digital data obtained by rotating original 8×8 digital data by 90 deg. is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing method for inputting data such as image data, performing rotation processing, and outputting the data, an apparatus therefor, and a data output apparatus.

[0002]

2. Description of the Related Art Conventionally, many data conversion circuits for inputting image data and rotating it by 90 ° have been proposed, and many methods for rotating such data by software have been proposed.

[0003]

When high-speed data rotation processing is required, it is generally performed by using a dedicated hardware circuit instead of software processing.

An example of such a hardware circuit is a customer-specific gate array. Such a gate array includes a register that holds input data in 1-bit units, and a data selector that outputs the data rotated in 1-bit units in the same manner as the arrangement of the data to be rotated. Moreover, since such a data selector needs to be provided for each rotation angle (for example, 90 ° right rotation or −90 ° rotation), there is a problem that the circuit configuration becomes very large. In addition, since the data selectors are arranged according to the angle to be rotated, the wiring between the data selectors is complicated, not only takes a lot of time for mapping, but it also causes a delay in data output. there were.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a data processing method, a device therefor, and a data output device capable of rotating data with a simple circuit configuration.

Another object of the present invention is to provide a data processing method, a device therefor and a data output device which can easily obtain rotated data by simply shifting the data using a shift register.

It is a further object of the present invention to provide a data processing method, a device therefor and a data output device which can obtain rotated data only by setting and reading the data.

[0008]

In order to achieve the above object, the data processing apparatus of the present invention has the following configuration. That is, in a data processing device for rotating digital data of N × M matrix, at least N holding means each holding M bit data of each row of the digital data, and each of the N holding means. Shift means for shifting the held digital data in 1-bit units, and means for reading the 1-bit data shifted out from each of the N holding means by the shift operation by the shift means to obtain rotation data. Have.

In order to achieve the above object, the data processing method of the present invention has the following configuration. That is, N ×
A data processing method for rotating digital data of M matrix, comprising the step of outputting M bit data of each row of the digital data and holding it in each of N registers, and a clock signal for each of the N registers. Is output and the held digital data is shifted in 1-bit units, and the N
It has a read step of reading N-bit data consisting of each 1-bit data shifted out of the individual registers, and a step of repeating the shift step and the read step M times.

[0010]

According to an embodiment of the present invention, the holding means is a shift register having a latch function.

Further, according to the embodiment of the present invention, the holding means (register) is a shift register having a latch function, and the control signals S0 and S1 are synchronized with the clock signal to shift from the least significant bit position to the most significant bit position. Direction, or data shift from the most significant bit position to the least significant bit position.

According to the embodiment of the present invention, when data is rotated clockwise, the bit shifted out from each register is the most significant bit.

According to the embodiment of the present invention, when data is rotated counterclockwise, the bit shifted out from each register is the least significant bit.

According to the embodiment of the present invention, when the data is rotated clockwise, the register for setting the data of the first row of the digital data is connected to the least significant bit position of the output bus.

According to the embodiment of the present invention, when the data is rotated in the counterclockwise direction, the register for setting the data of the first row of the digital data is connected to the most significant bit position of the output bus.

According to the embodiment of the present invention, the data processing method and device are included in a data output device such as a printer device or a display device, and the data rotated by the data processing method and device is a bit map. It is stored in the memory and displayed on the display, or stored in the print buffer and output to the printer engine for printing.

<First Embodiment> A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

In this embodiment, 8 × 8 bits, 90
An example of data processing for right rotation will be described.

FIGS. 1A and 1B are views for explaining the structure of the data before the rotation processing and the data after the rotation processing.

FIG. 1A shows the arrangement of input data, which shows the data before the rotation processing. FIG.
(B) shows the structure of the data after the 90 ° clockwise rotation process. In FIG. 1, the numbers in the horizontal direction are bit positions,
The vertical direction indicates the register name.

In FIG. 1, 8-bit data having bit positions 0 to 7 is stored in the register "DA" in the register "D".
8-bit data with bit positions 8 to 15 in "B"
Similarly, a total of 64 (8
Bit × 8) bit data is set.

In FIG. 1B, when the content of the register "DA" is read after the right rotation processing, the bit positions are 7, 15, 23, 31, 39, in order from the least significant bit position side.
47,55,63 data are obtained. When data is sequentially read up to the register "DH" in this manner, the data of FIG. 1B rotated 90 ° to the right as compared with FIG. 1A is obtained.

FIG. 2 is a block diagram showing the configuration of the data rotation circuit 101 for performing such data rotation processing.

In FIG. 2, 21 is an 8-bit input data bus, 22 is an 8-bit output data bus, and 23 to
Reference numeral 25 denotes a shift register, each of which is an 8-bit shift register.
A to “DH”, and register “DA”,
"DB", ... "DH" have the same circuit configuration.

FIG. 3 is a block diagram showing a circuit configuration of the shift register 23, and FIG.
6 is a timing chart showing the operation timing of No. 3 in FIG.

The 8-bit data of the register "DA" of FIG. 1A input from the input data bus 21 of FIG. 2 is input to the parallel input terminals (A to H) of the shift register "DA" (7: 0). Is entered. Similarly, the 8-bit data in the register “DB” in FIG.
B ”(7: 0) parallel input terminals (A to H).

These shift registers have the signal S0 (3
When 3) is high level and the signal S1 (32) is high level, parallel data is loaded at the rising edge of the clock signal (Clock) 31, the signal S0 (33) is high level, and the signal S1 (32) is low level. At that time, one bit is sequentially shifted at each rising edge of the clock, and the shifted data is output from the output terminal (QH). That is, here, the QH outputs of the shift registers 23 to 25 are connected to the output data bus 22, the output of the register DA is connected to the 0th bit, the output of the register DB is connected to the 1st bit, and so on. If the QH output of the register DH is connected to 7 bits, 90 ° clockwise rotation data can be obtained with 8 × 8 bits as shown in FIG. 1 (B).

FIG. 5 shows the data rotation circuit 10 of this embodiment.
1 is a block diagram showing a configuration of a data processing device using 1.
Portions common to FIG. 2 are indicated by the same numbers.

In the figure, 201 is a CPU such as a microprocessor for controlling the operation of the entire apparatus, and 202 is a C
The program memory stores various data such as a control program executed by the PU 201. A register group 203 includes the registers DA to DH shown in FIG.

FIG. 6 is a CPU 20 based on the configuration shown in FIG.
In the flowchart showing the processing of No. 1, the control program for executing this processing is stored in the program memory 202.

This process is started in a state where data is set in all the registers of the register group 203, for example, as shown in FIG. 1A. First, in step S1, the signal S0 (3
3) and S1 (32) are both set to a high level, data is read from each register of the register group 203 and set in the register of the data transfer circuit 101 via the input data bus 21. Here, the value of the register “DA” of the register group 203 is stored in the register “DA” 23 of the data transfer circuit 101 and the value of the register “DB” of the register group 203.
Is the register “DB” 24 of the data transfer circuit 101.
In the same manner, the register "D
The value of “H” is the register “DH” 2 of the data transfer circuit 101.
Set to 5, respectively. Thus, steps S2 to S
In 3, when the contents of all the registers of the register group 203 are set in the registers of the data transfer circuit 101, the process proceeds to step S4.

In step S4, the signal S0 (33) is set to high level and the signal S1 (32) is set to low level. Next, in step S5, the clock signal 31 is output for only one clock. Then, in step S6, the output bus 2
2 is read, and the read content is read in step S7.
Then, register of the register group (the first time is the register "D
A ”). As a result, the content of the register "DA" in FIG. 1B is set.

Next, in step S8, register "DA"
It is checked whether or not the data set for all "DH" has been completed. If not, the process returns to step S5, the clock signal 31 is output again for one clock, and the contents of the bus 22 are read and set in the register group 203 in step S6. To do. As a result, the contents of the register “DB” in FIG. 1B are set in the second processing. Similarly, by repeating these processes, data rotated by 90 ° to the right as shown in FIG. 1B is obtained in each register of the register group 203.

<Second Embodiment> As a second embodiment, an example of data rotation processing of 8 × 8 bit, -90 ° left rotation will be described.

FIG. 7 is a block diagram showing the circuit configuration of the second embodiment of the present invention.

FIG. 7A shows the input data before the rotation process, and FIG. 7B shows the data after the -90 ° rotation (90 ° left rotation) process. In FIG. 7, the horizontal direction indicates the bit position and the vertical direction indicates the register name.

In FIG. 7A, 8-bit data having bit positions 0 to 7 are stored in the register "IA", 8-bit data having bit positions 8 to 15 are stored in the register "IB", and so on. , Register "IA" to register "I"
A total of 64 bits of data is input to "H".

FIG. 7B shows data after the -90 ° rotation process. When the register "IA" is read after this rotation processing, the bit positions are 56, 4 in order from the least significant bit.
Data of 8, 40, 32, 24, 16, 8, 0 are obtained. If these data are sequentially read from the registers “IA” to “IH”, the data in FIG. 7A becomes −90 °.
The rotated (90 ° left) data is obtained.

FIG. 8 is a block diagram showing the configuration of the data rotation circuit 801 which performs this rotation processing.

In the figure, 61 is an 8-bit input data bus, 62 is an 8-bit output data bus, and 63 is a shift register. The circuit configuration of the registers "IA" to "IH" of the data rotation circuit 801 is the same as that shown in FIG. The difference between the circuit configuration of FIG. 8 and the circuit configuration of FIG. 2 is that the output of each shift register is changed from QH to QA, and the output of the register “IA” is at the most significant bit position, and the register “IB” is at the most significant bit position. Is connected to the second bit position, and so on, to the output of register "IH" at the least significant bit position.

The 8-bit data of the register "IA" of FIG. 7A input from the input data bus 61 of FIG. 8 is the shift register "IA" of the data rotation circuit 801.
It is input to the parallel input terminal of (7: 0). However, here, A represents the least significant bit position and H represents the most significant bit. Similarly, the contents of the register "IB" in FIG. 7 are input to the register "IB" (7: 0).

The operation of the circuit according to the second embodiment is that the signal S0 (33) shown in FIG.
(32) is set to a high level, and 8-bit parallel data is loaded into each shift register at the rising edge of the clock signal 31. When the signal S0 (33) is low level and the signal S1 is high level, the clock signal 3
At the rising edge of 1, the bits are sequentially shifted in the least significant bit direction. The data thus shifted is output from QA. Here, if the QA output of each shift register is connected to 0 to 7 bits of the output data bus 62, 8 × 8 bit, -90 ° counterclockwise rotation data can be obtained as shown in FIG. 7B.

The device configuration of the second embodiment is basically the same as that of FIG. 5, and the configuration of the registers of the register group 203 of FIG. 5 is changed to the registers “IA” to “IH” of FIG. Only the transfer circuit 801 is different.

The processing in the apparatus of the second embodiment will be described with reference to the flowchart of FIG. The control program for executing this processing is also the program memory 20.
2 is stored.

This processing is started in a state where data is set in all the registers of the register group 203 as shown in FIG. 7A, and first, in step S11, the signal S0 (3
3) and S1 (32) are both set to a high level, data is read from each register of the register group 203 and set in the register of the data transfer circuit 101 via the input bus 61. Here, the register I of the register group 203
The value of A is the register “IA” 63 of the data transfer circuit 101.
Then, the value of the register IB of the register group 203 is set in the register “IB” 64 of the data transfer circuit 101, and similarly, the value of the register IH of the register group 203 is set in the register “IH” 65 of the data transfer circuit 101. To be done. Thus, when the contents of all the registers (IA to IH) of the register group 203 are set in the registers of the data transfer circuit 101 in steps S12 to S13, step S12
Proceed to 14.

In step S14, the signal S0 (33) is set to low level and the signal S1 (32) is set to high level. Next, in step S15, the clock signal 31 is set to 1
Output clock only. Then, in step S16, the content of the output bus 62 is read, and the read content is set in the register of the register group (the first time is the register "IA") in step S17. As a result, the contents of the register "IA" in FIG. 7B are set.

Next, at step S18, the registers IA to IH are
Is checked for completion of the data set, and if not, the process returns to step S15, the clock signal 31 is output again for one clock, and the bus 6 is output in step S16.
The contents of 2 are read and set in the register group 203. As a result, the register "I" of FIG.
The contents of "B" are set. Similarly, by repeating these processes, data obtained by rotating the data of FIG. 7A by −90 ° as shown in FIG. 7B can be obtained in each register of the register group 203. become.

The above-mentioned data rotation circuit may be provided in a data output device such as a printer device or a display device. In this case, the display data or print data input from the host computer or the like is rotated by the data rotation circuit of this embodiment as needed, and the rotated data is stored in a bit map memory (VRAM), a print buffer, or the like. After storing the data in the printer engine, the data is output to the printer engine or the display for display or printing. As a result, the data can be displayed and printed by rotating the data at high speed in accordance with an instruction from the host computer or the like.

This is shown in FIGS. 10 (A) and 10 (B).
FIG. 10A shows an example applied to a display device,
FIG. 10B shows an example applied to a printer device.

In FIG. 10A, reference numeral 1001 denotes an input buffer for inputting display data from a host computer or the like and temporarily storing it, and reference numeral 1002 denotes a control unit for controlling the entire display device, which includes the CPU 201 and the data described above. The rotating circuit 101 and the like are included. A video memory (VRAM) 1003 stores display data displayed on the display 1004 in a bitmap format.
The display 1004 is a display unit such as a CRT or liquid crystal.

In FIG. 10B, reference numeral 2001 denotes an input buffer for inputting print data from a host computer or the like and temporarily storing the print data, and reference numeral 2002 denotes a control unit for controlling the entire printer apparatus, which includes the CPU 201 and the data described above. The rotating circuit 101 and the like are included. A print buffer 2003 stores print data output to the printer engine 2004 for printing, for example, in a bitmap format. The printer engine 2004 may be any type of printer engine such as an electrophotographic system, a thermal transfer system, or an inkjet system.

The present invention may be applied to a system composed of a plurality of devices such as a host computer, an interface and a printer, or to an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is implemented by supplying a program to a system or an apparatus. In this case, the storage medium storing the program according to the present invention constitutes the present invention. Then, by reading the program from the storage medium to the system or device, the system or device operates in a predetermined manner.

As described above, according to the present embodiment, the data selector can be omitted and the circuit configuration can be simplified by configuring the processing device for rotating and outputting the data input from the data bus by the shift register. Can be converted.

Further, not only the time required for mapping can be shortened, but also the data output time can be shortened.

[0055]

As described above, according to the present invention, it is possible to rotate data with a simple circuit configuration.

Further, according to the present invention, the rotated data can be easily obtained only by shifting the data using the shift register.

Further, according to the present invention, there is an effect that rotated data can be obtained only by setting and reading the data.

[0058]

[Brief description of the drawings]

FIG. 1 is a diagram illustrating 90 ° clockwise rotation processing of 8 × 8 bit data according to a first embodiment of this invention.

FIG. 2 is a block diagram showing a configuration of a data rotation circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a circuit configuration of a shift register of a data rotation circuit.

FIG. 4 is a timing diagram illustrating an operation of a shift register.

FIG. 5 is a block diagram showing a configuration of a data processing device according to the present embodiment.

FIG. 6 is a flowchart showing a rotation process in the data processing device of the first embodiment.

FIG. 7 is a diagram illustrating −90 ° rotation processing of 8 × 8 bit data according to the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a data rotation circuit according to a second embodiment.

FIG. 9 is a flowchart showing a rotation process in the data processing device of the second embodiment.

FIG. 10 is a block diagram showing an example of a data output device including the data rotation circuit according to the present embodiment.

[Explanation of symbols]

 21,61 Input data bus 22,62 Output data bus 23,24,25,63,64,65 Shift register 31 Clock signal 32 Signal S1 33 Signal S0 101,801 Data rotation circuit 201 CPU 202 Program memory 203 Register group

Claims (11)

[Claims] 1. A data processing device for rotating N × M matrix digital data, each holding unit holding at least N pieces of M-bit data of each row of the digital data, and said N pieces of holding means. In each of the above, shift means for shifting the held digital data in 1-bit units, and 1-bit data shifted out from each of the N holding means by the shift operation by the shift means are read out to obtain the rotation data. And a means for obtaining the data processing apparatus. 2. The data processing device according to claim 1, wherein when rotating in the clockwise direction, the shift means shifts the digital data from the most significant bit position toward the least significant bit position. 3. The data processing device according to claim 1, wherein when rotating in the counterclockwise direction, the shift means shifts the digital data from the least significant bit position toward the most significant bit position. 4. A data processing device for rotating an N × N matrix of digital data, each of which holds at least N holding means for holding N-bit data of each row of the digital data, and said N holding means. In each of the above, shift means for shifting the held digital data from the least significant bit position toward the most significant bit position in 1-bit units, means for executing the shift by the shift means N times, and shift by the shift means. A reading means for reading N-bit data from the N holding means at each operation, and shifting from the holding means holding the data of the first row of the digital data among the N holding means. The 1-bit data to be output is the least significant bit, and thereafter, the 1-bit data to be sequentially shifted out from the holding means is the first. Go assigned from the least significant bit position side, the data processing apparatus characterized by obtaining the rotation data of the clockwise one-bit data is shifted out of the N-th holding means as the most significant bit. 5. A data processing device for rotating N × N matrix digital data, each holding unit holding at least N pieces of N-bit data of each row of the digital data, and said N pieces of holding means. In each of the above, shift means for shifting the held digital data from the most significant bit position toward the least significant bit position in 1-bit units, means for performing the shift by the shift means N times, and shift by the shift means. A reading means for reading N-bit data from the N holding means at each operation, and shifting from the holding means holding the data of the first row of the digital data among the N holding means. The 1-bit data that is output is the most significant bit, and the 1-bit data that is sequentially shifted out from the holding means is the previous bit. Go assigned from the most significant bit position side, the data processing apparatus characterized by obtaining the rotation data of the left-handed direction one bit data is shifted out of the N-th holding means as the least significant bit. 6. A data output device comprising the data processing device according to claim 1. 7. The data output device according to claim 6, wherein the data output device is a printer device. 8. The data output device according to claim 6, wherein the data output device is a display device. 9. A data processing method for rotating N × M matrix digital data, comprising the step of outputting M-bit data of each row of the digital data and holding the M-bit data in each of N registers, A clock signal is output to each of the registers to shift the held digital data in 1-bit units, and N bits each consisting of 1-bit data shifted out of the N registers by the shift step. A data processing method, comprising: a reading step of reading data, and a step of repeating the shift step and the reading step M times. 10. The data processing method according to claim 9, wherein:
When rotating in the clockwise direction, the digital data is shifted from the most significant bit position to the least significant bit position in the shifting step. 11. The data processing method according to claim 9, wherein:
When rotating in the counterclockwise direction, the digital data is shifted from the least significant bit position toward the most significant bit position in the shifting step.