JPH09190515A - Ic card system and its data transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the transmission of data without discriminating the external processors of different transmission speeds on the side of an IC card by detecting the transmission speed of specified data and transmitting and receiving the data at this detected speed when the specified data that are previously arranged between the external processors are received. SOLUTION: When an IC card 20 is connected to an external processor 10, a CPU 22 detects this connection and sends the initial answer information to the processor 10. The processor 10 sends first the data to the card 20, i.e., the connection destination in a format that is prescribed by the communication protocol. The card 20 detects the transmission speed of the data received from the processor 10 and performs the subsequent communication at this detected speed. Then, the processor 10 sends the data to the card 20 which receives the data at the set speed. The card 20 recognized the command contents and ends the communication when the recognition result is affirmative.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card system for exchanging data with an external device, and more particularly, to an IC card system capable of changing the data transmission rate according to the external processing device. The present invention relates to a data transmission method.

[0002]

2. Description of the Related Art Conventionally, a technique for exchanging data between an IC card and an external processing device has been widely known. With such a technique, the IC card can receive and store data from the external processing device, transmit the data to another external processing device, and use the data between different external processing devices. It became so. At this time, since the transmission speed of the IC card is generally fixed, it is necessary for the external processing device side to set the transmission speed in advance according to the transmission performance of the IC card.

[0003]

By the way, in recent years, on the side of the external processing device, the performance of the system, especially the CPU, has been remarkably improved, so that the overall processing speed including communication can be performed at high speed. It was in spite of,
Since the data transmission speed in the IC card is still fixed, there is a problem that the external processing device cannot perform the processing at high speed. Further, since the IC card needs to perform data transmission with a plurality of different external processing devices, the transmission speed of these is also restricted by that of the IC card, and as a result, the processing of the entire system cannot be performed at high speed. There was also a problem. Conversely, on the IC card side, since it is not possible to distinguish between external processing devices with different transmission rates, it is not possible to perform data transmission that matches the transmission rate of the external processing device of the other party, which reduces processing efficiency. It was

The present invention has been made in view of the above problems, and an object thereof is to enable external processing devices having different transmission speeds to perform data transmission without distinction on the IC card side, An object of the present invention is to provide an IC card system that can execute the processing of the entire system at high speed and a data transmission method thereof.

[0005]

In order to solve the above-mentioned problems, the present invention according to claim 1 provides an IC card system for performing data transmission between an IC card and an external processing device. When the IC card receives the specific data pre-arranged with the external processing device, the transmission speed detecting means for detecting the transmission speed of the specific data, and the transmission for transmitting or receiving the data at the detected transmission speed And means. The invention according to claim 2 is characterized in that, in the invention according to claim 1, the specific data is a head byte of a format defined by a communication protocol. According to a third aspect of the invention, in the first aspect of the invention, the IC card is provided with specific data transmission requesting means for requesting transmission of the specific data,
It is characterized in that the external processing device is provided with a specific data transmitting means for transmitting the specific data to the IC card when there is a request for transmitting the specific data.
In the invention according to claim 4, in the invention according to claim 1, the transmission rate detecting means detects the transmission rate of the specific data by measuring a time required for receiving the specific data. It is characterized by doing. According to a fifth aspect of the invention, in the fourth aspect of the invention, the transmission rate detecting means pays attention to a transmission pattern of the specific data, and from the reception start to the reception end of the transmission pattern. It is characterized in that the time is measured and the quotient obtained by dividing the time by the number of bits of the specific data is detected as the transmission rate. According to a sixth aspect of the present invention, in an IC card system data transmission method for performing data transmission between an IC card and an external processing device, the IC card is arranged in advance with the external processing device. When receiving the specified data, the IC card includes a step of detecting a transmission rate of the specified data and a step of causing the IC card to transmit or receive data to or from the external processing device at the detected transmission rate. I am trying.

According to the present invention, before the data is transferred between the external processing device and the IC card, the IC card is
The specific data determined in advance is received from the external processing device. It is relatively easy to detect the transmission rate from the transmission pattern, etc., even if the specific data arrives at any transmission rate if the data is agreed in advance. Since the IC card subsequently transmits and receives data at the detected transmission rate, it becomes possible to communicate without distinguishing a plurality of external processing devices.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

1: Configuration Hereinafter, a preferred embodiment of the present invention will be described.
In the IC card system according to the present embodiment, the IC card receives certain specific data from the external processing device before data transmission between the external processing device and the IC card,
The transmission rate is set by this reception, and data transmission is performed at this transmission rate. FIG. 1 is a block diagram showing the configuration of an IC card system according to an embodiment of the present invention. As shown in this figure, the external processing device 10 and the IC
Data is exchanged with the card 20 via the I / O ports 11 and 21, respectively. Here, the IC card 20
A CPU 22 that executes various processes, a RAM 23 that stores various data, and a ROM 2 that stores a basic program.
4 and data is transferred via the bus B. The clock CLK from the timer 25 is supplied to the CPU 22 and is used for controlling the increment and decrement processes described later. In addition, the external processing device 10 and the IC card 20
The communication with and may be performed in a state of being mechanically connected via a connector, or in a state of being wirelessly connected with a certain distance. Actually, the communication protocol described below is used.

1-1: Communication Protocol The communication protocol according to the present embodiment will be described with reference to FIG. The communication protocol according to the present embodiment is for serial communication with a total of 10 bits in which a character bit (8 bits) is inserted between a start bit ST (1 bit) and a parity bit BP (1 bit). In addition, each bit corresponds to a high level of “1” and is low.
The level corresponds to “0”. Here, when the character bit is “00000000” (that is, when the hexadecimal notation is [00] _H ), if the error code is even parity, the parity bit is also “0”. Therefore, the I / O port 11 , 21 are at the Low level during the period corresponding to 10 bits from the start bit ST to the parity bit BP.

2: Operation Next, the operation of the IC card system according to the above embodiment will be described. FIG. 3 is a flowchart showing an operation (main routine) viewed from the IC card 20 side in the overall operation of this IC card system. In addition, IC
Strictly speaking, the operation subject of the card 20 is the CPU 22, but it is not particularly distinguished in this description.

First, the IC card 20 is replaced by the external processing device 1.
When connected to 0 through a wired or wireless connection, the CPU 22
Detects this connection and sends initial response information ATR to the external processing device 10 in step S1. When this initial response information ATR is received, the external processing device 10
Sends data [00] _H to the IC card 20. The data [00] _H is first transmitted to the IC card 20 to which the external processing device 10 is connected in the format defined by the communication protocol, but the content thereof will be described later. This is because it is suitable for detecting the transmission rate. In step S2, the IC card 20 detects the data transmission speed from the external processing device 10 by receiving the data, and sets the subsequent communication at that transmission speed (transmission speed adjusting process). The details of this process will be described later.

After this transmission processing adjustment processing, the external processing device 10 transmits the data to be transmitted to the IC card 20, and the IC card 20 sends the data to the IC card 20 in step S3.
The data is received at the set transmission rate (reception processing). The details of the data reception process in the IC card 20 will be described later. Then, upon receipt of all the data, the IC card 20 recognizes the content of the command composed of the received data in step S4, and determines in step S5 whether the content of the command is a command for instructing the end of communication. Determine whether. If the determination result is “Yes”, the IC card 20 ends the communication with the external processing device 10, while if the determination result is “No”, in step S6, the process corresponding to the command is executed, The response that is the execution result is stored in RAM
The data is stored in the buffer area allocated to No. 23. Then, in step S7, the IC card 20 transmits the stored data to the external processing device 10 at the set transmission speed.
Send to Details of the transmission process in step S7 will be described later.

After the transmission processing, the IC card 20
In step S8, the presence or absence of received data is determined.
Specifically, if there is received data, the I / O port 21
Since the communication level of is set to Low level by the start bit ST, the presence or absence of received data is determined by detecting this. If the result of this determination is nothing,
This step S8 is repeatedly executed to wait until the received data becomes available. On the other hand, if so, the procedure returns to step S3 and the receiving process for the data is executed.

After that, the IC card 20 repeats the process of executing the command composed of the received data and transmitting the response every time there is received data until the end command is received.

2-1: Transmission Rate Adjusting Process First, the details of the transmission rate adjusting process executed in step S2 of the above-mentioned main routine (see FIG. 3) will be described. In this transmission speed adjustment processing, the IC card 20 receives the specific data that has been arranged in advance with the external processing device 10, detects the transmission speed of the data from the communication level at that time, and performs the subsequent data transmission. Is a setting process for executing at the detected transmission speed. In addition, in the present embodiment, the above-mentioned specific data is stored in FIG.
It is [00] _H shown in (a).

FIG. 4 is a flowchart showing this processing. First, in steps Sa1 to Sa4, it is measured how long it took to receive the 10-bit data of [00] _H of the specific data, and the transmission rate from the external processing device 10 is detected. . That is, the IC card 20 receives the I / O in step Sa1.
It is determined whether or not the communication level of the port 21 has become the Low level by the start bit ST associated with [00] _H of the specific data. If not at Low level, L
While the procedure returns again to wait until it becomes the ow level,
When the low level is reached, the IC card 20 performs step S
At a2, the timer counter TC is reset to zero.

Then, the IC card 20 operates in step Sa.
3, the communication level of the I / O port 21 is set to High by the stop bit SP related to [00] _H of specific data.
It is determined whether or not the level becomes the h level. If it is not at the high level, the IC card 20 proceeds to step Sa4.
In step 1, after incrementing the timer counter TC by “1”, the procedure is returned to step Sa3 while
When the level becomes the h level, the IC card 20 causes the procedure to exit the loop of steps Sa3 to Sa4, and then proceeds to step Sa5.
At the timer counter T
[00] _H is sent to the external processing device 10 as a signal that C has been set.

Here, the increment processing in step Sa4 is performed by the clock CLK of the timer 25 (see FIG. 1).
If it is executed in synchronism with the above, the value of the timer counter TC immediately after exiting from the loop is [0
0] It indicates how many times the period of the clock CLK is required to receive the 10-bit data for _H. In other words, the value of the timer counter TC immediately after exiting the loop indirectly indicates the time required for 10-bit data transmission, as shown in FIG. 2B. Then, based on the set value of the timer count TC, the transmission rate in the subsequent data transmission / reception processing is determined.

2-2: Reception Processing Next, the reception processing executed in step S3 of the above-mentioned main routine (see FIG. 3) will be described. This receiving process is a process of receiving all the data transmitted from the external processing device 10 byte by byte at the transmission rate determined by the value of the timer counter TC.

FIG. 5 is a flowchart showing this receiving process. First, in step Sb1, the IC card 20 sets the initial value of the address of the buffer that stores the received data in the register Ra. Here, the buffer is an area allocated in the RAM 23 by the CPU 22. Next, in the IC card 20, step S
In b2, 1-byte data (strictly speaking, 10-bit data because it includes the start bit ST and the parity bit BP) is received at the transmission rate determined by the value of the timer counter TC. This processing will be described later. When the IC card 20 receives 1-byte data, it stores this received data in the buffer at the address set in the register Ra. As will be described later, since one byte of received data is set in the register R2, the actual processing in step Sb3 is performed by using the data set in the register R2 in the buffer designated by the address of the register Ra. It becomes the processing to transfer to.

Then, in step Sb4, the IC card 20 determines whether or not all the data has been received. Note that this determination is performed as follows. For example, first, if 1 byte of data is transmitted after a certain period of time, and the next 1 byte of data is not received even after a certain period of time has elapsed after receiving 1 byte of data Determines that all data has been received.
Secondly, by transmitting information indicating the amount of data to be transmitted at the start of transmission, if the IC card 20 unconditionally receives this information and receives the data amount indicated by this information, Determine that all data has been received.

Now, if the result of the determination in step Sb4 is "No", the IC card 20 registers
After incrementing the value of a by "1" and incrementing the buffer address to be stored next time, the procedure is returned to step Sb2, and thereafter, the processing of steps Sb2 to Sb5 is performed until all the data are received. repeat. on the other hand,
If the determination result in step Sb4 is "Yes", this reception process ends, and the next procedure is step S4 in the main flowchart.

2-2-1: Data Reception Processing for One Byte Here, details of the data reception processing for one byte executed in step Sb2 of the reception processing will be described. The reception in this embodiment is performed by acquiring the communication level at the intermediate timing of each bit.

FIG. 6 is a flowchart showing this processing. First, in step Sb201, the IC card 2
0 divides the value of the timer counter TC by 10 and sets the quotient in the register BR. As described above, the value of the timer counter TC indicates the time required for 10-bit data transmission.
As shown in (b), the time required for 1-bit data transmission is set.

Next, in step Sb202, the IC card 20 sets a product obtained by multiplying the value of the register BR by 1.5 to the register R1 and also sets the value of the register BR to 9.5.
The multiplied product is set in the register R3, and the register R4 is reset to zero. For register R4,
This is for parity, and here it is intended to be reset because it is before reception. After this, IC card 20
Decrements the values of registers R1 and R3 in step Sb203. The decrement process is executed in synchronization with the clock CLK, similarly to the increment process of the timer counter TC. Further, since the reception process itself is activated when the communication level of the I / O port 21 is changed to the Low level by the start bit ST, the registers R1 and R3 are respectively set.
In data transmission of 1 byte, start bit ST
Will indicate the progress after the low level.

Next, the IC card 20 executes step Sb2.
In 04, it is determined whether or not the value of the register R1 becomes zero. When this receiving process is activated for the first time, in step Sb202, the register R1 determines in step Sb202 how many times the period of the clock CLK is 1.5 times the time required for 1-bit data transmission (register BR). The indicated value is set, and this value is set in step Sb2.
In 03, it is decremented in synchronization with the clock CLK by the timer 25. Therefore, the fact that the value of the register R1 becomes zero for the first time means that the progress of the data transmission indicates that the start bit ST has been set, as shown in FIG.
From the timing t _{0 when} it becomes Low level due to
This means that the time for one bit has elapsed, that is, the intermediate timing t _1.5 in the most significant bit MSB of the character bits has been reached.

Therefore, if the determination result in step Sb205 is "Yes", the communication level of the I / O port 21 is determined in the next step Sb205. On the other hand, if the determination result is “No”, it means that the progress of data transmission has not yet reached the intermediate timing t in the relevant bit, so the IC card 20 returns the procedure to step Sb203 again, and the value of each register is changed. Is decremented according to the progress of transmission.

Now, in step Sb205, the IC
The communication level of the I / O port 21 of the card 20 is Low.
It is determined whether or not it is a level. As mentioned above,
The High level of each bit corresponds to "1", and the Low level
Since the level corresponds to “0”, the IC card 20
If "Yes" is determined, the carry flag Cin is set to "0" in step Sb206, while "N" is set.
If it is "o", the carry flag Cin is set to "1" in step Sb207.

Next, the IC card 20 executes the step Sb2.
08, the value of the register R4 and the carry flag Cin
The exclusive OR with the value of is reset in the register R4,
In step Sb209, it is determined whether or not the value of the register R3 has become zero. When this receiving process is activated, 1 is set in the register R3 in step Sb202.
A value indicating how many times the cycle of the clock CLK is 9.5 times the time (register BR) required for bit data transmission is set, and this value is set by the timer in step Sb203. Clock CL by 25
It is decremented in synchronization with K. Therefore, the fact that the value of the register R3 has become zero means that the progress of the data transmission indicates that the start bit ST has been set, as shown in FIG.
9.5 from the timing t _{0 when} it becomes Low level due to
This means that the time for one bit has passed, that is, the intermediate timing t _9.5 of the parity bit BP has been reached. Therefore, the determination result of step Sb209 is "Y
If “es”, all the character bits before that have been received at this point, so the IC card 20 branches the processing procedure to step Sb212 described later.

On the other hand, if the result of this determination is "No", the IC card 20 determines in step Sb210
After shifting each bit of the register R2 shown in FIG. 10 to the upper bit, the carry flag Cin at the present time is set to the least significant bit of the register R2. After this,
Next, the IC card 20 sets the value of the register BR in the register R1 so as to obtain the communication level at the intermediate timing of the character bit next time, and then returns the processing procedure to step Sb203 again.

Such steps Sb203 to Sb21
According to the loop processing consisting of 1, first, in the first time,
The most significant bit MSB of the received character bit is acquired and set in the register R2, and in the second time,
The next most significant bit 2SB is received at timing t _2.5 (see FIG. 2B) and is bit-shifted and set in the register R2. Thereafter, the same processing is repeated eight times for each bit MSB to LSB, and the character bit Are all earned. At this point in time, the content of the register R2 itself is the 1-byte data itself received by the processing of FIG. 6, so it is transferred to the buffer in step Sb3 in FIG. 5, as described above. Then, in the ninth time, the parity bit is acquired at the timing t _9.5 , the exclusive OR of all 8 bits of the character bit and the parity bit is set in the register R4, and the loop processing is performed midway. It is designed to come off.

After exiting the loop processing, the IC card 20 determines in step Sb212 whether the value of the register R4 is zero. Since the error code in this embodiment has an even parity, the value of the register R4 when the loop processing is exited is originally
It should have been zero. Nevertheless, if the value of the register R4 is not zero, it means that a code error has occurred in any of the bits, and therefore the IC card 20 causes the IC card 20 to execute the step Sb217.
At, an error condition is set and this processing is forcibly terminated.

On the other hand, if the decision result in the step Sb212 is "No", the IC card 20 determines the stop bit SP in the next steps Sb213 to Sb216.
Is normally received. That is, the IC card 20 proceeds to the register BR in step Sb213.
Is set in the register R1, and this is set in step SB.
In step 214, it is decremented in synchronization with the clock CLK, and in step Sb215, it is determined whether or not the decrement result is zero. If "No", the processing procedure is returned to step Sb214 again. The communication level of the I / O port 21 at that time is High
It is determined whether or not it is at the h level. At this point in time, since the stop bit SP has been transmitted, the communication level should originally have been the High level. Nevertheless, if it is Low level,
Since this is an obvious communication error, the IC card 20 also executes the step S in the same manner as in the case where the error code occurs.
An error state is set at b217, and this process is forcibly terminated.

On the other hand, if the result of the determination in step Sb216 is "Yes", the IC card 20 determines that one byte of data has been normally received, terminates this reception process, and then the procedure shown in FIG. And step Sb3.

As described above, in the data receiving process for one byte shown in FIG. 6, the data serially transmitted from the external processing device 10 is sequentially acquired at the interval based on the value of the timer counter TC, and the register R2 is used. Data of 1 byte is obtained by bit-shifting and storing the data. Then, all the bytes are sequentially stored in the buffer by the receiving process shown in FIG. 5, and the command composed of the received data is recognized in the IC card 20.

2-3: Transmission Processing Next, the transmission processing executed in step S7 of the above-mentioned main routine (see FIG. 3) will be described. This transmission processing is for transmitting data, which is the execution result of the processing corresponding to the command, to the external processing device 10.

FIG. 7 is a flow chart showing this transmission processing. First, the IC card 20 resets the register R5 to zero in step Sc1. Register R
No. 5 is for the parity byte to be transmitted at the end, and here it is intended to be reset because it is before transmission. Next, in the IC card 20, step S
In c2, the total number of bytes of data to be transmitted is set in the register LC. The parity byte is excluded from this. Then, in step Sc3, the IC card 20 sets the initial address value of the buffer in which the data to be transmitted is stored in the register Ra.

Next, the IC card 20 operates in step Sc4.
At, the data corresponding to the address set in the register Ra is set as 1 byte of the data to be transmitted. As will be described later, since the data set in the register R2 is sequentially bit-shifted and transmitted in the 1-byte transmission data, the actual processing in step Sc4 is the data of the buffer address indicated by the register Ra. Is transferred to the register R2.

Then, the IC card 20 performs step Sc.
1 of the data set as the transmission byte in 5
The bytes are transmitted to the external processing device 10. In addition,
The details of this transmission processing will be described later. Next, in step Sc6, the IC card 20 sends out the parity byte in the subsequent processing, and therefore, the exclusive logic of each bit in the transmitted 1-byte data and each bit of the register R5 which is currently set. The sum is reset in the register R5. Therefore, by repeating this process, the exclusive OR of the transmitted bytes
5 will be accumulated.

After that, the IC card 20 transmits 1-byte data, and accordingly, in step Sc7,
The value of the register LC is decremented by "1", and it is determined in step Sc8 whether or not the value of the register LC becomes zero. The fact that this determination result is zero means that all the data corresponding to the total number of bytes set in step Sc2 has been transmitted, so that the IC card 20 transmits the parity byte,
The procedure is branched to step Sc10 described below. on the other hand,
The fact that the determination result of step Sc8 is “No” means that all the data to be transmitted has not been transmitted, so the IC card 20 is stored in the next buffer address in step Sc9. In order to transmit the data, the value of the register Ra is incremented by "1" and the procedure is returned to step Sc4. IC card 2
After that, 0 means that the loop process consisting of steps Sc4 to Sc9 is repeatedly executed until all the data to be transmitted are transmitted.

When all the data to be transmitted have been transmitted, the determination result of step Sc8 becomes "Yes", and the loop processing is exited.
In c10, the value of the register R5 is set as 1 byte of data to be transmitted. As described above, the exclusive OR of the transmission data is accumulated in the value of the register R5 for each bit, and this is set as the parity byte. Then, in step Sc11, the IC card 20 transmits the data set as the parity byte to the external processing device 10, terminates this routine, and executes the next procedure as step S8 of the main routine (see FIG. 3). To do. The details of this transmission process are the same as those in step Sc5 described above, and the details will be described below.

2-3-1: Data Transmission Process for 1 Byte: Here, step Sc5 or Sc1 of the reception process described above.
Details of the 1-byte data transmission process executed in 1 will be described. This transmission process is a process of setting the communication level of the I / O port according to the data to be transmitted.

8 and 9 are flowcharts showing this processing. First, step Sc501 shown in FIG.
At, the IC card 20 sets the value of the register BR in the register R1, sets the product of the value of the register BR multiplied by 9 in the register R3, and further resets the register R4 to zero. The register R4 is for parity, and is intended to be reset because it is before transmission here.

Next, in step Sc502, the IC card 20 sets the communication level of the I / O port 21 to the Low level. After that, the IC card 20 decrements the values of the registers R1 and R3 in step Sc503. The decrement process is executed in synchronization with the clock CLK, similarly to the increment process of the timer counter TC. The decrement process itself is executed after the I / O port 21 is set to the Low level in the immediately preceding step. Therefore, the registers R1 and R2 each progress from the timing t ₀ (see FIG. 2B) when the registers R1 and R2 are at the Low level corresponding to the start bit ST at the first activation of the data transmission of 1 byte. Will be shown. In the period corresponding to the start bit ST, it is necessary to be the Low level only for the time indicated by the register BR, so the IC card 20 determines whether or not the value of the register R1 becomes zero in step Sc503. .

When this process is started for the first time, the time (register BR) required for 1-bit data transmission is stored in the clock C in the register R1 in step Sc202.
A value indicating how many times the cycle of LK is set is set, and this value is decremented in synchronization with the clock CLK by the timer 25 in step Sc203. Therefore, the fact that the value of the register R1 becomes zero for the first time means that, as shown in FIG. 2B, from the timing t ₀ when the communication level changes from the High level to the Low level, the L level is maintained for the time indicated by the register BR
This means that the ow level continues and the start bit ST is transmitted, in other words, the progress of data transmission is
This means that the leading timing t ₁ in the most significant bit MSB of the character bit has been reached.

Therefore, if the determination result in step Sc504 is "No", it means that the progress of data transmission has not yet reached the start timing of the bit, and therefore the IC card 20 steps the procedure again. Returning to Sc503, the value of each register is decremented according to the progress of transmission. On the other hand, if the determination result is "Yes", the IC card 20 sets the communication level in accordance with the character bit in the next step Sc.
505 and Sc506 are executed.

That is, the 1-byte data to be transmitted at this point has already been registered in the register R in step Sc4.
Since it is set to 2 (step Sc4), first,
In step Sc505, the IC card 20 bit-shifts the register R2 and sets the bit data overflowing at this time to the carry flag Cout. Next, I
In step Sc506, the C card 20 sets the communication level of the I / O port 21 corresponding to the value of the carry flag Cout. Specifically, carry flag C
If the value of out is "0", the communication level is set to the low level, while if the value of carry flag Cout is "1", the communication level is set to the high level.

Next, the IC card 20 performs step Sc5.
07, the value of the register R4 and the carry flag Co
The exclusive OR with the value of ut is reset in the register R4, and it is determined in step Sc508 whether the value of the register R3 has become zero. When this data transmission process is activated, the register R3 stores in step Sc502.
In step Sc503, a value is set which indicates how many times the period of the clock CLK is nine times the time (register BR) required for 1-bit data transmission. It is decremented in synchronization with the clock CLK by 25. Therefore, the fact that the value of the register R3 has become zero means that in FIG.
In (b), it means that the progress of data transmission has reached the leading timing t ₉ of the parity bit BP.

Therefore, if the result of the determination in step Sc508 is "Yes", all the character bits before that are transmitted at this point, so the IC card 20 branches the processing procedure to Sc510 in FIG. Let On the other hand, if this determination result is “No”, the IC card 20 determines in step Sc509 that
After setting the value of the register BR in the register R1 so as to set the communication level in the same manner at the start timing of the next character bit, the processing procedure is performed again in step Sc50.
Return to 3.

Such steps Sc503 to Sc50
According to the loop process consisting of 9, first, in step Sc5
03 and Sc504, the start timing of each bit is detected, and then step Sc505
Then, in Sc506, the communication level is set corresponding to the bit. By repeating these processes eight times for each bit, I / O corresponding to all of the start bit ST and the character bit is performed.
The communication level of the O port 21 is set. And 9
At the first time, the total of the exclusive ORs of all 8 bits of the character bits is set in the register R4 so that the loop processing can be exited on the way.

After exiting the loop processing, the IC card 20 determines in step Sc510 shown in FIG. 9 whether the value of the register R4 is zero. Since the error code in this embodiment is even parity, the parity bit to be transmitted must be set depending on the character bit. That is, the value of the parity bit must be set according to the value of the register R4 at the present moment when the total of the exclusive OR of all 8 bits of the character bit is set. Therefore, the IC card 20 has the register R4 at this point.
Is zero, the carry flag Cout is set to "0" in step Sc511, while if the register R4 is not zero, step Sc512.
After setting the value of the carry flag Cout to "1" in step S513, the communication level of the I / O port 21 is set as the parity bit BP in accordance with the value of the carry flag Cout in step Sc513. As a result,
The total of the exclusive OR of all 8 bits of the character bit and the exclusive OR of the parity bit are always even (zero).

Next, the IC card 20 performs step Sc5.
In step 14, the value of the register BR is set in the register R1, and this is set in the clock CL in step Sc515.
Decrement in synchronism with K, and determine in step Sc516 whether the decrement result is zero,
If “No”, it indicates that the progress status of the transmission has not reached the rear end timing t ₁₀ of the parity bit in FIG. 2, so the IC card 20 returns the procedure to step Sc515 again, and sets the value of the register R1. Decrement as the transmission progresses. On the other hand, the determination result is “Yes”
If so, the IC card 20 executes step Sc517.
Corresponding to, the communication level of the I / O port 21 is set to the high level because of the stop bit SP.

Then, the IC card 20 performs step Sc.
In step 518, the value of the register BR is set in the register R1 again, and in step Sc519, it is decremented in synchronization with the clock CLK, and then in step Sc52.
At 0, it is determined whether or not the decrement result is zero. This determination is performed in order to secure the stop bit SP whose communication level is the High level for the time indicated by the value of the register BR. Therefore, step S
If the determination result of c520 is “No”, it means that the progress status of the transmission has not reached the rear end timing t ₁₁ of the stop bit SP in FIG.
0 returns the procedure to step Sc519 again, and decrements the value of the register R1 according to the progress of transmission. On the other hand, if the determination result is “Yes”, the IC card 2
0 ends the data transmission process for 1 byte, and if the process is related to Sc5 in FIG. 7, the next procedure is step Sc6, and the process is S in FIG.
If it is related to c11, the next procedure is step S8 in FIG.

As described above, in the data transmission process for one byte shown in FIGS. 8 and 9, one byte of data to be transmitted is serially bit by bit at intervals based on the value of the timer counter TC. , To the external processing device 10. Then, by performing such processing on all of the bytes to be transmitted by the transmission processing shown in FIG.
Will be sent to.

According to the IC card system according to such an embodiment, the IC card 20 transmits the specific data which is preliminarily arranged before the data is exchanged between the external processing device 10 and the IC card 20. To receive. If the data is special pre-arranged data, it is relatively easy to detect the transmission rate from the transmission pattern regardless of the transmission rate of the data. Since the IC card 20 transmits and receives data thereafter at the detected transmission speed, it becomes possible to communicate without distinguishing a plurality of external processing devices.

3: Modified Example In the IC card system according to the above-described embodiment, the IC is transferred from the external processing device 10 before the data is transferred.
Although the specific data transmitted to the card 20 is [00] _H , the present application is not limited to this. Further, in such an IC card system, the external processing device 10 and the IC card 20
Although the communication protocol with the serial standard is as shown in FIG. 2A, the present application is not limited to this. In short, in the communication protocol, data that can detect the data transmission rate is arranged in advance, the IC card receives the data before the data is exchanged, and the transmission rate is detected during the reception. For subsequent data transmission, it suffices to carry out at the detected transmission rate.

Further, in the IC card system according to the above embodiment, the data transmission rate per bit set in the register BR is not limited, but the data transmission rates are generally 9600 bps and 19200 bps.
s, 38400bps ……. Therefore, in the above-described embodiment, after the timer counter TC is set, a process of resetting the value of the timer counter TC to a value corresponding to the closest transmission speed among the standard transmission speeds may be added.

Further, in the above embodiment, the increment process or the decrement process of the register or the counter indicating the progress of the data transmission is executed in synchronization with the clock CLK by the timer 25, and the other processes are executed. The time required for processing was ideally set to zero. However, in actuality, other processes are also executed depending on the clock CLK to some extent. Therefore, if the frequency of the clock CLK is sufficiently higher than the data transmission rate, the time spent for each of the other processes can be ignored, but if not,
It is desirable to correct the value indicating the time set in the registers R1 and R3 in consideration of the time spent in other processes.

[0058]

As described above, according to the present invention, I
Since the C card can communicate with each other without distinguishing a plurality of external processing devices, it is possible to perform data transmission with the external processing devices at an optimum transmission speed according to the external processing device and the environment. In addition, even if the external processing device is improved, it becomes possible for the user to perform data transmission at the optimum transmission speed without particular awareness.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an IC card system according to an embodiment of the present invention.

FIG. 2A is a diagram for explaining a communication protocol of the IC card system, and FIG. 2B is a diagram for explaining various timings of the IC card system.

FIG. 3 is a flowchart showing a main routine viewed from the IC card side of the IC card system.

FIG. 4 is a flowchart showing an operation of a transmission rate adjusting process in the main routine.

FIG. 5 is a flowchart showing an operation of a reception process in the main routine.

FIG. 6 is a flowchart showing an operation of a data receiving process for one byte in the receiving process.

FIG. 7 is a flowchart showing an operation of transmission processing in the main routine.

FIG. 8 is a flowchart showing an operation of data transmission processing for 1 byte in the transmission processing.

FIG. 9 is a flowchart showing an operation of data transmission processing for 1 byte in the transmission processing.

FIG. 10 is a register R in the IC card system
It is a figure for demonstrating operation | movement of 2.

[Explanation of symbols]

 10 ... External processing device, 20 ... IC card, 21 ... I / O port, 22 ... CPU, 23 ... RAM, 24 ... ROM

Claims (6)

[Claims] 1. An IC card system for transmitting data between an IC card and an external processing device, wherein when the IC card receives specific data prearranged with the external processing device, the specific data is received. An IC card system, comprising: a transmission rate detecting means for detecting the transmission rate of the data; and a transmitting means for transmitting or receiving data at the detected transmission rate. 2. The IC card system according to claim 1, wherein the specific data is a head byte of a format defined by a communication protocol. 3. The invention according to claim 1, wherein the IC
Specific data transmission requesting means for requesting transmission of the specific data to the card, while specific data transmission for transmitting the specific data to the IC card when the external processing device requests to transmit the specific data An IC card system comprising means. 4. The IC card according to claim 1, wherein the transmission rate detecting means detects the transmission rate of the specific data by measuring a time required to receive the specific data. system. 5. The invention according to claim 4, wherein the transmission rate detecting means focuses on the transmission pattern of the specific data, measures the time from the reception start to the reception end of the transmission pattern, and measures the time. Is divided by the number of bits of the specific data to detect as a transmission rate, an IC card system. 6. A data transmission method of an IC card system for transmitting data between an IC card and an external processing device, wherein the IC card receives specific data prearranged with the external processing device. Data of an IC card system, comprising: a step of detecting a transmission rate of the specific data; and a step of causing the IC card to transmit or receive data to or from the external processing device at the detected transmission rate. Transmission method.