JP3418734B2 - Serial data transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface data transfer method using DMA (Direct Memory Access) transfer, and relates to a system in which a host system controls peripheral devices by serial communication in a facsimile machine or the like. The present invention relates to a serial data transfer method.

[0002]

2. Description of the Related Art Conventionally, many serial data transfers using DMA transfer are known as disclosed in Japanese Patent Laid-Open No. 2-73445. When data transfer between a memory and a peripheral device is performed by serial data transfer using such DMA transfer, parallel data from the memory is converted into serial data and transferred to the peripheral device, and conversely serial data from the peripheral device is transferred. A shift register is provided to convert the data into parallel data and transfer the data to the memory.
This shift register is provided for each serial port to which the peripheral device is connected, and DMA transfer is used for data transfer between the memory and the shift register.

[0003]

However, in such a conventional serial interface, in order to realize a plurality of serial ports for, for example, a motor drive unit and an operation unit in a facsimile machine, a shift register is serially connected. There is a problem that the number of ports must be provided, the circuit scale increases, and the cost increases.

Further, in order to realize a serial port having a transfer data width that varies depending on the type of peripheral device, it is necessary to equip the same number of shift registers as the number of serial ports, which increases the circuit scale. There was a problem that the cost would be high.

Similarly, in order to realize the serial ports having different transfer clocks in order to match the operating speed of the peripheral device, it is necessary to equip the same number of shift registers as the serial ports, which increases the circuit scale. There was a problem that the cost would be high.

Therefore, the present invention has been made to solve such a problem, and an object thereof is to provide a serial data transfer method capable of realizing a plurality of serial ports with one shift register. To do.

It is another object of the present invention to realize a serial data transfer method capable of realizing serial ports having different transfer data widths with a single shift register.

It is another object of the present invention to realize a serial data transfer method capable of realizing serial ports having different transfer speeds with a single shift register.

[0009]

According to a first aspect of the present invention, there is provided one shift register shared by serial ports for each peripheral device, and data transfer between the memory and the shift register is centrally performed by DMA transfer. A serial data transfer method that does not involve a processing device, and has a counter that counts a fixed period in synchronization with a predetermined synchronization signal, and a plurality of DMA transfer addresses corresponding to each serial port can be timed by this count value. It is generated by division, and serial transfer of a plurality of channels is performed using the same shift register in the fixed period.

Further, in the invention described in claim 2, the transfer data width of the DMA transfer is changed according to the count value of the counter, and serial transfer having different transfer data widths is performed by using the same shift register in the fixed period. It is the one.

According to a third aspect of the present invention, the transfer clock is changed according to the count value of the counter, and serial transfer having different transfer rates is performed using the same shift register during the certain period. .

On the other hand, the invention according to claim 4 has a transfer request setting means which is set by a transfer request from the central processing unit and is reset after the transfer is completed. The same DMA address is generated a plurality of times, the central processing unit monitors the setting state of the transfer request setting means, and updates the data in the memory after the transfer is completed so that each serial port can be driven a plurality of times during the certain period. It is the one.

Further, in the invention described in claim 5, the central processing unit has a transfer byte number setting means for setting the transfer byte number, and DM is set according to the count value of the counter.
A transfer address is changed, and when one transfer is completed, the value of the transfer byte number setting means is subtracted, a plurality of DMA transfer addresses are generated in the certain period, and the value of the transfer byte number setting means becomes zero. Until that time, DMA transfer is performed.

[0014]

According to the method of the present invention, the shift register is time-divided by the count value of the main scanning counter which counts one scan in synchronization with a predetermined synchronizing signal, for example, a main scanning synchronizing signal of a facsimile machine or the like. Therefore, one shift register can realize a plurality of serial ports.

Further, according to the method of claim 2,
Since the transfer data width of the DMA transfer is changed according to the count value of the counter, serial ports having different transfer data widths can be realized by one shift register.

Further, according to the method of claim 3, since the transfer clock is changed according to the count value of the counter, serial ports having different transfer speeds can be realized by one shift register.

On the other hand, according to the method of claim 4, by resetting the transfer request setting means set by the central processing unit after the end of the transfer, the central processing unit detects the end of the transfer and transfers the transfer data in the memory. Can be updated, so that serial transfer can be performed a plurality of times for each channel during the fixed period counted by the counter.

According to the method of the fifth aspect, the central processing unit sets the number of bytes to be transferred in a fixed period in the transfer byte number setting means, so that the central processing unit can be interposed thereafter. Since the transfer of the set number of bytes is performed without a large amount, a large amount of serial transfer can be performed without increasing the software load on the central processing unit.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing components for realizing a serial data transfer method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an internal configuration of the serial input / output device (hereinafter abbreviated as SIO). .

In FIG. 1, reference numeral 1 is a central processing unit (hereinafter,
It is abbreviated as CPU), has a ROM (Read Only Memory) inside, and controls, for example, the entire facsimile apparatus according to a system program stored in this ROM.

Reference numeral 2 denotes a DMA controller, which is a CPU 1
The data transfer between the shift register in the SIO 3 and the RAM (random access memory) 5 is controlled without using the SIO 3, and addresses ADD0 to ADD1 from the SIO 3 are controlled.
5 (16 bits) is output to the address bus 7 of the system. Further, the DMA controller 2 outputs a DMA request to the CPU 1, and the CPU 1 responds to the DMA request.
Input the DMA acknowledge output from.

The SIO 3 has, for example, a shift register having a width of 32 bits (4 bytes), converts parallel data DMA-transferred from the RAM 5 into serial data via the shift register, and outputs the serial data to the peripheral device 8. ,
The serial data input from the peripheral device 8 is converted into parallel data via the shift register and DMA-transferred to the RAM 5. The internal configuration of the SIO 3 will be described later in detail with reference to FIG.

The main scanning counter 4 counts a reference clock input from the outside to generate a main scanning synchronizing signal,
The count value at this time is used as the main scan counter value and SIO3
Output to. This main scanning synchronization signal is the same as the main scanning synchronization signal used for image reading and image recording in a facsimile machine. In the present embodiment, this main scanning synchronization signal is generated in the main scanning counter 4. It is also possible to use the main scanning synchronization signal used for image reading and image recording.

The RAM 5 serves as a work area used by the system program and a storage area for the system program to access serial transfer data. This RAM5
Output enable terminal OE (negative logic) of
The read signal RDB (negative logic) from the PU1 and the memory read signal MEMRDB (negative logic) from the DMA controller 2 are given through the AND gate (OR gate of negative logic) 5a, and the write enable terminal WE (negative logic). ) Is a write signal WRB (negative logic) from the CPU 1.
And a memory write signal MEM from the DMA controller 2
WRB (negative logic) is applied through an AND gate (negative logic OR gate) 5b. Also, this RAM5
It is connected to the CPU 1 and SIO 3 via the data bus 6, and also to the CPU 1 and DMA via the address bus 7.
It is connected to the controller 2.

As shown in FIG. 2, the SIO 3 includes a timing controller 31, a clock generator 32, a DMA address generator 33, a PS (parallel → serial) / SP (serial → parallel) shift register 34, and a transfer byte number. It comprises a setting register 35, a DREQ generator 36, and a transfer request register 37.

The timing control unit 31 controls the generation timing of the DMA transfer address, and the DMA address generation unit 33 controls the DMA address A corresponding to the main scanning counter value.
Generate DD0 to ADD15. Similarly, the generation timing of the DMA request is controlled, and the DREQ (DMA request) generation unit 36 generates the DMA request DREQ. In addition, the same signal lines SIOSCK and SIOS
Drive channel identification signals SIOSEL0-n for the peripheral device 8 to identify which channel of serial I / O mixed on ID and SIOSOD is driven are generated. Further, transfer data width designation signals DMA1BT to DMAnB for designating the transfer data width to the DMA controller 2
T is generated (corresponding to claim 2). Further, the timing for resetting the transfer request flag of the transfer request register 37 is generated (corresponding to claim 4). Further, the timing for decrementing the transfer byte number setting register 35 is generated (corresponding to claim 5).

The clock generator 32 generates a serial transfer clock. Further, since different transfer clocks are generated corresponding to the count value of the main scanning counter 4, the transfer clock is changed by a signal from the timing control section 31 (corresponding to claim 3).

The DMA address generation unit 33 executes the DMA at the address generation timing from the timing control unit 31.
Addresses ADD0 to ADD15 and a memory read / write signal MEMRW are generated. When all bits of serial data are received, the above DMA addresses ADD0 to ADD
15 and the memory read / write signal MEMRW are switched.

The shift register 34 includes a clock generator 3
With the shift clock from 2, the transfer data from the RAM 5 is converted from parallel to serial, and the obtained serial data SIOSOD is sent to the peripheral device 8 together with the shift clock SIOSCK, and the serial input data SI
Convert OSID to serial / parallel. Data is read from the shift register 34 by the read signal SIORDB from the DMA controller 2 and written by the write signal SIOWRB.

The transfer byte number setting register 35 is
The number of transfer bytes set by 1 is decremented by a signal from the timing control unit 31, and a DMA request generation request signal is generated in the DREQ generation unit 36 until it counts up (becomes zero) (corresponding to claim 5).

The DREQ generation unit 36 generates a DMA request DREQ to the DMA controller 2 at the DREQ generation timing from the timing control unit 31. In addition, the read signal SIORD from the DMA controller 2
B, DMA request D by write signal SIOWRB
Reset REQ. Furthermore, the timing control unit 31
Transfer data width designation signals DMA1BT to DMAnB from
The read signal SIORD depends on the transfer data width of T.
B, the write signal SIOWRB is counted, and the DMA request DREQ is reset (corresponding to claim 2). Further, a DMA request DREQ is generated by a DMA request generation request signal from the transfer byte number setting register 35 (corresponding to claim 5).

The transfer request register 37 sends a DMA to the DREQ generator 36 according to the transfer request flag set by the CPU 1.
The generation request signal of the request DREQ is output, and after the transfer is completed, the signal is reset by the signal from the timing control unit 31. The CPU 1 can poll the register 37 and update the transfer data in the RAM 5 if the transfer request flag is reset (corresponding to claim 4).

The first embodiment of the serial data transfer method according to the present invention will be described below.

FIG. 3 is an operation flowchart of the SIO 3 in the first embodiment, and FIG. 4 is an operation flowchart of the DMA controller 2. Further, FIG. 5 is a timing chart of the input / output signals of each part in the first embodiment. In FIG. 5, when the main scanning counter 4 is 00h (h indicates hexadecimal notation), SIO channel 0 of serial I / O is shown.
When the main scanning counter 4 is 01h (having the transmission data buffer at the address XX00h and the reception data buffer at the address XX01h) is driven, the serial I / O
SIO channel 1 (having a transmission data buffer at address XX02h and a reception data buffer at address XX03h) is driven and the main scan counter 4 is 02h, SIO channel 2 of serial I / O (address XX04h
A transmit data buffer, and a receive data buffer at address XX05h) are driven, and three serial I / Os are used as a transfer clock, an input / output data line, and a shift register 3.
4 shows that 4 is used by time division.

Now, when the system starts up, SIO3
Executes processing according to the flowchart of FIG. First,
When the generation timing of the DMA address corresponding to the value of the main scanning counter 4 comes (decision 101), the DMA address corresponding to the main scanning counter value (“00h” in the example of FIG. 5) becomes the transmission data buffer (FIG. 5). In the example, "XX00
h ") and at the same time, the memory read / write signal ME
The MRW is read (MEMRW is "Hi" in FIG. 5) (process 102). Next, when the DMA request generation timing in the memory → shift register direction comes (decision 10
3) Enable the DMA request DREQ (process 104).

When the DMA controller 2 receives the above-mentioned DMA request, the DMA controller 2 performs processing such as priority comparison with other DMA channels, and then executes the processing of this DMA according to the flowchart of FIG. When the execution of the DMA is started in FIG. 4, when the memory read / write signal MEMRW is read (MEMRW is “Hi” in FIG. 5), the SIO
The addresses ADD0 to ADD15 from 3 are output to the address bus 7 (decision 201 → process 202). Next, RA
A memory read signal MEMRDB is generated for M5, transfer data is output to the data bus 6, and SIO
Register write signal SI to the shift register 34 of 3
OWRB is generated, and DMA transfer from memory to shift register is performed (process 203).

SIO3 is a register write signal SIOW
The RB confirms the end of the DMA transfer (decision 105),
The DMA request DREQ is disabled (process 106). After that, a transfer clock is generated and serial transfer is performed (process 107). In FIG. 5, SIOSCK is a transfer clock, SIOSOD is output data, and SIOSID.
Indicates input data. In FIG. 5, as output data SIOSOD, "00000000", "010"
Input data S for "00000" and "00100000"
As the IOS ID, "10000000", "1100"
"0000" and "10100000" are shown as an example.

When the serial transfer is completed, the DMA address is changed to the reception data buffer address ("XX" in the example of FIG. 5).
01h "), and the memory read / write signal ME
The MRW is switched to write (MEMRW is "Low" in FIG. 5) (process 108).

When the DMA request generation timing in the shift register → memory direction comes, the DMA request DRE
Q is enabled (decision 109 → process 110).

The DMA controller 2 executes the processing according to the flowchart of FIG. 4 similarly to the above. That is,
When the memory read / write signal MEMRW is write (MEMRW is “Low” in FIG. 5), the address from the SIO 3 is output to the address bus 7 (decision 201 → process 2).
04). Next, the register read signal SIORDB is generated for the shift register 34 of the SIO 3, the transfer data is output to the data bus 6, and the memory write signal MEMWRB is generated for the RAM 5 to perform the shift register → memory DMA transfer. (Process 205).

In the same manner as above, the SIO 3 confirms the end of the DMA transfer by the register read signal SIORDB,
The DMA request DREQ is disabled (process 112). Then, the process returns to the first determination 101 and the series of processes described above is repeated.

That is, when the main scanning counter 4 is 00h, the SIO channel 0 having the transmission data buffer at the address XX00h and the reception data buffer at the address XX01h is driven, and when the main scanning counter 4 is 01h,
Send data buffer at address XX02h, address X
SIO channel 1 with receive data buffer in X03h
Is driven and the main scanning counter 4 is 02h, the transmission data buffer is stored in the address XX04h and the address XX05.
The SIO channel 2 having the receive data buffer in h is driven.

As described above, since the shift register 34 is used by being time-divided by the count value of the main scanning counter 4, one shift register 34 can realize a plurality of serial ports. As a result, the circuit scale can be reduced and the cost can be reduced.

Next, a second embodiment of the serial data transfer method according to the present invention will be described.

FIG. 6 is an operation flowchart of the SIO 3 in the second embodiment, and FIG. 7 is an operation flowchart of the DMA controller 2. In addition, FIG. 8 is a timing chart of input / output signals of each part in the second embodiment. In FIG. 8, when the main scanning counter 4 is 00h, the SIO channel 0 (address XX0) of 24-bit serial I / O is shown.
Transmission data buffer at 0h to XX02h, address XX
When the reception data buffer is driven in 03h to XX05h and the main scanning counter 4 is 01h in the same manner, 16-bit serial I / O SIO channel 1 (address XX).
Send data buffer, address X in 06h to XX07h
X08h to XX09h are driven), and two serial I / Os having different transfer data widths are driven by the transfer clock, the input / output data line, and the shift register 3.
4 shows that 4 is used by time division.

When the system is started up, SIO3 is set to FIG.
The process is executed according to the flowchart of. First, when the generation timing of the DMA address corresponding to the value of the main scanning counter 4 comes (decision 301), it corresponds to the counter value (“00h” in the example of FIG. 8) and becomes the transmission data buffer D.
The MA address (“XX00h” in the example of FIG. 8) is generated, at the same time, the memory read / write signal MEMRW is read (MEMRW is “Hi” in FIG. 8), and the signal DMA3BT indicating 3-byte transfer is enabled (Processing). Thirty
2). Next, when the DMA request generation timing in the memory → shift register direction comes (decision 303), the DMA
Enable the request DREQ (process 30)
4).

When the DMA controller 2 receives the above DMA request, it performs processing such as comparison of priorities with other DMA channels, and then executes this DMA processing according to the flowchart of FIG. When DMA execution is started in FIG. 7, when the memory read / write signal MEMRW is read (MEMRW is “Hi” in FIG. 8), the number of DMA transfer bytes (transfer data width) based on the signal DMA3BT indicating 3-byte transfer. (Judgment 402), the process branches to process 403, and addresses ADD0-A from SIO3
DD15 is output to the address bus 7. Next, RAM5
A read signal MEMRDB is generated to output the transfer data to the data bus 6, and a register write signal SIORDB is generated to the shift register 34 of SIO3 to perform a DMA transfer from memory to shift register (process 404). Signal DMA3BT indicating 3-byte transfer
Is enabled, the address is incremented (process 405), and after determining 406 whether or not the DMA is completed three times, the process returns to process 403 and the incremented address is output to the address bus 7. This operation is repeated three times to complete the 3-byte DMA transfer.

SIO3 is a register write signal S for three times.
The IOWRB confirms the end of the 3-byte DMA (decisions 305 and 306), and disables the DMA request DREQ (process 309). After that, the transfer clock SIOSCK is generated, and the output data SIOSOD and the input data SIOSID are serially transferred (process 31).
0). In FIG. 8, output data SIOSOD and input data S
As in the above-described embodiment, the IOS ID uses arbitrary data.

When the serial transfer is completed, the DMA address is changed to the reception data buffer address ("XX" in the example of FIG. 8).
03h "), memory read / write signal ME
The MRW is switched to write (MEMRW is "Low" in FIG. 8) (process 311).

When the DMA request generation timing in the shift register → memory direction comes, the DMA request DRE
Q is enabled (decision 312 → process 313).

The DMA controller 2 executes the processing according to the flowchart of FIG. 7 as described above. That is,
When the memory read / write signal MEMRW is write (MEMRW is “Low” in FIG. 8) (decision 401), the number of DMA transfer bytes is determined based on the signal DMA3BT indicating 3-byte transfer (decision 415), and the process 416 is performed. It branches and outputs the addresses ADD0 to ADD15 from SIO3 to the address bus 7. Next, a register read signal SIORDB is generated for the shift register 34 of the SIO 3 to output the transfer data to the data bus 6, and
A memory write signal MEMWRB is generated for the RAM 5 and a DMA transfer from the shift register to the memory is performed (process 417). Since the signal DMA3BT indicating the 3-byte transfer is enabled, the address is incremented (process 418), and after the determination 419 as to whether or not the DMA is completed three times, the process returns to the process 416 and the incremented address is output to the address bus 7. Performs DMA transfer from shift register to memory. This operation is repeated three times to complete the 3-byte DMA transfer.

Similarly, the SIO 3 confirms the end of the DMA transfer by the register read signal SIORDB three times,
The DMA request DREQ is disabled (decision 314 → decision 315 → process 318). Then, the process returns to the first determination 301, and the series of processes described above is repeated.

That is, when the main scanning counter 4 is 00h, a 24-bit (3-byte) serial I / O having a transmission data buffer at addresses XX00h to XX02h and a reception data buffer at addresses XX03h to XX05h.
SIO channel 0 of the main scanning counter 4 is driven by 01
When it is h, the SIO channel 1 of 16-bit (2-byte) serial I / O having the transmission data buffer at the addresses XX06h to XX07h and the reception data buffer at the addresses XX08h to XX09h is driven.

As described above, since the serial ports having different transfer data widths can be realized by one shift register 34, in addition to the effect of the first embodiment, the circuit scale can be further reduced and the cost can be reduced. Can be achieved.

Next, a third embodiment of the serial data transfer method according to the present invention will be described.

FIG. 9 is an operation flowchart of the SIO 3 in the third embodiment, and FIG. 10 is an operation flowchart of the DMA controller 2. In addition, FIG. 11 is a timing chart of input / output signals of each part in the third embodiment. In FIG. 11, when the main scanning counter 4 is 00h,
Low-speed serial I / O SIO channel 0 (address XX
When the send data buffer is driven at 00h and the receive data buffer is at address XX01h, and when the main scanning counter 4 is 01h, the SIO channel 1 of the high-speed serial I / O (send data buffer at address XX02h,
The address XX03h has a receive data buffer), and two serial I / Os having different transfer rates use the transfer clock, the input / output data line, and the shift register 34 in a time-division manner.

When the system is started up, SIO3 is set in FIG.
The process is executed according to the flowchart of. First, when the generation timing of the DMA address corresponding to the value of the main scanning counter 4 comes (decision 501), the DMA address corresponding to the counter value (“00h” in the example of FIG. 11) becomes the transmission data buffer (FIG. 11). In this example, "XX00h") is generated, and at the same time, the memory read / write signal MEMRW is read (MEMRW is "Hi" in FIG. 11) (process 5).
02). Next, when the DMA request generation timing in the memory → shift register direction comes (decision 503), DM
Enable A-request DREQ (process 50)
4).

When the DMA controller 2 receives the above DMA request, it performs processing such as comparison of priorities with other DMA channels, and then executes the processing of this DMA as shown in FIG.
Execute according to the flowchart in. When the DMA execution is started in FIG. 10, the memory read / write signal MEMR
When W is a lead (MEMRW is “Hi” in FIG. 11),
Addresses ADD0 to ADD15 from SIO3 are output to address bus 7 (decision 601 → process 602). Next, the memory read signal MEMRDB is generated for the RAM 5, the transfer data is output to the data bus 6, and the register write signal SIOWRB is generated for the shift register 34 of the SIO 3 to perform the DMA transfer from the memory to the shift register ( Process 603).

SIO3 is a register write signal SIOW.
Confirm the end of DMA by RB, DMA request D
Disable REQ (decision 505 → process 50)
6). After that, the count value of the main scanning counter 4 (see FIG.
00h), a transfer clock (low-speed clock SIOSCK0 in FIG. 11) is selected (decision 507 → process 508), a transfer clock SIOSCK0 is generated, and output data SIOSOD and input data SIOSID are serially transferred (process 511). ).

When the serial transfer is completed, the DMA address is set to the reception data buffer address ("X" in the example of FIG. 11).
X01h "), and the memory read / write signal M
The EMRW is switched to write (MEMRW is “Low” in FIG. 8) (process 512).

When a DMA request generation timing in the shift register → memory direction comes, a DMA request DRE
Q is enabled (decision 513 → process 514).

The DMA controller 2 executes the processing according to the flow chart of FIG. 10 similarly to the above. That is, when the memory read / write signal MEMRW is write (MEMRW is “Low” in FIG. 11) (determination 60
1), the addresses ADD0 to ADD15 from SIO3 are output to the address bus 7 (process 604). Next, SI
Register read signal S to the O3 shift register 34
IORDB is generated, the transfer data is output to the data bus 6, and the memory write signal M is sent to the RAM 5.
EMWRB generated, shift register → memory DMA
Transfer is performed (process 605).

Similarly, the SIO 3 confirms the end of the DMA transfer by the register read signal SIORDB,
Disable request DREQ (decision 51
5 → Process 516). Then, returning to the first decision 501,
The series of processes described above is repeated.

That is, when the main scanning counter 4 is 00h, the SIO channel 0 of the low-speed serial I / O having the transmission data buffer at the address XX00h and the reception data buffer at the address XX01h (transfer clock S in FIG. 11).
IOSCK0) is driven and the main scanning counter 4 is set to 0 in the same manner.
At 1h, the SIO channel 1 (transfer clock SIOSCK0 in FIG. 11) of the high-speed serial I / O having the transmission data buffer at the address XX02h and the reception data buffer at the address XX03h is driven.

As described above, since the serial ports having different transfer rates can be realized by one shift register 34, in addition to the effect of the first embodiment, the circuit scale can be further reduced and the cost can be reduced. Can be planned.

Next, a fourth embodiment of the serial data transfer method according to the present invention will be described.

FIG. 12 is an operation flowchart of the SIO 3 in the fourth embodiment, and FIG. 13 is an operation flowchart of the DMA controller 2. In addition, FIG. 14 is a timing chart of input / output signals of each part in the fourth embodiment. In FIG. 14, the main scanning counter 4 has 00h, 03
When h, ..., SIO channel 0 of serial I / O
When the main scanning counter 4 is 01h and 04h (the transmission data buffer is located at the address XX00h and the reception data buffer is located at the address XX01h), the SIO channel 1 of the serial I / O (the transmission data buffer at the address XX02h, (The reception data buffer is provided at the address XX03h), and the main scanning counter 4 operates at 02h,
When 05h, SIO channel 2 of serial I / O (transmission data buffer at address XX04h, address XX
05h has a reception data buffer), and three serial I / Os transfer clock, input / output data line,
It shows that the shift register 34 is used in a time division manner.

When the system is started up, SIO3 is set in FIG.
The process is executed according to the flowchart of 2. First, when the generation timing of the DMA address corresponding to the value of the main scanning counter 4 comes and the request flag of the transfer request register 37 is "1", it corresponds to the main scanning counter value ("00h" in the example of FIG. 14). And becomes a transmission data buffer DM
The A address (“XX00h” in the example of FIG. 14) is generated, and at the same time, the memory read / write signal MEMRW is read (MEMRW is “Hi” in FIG. 14) (determination 70).
1 → judgment 702 → process 703). Next, when the DMA request generation timing in the memory → shift register direction comes (decision 704), the DMA request DREQ is enabled (process 705).

When the DMA controller 2 receives the above DMA request, it performs processing such as priority comparison with other DMA channels, and then executes the processing of this DMA as shown in FIG.
Execute according to the flowchart in. When the DMA execution is started in FIG. 13, the memory read / write signal MEMR
When W is a lead (MEMRW is “Hi” in FIG. 14),
Addresses ADD0 to ADD15 from SIO3 are output to address bus 7 (decision 801 → process 802). Next, the memory read signal MEMRDB is generated for the RAM 5, the transfer data is output to the data bus 6, and the register write signal SIOWRB is generated for the shift register 34 of the SIO 3 to perform the DMA transfer from the memory to the shift register ( Process 803).

SIO3 is a register write signal SIOW
The RB confirms the end of the DMA transfer, and disables the DMA request DREQ (decision 706 → process 707). After that, the transfer clock SIOSCK is generated, and the output data SIOSOD and the input data SIOSID are generated.
Is serially transferred (process 708).

When the serial transfer is completed, the DMA address is changed to the reception data buffer address ("X" in the example of FIG. 14).
X01h "), and the memory read / write signal M
Write EMRW (in FIG. 14, MEMRW is “Lo”
w ″) (process 709).

When the DMA request generation timing in the shift register → memory direction comes, the DMA request DRE
Q is enabled (decision 710 → process 711).

The DMA controller 2 executes the processing according to the flow chart of FIG. 13 similarly to the above. That is, when the memory read / write signal MEMRW is write (MEMRW is “Low” in FIG. 14) (determination 80
1), the addresses ADD0 to ADD15 from SIO3 are output to the address bus 7 (process 804). Next, SI
Register read signal S to the O3 shift register 34
IORDB is generated, the transfer data is output to the data bus 6, and the memory write signal M is sent to the RAM 5.
EMWRB generated, shift register → memory DMA
Transfer is performed (process 805).

Similarly, the SIO 3 confirms the end of the DMA transfer by the register read signal SIORDB,
While disabling the request DREQ,
The request flag of the transfer request register 37 is reset (decision 712 → process 713). Then, the process returns to the first determination 701, and the series of processes described above is repeated. The CPU 1 monitors the request flag of the transfer request register 37 by polling. When it detects that the request flag has been reset, it confirms the end of transfer and updates the transfer data in the RAM 5.

That is, the main scanning counter 4 sets 00h, 0
3h, ..., SIO channel 0 having a transmission data buffer at address XX00h and a reception data buffer at address XX01h is driven, and when the main scanning counter 4 is 01h, 04h, transmission data buffer at address XX02h, The SIO channel 1 having the receive data buffer at the address XX03h is driven, and the main scan counter 4
Is 02h and 05h, the SIO channel 2 having the transmission data buffer at the address XX04h and the reception data buffer at the address XX05h is driven.

By the way, in the first to third embodiments, only one data transfer was possible in one channel during one scanning, but in this embodiment, each data is formed by time division. Since the SIO channel can be driven multiple times during one scan, in addition to the effect of the first embodiment, serial transfer can be performed multiple times for each channel during one scan, and the amount of data transfer can be increased. .

Next explained is a fifth embodiment of serial data transfer method according to the invention.

FIG. 15 is an operation flowchart of the SIO 3 in the fifth embodiment, and FIG. 16 is an operation flowchart of the DMA controller 2. In addition, FIG. 17 is a timing chart of the input / output signals of each part in the fifth embodiment. In FIG. 17, the main scanning counter 4 is 00h to 05h.
, The serial I / O SIO channel 0 (addresses XX00h, XX02h, XX04h, XX06h, X
Send data buffers at X08h and XX0ah, addresses XX01h, XX03h, XX05h, XX07h, X
X09h and XX0bh have reception data buffers).

When the system is started up, SIO3 is set in FIG.
The process is executed according to the flowchart of FIG. First, when the generation timing of the DMA address corresponding to the value of the main scanning counter 4 comes and the transfer byte number setting register 35 is not 0, the main scanning counter value (“00” in the example of FIG. 17).
corresponding to "h"), a DMA address ("XX00h" in the example of FIG. 17) that serves as a transmission data buffer is generated, and at the same time, the memory read / write signal MEMRW is read (FIG. 1).
In step 7, MEMRW is set to “Hi”) (decision 901 → decision 902 → process 903). Next, when the DMA request generation timing in the memory → shift register direction comes (decision 904), the DMA request DREQ is enabled (process 905).

When the DMA controller 2 receives the above DMA request, it performs processing such as priority comparison with other DMA channels, and then executes the processing of this DMA as shown in FIG.
Execute according to the flowchart in. When the DMA execution is started in FIG. 16, the memory read / write signal MEMR
When W is the lead (MEMRW is “Hi” in FIG. 17),
Addresses ADD0 to ADD15 from SIO3 are output to address bus 7 (determination 1001 → processing 1002).
Next, the memory read signal MEMRDB is generated for the RAM 5, the transfer data is output to the data bus 6, and the register write signal SIOWRB is generated for the shift register 34 of the SIO 3 to perform the DMA transfer from the memory to the shift register ( Process 1003).

SIO3 is a register write signal SIOW.
The RB confirms the end of the DMA transfer, and disables the DMA request DREQ (decision 906 → process 907). After that, the transfer clock SIOSCK is generated, and the output data SIOSOD and the input data SIOSID are generated.
Is serially transferred (process 908).

When the serial transfer is completed, the DMA address is changed to the reception data buffer address ("X" in the example of FIG. 17).
X01h "), and the memory read / write signal M
Write EMRW (MEMRW is "Low" in Figure 17)
(Process 909).

When a DMA request generation timing in the shift register → memory direction comes, a DMA request DRE
Q is enabled (decision 910 → process 911).

The DMA controller 2 executes the processing according to the flow chart of FIG. 15 as described above. That is, when the memory read / write signal MEMRW is a write (MEMRW is “Low” in FIG. 17), the addresses ADD0 to ADD15 from SIO3 are output to the address bus 7 (decision 1001 → process 1004). Next, SIO
Register read signal SI to the shift register 34 of 3
ORDB is generated, the transfer data is output to the data bus 6, and the memory write signal ME is sent to the RAM 5.
MWRB is generated, and DMA transfer from the shift register to the memory is performed (process 1005).

Similarly, the SIO 3 confirms the end of the DMA transfer by the register read signal SIORDB,
Disable request DREQ (decision 91
2 → Process 913). Also, the transfer byte number setting register 3
Decrement 5 and add DMA address ADD
Increment 0 to ADD15. Then, the process returns to the first determination 701, and the series of processes described above is repeated.

That is, the main scanning counter 4 is 00h to 0.
When it is 5h, addresses XX00h, XX02h, XX0
4h, XX06h, XX08h, XX0ah, send data buffers, addresses XX01h, XX03h, XX0.
The SIO channel 0 having the receive data buffers at 5h, XX07h, XX09h, and XX0bh is driven without software intervention by the CPU 1.

By the way, in the fourth embodiment, 1
1 for bulk data transfer on each channel between scans
Since it is necessary to intervene the software by the CPU 1 for each transfer, the load on the CPU 1 increases, but in the present embodiment, a large amount of serial transfer is possible during one scan without causing such a problem. Become.

In each of the above-described embodiments, the counter for counting a fixed period in synchronization with a predetermined synchronization signal is used as a counter in synchronization with a main scanning synchronization signal in a facsimile machine or the like.
Although the main scanning counter 4 that counts between scans is used, the present invention is not limited to this, and a counter of this type used in the system is applied depending on the system to which the present invention is applied. Is.

[0089]

According to the first aspect of the present invention, a central processing unit is provided which is provided with one shift register shared by serial ports for each peripheral device and which transfers data between the memory and the shift register by DMA transfer. This is a serial data transfer method that is performed without intervention, and has a counter that counts a certain period in synchronization with a predetermined synchronization signal, and a plurality of DMAs corresponding to each serial port by this count value.
Since the transfer addresses are generated in a time-sharing manner and the serial transfer of a plurality of channels is performed using the same shift register in the fixed period, a plurality of serial ports can be realized by one shift register, and the circuit scale becomes large. There is an effect that the size can be reduced and the cost can be reduced.

Further, according to the second aspect of the present invention, the transfer data width of the DMA transfer is changed according to the count value of the counter, and the serial transfer having the different transfer data width is performed using the same shift register in the fixed period. As a result, in addition to the effect of claim 1, serial ports having different transfer data widths can be realized by one shift register, and the circuit scale can be further reduced and the cost can be reduced.

According to the invention of claim 3, the transfer clock is changed according to the counter value of the counter,
Since serial transfer with different transfer rates is performed using the same shift register in the fixed period, in addition to the effect of claim 1, a plurality of serial ports with different transfer rates can be realized by one shift register, Further, there is an effect that the circuit scale can be reduced and the cost can be reduced.

On the other hand, according to the invention described in claim 4, there is provided a transfer request setting means which is set by a transfer request from the central processing unit and is reset after the transfer is completed, and the transfer count is set to a fixed period depending on the count value of the counter. The same DMA address is generated a plurality of times, the central processing unit monitors the setting state of the transfer request setting means, and updates the data in the memory after the transfer is completed, so that each serial port is driven a plurality of times within a certain period. Therefore, in addition to the effect of the first aspect, there is an effect that the serial transfer can be performed plural times in each serial port in a certain period, and the data transfer amount can be increased.

According to the invention of claim 5, the central processing unit has a transfer byte number setting means for setting the transfer byte number, and changes the DMA transfer address according to the count value of the counter. When one transfer is completed, the value of the transfer byte number setting means is subtracted, a plurality of DMA transfer addresses are generated in a certain period, and DMA transfer is performed until the value of the transfer byte number setting means becomes zero. Therefore, in addition to the effect of claim 1, there is an effect that a large amount of serial transfer can be performed in a certain period without increasing the load of software by the central processing unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing components that realize a serial data transfer method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of the SIO 3 shown in FIG.

FIG. 3 is an operation flowchart of SIO in the first embodiment.

FIG. 4 is an operation flowchart of the DMA controller according to the first embodiment.

FIG. 5 is a timing chart showing the operation of the first embodiment.

FIG. 6 is an operation flowchart of SIO in the second embodiment.

FIG. 7 is an operation flowchart of the DMA controller according to the second embodiment.

FIG. 8 is a timing chart showing the operation of the second embodiment.

FIG. 9 is an operation flowchart of SIO in the third embodiment.

FIG. 10 is an operation flowchart of the DMA controller according to the third embodiment.

FIG. 11 is a timing chart showing the operation of the third embodiment.

FIG. 12 is an operation flowchart of SIO in the fourth embodiment.

FIG. 13 is an operation flowchart of the DMA controller according to the fourth embodiment.

FIG. 14 is a timing chart showing the operation of the fourth embodiment.

FIG. 15 is an operation flowchart of SIO in the fifth embodiment.

FIG. 16 is an operation flowchart of the DMA controller according to the fifth embodiment.

FIG. 17 is a timing chart showing the operation of the fifth embodiment.

[Explanation of symbols]

1 CPU 2 DMA controller 3 SIO 4 Main scanning counter 5 RAM 6 data bus 7 address bus 8 peripheral devices 31 Timing control unit 32 clock generator 33 DMA address generator 34 shift register 35 Transfer byte number setting register 36 DREQ generator 37 Transfer Request Register

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Claims (5)

(57) [Claims] 1. A shared serial port for each peripheral device
A serial data transfer method in which data is transferred between the memory and the shift register by DMA transfer without using a central processing unit.
And has a counter that counts a fixed period in synchronization with a predetermined synchronization signal, and a plurality of DMA transfer addresses corresponding to each serial port are generated in a time-division manner by this count value. A serial data transfer method characterized in that transfer is performed using the same shift register. 2. The DMA according to the count value of the counter
2. The serial data transfer method according to claim 1, wherein the transfer data width of the transfer is changed, and serial transfer with different transfer data widths is performed using the same shift register during the fixed period. 3. The serial data transfer method according to claim 1, wherein the transfer clock is changed according to the count value of the counter, and serial transfer with different transfer rates is performed using the same shift register during the fixed period. 4. A transfer request setting unit that is set by a transfer request from the central processing unit and is reset after the transfer is completed, and has the same D during the certain period depending on the count value of the counter.
By generating the MA address a plurality of times, the central processing unit monitors the setting state of the transfer request setting means, and updates the data in the memory after the transfer is completed, so that each serial port can be driven a plurality of times during the certain period. The serial data transfer method according to claim 1, characterized in that 5. The transfer byte number setting means for setting the transfer byte number in the central processing unit, the DMA transfer address is changed according to the count value of the counter, and the transfer byte is set when one transfer is completed. 2. The number of the number setting means is subtracted, a plurality of DMA transfer addresses are generated in the fixed period, and the DMA transfer is performed until the value of the transfer byte number setting means becomes zero.
Serial data transfer method described.