JPH06187281A - Microcomputer and data transfer control circuit between data input/output device - Google Patents

Abstract

PURPOSE:To make it possible to perform a data transfer without time loss and load even when plural data input/output devices are connected with a CPU by returning a strobe signal again by looping back the acknowledge signal from a data input/output device by the capacitor and the resistance provided in a timing control circuit. CONSTITUTION:By providing a resistance 1 and a capacitor 2 in a timing control circuit, a means delaying the acknowledge signal ACK from a data input/output device, outputting the signal as a strobe signal STB and returning the acknowledge signal ACK of the second time from the data input/output device is provided. At this point, the data input/output device is the one which has a hand shake signal which is required for a data bus and a data transfer control or the strobe signal STB to be a timing signal transmitting data and the acknowledge signal ACK showing the completion of a reception and performs the input/ output of data. A printer of a centronics specification, etc., conforms to this.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention can be used as an interface circuit between a microcomputer and a data input / output device, and is particularly effective for a device such as a printer having a slow driving speed.

[0002]

2. Description of the Related Art Since a conventional data input / output device has a different processing speed from a CPU, the processing speed has been shifted by an interrupt or DMA or time-division processing has been performed.

[0003]

[Problems to be Solved by the Invention] Conventional interrupt and DM
In A, a time loss is caused by applying a load to the CPU or stopping it. That is, CP
Other processes could not be executed because the side that forms the central functions such as U and DMA was directly controlled. Therefore, as a result of earnest research, even if a plurality of data input / output devices are connected to the CPU, the internal bus can be used even when the circuit part is operating because the control function is controlled by the side that constitutes the local function, and time loss and The purpose is to transfer data without imposing a load on the central part of the CPU or DMA.

[0004]

In order to achieve the above object, the present invention provides a data input / output device (a data input / output device means a data bus and a data transfer control) by providing a resistor and a capacitor in a timing control circuit. A handshake signal required for transmission, that is, a STROBE signal [hereinafter abbreviated as STB] which is a timing signal for transmitting data and a signal ACKNOWLEDGE signal [hereinafter AC
Abbreviated as K], which is a device for inputting / outputting data and corresponds to a printer or the like of the Centronics specification, and also includes those widely used in other circuits such as a parallel interface of a data bus. Means for delaying the acknowledge signal from (1) and outputting it as a strobe signal, and for returning the second acknowledge signal from the data input / output device.

[0005]

The capacitor and the resistor provided in the timing control circuit delays the acknowledge signal from the data input / output device and outputs it as a strobe signal, and returns the second acknowledge signal from the data input / output device.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is classified into a memory section, a counter section, a timing section, a control section, and a transfer data setting section. Hereinafter, a block diagram, a functional description of each unit, an external connection, a control procedure, and a flowchart will be sequentially described with reference to the drawings.

FIG. 1 shows a memory map for explaining the memory section of the present invention. The memory section stores data for transfer to a data input / output device, and the CPU reads and writes the data.

[Outer 1] The location of the CPU in the memory access space is selected by moving the address. In that case, from address 0H to FFF.
The value obtained by adding the offset address to the FH address becomes the memory address for the CPU.

[Outside 2] (0V), and when an offset is set, it is added to the above address.

FIG. 2 is a diagram showing the counter section, and the counter section selects a storage location (address) for sequentially inputting and outputting the data stored in the memory section. The address is counted up by the clock signal generated by the timing control and added up to the address set by the transfer data setting unit. Also, counting is started by the start signal of the interface section, and the count is returned to zero by the reset signal. In FIG. 2, the data stored in the memory is selected by counting up the addresses A0 to A15.

In the data transfer, the timing control section transfers data according to the processing speed of the data input / output device (handshake control) and gives the timing of data selection to the counter section. In the data transfer, the data is output to the data bus in synchronization with the strobe signal (STB), and when the data input / output device receives the data, the acknowledge signal (ACK) is returned to generate the next strobe signal based on the signal. Let That is, the acknowledge signal is looped back and the strobe signal is returned, so that the setting value is repeated while synchronizing. The output of the data transfer will be described in more detail with reference to FIG. 3. When one pulse signal for starting the handshake is input, the data is sent to the data input / output device as a strobe signal (STB), and the data is transmitted. When the input / output device receives the data, it returns an acknowledge signal (ACK) and returns to the gate B. Is a data transfer enable signal, and when this signal is ON, the ACK signal returns to gate A and ST
It is output as a B signal. At this time, the signal is delayed due to the time constant of the resistor 1 and the capacitor 2, and when the exchange of the ACK signal and the STB signal corresponding to the processing delay of the data input / output device is repeated and the number of transfer data becomes the value set by the CPU. Is turned off and the data transfer ends.

The timing control section shown in FIG. 3 is considered as shown in FIG. Further, at the time of data input, the STB signal is output from the data input / output device, so that the timing control unit inputs data in synchronization with the STB signal and the timing is as shown in FIG.

The interface unit is a CP as shown in FIG.
U has each command and each status for controlling the circuit unit of the present invention. The command has a start signal (STR) to start data transfer and a reset signal (CRS) to zero the counter at the end of data transfer, and the status is a transfer signal (BSY) indicating whether or not data transfer is currently in progress. Is prepared. The command is composed of 8-bit registers and is write-only, and the status is also composed of 8-bit registers and is read-only.

[Outside 3] Make a bell and assign a command to address 0H and status to address 1H. When an offset is set, it is added to the above address.

The transfer data setting unit will be described with reference to FIG. 7. The transfer data setting unit converts the number of data to be transferred into a hexadecimal number, and sets the lower 8 bits to the set value 1 and the upper 8 bits to the set value 2. Set to. Setting range is 0H to FFFFH
It is possible up to.

[Outside 4] Value 1 (lower byte) and address 3H are assigned to setting value 2 (upper byte). If you set an offset,
Add to the above address.

The control procedure of the circuit section of the present invention by the CPU will be described in detail below. I) When outputting data to the data input / output device 1. The CPU reads the status of the interface section and confirms that bit0 (BSY) is 0. [Waiting for data transfer circuit] 2. If the circuit of the present invention is not in operation (BSY = 1),
The number of bytes of data to be transmitted is output to the transfer data setting section. [Setting of number of transmission bytes] 3. BI of interface command by CPU
Write 0, 1, 0 to T1 (CRS). [Reset counter (zero clear)]

[Outside 5] Write. [Set data transfer input / output switching to output] 5. BI of interface command by CPU
Write 1 to T0 (STR). [Start of data output to data input / output device] 6. The CPU reads the status of the interface section and confirms that bit0 (BSY) is 1. [End of data transfer] II) When inputting data from the data input / output device 1. The CPU reads the status of the interface section and confirms that bit0 (BSY) is 0. [Waiting for data transfer circuit] 2. If the circuit of the present invention is not in operation (BSY = 1),
The number of bytes of the received data is output to the transfer data setting section. [Setting of number of received bytes] 3. BI of interface command by CPU
Write 1, 1, 0 to T1 (CRS). [Reset counter (zero clear)]

[Outside 6] Write. [Set data transfer input / output switching to input] 5. BI of interface command by CPU
Write 1 to T0 (STR). [Starting data input from the data input / output device] 6. The CPU reads the status of the interface section and confirms that bit0 (BSY) is 1. [End of data transfer] 7. The CPU reads the data from the address 0H to the setting address of the memory.

[0014]

As described above, the data transfer control circuit of the present invention loops back the acknowledge signal and returns the strobe signal again, so that even if a plurality of data input / output devices are connected to the CPU, a time loss occurs. Data can be transferred without increasing the load.

[Brief description of drawings]

FIG. 1 is a memory map illustrating a memory unit of the present invention.

FIG. 2 is a block diagram showing a counter unit.

FIG. 3 is a schematic diagram showing a handshake control circuit.

FIG. 4 is a timing chart when outputting data.

FIG. 5 is a timing chart when inputting data.

FIG. 6 is a word format for circuit control.

FIG. 7 is a word format for limiting transfer data.

FIG. 8 is a connection diagram with the outside.

FIG. 9 is a flowchart when outputting transfer data.

FIG. 10 is a flowchart when inputting transfer data.

FIG. 11 is a data transfer control circuit diagram.

[Explanation of symbols]

 1 resistor 2 capacitor

Front Page Continuation (72) Inventor Takayuki Tamura 30 No. 11 Noue, Teramoto, Itami City, Hyogo Pref.

Claims (2)

[Claims] 1. The same number of data input / output devices as means for automatically transferring data without performing program control by the CPU and performing handshake control on hardware without suspending the CPU. Data transfer control circuit between the adopted microcomputer and data input / output device. 2. The automatic data transfer means according to claim 1, wherein the resistor R and the capacitor C are inserted as an integrating circuit in the acknowledge circuit to delay the acknowledge signal and feed it back to the strobe circuit. A data transfer control circuit between a characteristic microcomputer and a data input / output device.