JPH09190461A - Simulator for verification of polyphase clock input logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time of test pattern correction and simulation without considering delay with a data signal at the time of generating a test pattern. SOLUTION: A compile means 2 compiles an inputted logic circuit model 1 and generates a simulation model 3 and a dividing means 4 divides the simulation model 3 generated by the compile means 2 into modules 5 and 6 by clock. A simulation means 7 executes the simulation of the modules 5 and 6 in parallel through the use of the test pattern 8 and an analyzing means 9 analizes the simulation result of the simulation means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulator for verifying a multi-phase clock input logic circuit, and more particularly to a logic circuit for inputting a multi-phase clock in a computer system including an LSI (Large Scale Integrated Circuit), a PKG (package) and the like. Regarding verification.

[0002]

2. Description of the Related Art Conventionally, in this type of logic detection, a model configuration at the time of simulation as shown in FIG. 6 has been used. That is, the model at the time of simulation is composed of a simulator (including a simulation engine) 50 for executing the simulation and a simulation model 60 in which logic information is described.

The clock pins of the simulation model 60 to which the multi-phase clock is input are respectively connected to the signal line 110 for inputting the clock frequency α and the signal line 120 for inputting the clock frequency β. Also,
The input / output pin of the simulation model 60 is the signal line 11
1, 121 are respectively connected and controlled by the simulator 50.

In the simulation using the above model, as shown in FIG. 5, the model of the logic circuit 41 input to the simulator 50 is compiled by the compiling means 42,
The simulation model 43 (simulation model 60 in FIG. 5) is created.

The simulation means 44 gives a test pattern 45 for verifying the created simulation model 43 to execute a simulation, and the analysis means 46 analyzes the simulation result of the simulation means 44. That is, the analysis means 46 performs timing verification based on the output of each flip-flop in the simulation model 43 and logic verification at the output pin.

When a simulator for generating a clock signal of a single frequency is used for a simulation model using a polyphase clock, a simulator for generating a clock signal of the multiphase from the clock signal of the single frequency is used. There is also a method of arranging for simulation by inserting it between the and the simulation model. This method is disclosed in JP-A-62-1
It is described in detail in Japanese Patent No. 233848.

[0007]

In the above-mentioned conventional simulator, the number of clocks input to the logic circuit is one.
The target is a phase-locked loop circuit, and a flip-flop is operated at the timing of one clock to sample the circuit information of the logic circuit.

In the case of a multi-phase clock, since only one clock frequency and sampling time value can be set, verification of a logic circuit operating at a clock frequency other than the set clock frequency and sampling time value are reset separately. Have to simulate.

Therefore, the test pattern must be created in consideration of a clock other than the frequency currently being simulated, which increases the number of patterns and the number of test pattern creation steps.

Further, in the case of a method of inserting a circuit for generating a multi-phase clock frequency from a clock signal of a single frequency between a simulator and a simulation model, a multi-phase clock signal from a single clock signal generated by the simulator is used. Since the signal is created by the circuit inserted between the simulator and the simulation model, the delay from the simulator to the clock pin of the simulation model causes a delay difference with the data signal, and unnecessary pulses such as spikes are generated. There is a risk of creating it. Therefore, in order to accurately measure the circuit information of the logic circuit, its delay must be taken into consideration when creating the test pattern.

Therefore, an object of the present invention is to solve the above problems, and to reduce the number of times of test pattern modification and simulation without considering the delay between the test pattern and the data signal. It is to provide a simulator for verifying a clock input logic circuit.

[0012]

A multi-phase clock input logic circuit verification simulator according to the present invention is a multi-phase clock input logic circuit verification simulator for performing logic verification of a logic circuit having a multi-phase clock as an input. The logic circuit is provided with a dividing means for dividing the logic circuit into a plurality of modules corresponding to the respective multi-phase clocks, and a means for performing simulations in parallel with each other using the clocks corresponding to the plurality of modules.

In addition to the above-mentioned configuration, another simulator for verifying a multi-phase clock input logic circuit according to the present invention is arranged such that when inputting / outputting a signal between the plurality of modules, the timing of the signal from the output source module is output to the output destination module. It is provided with means for adjusting and controlling with a clock corresponding to the module.

In another simulator for verifying a multi-phase clock input logic circuit according to the present invention, in the above structure, the dividing means is the same partial logic circuit including a flip-flop for inputting each of the multi-phase clocks to the logic circuit. It is configured to be divided into individual modules for each clock.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

When simulating a logic circuit using a multi-phase clock, the simulation model created by compiling the logic circuit model by the compiling means is divided into modules for each clock frequency by the dividing means, and the simulation for each module is simulated. By means of parallel execution.

This makes it possible to reduce the number of times of test pattern modification and simulation without considering the delay between the test pattern and the data signal.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure, a simulator for verifying a multi-phase clock input logic circuit according to an embodiment of the present invention comprises a compiling means 2, a dividing means 4, a simulating means 7, and an analyzing means 9.

The compiling means 2 compiles the input logic circuit model 1 to create a simulation model 3, and the dividing means 4 composes the simulation model 3 created by the compiling means 2 into modules 5 and 6 for each clock.
Divided into

The simulation means 7 performs the simulation of these modules 5 and 6 in parallel using the test pattern 8, and the analysis means 9 performs the simulation means 7.
Analyze the simulation results of.

FIG. 2 is a diagram showing a model configuration during simulation according to an embodiment of the present invention. In the figure, one embodiment of the present invention uses the same number of simulation engines 12 and 13 as the number of clock signal lines of different frequencies, and hereinafter, a simulation using a two-phase clock having two clock signals of different frequencies. Describe the model.

The simulation model according to one embodiment of the present invention comprises a simulator 1, two simulation engines 12 and 13, a signal controller 14 between modules, and two simulation models 15 and 16. There is.

The simulator 1 controls the simulation engines 12 and 13 and the signal controller 14, respectively, and the simulation engines 12 and 13 are divided into two simulation models 15 and 16 for each input clock frequency.
Verify each. The signal control unit 14 controls the signal propagation between the simulation models 15 and 16 during the simulation and the timing of the signal propagation. The signal control unit 14
Is composed of a buffer memory, and is realized by associating a write clock and a read clock for the buffer memory with an output source and an output destination, respectively.

The simulation models 15 and 16 are obtained by dividing the simulation model to be verified by the input clock frequency. The simulation model 15 is a flip-flop (hereinafter,
F / F) and a combinational circuit for inputting the output signal of the F / F.

In addition, the simulation model 16 receives an input of a clock frequency β different from the clock frequency α.
/ F and a combinational circuit for inputting the output signal of the F / F.

Here, a clock signal of clock frequency α is input to the simulation model 15 via the clock signal line 101, and a clock signal of clock frequency β is input to the simulation model 16 via the clock signal line 102. .

In the simulation using the above model, the logic circuit model 1 input to the simulator 11 is compiled by the compiling means 2 and the simulation model 3 is obtained.
Create

The dividing means 4 uses the simulation model 3 created by the compiling means 2 as a simulation model 15 (module 5) to which a clock signal having a clock frequency α is input, and a simulation model 16 to which a clock signal having a clock frequency β is input. (Module 6)
And split into

The simulation means 7 gives a test pattern 8 for verifying the created simulation models 15 and 16 and executes the simulation. That is, the simulation engines 12 and 13 execute simulations on the simulation models 15 and 16 at the same time according to the clock frequencies α and β,
Timing verification is performed by the F / F of each of the simulation models 15 and 16, and logic verification is performed at a sampling time that matches the frequency.

The simulation engines 12 and 13 execute the simulation in synchronization with each other, and the signal value between the simulation models 15 and 16 is manipulated by the signal control unit 14 in accordance with both clock timings. During this period, the simulation engines 12, 13 and the signal control unit 14 are controlled by the simulator 11.

The analysis means 9 analyzes the simulation result of the simulation means 7, that is, the simulation results of the simulation engines 12 and 13. That is, the analysis means 9 performs timing verification based on the output of each flip-flop in the simulation models 15 and 16 and logic verification at the output pin.

FIG. 3 is a diagram showing a specific example of a model configuration during simulation according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of an observed waveform of an output signal in the model configuration of FIG. In these figures, the simulation model 20a is composed of an F / F 21 and a combinational circuit 22, and the simulation model 20b is an F / F 23.
It is composed of In addition, simulation model 3
0 is composed of F / Fs 31, 34 and combinational circuits 32, 33.

These simulation models 20a, 2
0b and the simulation model 30 are simulated by designating the clock frequency and the sampling time with the simulation engines 12 and 13 described above.
As with the observed waveform shown in FIG. 4, sampling points can be specified according to the frequency of each module.

Although not shown, the signal 1 input to the simulation model 20a is provided between the simulation model 20a and the simulation model 30.
A signal control unit 14 is provided which outputs the signal 104, which is output from the simulation model 20 a in synchronization with the clock signal 101, to the simulation model 30 in synchronization with the clock signal 102.

The clock signal 1 is placed between the simulation model 30 and the simulation model 20b.
The signal control unit 14 that outputs the signal 105 output from the simulation model 30 in synchronization with 02 to the simulation model 20b in synchronization with the clock signal 101 is provided.

Therefore, the simulation model 20b outputs the signal 106 synchronized with the clock signal 101, and the simulation model 30 outputs the clock signal 1
A signal 107 synchronized with 02 is output.

As described above, when simulating a logic circuit using a multiphase clock, the simulation model 3 created by compiling the logic circuit model 1 by the compiling means 2 is divided by the dividing means 4 into modules for each clock frequency. By executing the simulations for the respective modules 5 and 6 in parallel by the simulation means 7, the number of times of test pattern modification and simulation is reduced without considering the delay between the test pattern 8 and the data signal. can do.

[0038]

As described above, according to the present invention, in a multi-phase clock input logic circuit verification simulator for performing logic verification of a logic circuit having a multi-phase clock as an input, the logic circuit corresponds to each multi-phase clock. The test pattern is divided into a plurality of modules, and simulations are performed in parallel with each other using the clocks corresponding to each of the modules, so that the test pattern can be created without considering the delay between the test signal and the data signal. The number of corrections and simulations can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a model configuration during simulation according to an embodiment of the present invention.

FIG. 3 is a diagram showing a specific example of a model configuration during simulation according to an embodiment of the present invention.

4 is a diagram showing an example of an observed waveform of an output signal in the model configuration of FIG.

FIG. 5 is a configuration diagram showing a conventional example.

FIG. 6 is a diagram showing a model configuration during simulation according to a conventional example.

[Explanation of symbols]

 1 Logic Circuit Model 2 Compile Means 3 Simulation Model 4 Dividing Means 5, 6 Modules 7 Simulation Means 8 Test Patterns 9 Analyzing Means 11 Simulators 12, 13 Simulation Engines 14 Signal Controllers 15, 16 Simulation Models

Claims (3)

[Claims] 1. A multi-phase clock input logic circuit verification simulator for performing logic verification of a logic circuit having a multi-phase clock as an input, wherein the logic circuit is divided into a plurality of modules corresponding to each of the multi-phase clocks. A simulator for verifying a multi-phase clock input logic circuit, comprising: dividing means and means for performing simulation in parallel with each other using clocks corresponding to each of the plurality of modules. 2. The device according to claim 1, further comprising means for adjusting and controlling the timing of the signal from the output source module at the time of inputting / outputting the signal between the plurality of modules with a clock corresponding to the output destination module. Simulator for multi-phase clock input logic circuit verification. 3. The dividing means is configured to divide the logic circuit into a partial logic circuit including a flip-flop for inputting each of the multiphase clocks into individual modules for each same clock. The simulator for verifying a multi-phase clock input logic circuit according to claim 1 or 2.