JPH09160943A - Method for preparing test vector in logic simulator and system therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert a logical verification result into each test vector form of each IC vender without being conscious of the difference of the IC vender and an AD tool. SOLUTION: The parameter defining the signal name of the I/O cell of a design circuit is described in an I/O cell library 1 defining an input/output function. By using the parameter receiving delivering function that the circuit expression/hardware description language of a logic simulator 3, the parameter is received and delivered by the logic simulator 3 and the logic verification of circuit data 2 is performed. The I/O cell signal value of the design circuit which is obtained as the logic verification result and the signal name of each cell obtained based on the parameter are written in a non-processing system log file 4 by using the input/output function that the circuit expression/hardware description language has. Next, the test vectors of various kinds of forms are prepared by a conversion means 6 by utilizing the data stored in the source file 4 of a test vector parameter and the non-processing system log file 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION When IC manufacturing depends on an IC vendor, logic data of the IC to be manufactured and test data (test pattern) for testing the IC are usually used as design data from the IC vendor. ) Is released (the test data requested by the IC vendor is hereinafter referred to as a test vector). When a commercially available CAD tool (a tool for performing logic verification of an IC equipped with a simulator) is used as a verification tool in the logic design verification when designing an IC, the verification result is directly used as release data by the IC vendor. However, the verification result must be converted into the test vector format required by the IC vendor.

Since each IC vendor has its own test vector format, when a commercially available CAD tool is used as described above, a conversion tool for converting the verification result into the test vector format of each IC vendor is required. Becomes Moreover, the input / output format of the CAD tool is
Since it depends on the AD tool, the conversion tool must be prepared for each CAD tool.

The present invention relates to a method and system for creating a test vector in a logic simulator for converting a verification result obtained by using a commercially available CAD tool into a test vector required by an IC vendor, and particularly to the present invention. IC designers can check the verification results of commercially available CAD tools for each I without being aware of the differences between IC vendors and CAD tools.
The present invention relates to a method and system for creating a test vector that can be converted into a C vendor test vector format.

[0004]

2. Description of the Related Art FIGS. 5 and 6 are diagrams showing a schematic configuration of a test vector format required by an IC vendor, and FIGS. 5 and 6 exemplify two different test vector formats. FIG.
Is a diagram showing a first test vector format (A format),
The A format test vector includes a test vector header indicating a test data name, a logic circuit name, etc., a timing designating section for designating the positive / negative of the pulse given to each terminal of the IC, a pulse length, etc., and a test block in which a test pattern is described. Etc. The test block is I manufactured by the IC vendor.
This is a portion for describing a test pattern for testing C. In the example of the figure, each terminal name of the IC is defined after “FORM =”, and the signal given to the terminal of the IC is defined by the input description and the output description. The logic level is specified, and the signal value of the input / output signal of each terminal described after FORM = "is described in the above" input description "and" output description ".

In the example shown in the figure, @ 1 follows "FORM ="
2, CLK, BUSC, ... And "N", "0", "P", ... in the input description / output description, but ("0", "1", "P" and "N" are inputs, "L", "H", "Z" and "X" are outputs),
This is after the space 12 (@ indicates a space)
The test pattern is given as "N" to the CLK terminal, "0" to the BUSC terminal, "P" to the CLR terminal, ..., and correspondingly, from the corresponding terminal designated by "FORM =" to "L". , "L", ..., "H" are generated (in the horizontal direction, a test pattern sequence at a certain time point is shown, the first row is the test pattern sequence at the first time point, and the second row is the test pattern sequence). The eye is the test pattern row at the second time point, the third row is the test pattern row at the third time point, ... Here, the terminals of the IC have an input terminal, an output terminal, and a bidirectional terminal, and the portion shown as "bidirectional" in the figure is the signal value of the bidirectional terminal whose input / output is switched by the control signal. .

FIG. 6 shows the second test vector format (B format).
FIG. 4 is a diagram showing a B-type test vector including a test vector header indicating a test data name, a logic circuit name, etc., a terminal definition section, a timing designating section, a test block describing a test pattern, and the like. . In the B format, the terminals are defined in the terminal definition section, and for example, each input terminal has “CLK1 REF = 1” and “SMC1 REF =
2 ”, ..., (where the CKL1 terminal is“ 1 ”,
It means that the SMC1 terminal corresponds to "2", ...,), the input terminal is "IN", the output terminal is "OUT",
Bidirectional terminals are shown as "IO". In the test block, the signal value of each terminal defined as described above is described. In the example of the figure, CL is set at timing TM1.
The case where P (positive pulse) is given to the K terminal (REF = 1) and "0", ... Is given to the SMC1 terminal (REF = 2) ("P", "0", ... Same as 5).

As shown in FIGS. 5 and 6, the test vector format differs depending on the IC vendor, and a CAD tool (a tool for performing logic verification of an IC equipped with a simulator) is designed at the time of IC design. When the verification result obtained by using is directly released to the IC vendor as release data, it is necessary to convert the verification result into a test vector format corresponding to each IC vendor.

FIG. 7 is a diagram showing the configuration of a conventional conversion system for converting the logic verification result obtained by the CAD tool into the test vector format of each IC vendor. In the figure, 51 is a circuit data file storing circuit data of an IC which is a logic verification target, 52 and 53 are first and second processing systems including a simulator for verifying the logic of the above IC ( The CAD tool described above),
As the second processing systems 52 and 53, commercially available products are usually used. For example, the processing system X is a CAD tool manufactured by X company, and the processing system Y is a CAD tool manufactured by Y company. Processing system 5
Reference numerals 2 and 53 denote compilers 52a and 53a for compiling the circuit data stored in the circuit data file 51 to generate executable configuration data 52b and 53b corresponding to the circuit configuration, and the configuration data 52b and 53b. Simulators 52c and 53c for simulating the logical operation of the IC based on 53b to obtain a logic verification result and simulator log files 52d and 53d for storing the simulation result are provided. 55-60 is the above simulator log file 52
d, 53d is a converting means for converting the logic verification result stored in each company into a test vector in the format of each company.
60 is prepared for each of the processing system 52 and the processing system 53, and for each of the IC vendors A to C.

In the figure, for example, the IC designer uses the processing system 52 manufactured by X company to verify the logic of the IC, stores the logic verification result in the simulator log file 52d, and manufactures the IC. When the request is made to the company A, the converting means 5 is used by using the tester information for the company A and the logic verification result.
5 creates a test vector in the format of Company A. Similarly, the IC designer uses the processing system 53 manufactured by Y Co.
C logic verification is performed, and simulator log file 53d
When the logic verification result is stored in the A and the manufacturing of the IC is requested to the A company, the converting means 58 creates the A company format test vector by using the A company tester information and the logic verification result. To do. That is, the IC designer must select an appropriate conversion means according to the processing system used and the IC vendor, and create a test vector in each company format.

[0010]

As described above, conventionally, the conversion means is prepared for each processing system and each IC vendor,
The IC designer has to create a test vector by using an appropriate conversion means according to the processing system used and the IC vendor. Generally, the format of log files of commercially available CAD tools differs for each CAD tool, so multiple C
When using an AD tool to request the manufacture of ICs from a plurality of IC vendors, as the conversion means, [the number of simulator log file formats] × [the number of IC vendor formats]
Therefore, the designer needs to select an appropriate conversion means according to the used CAD tool or IC vendor from the conversion means. Therefore, the above-mentioned conversion work imposes a heavy burden on the designer.

The present invention has been made in consideration of the above-mentioned problems of the prior art, and the object of the present invention is predetermined without the IC designer being aware of the difference between the IC vendor and the CAD tool. A test vector creation method and system in a logic simulator capable of converting a result of logic verification by a logic simulator into a test vector format of each IC vendor by creating a log file storing a verification result in one procedure. Is to provide.

[0012]

FIG. 1 is a schematic block diagram of the present invention. In FIG. 1, reference numeral 1 denotes an I / O cell library that defines the function of the I / O cell of the design circuit. The I / O cell library 1 describes parameters that define the signal name of the I / O cell. Reference numeral 2 is a file that stores circuit data of the designed circuit. Reference numeral 3 is a logic simulator. The logic simulator 3 has an input / output function and can perform an input / output procedure with a processing system in which the simulator runs. A circuit model having a characteristic expression function by definition / a circuit model expressed / described in a hardware description language is simulated, and a logic verification result is output. Reference numeral 4 denotes a non-processing system log file. The non-processing system log file 4 includes the signal value of the I / O cell of the design circuit and its signal in the logic verification result of the logic simulator 3 using the input / output function. The name is written. Reference numeral 5 is a source file of test vector parameters created by using the characteristic expression function defined by the user, and stores header information of the test vector. Reference numeral 6 is a conversion means, which creates test vectors of various formats based on the data stored in the non-processing system log file 4 and the source file 5 of the test vector parameters.

In order to solve the above-mentioned problems, the inventions of claims 1 and 2 of the present invention, as shown in FIG. 1, include an input / output cell of a design circuit in an I / O cell library 1 which defines an input / output function. And a parameter that defines the signal name of the bidirectional cell is described, and the parameter is passed to the logic simulator 3 by using the parameter transfer function of the circuit expression / hardware description language of the logic simulator 3 to perform logic verification and logic verification. Input / output / of the resulting design circuit
The signal value of the bidirectional cell, the signal value of the control signal of the bidirectional cell, and the signal name of each cell obtained based on the above parameters are written into the non-processing system log file 4 using the input / output function, and the test vector is written. By using the test vector header defined by the parameter source file 4 and the data stored in the non-processing system log file, the converting means 6 creates test vectors of various formats.

In the present invention, as described above, the circuit representation / hardware description language has the parameter passing function and the input / output function, and the signal of the I / O cell portion of the design circuit data is traced for designing. The signal value of the I / O cell of the circuit,
Since a non-processing system log file that stores signal names and the like is generated and test vectors of various formats are created based on the data stored in the non-processing system and the specified IC vendor information, the circuit designer , It is possible to create various types of test vectors without having to be aware of the logic simulator used and each vendor format.

[0015]

FIG. 2 is a diagram showing the configuration of a system according to an embodiment of the present invention. In the figure, 51 is the same as that in
The circuit data file 51 is a circuit data file that stores the circuit data of the IC to be subjected to the logic verification shown in FIG. Reference numerals 52 and 53 are first and second processing systems including a simulator for verifying the logic of the IC. The processing systems 52 and 53 use circuit data and I (described later).
52 for compiling / O cell library and the like to generate configuration data 52b, 53b
a, 53a and the configuration data 52
Simulators 52c and 53c for simulating the logical operation of the IC based on b and 53b to obtain a logical verification result
And simulator log files 52d and 53d for storing the above simulation results.

Here, the processing system 52,
53 is assumed to have the following features. That is, the circuit expression (or the hardware language for describing the circuit expression) satisfies the following requirements, and has a function of digitally simulating a circuit model using the circuit expression. (1) Input / output procedures between the input / output function and the processing system on which the simulator runs must be possible. That is, the signal name,
It must be equipped with a function to read signal values from a specified file and write them to a specified file (hereinafter, this function is called the input / output function). As will be described later, this function is used to write a signal name, a signal value, etc. in a non-processing system log file (a test vector is created using the log information stored in this file).

(2) There is a parameter passing mechanism from the upper level to the lower level of the design hierarchy. That is, parameters such as signal names defined at the upper level of the design layer can be passed to the lower level of the design layer (hereinafter, this function will be referred to as parameter passing function). With this function, as will be described later, the parameters (signal names etc.) described in the source program of the I / O cell library can be reflected in the logic simulation result log.

(3) The user can define characteristics as a circuit expression. That is, prepare a declaration that can describe the contents to be defined in the test vector header, and use this function to create a test vector header in the specified IC vendor format as described later (hereinafter, this function will be tested). Vector parameter description function). In a simulator for verifying logic of a digital circuit, VHDL is usually used as a hardware description language, and the above (1)
As the above, VRED “REDA”, “WRITE”, etc. can be used. As above (2), the signal name passing function by the generic parameter in VHDL can be used, and further above (3) Is VHDL "AT
TRIBUTE "(attribute definition command) can be used. In the following description, the case where VHDL is used as the hardware description language will be described.

Reference numerals 10 and 20 are parts added in the present invention. 10 is an input file consisting of a test vector parameter definition file 11 and an I / O cell library 12 with an input / output function, and 20 is a non-processing log file. 21 is an output unit including a conversion unit 22 and a conversion unit 22. The parameter definition file 11 of the input file unit 10 defines the correspondence between terminal names and test patterns in the test vector. In addition, the I / O cell library 12 with an input / output function has a function of the I / O cell (described later) of the IC to VHD.
It is a file described in the L language, and the parameters are described therein, and the result is obtained by compiling the I / O cell library 12 and the result obtained by compiling the source program (design data) of the circuit data as described later. A simulation is performed and the signal name and the like are reflected in the non-processing system log file 21.

In the non-processing system log file 21 of the output unit 20, among the logic verification results by the processing systems 52 and 53,
The signal value of the I / O cell of the IC is added with the signal name and stored, and the test vector of each company format is created based on this. The signal value of the I / O cell is the signal value of each pin of the IC, and the signal value of the control signal for controlling the bidirectional I / O cell is also stored for the bidirectional terminal. Reference numeral 22 is a conversion means for converting the signal name, logic, etc. of the I / O cell stored in the non-processing system log file 21 into a test vector of each company format, and the conversion means 22 is a parameter for generating a test vector header portion. By giving 31 the conversion means 2
2 generates a test vector according to the IC vendor format.
The description of the parameter 31 uses the test vector parameter description function of the VHDL language described above. This allows
The IC designer can describe the parameters corresponding to the test vector header portion without being aware of the CAD tool or the test vector format of each company.

In the simulator log files 52d and 53d provided in the respective processing systems 52 and 53, all signal values (not only input / output signals but I
(Including each signal value of the internal element of C) can be dropped, but the data necessary for creating the test vector is the signal value of the input / output pin of the IC and not all the simulation results are necessary. Since the format of the simulator log file is different for each CAD tool, in order to create a test vector of each company format from the simulator log file, conversion means for each CAD tool is required as shown in FIG. .

On the other hand, as in the present invention, the non-processing system log file 21 is provided, and the signal name, signal value, etc. of the I / O cell of the IC are stored therein, which is necessary for the test vector creation. The log file 22 that does not depend on the format of the simulator that stores the data can be generated. If the converting means 22 has a function of converting the log data into a test vector of each company format according to the designation of the parameter 31, the test vector of each company format can be created only by giving the parameter 31. You can Moreover,
If the description of the I / O cell library 12 with the input / output function, the description of the circuit data, the description of the parameter 31 and the like can be performed uniformly in the VHDL language, the IC designer can determine the difference between the processing systems 52 and 53. It is possible to create a test vector in each company format without being aware of the difference in each company's vector format.

FIG. 3 is a diagram showing an example of the I / O cell model of the LSI. As shown in FIG. 3, an LSI normally has a logic function circuit for performing desired logical operations and the like, an input cell for giving an input signal given from an external pin to the logic function circuit, and an output of the logic function circuit to an external pin. It has an output cell for outputting and an I / O cell including a bidirectional cell whose signal direction is controlled by a control signal. The data necessary for creating the test vector is the signal name of the I / O cell (for example, i1, o1 in the figure) and its signal value. Further, in the case of a bidirectional cell, the signal direction (input state or output state) as well as its signal value is required. Since the signal direction of the bidirectional cell is determined by the signal value of the control signal (c1 in the figure) given to the bidirectional cell, the data necessary for the bidirectional cell is the signal name of each signal (for example, b
1, c1) and their signal values. In this embodiment,
As shown in FIG. 3, the parameters described in the I / O cell library 12 with the input / output function are reflected in the outputs of the processing systems 52 and 53 by the parameter transfer function of the VHDL described above, and the input / output function of the VHDL described above is changed. Utilizing the processing system 52,
The signal name is written in the non-processing system log file 21 together with the logic verification result of 53.

FIG. 4 is a diagram for explaining the operation of the system of the embodiment shown in FIG. 2, and the conversion processing procedure in this embodiment will be explained with reference to FIGS. 3 and 4. . First, the parameters for passing to the design level are described in the I / O cell library (source program) 31. Next, a circuit design is performed using the I / O cell library 31, and a configuration file (source of the design circuit) 32 is created (step S1). As a result, as shown in the figure, the actual signal names i1 (input cell signal names), o1 (output cell signal names), b1 (bidirectional cell signal names), c1 of each I / O cell are set as parameters. A configuration file (source program) 32 containing (signal names of control signals of bidirectional cells) and the like is created. Next, the configuration file 32 and the I / O cell library 31 are compiled by an existing processing system to obtain an I / O cell library object program 33 and a design circuit object program 34 (step S2). Then, a logic simulation is performed by the existing processing system using the above object programs 33 and 34 (step S
3) Write the signal value obtained by logic verification using the above-mentioned input / output function in the non-processing system log file 36 together with the signal name.

The data written in the non-processing system log file 36 is, as shown in the figure, a signal value (a simulation result) of each I / O cell at each time point and a signal name. In the example of the figure, each time point (0, 50, 80,
...), the signal value of the clock terminal CLK, the signal value of the output cell o1, the signal value of the input cell i1, the signal value of the bidirectional cell b1, and the control signal c1 indicating the signal direction of the bidirectional cell. ing. Note that the figure illustrates the case where the control signal c1 of the bidirectional cell changes from high level to low level midway, and the signal direction of the bidirectional cell b1 changes at this point. As described above, the non-processing system log file 36 is created, and the test vector source file 35 describing the test vector head part such as the designer and the circuit name is created using the test parameter description function of the VHDL language. And the non-processing system log file 3
6 and the test vector source file 35 from FIG. 5 and FIG.
A test vector of each vendor format as shown in (1) is created (step S4).

[0026]

As described above, in the present invention, the parameter passing function and the input / output function of the circuit expression / hardware description language are used to obtain the signal value, signal name, etc. of the I / O cell of the design circuit. Generates a non-processing system log file that stores the data, and stores the data stored in the non-processing system and the specified IC
Since the test vectors of various formats are created based on the vendor information, the circuit designer can create test vectors of various formats without being aware of the logic simulator to be used and each vendor format. Therefore, it is not necessary to provide a plurality of converting means according to each vendor format and select a required converting means from the plurality of converting means according to the logic simulator to be used and each vendor format as in the conventional case. Moreover, since various test vectors can be created with one expression and procedure, the burden on the IC designer can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of the present invention.

FIG. 2 is a diagram showing a configuration of a system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an I / O cell model of an LSI.

FIG. 4 is a diagram illustrating an operation of the system according to the embodiment of this invention.

FIG. 5 is a diagram showing a schematic configuration of a test vector format requested by an IC vendor.

FIG. 6 is a diagram showing a schematic configuration of another test vector format requested by an IC vendor.

FIG. 7 is a diagram showing a configuration of a conventional conversion system.

[Explanation of symbols]

 1 I / O cell library 2 File storing circuit data 3 Logic simulator 4 Non-processing system log file 5 Test vector parameter source file 6 Converting means 51 Circuit data file 52, 53 First and second processing system 52b, 53b Configuration data 52a, 53a Compiler 52c, 53c Simulator 52d, 53d Simulator log file 10 Input file 20 Output section 11 Parameter definition file 12 I / O cell library with I / O function 21 Non-processing system log file 22 Conversion means

Claims (2)

[Claims] 1. A function that has an input / output function and is capable of performing an input / output procedure with a processing system in which a simulator runs, and has a function of passing parameters from a higher level to a lower level of a design hierarchy and a characteristic expression function defined by a user. Utilizing the logic verification results of a logic simulator that simulates a circuit model that is provided / described in a provided circuit representation / hardware description language,
A test vector creating method for creating test vectors of various formats. The circuit data of a design circuit is created, and the input / output cells and the bidirectional of the design circuit are added to an I / O cell library that defines input / output functions. Describe the parameter that defines the signal name of the cell, pass the parameter written in the I / O cell library to the logic simulator using the above-mentioned parameter passing function, and use the circuit data and the I / O cell library to pass the logic. The logic verification of the above-mentioned design circuit is performed by a simulator, and it is obtained based on the above-mentioned parameters and the signal value of the input / output / bidirectional cell of the above-mentioned design circuit and the signal value of the control signal of the bidirectional cell obtained as a result of the logic verification. Write the signal name of each cell to the log file of the non-processing system by using the above input / output function. The test vector header is defined by using the user-defined characteristic expression function of the target description language, and the test vector header and the data stored in the non-processing system log file are used to generate test vectors of various formats. A method for creating a test vector in a logic simulator, which is characterized by creating it. 2. The input / output procedure with a processing system having an input / output function and running by a simulator is possible, and the function of passing parameters from the upper level to the lower level of the design hierarchy and the characteristic expression function defined by the user are provided. Utilizing the logic verification results of a logic simulator that simulates a circuit model that is provided / described in a provided circuit representation / hardware description language,
A test vector creation system for creating test vectors of various formats, including an I / O cell library that describes parameters that define signal names of input / output cells and bidirectional cells of a design circuit,
Non-processing system log file that stores the logic verification result by the logic simulator, test vector header definition file that defines the test vector header by using the user-defined characteristic expression function, the above-mentioned non-processing system log file and test vector header And a conversion means for creating test vectors of various formats from the definition file, and the parameters described in the I / O cell library are transferred to the logic simulator by using the transfer function of the parameters, and the circuit data of the design circuit and the I / O The logic verification of the design circuit is performed by a logic simulator using the O cell library, and the input / output / bidirectional cell signal values and the bidirectional cell control signal signal values of the design circuit obtained as logic verification results , The signal name of each cell obtained based on the above parameters, There are written to the non-processing system log file, and the test vector header definition file,
A test vector creation system in a logic simulator, characterized in that a test vector of various formats is created by the conversion means using a non-processing system log file.