JPH09186730A - Absolute phase detector and digital modulation wave demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably detect at which phase locking is made by improving the S/N equivalently for a synchronizing signal part. SOLUTION: A tentative discrimination section receives an I signal and a Q signal demodulated by a demodulator 1 to execute tentative discrimination processing of a received symbol and a synchronizing pattern acquisition section 5 executes the acquisition processing of a synchronizing pattern subjected to tentative decision to generate a frame synchronizing signal. A reception signal averaging section 7 receives the I signal and the Q signal demodulated by the demodulator 1 and the frame synchronizing signal to execute the averaging processing of a reception signal point at a symbol timing interval only for a time of the synchronizing pattern. A synchronization detection section 9 decides at which phase the synchronization pattern is locked based on the averaged signal. A reception symbol hard decision section 11 uses the phase information to decide the reception symbol with phase uncertainty eliminated therefrom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute phase detector and a digital modulation wave demodulation device capable of stably detecting an absolute phase of a multilevel phase modulation wave or a multilevel phase amplitude modulation wave.

SUMMARY OF THE INVENTION The present invention relates to stability improvement when performing absolute phase detection of a multilevel phase modulated wave or a multilevel phase amplitude modulated wave by a fixed synchronization pattern with a small number of signal point arrangements. By averaging the signal point positions of the obtained synchronization pattern at symbol timing intervals or performing low-pass filtering operation on this, absolute phase detection is stable even at low C / N when the demodulated signal point positions spread. It was made possible.

Here, the absolute phase detection means detecting a phase error of a signal point to be demodulated to detect a correct reception signal point. That is, when the phase-modulated signal is synchronously detected, it is necessary to know the frequency and phase of the unmodulated carrier before modulation. However, when reproducing the non-modulated carrier on the demodulation side, it is generally difficult to reproduce the carrier of the same phase, and the signal point to be demodulated is, for example, Q.
In the case of PSK, a phase error that is an integral multiple of π / 2 occurs.
Absolute phase detection is performed to detect this phase error and obtain a correct reception signal point.

[0004]

As is well known, in digital phase amplitude modulation, data transmission is performed by changing the phase and amplitude of a carrier wave at equal intervals, that is, symbol timing intervals.

For example, in BPSK (two-phase phase shift keying), the amplitude is not changed, the phase is changed to 45 degrees or 225 degrees, and one symbol is assigned to the phase. In this case, the phase takes only two values, so 1
1-bit data can be transmitted by a symbol.

In QPSK (4-phase phase shift keying), data transmission is performed using four phases of 45 degrees, 135 degrees, 225 degrees, or 315 degrees. This QPSK
Then, since the phase can take four values, 2-bit data transmission is possible with one symbol.

An example of the QPSK modulated wave is shown in FIG.
The constellation points of K and QPSK are shown in FIG. The signal point is a value that the phase and amplitude of the modulated wave can take on an orthogonal plane.

In addition to this, 8PSK (8-phase phase shift keying), 16PSK (16-value phase shift keying), etc. are known as multi-level phase modulation in which only the phase is changed without changing the amplitude.

Further, there is also multilevel phase amplitude modulation in which not only the phase but also the amplitude is changed to further increase the number of bits that can be transmitted in one symbol. For example, 16QAM (16-value quadrature amplitude modulation) is available. ), 64QAM
(64-valued quadrature amplitude modulation) and the like. The arrangement of these signal points is shown in FIG. FIG. 12 shows the phase relationship between the modulated wave and the demodulated wave.
Shown in

FIG. 13 shows an example of a conventional absolute phase detection circuit. A conventional method for detecting the absolute phase of QPSK from a time-division BPSK synchronization pattern will be described with reference to FIG.

Here, it is assumed that the carrier reproduction system of the demodulator 101 uses QPSK, and as shown in FIG. 14, the data is QPSK and the synchronization signal is time division multiplexed with BPSK for transmission.

The demodulated I signal and Q signal output a positive value (+) when the eye opening point is "1" and a negative value (-) when the eye opening point is "0". To do.

Now, as the synchronization pattern, {00010011010
If 11110} is transmitted by BPSK, a phase uncertainty of π / 2 × n occurs in the I signal and the Q signal, so the following (1)
One of the four patterns of (2) to (2) is output as the I signal and Q signal of the demodulator 101. However, + is a positive value,-
Indicates a negative value.

Pattern (1) I: {--- +-++-+-++++-} Q: {--- +-++-+-++++-} Pattern (2 ) I: {+++-++-+-+ ---- +} Q: {--- +-++-+-++++-} Pattern (3) I: {++ +-++-+-+ ---- +} Q: {+++-++-+-+ ---- +} Pattern (4) I: {--- +-++ -+-++++-} Q: {+++-++-+-+ ---- +} Therefore, as I signal or Q signal, {+++-++-+-+
---- +} or {--- +-++-+-++++-} is detected,
Since it can be seen that the synchronization has been captured, for example, if the first symbol at this time is {I, Q} = {-,-}, the phase error is 0 {I, Q} = {+,-} For example, if the phase error is π / 2 {I, Q} = {+, +}, then if the phase error is π {I, Q} = {−, +}, then the phase error is 3π / 2. I understand.

This information can be used to make a symbol determination with the phase uncertainty removed.

[0016]

However, in a poor reception environment in which the C / N is deteriorated due to non-linearity or rainfall in the satellite transmission line, the reception signal points spread as shown in FIG. When a modulation method with a large number of signal point arrangements is used, there is a high probability that the adjacent symbol areas will be erroneously determined, making it difficult to detect the synchronization pattern.

Therefore, by using only the modulation method of the synchronization pattern portion as a modulation wave having a smaller number of signal points than that of the data transmission portion, the area for one symbol can be widened and the probability of error between adjacent portions can be reduced. Can be considered.
For example, if 8PSK modulation is used for data transmission and BPSK is used for the synchronization part, synchronization detection during demodulation becomes easy even in a poor transmission state.

However, when it is attempted to correct the phase uncertainty of n × π / 4 (n: integer) of 8PSK from the demodulation phase information of this BPSK synchronization signal, the demodulation signal point of the synchronization signal portion is shown in FIG. As described above, in the case of spreading by π / 8 or more, the phase may be corrected to a phase adjacent to the original phase, and a correct received symbol may not be obtained.

The present invention has been made in view of the above circumstances, and an object thereof is to enable stable detection of correct phase information from a synchronization pattern extracted from a demodulated signal in which the above-described deterioration has occurred. Another object of the present invention is to provide an absolute phase detector and a digital modulation wave demodulation device.

[0020]

In order to achieve the above-mentioned object, the invention of claim 1 is a multi-valued method in which a synchronizing signal portion having a number of signal points smaller than the number of signal points of a data signal portion is multiplexed on the data signal portion. When demodulating a phase-modulated wave or a multi-level phase-amplitude modulated wave, a detector that detects the absolute phase of the demodulated baseband signal calculates the average per multiple symbols at the symbol timing intervals for the synchronization signal part. It is characterized by comprising an averaging means and an absolute phase detecting means for detecting the absolute phase of the synchronization signal based on the averaged signal obtained by the averaging means.

According to a second aspect of the present invention, a multilevel phase modulated wave or a multilevel phase amplitude modulated wave formed by multiplexing a synchronizing signal part having a smaller number of signal points than the number of signal points of the data signal part is demodulated. At this time, in a detector that detects the absolute phase, a provisional determination unit that inputs the I signal and the Q signal demodulated by the demodulator and performs the provisional determination process of the received symbol, and the provisional determination unit performs the provisional determination. The synchronization pattern capturing unit that executes the synchronization pattern capturing process to generate the frame synchronization signal, the I signal, the Q signal demodulated by the demodulator, and the frame synchronization signal are input, and only the time of the synchronization pattern is input. Which received signal averaging unit executes the process of averaging the received signal points at the symbol timing intervals, and which synchronization pattern is based on the averaged signal output from this received signal averaging unit. A synchronization determination unit that determines whether or not the phase is locked, and a reception symbol hard determination unit that determines the reception symbol from which the phase uncertainty is removed by using the phase information of the synchronization determination unit. There is.

According to a third aspect of the present invention, a multilevel phase modulated wave or a multilevel phase amplitude modulated wave formed by multiplexing a synchronization signal part having a smaller number of signal points than the number of signal points of the data signal part is demodulated. At this time, in the detector for detecting the absolute phase, a low-frequency signal is extracted by extracting the signal point positions of only “0” symbols or only “1” symbols in the sync signal portion in the demodulated baseband signal. It is characterized by comprising a band pass filter and an absolute phase detecting means for detecting the absolute phase of the synchronization signal based on the signal filtered by the low pass filter.

The invention of claim 4 is a digital modulated wave demodulating device comprising the absolute phase detector according to claim 1 or 2.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

<Principle of the Present Invention> FIG. 1 shows a basic configuration of a multilevel phase amplitude modulated wave demodulator as a digital modulated wave demodulator according to the present invention.

The present invention equivalently improves the S / N of the synchronizing signal portion by executing the averaging process of the received signal points of the synchronizing signal portion, and stabilizes which phase is locked. It can be detected by. For example, when 8PSK modulation is used for data transmission and a signal transmitted using BPSK for the sync signal part is demodulated, the sync signal part is averaged as shown in FIG. 2 to obtain a correct received symbol. You can

Therefore, as shown in FIG. 1, the demodulator of the present invention has a demodulator 1, a received symbol provisional decision section 3, a synchronization pattern acquisition section 5, and an average received signal for the synchronization signal section. It has a basic configuration including a conversion unit 7, a synchronization pattern synchronization detection unit, and a received symbol hard decision unit 11.

The tentative decision unit 3 inputs the I and Q signals demodulated by the demodulator 1 and executes the tentative decision process of the received symbol. A capture process is executed to generate a frame sync signal. On the other hand, the received signal averaging unit 7 inputs the I signal and the Q signal demodulated by the demodulator 1 and the frame synchronization signal, and averages the received signal points at the symbol timing intervals only for the time of the synchronization pattern. To execute. The synchronization detector 9 determines at which phase the synchronization pattern is locked based on the averaged signal. The received symbol hard decision unit 11 uses this phase information to decide the received symbol from which the phase uncertainty has been removed.

The demodulating device shown in FIG. 1 is shown in FIG.
As shown in, the signal transmitted in the time division multiple layer is demodulated. In this time division multiple layer transmission, 8P is set as data 1.
The SK signal, the QPSK signal as the data 2, the BPSK signal as the data 3, and the BPSK signal as the synchronization signal are time-division multiplexed, and the multiplexed signal is orthogonally modulated by the orthogonal modulator and transmitted as a hierarchical modulated wave. in this case,
The signals of data 1 to data 3 are time-axis compressed. Further, since the synchronization signal is particularly important, it is a BPSK modulated wave that is resistant to deterioration of the transmission environment.

When demodulating the modulated wave generated as described above, the modulated wave is first treated as 8PSK, carrier reproduction and symbol timing reproduction are performed, and a reception signal point is obtained. Furthermore, it is necessary to detect the sync signal at the beginning of the signal and correct the phase uncertainty of the reproduced carrier before taking out the received symbol.

First, in the absolute phase detection using the synchronization signal, the 8PSK-demodulated synchronization signal is BPSK-modulated and may be demodulated in eight phases as shown in FIG. In FIG. 4, the arrow in the figure indicates the locus of movement of the reception signal point when the transmitted synchronization signal changes from 0 to 1. It is good if demodulation can be performed with "0" in the figure, but in other cases, it is necessary to correct the phase.

For example, FIG. 6 shows the relationship between the modulation phase and the demodulation phase at each signal point of BPSK, QPSK, and 8PSK. As shown in FIG. Therefore, it can be understood that the phase on the demodulation side is shifted by +90 degrees.

In the present invention, this phase correction is carried out in a stable manner, and a concrete apparatus configuration example shown in FIG. 5 will be described below.

<Specific Example of Device Configuration> The circuit shown in FIG. 5 captures a BPSK synchronization pattern from the demodulated received signal point arrangement and determines a received symbol with a correct phase. And the demapping ROM 23
, Eight 16-bit shift registers 25, OR gate circuit 27, two latch circuits 29, 29 ', averaging circuit 31, synchronous phase detection circuit 33, 8PSK symbol determination circuit 35, and QPSK. Symbol determination circuit 37
And a BPSK symbol determination circuit 39 and two parallel / serial conversion circuits 41 and 43.

The demapping ROM 23 has eight phase angles (0 deg, 45 deg, 90 deg, 1 deg.) As shown in FIG.
35 deg, 180 deg, 225 deg, 270 deg, and 315 deg) are stored, the sync signal portion demodulated by the quadrature demodulator 21 is input, and any pattern corresponding to the input sync signal is 8 1 selected from one of the phase patterns
It is output to the 6-bit shift register 25.

The 16-bit shift register group 25 is composed of eight 16-bit shift registers corresponding to the eight phase patterns supplied from the demapping ROM 23. It is generated and supplied to the OR gate circuit.

The OR gate circuit 27 is an 8-input OR circuit, which generates a frame synchronization signal when any of the eight shift registers 25 outputs a signal indicating that the frame has been synchronously captured. Synchronous signal to each latch circuit 2
9, 29 ', D flip-flops 43, and 16 counters 47, respectively.

The two latch circuits 29 and 29 'are circuits for latching the I and Q coordinates of the last symbol of the sync signal portion among the demodulated signal points by the frame sync signal.

The averaging circuit 31 is a circuit for averaging the received signal points at the symbol timing intervals only for the time of the sync pattern, and the D flip-flop (D- FF) 45
And a full adder 47 and a 16 counter 49.

The D flip-flop 45 is a full adder 47.
Together with this, a cumulative adder circuit is configured to input and hold the 10-bit signal supplied from the full adder 47, and reset the processing of outputting the previously input 10-bit signal to the full adder 47 from the 16 counter 49. The cumulative addition is repeatedly executed until the signal is supplied.

The full adder 47 is a two-input full adder of 10 bits and 6 bits, and outputs the 6-bit signal supplied from the latch circuit 29 and the 10-bit signal supplied from the D flip-flop 45. In addition to performing addition, a process of supplying the upper 10 bits of the added 16-bit signal to the D flip-flop 45 is executed. When the cumulative addition for 16 symbol periods is completed, the lower 4 bits of the cumulative result are discarded and the 6-bit cumulative data is output to the synchronous phase detection circuit 33.

The 16 counter 49 is composed of a 4-bit counter and counts the frame synchronization signal output from the OR gate circuit 25. When the frame synchronization signal is counted 16 times, a reset signal is generated, Output to the D flip-flop 45.

The synchronization phase detection circuit 33 is a circuit for determining at which phase the synchronization pattern is locked based on the averaged signal, and the determination signal (3 bits of phase information) is determined by the 8PSK symbol determination circuit 35 and QPSK. It outputs to the symbol determination circuit 37 and the BPSK symbol determination circuit 39.

The 8PSK symbol determination circuit 35 inputs the I signal and the Q signal demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and outputs the 8PSK portion (corresponding to data 1 in FIG. 3). The received symbol determination process is executed. Further, the QPSK symbol determination circuit 37 inputs the I signal and the Q signal demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and outputs the QPSK portion (corresponding to data 2 in FIG. 3). The received symbol determination process is executed. Further, the BPSK symbol determination circuit 39 inputs the I signal and Q demodulated by the quadrature demodulator 21 and the determination signal from the synchronous phase detection circuit 33, and inputs the BPSK portion (FIG. 3).
(Corresponding to the data 3) of the received symbol) is executed.

The parallel / serial conversion circuit 41 converts the 8PSK symbol supplied from the 8PSK symbol determination circuit 35 into a serial signal and outputs it. Further, the parallel / serial conversion circuit 43 converts the QPSK symbol supplied from the QPSK symbol determination circuit 37 into a serial signal and outputs the serial signal.

Here, the demapping ROM 23 and 16
A bit shift register 25, an OR gate circuit 27,
The latch circuit 29, the averaging circuit 31, and the synchronous phase detection circuit 33 constitute the absolute phase detection circuit of the present invention, and the demodulator 21, the absolute phase detection circuit, the 8PSK symbol determination circuit 35, and the QPSK symbol determination. A symbol determination circuit including a circuit 37 and a BPSK symbol determination circuit 39, two parallel / serial conversion circuits 41 and 43, and a digital modulated wave demodulation device according to the present invention are configured.
The quadrature demodulator 21 corresponds to the demodulator 1 of FIG. 1, the demapping ROM 23 corresponds to the received symbol provisional determination unit 3 of FIG. 1, the 16-bit shift register 25 and the OR gate circuit 27 of FIG. The averaging circuit 31 corresponds to the synchronization pattern capturing section 5, and the averaging circuit 31 corresponds to the reception signal point averaging section 7 in FIG.
The synchronization phase detection circuit 33 corresponds to the synchronization detection unit 9 and
The K symbol determination circuit 35, the QPSK symbol determination circuit 37, and the BPSK symbol determination circuit 39 correspond to the received symbol hard determination unit 11 in FIG.

In the configuration of FIG. 5, when the I signal and the Q signal are output from the quadrature demodulator 21, synchronization detection is first performed using the demapping ROM 23 for all eight phase angles. Here, {0001001101011110} is taken as an example of the synchronization pattern to be detected.

When the synchronization is captured by any of the patterns for the eight phase angles stored in the demapping ROM 23, the OR gate circuit 27 generates a frame synchronization signal.

At this time, if the C / N is good, out of the eight gate outputs, the signals that are stably captured are output from three gates, but if the C / N deteriorates, the The two become particularly unstable. Therefore, if at least one of the eight gate outputs is detected as a sync signal at equal intervals, it is considered that the sync signals have been captured synchronously, and a frame sync signal is generated. The generated frame synchronization signal is supplied to the latch circuit 29, the D flip-flop 45, and the 16 counter 49, respectively.

When the sync signal is detected, the OR gate circuit 27
When the frame sync signal is supplied from the 16-symbol interval of 16 symbols in the sync symbol interval, the 10-bit D flip-flop 43 and the 10-bit and 6-bit 2-input full adder 47 are used. Perform cumulative addition. The operation of dividing by 16 by truncating the lower 4 bits is performed on the accumulated result.

The 16-counter 49 counts the number of times the frame synchronization signal is output. When the frame synchronization signal is output 16 times, a reset signal is generated and supplied to the reset terminal of the D flip-flop 45, whereby cumulative addition is performed. Is reset.

When the cumulative addition is completed and an averaged signal in the 16-symbol section is generated, the averaged signal is output to the synchronous phase detection circuit 33.

The synchronization phase detection circuit 33 determines on which phase the synchronization pattern is locked based on the averaged signal, and the determination signal is used as the 8PSK symbol determination circuit 35, Q.
This is output to the PSK symbol determination circuit 37 and the BPSK symbol determination circuit 39 to stably execute the symbol determination.

FIG. 8 shows another embodiment of the present invention. In this embodiment, a filter circuit 51 is used instead of the averaging circuit 31 shown in FIG. 5
Is the same as that shown in FIG.

The filter circuit 51 includes two digital low pass filter (LPF) 53, 53 '. The 6-bit signal from the latch circuit 29 and the frame synchronization signal from the OR gate circuit 27 are input to the LPF 53, and similarly, the LPF 53 ′ receives the 6-bit signal from the latch circuit 29 ′ and the frame from the OR gate circuit 27. The sync signal and the low-pass filtered signal are input to the sync phase detection circuit 33.

In the above-described embodiment, the S / N of the sync signal portion is equivalently improved by averaging a plurality of symbols of the sync signal portion, but in this embodiment, the S / N of the sync signal portion is improved. Take out only the symbol, and then B
The signal point position of only the "0" symbol or only the "1" symbol of PSK is extracted and low pass filtered by LPFs 53 and 53 '. As a result, the same effect as that of the embodiment shown in FIG. 5 can be obtained with a simple circuit configuration.

The filter circuit 51 is a digital L
Although it can be easily configured by using the PFs 53 and 53 ′, an analog filter can also be configured by placing a D / A converter and an A / D converter before and after the filter. In short, if only the DC component of the signal point can be extracted, the effect of improving the S / N of the sync signal portion can be expected.

[0057]

As described above, according to the invention of each claim, when the absolute phase detection of the multi-level phase modulated wave or the multi-level phase amplitude modulated wave is performed by the fixed synchronization pattern with a small number of signal points, demodulation is performed. It is possible to stably perform absolute phase detection even at low C / N when the signal point positions are diffused.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 2 is an explanatory diagram of the principle of the present invention showing a state in which a synchronization signal portion is averaged.

FIG. 3 is an explanatory diagram showing the principle of time division multiple layer transmission which is a demodulation target of the multilevel phase amplitude modulation wave demodulation device.

FIG. 4 is an explanatory diagram showing a synchronization phase of a 8PSK-demodulated BPSK modulated wave.

FIG. 5 is a block diagram showing a specific configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 6 is an explanatory diagram showing a relationship between a modulation phase and a demodulation phase.

FIG. 7: BPSK demapping R corresponding to eight phases
It is explanatory drawing which shows the content of OM.

FIG. 8 is a block diagram showing another specific configuration of a multilevel phase amplitude modulation wave demodulation device as a digital modulation wave demodulation device according to the present invention.

FIG. 9 is an explanatory diagram showing an example of a QPSK modulated wave.

FIG. 10 is an explanatory diagram showing a signal point arrangement of BPSK and QPSK.

FIG. 11 is an explanatory diagram showing signal point arrangements of 16QAM and 64QAM.

FIG. 12 is an explanatory diagram showing a phase relationship between a modulated wave and a demodulated wave.

FIG. 13 is a block diagram showing a configuration of a conventional absolute phase detection circuit using a synchronization pattern.

FIG. 14 is an explanatory diagram showing the structure of a data format.

FIG. 15 is an explanatory diagram showing spreading of received signal points.

FIG. 16 is an explanatory diagram showing a case where a BPSK signal which is a synchronization signal crosses an 8PSK determination boundary line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Demodulator 3 Received symbol tentative determination unit 5 Synchronization pattern capture unit 7 Received signal point averaging unit 9 Synchronization detection unit 11 Received symbol hard decision unit 21 Quadrature demodulator 23 Demapping ROM 25 16-bit shift register 27 OR gate circuit 29 Latch Circuit 31 Averaging circuit 33 Synchronous phase detection circuit 35 8PSK symbol determination circuit 37 QPSK symbol determination circuit 39 BPSK symbol determination circuit 41, 43 Parallel / serial conversion circuit 45 D flip-flop 47 Full adder 49 16 counter 51 Filter circuit 53, 53 '' Digital low pass filter (LPF)

Claims (4)

[Claims] 1. When demodulating a multi-level phase modulation wave or a multi-level phase amplitude modulation wave, which is formed by multiplexing a synchronization signal part having a smaller number of signal points than the number of signal points of the data signal part on the data signal part, the absolute value thereof is demodulated. In the detector that detects the phase, based on the averaging means that obtains the average per multiple symbols at the symbol timing intervals for the synchronization signal part in the demodulated baseband signal, and the averaging signal obtained by this averaging means. An absolute phase detector comprising: an absolute phase detecting means for detecting the absolute phase of the synchronization signal. 2. When demodulating a multi-level phase modulated wave or a multi-level phase amplitude modulated wave, which is formed by multiplexing a synchronization signal part having a smaller number of signal points than the number of signal points of the data signal part on the data signal part, the absolute value thereof is demodulated. In a detector for detecting a phase, a tentative determination unit that inputs the I signal and the Q signal demodulated by the demodulator and performs the tentative determination process of the received symbol, and capture of the synchronization pattern tentatively determined by the tentative determination unit A synchronization pattern capturing unit for executing processing to generate a frame synchronization signal, an I signal, a Q signal demodulated by the demodulator, and the frame synchronization signal are input, and received at symbol timing intervals only for the time of the synchronization pattern. The received signal averaging unit that executes the process of averaging the signal points, and at which phase the synchronization pattern locks based on the averaged signal output from this received signal averaging unit. An absolute phase detection characterized by comprising: a synchronization determination unit for determining whether or not there is a received signal, and a reception symbol hard determination unit for determining a reception symbol with phase uncertainty removed by using the phase information of the synchronization determination unit. vessel. 3. When demodulating a multilevel phase modulated wave or a multilevel phase amplitude modulated wave formed by multiplexing a synchronization signal part having a smaller number of signal points than the data signal part in the data signal part, the absolute value thereof is demodulated. In a detector for detecting a phase, a low pass filter for extracting a signal point position of only “0” symbol or only “1” symbol for a synchronizing signal portion in a demodulated baseband signal and performing a filtering operation, An absolute phase detector that detects the absolute phase of the synchronization signal based on the signal filtered by the low-pass filter, and an absolute phase detector. 4. A digital modulated wave demodulating device comprising the absolute phase detector according to claim 1. Description: