JPH09186616A - Fm receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver whereby the fluctuation of a reception signal level which is detected in a reception signal level detecting circuit is restricted even by the modulation degree and the modulation frequency of a reception signal. SOLUTION: An FM intermediate frequency signal is converted in an A/D converter 1, supplied to an FM demodulating circuit 31 as an input signal through a digital filter 2 and demodulated. A lagging signal obtained by lagging the input signal by 90 deg. is taken-out from the FM demodulating circuit 31 and a value based on the input signal is adopted as X, the value based on the lagging signal is Y and αis a constant. At this time, the operation of X<2> +Y<2> +|αXY| is execute, the constant α (0<α) IS set to satisfy Xmax + Ymax -(X<2> +Y<2> )≈|αXY|and a demodulation output is turned on/off based on the reception signal level based on an operation output.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an FM receiver having a squelch circuit.

[0002]

2. Description of the Related Art A squelch circuit for turning on / off an FM demodulation output depending on the presence or absence of a received signal is often controlled by the noise level of the FM demodulation output. However, when it is difficult to detect the noise level of the FM demodulation output, the presence or absence of the reception signal is determined based on the reception signal level, and the FM demodulation output is turned on and off based on the presence or absence of the reception signal.

There are two methods of detecting the received signal level: absolute value detection and effective value detection. The method of RMS detection is to find the real and imaginary parts of the received signal instantaneous value,
They are obtained by squaring each of them, then adding up, and obtaining the square root of the addition result. As a simple method for obtaining the real part and the imaginary part of the received signal instantaneous value, when the digital signal processing is used, the real part and the imaginary part are obtained by using a delay device which causes a phase difference of 90 degrees between the input and output signals. You can

A conventional example in which a method based on digital signal processing is used as a method for detecting a received signal level is configured as shown in FIG. In FIG. 4, the FM intermediate frequency signal is A / D converted by the A / D converter 1, and the digital FM intermediate frequency signal output from the A / D converter 1 is supplied to the digital filter 2 forming a bandpass filter. The band-limited digital FM intermediate frequency signal is supplied to the digital FM demodulation circuit 3 and the reception signal level detection circuit 18. Digital FM demodulation circuit 3
The FM demodulation output output from is output via the switch circuit 14.

On the other hand, the received signal level detected by the received signal level detection circuit 18 is the signal level discrimination circuit 19
And compares it with the judgment level (level at which it should be judged that a signal has been received) set in the signal level judgment circuit 19, and when the detected reception signal level is equal to or higher than the judgment level, the switch circuit 14 is turned on. The switch circuit 14 is controlled to the off state when the level is below the determination level. The reception level detection circuit 18, the signal level determination circuit 19, and the switch circuit 14 form a squelch circuit. The determination level of the signal level determination circuit 19 is provided with a hysteresis of a predetermined width (hereinafter, also referred to as a hysteresis width of the squelch circuit).

Here, the frequency of the FM intermediate frequency signal is A /
The sampling frequency fs in the D converter 1 is set to 1/4, and the center frequency of the pass band of the digital filter 2 forming the band pass filter is set to fs / 4.

The received signal level detection circuit 18 is composed of a shift register 4, multipliers 5 and 6, an adder 7 and a square root calculation circuit 17. The digital FM intermediate frequency signal whose band is limited by the digital filter 2 is supplied to the shift register 4, and the shift register 4 outputs the signal with a delay of one sampling period. Shift register 4
Since the frequency of the shift pulse of is also set to the frequency fs, the shift by the shift register 4 causes a phase difference of 90 degrees between the signal input to the shift register 4 and the signal output from the shift register 4. ing.

The output signal from the shift register 4 is a multiplier 5
, The input signal of the shift register 4 is squared by the multiplier 6, the output of the multiplier 5 and the output of the multiplier 6 are added in the adder 7, and the output of the adder 7 is squared. To the signal level determination circuit 19, and the square root calculation circuit 1 is supplied with the output of the square root calculation circuit 17.
When the signal level determination circuit 19 determines that the signal level based on the value of the signal output from 7 is equal to or higher than the determination level, the switch circuit 14 is in the ON state, and when the signal level determination circuit 19 determines that the signal level is lower than the determination level. The switch circuit 14 is controlled to the off state.

[0009]

However, in the FM receiver as described above, a bandpass filter is inserted to limit the reception band. However, a part of the intended reception signal is also generated by the bandpass filter. Attenuated. The level to be attenuated depends on the spread of the spectrum of the received signal, and the larger the modulation index or the higher the modulation frequency, the greater the signal component attenuated by the band filter,
There is a problem that the reception signal level detected by the reception signal level detection circuit is lowered.

Further, the fluctuation of the reception signal level detected by the reception signal level detection circuit is caused not only by the change of the modulation index and the modulation frequency but also by the center frequency of the pass band of the band pass filter and the frequency of the FM intermediate frequency signal. It is also caused by the frequency shift between them. If the frequency of the FM intermediate frequency signal is at the center frequency of the pass band of the band pass filter,
Although the signal level attenuated by the bandpass filter is minimum, the frequency of the FM intermediate frequency signal deviates from the center frequency of the passband of the bandpass filter, so that the high level component close to the center of the frequency of the FM intermediate frequency signal. Is attenuated by the bandpass filter, and the detected reception signal level is lowered.

Here, when the detected received signal level is received and the detected received signal level exceeds the discrimination level set to a level just near the noise level, it is discriminated that there is a received signal, and is less than the discrimination level. In case of, the presence or absence of the received signal is determined by determining that there is no received signal, and F
When performing squelch control for selectively blocking the M demodulation output, the detected reception signal level fluctuates based on the modulation index and the modulation frequency. Although the signal level determination circuit has the hysteresis width as described above, if the fluctuation width of the reception signal level exceeds the hysteresis width, the FM demodulation output is turned on / off during reception, which causes a trouble in reception. Cause problems.

An object of the present invention is to provide an FM receiver in which fluctuations in the received signal level detected by the received signal level detection circuit are suppressed even by the modulation degree and the modulation frequency of the received signal.

[0013]

An FM receiver according to the present invention uses an A / D-converted FM intermediate frequency signal that has passed through a bandpass filter for band limitation as an input signal.
In an FM receiver equipped with a digital FM demodulation circuit for M demodulation, the input signal from the digital demodulation circuit is
When a delay signal delayed by 0 degree is taken out, a value based on the input signal is X, a value based on the delay signal is Y, and α is a constant,

[0014]

(Equation 3)

The above-mentioned FM is provided with a calculation means for performing the calculation of
A value based on the input signal when the frequency of the intermediate frequency signal deviates within a predetermined frequency range from the center frequency of the pass band of the band pass filter and there is no attenuation of the FM intermediate frequency signal by the band pass filter ( Xma
x) and the value based on the lag signal when there is no attenuation of the FM intermediate frequency signal by the bandpass filter is (Ymax),

[0016]

(Equation 4)

A constant α (0 <α) is set so as to satisfy the condition, the output signal from the calculating means is output as a reception signal level, and the FM demodulation output is turned on / off based on the reception signal level. And

According to the FM receiver of the present invention, the FM reception is provided with the digital FM demodulation circuit for FM demodulating the A / D-converted FM intermediate frequency signal that has passed through the band pass filter for band limitation as an input signal. In the machine, a delayed signal obtained by delaying the input signal by 90 degrees is taken out from the digital demodulation circuit, a value based on the input signal is X, a value based on the delayed signal is Y, and α is a constant. When
The calculation according to the equation (3) is performed, and the calculation output signal is output as the reception signal level. Here, when the frequency of the FM intermediate frequency signal output from the bandpass filter is deviated from the center frequency of the passband of the bandpass fill within a predetermined frequency range, a constant α Is set.

However, when the frequency of the FM intermediate frequency signal deviates from the center frequency of the pass band of the band pass filter, the level of the FM intermediate frequency signal output from the band pass filter decreases due to the increase in the deviation amount. To be made. On the other hand, when the frequency of the FM intermediate frequency signal deviates from the center frequency of the pass band of the band pass filter, the value of | αXY | is increased based on the increase of the deviation amount. Therefore, when the frequency of the FM intermediate frequency signal deviates from the center frequency of the pass band of the band pass filter,
The changing direction of the sum of the first term and the second term and the changing direction of the third term in the equation (3) for the shift are opposite to each other.

When the deviation of the frequency of the FM intermediate frequency signal from the center frequency of the pass band of the band pass filter is within a predetermined frequency range, formula (4) is established, and the frequency of the FM intermediate frequency signal is band pass. When the frequency deviates from the center frequency of the pass band of the filter, the detected change in the received signal level is corrected, and the variation of the frequency of the FM intermediate frequency signal within a predetermined range from the center frequency is corrected. The fluctuation of the detection level of the received signal is suppressed within a predetermined range.

In the FM receiver according to the present invention, the multiplication value of the value X and the value Y in the calculation of the calculating means is the digital F
The output from the M demodulation circuit is characteristic. By doing so, the value X and the value Y in the calculation means are
The multipliers 1 and 2 are unnecessary, and the number of multipliers is reduced by one.

In the FM receiver according to the present invention, the digital FM demodulation circuit is a quadrature type digital demodulation circuit or an arc tangent type digital demodulation circuit.

In the FM receiver according to the present invention, the A / D-converted FM intermediate frequency signal input to the digital FM demodulation circuit is sampled at a frequency four times the FM intermediate frequency. And

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an FM receiver according to the present invention will be described below. FIG. 1 is a block diagram showing the configuration of the main part of an FM receiver according to an embodiment of the present invention.

In the FM receiver according to the present embodiment, the FM intermediate frequency signal whose amplitude is limited via the limiter 12 is A / D converted by the A / D converter 1, and then the A / D converter 1 outputs the FM intermediate frequency signal. The output digital FM intermediate frequency signal is supplied to a digital filter 2 which constitutes a bandpass filter to limit the band, and the band limited digital FM intermediate frequency signal is supplied to a quadrature type digital FM demodulation circuit 31 and received signal level. It is supplied to the detection circuit 11.
The FM demodulation output output from the digital FM demodulation circuit 31 is transmitted via the switch circuit 14.

On the other hand, the received signal level detected by the received signal level detection circuit 11 is the signal level discrimination circuit 13
And compares it with the determination level (level based on the level at which a signal should be determined to have been received) set in the signal level determination circuit 13, and when the detected reception signal level is equal to or higher than the determination level, the switch circuit 14 is turned on, and when it is below the determination level, the switch circuit 14 is turned off. The reception level detection circuit 11, the signal level determination circuit 13, and the switch circuit 14 form a squelch circuit. The determination level of the signal level determination circuit 13 is provided with a hysteresis of a predetermined width (hereinafter, also referred to as a hysteresis width of the squelch circuit).

Here, the sampling frequency fs in the A / D converter 1 is set to 4 times the frequency of the FM intermediate frequency signal, and the center frequency of the pass band of the digital filter 2 is f.
The frequency is set to s / 4. Further, the quadrature type FM demodulation circuit 31 is supplied with the digital FM intermediate frequency signal whose band is limited by the digital filter 2 and shifts the digital FM intermediate frequency signal by one sampling period, the output of the shift register 32 and the digital filter 2. And a multiplier 33 for multiplying the band-limited digital FM intermediate frequency signal.

The received signal level detection circuit 11 is composed of multipliers 5, 6 and 9, adders 7 and 10, and an absolute value calculation circuit 8. The output signal from the shift register 32 is squared by the multiplier 5, the input signal of the shift register 4 is squared by the multiplier 6, and the output of the multiplier 5 and the output of the multiplier 6 are added by the adder 7. . The FM demodulation output is supplied to the absolute value calculation circuit 8 to obtain the absolute value of the FM demodulation output, and the output of the absolute value calculation circuit is multiplied by a constant α (α> 0) in the multiplier 9 to obtain the output of the multiplier 9. The output of the adder 7 is added by the adder 10, the output of the adder 10 is supplied to the signal level determination circuit 13, and the signal level determination circuit 13 determines that the signal level based on the output of the adder 10 is at or above the determination level. Then, the switch circuit 14 is turned on and the signal level determination circuit 13 determines that the level is lower than the determination level.
When it is determined in step S1, the switch circuit 14 is controlled to the off state.

In the FM receiver according to the present embodiment configured as described above, the amplitude of the FM intermediate frequency signal is limited by the limiter, and the FM intermediate frequency signal is A / D converted by the A / D converter 1. To be converted. As described above, the sampling frequency fs of the FM intermediate frequency signal in the A / D converter 1 is set to a frequency four times the FM intermediate frequency. The A / D converted digital FM intermediate frequency signal is supplied to the digital filter 2 and band-limited.

On the other hand, the frequency of the shift pulse of the shift register 32 is also set to the frequency fs, and the signal input to the shift register 4 by the shift by the shift register 32, that is, the digital FM intermediate frequency band-limited by the digital filter 2 is set. There is a 90-degree phase difference between the signal (based on the FM intermediate frequency signal) and the digital FM intermediate frequency signal output from the shift register 32 (based on the FM intermediate frequency signal). Therefore, the multiplier 3
Digital F band-limited by the digital filter 2 by multiplication of input and output of the shift register 32 in FIG.
The M intermediate frequency signal signal is FM demodulated.

In the above description, the value based on the input signal of the shift register 4 is X (hereinafter also simply referred to as the input signal X),
If the value based on the output signal of the shift register 4 is Y (hereinafter also simply referred to as the output signal Y), the output of the multiplier 5 is Y squared, and the output of the multiplier 6 is X squared, The input of the absolute value calculation circuit 8 is XY, and the absolute value calculation circuit 8
Output is | XY |, and the output of the multiplier 9 is α | XY |
Becomes Therefore, the output of the adder 10 is (5) below.
As shown in the equation, this output is sent to the signal level determination circuit 13 as the received signal level. Here, since α is α> 0, α | XY | is equal to | αXY |.

[0032]

(Equation 5)

When the received signal level is expressed as MAG and the received signal level MAG is obtained as an effective value by the signals X and Y having the same level having a 90-degree phase difference, the received signal level MAG is calculated by the following equation (6). You can ask.

[0034]

(Equation 6)

Here, when X is Asin (2πωx), the received signal level MAG obtained by the effective value is as shown in the following equation (7).

[0036]

(Equation 7)

Further, since the relative value, not the absolute value, can be known for detecting the reception signal level, the value of the following expression (8) may be used as the reception signal level MAG without obtaining the square root.

[0038]

(Equation 8)

In this case, the square root calculation process can be omitted. Returning to this embodiment, the adder 7
Corresponds to the value of the equation (8), and the output α | XY | of the multiplier 9 is added to the output of the adder 7 as a correction value by the adder 10, but the square root calculation is unnecessary. There is no change.

The absolute value of the sine wave | Asin (2πω
When the received signal level MAG is obtained by x) |, the average value of the received signal level MAG is (2A / π).

Although the method of obtaining the absolute value is simple in processing, in digital signal processing, when the number of sampling points is small with respect to the frequency of the signal, the probability that the peak value of the input signal can be sampled becomes low. The frequency of the FM intermediate frequency signal is 1/4 of the sampling frequency fs.
When the phase relationship between the sampling pulse and the FM intermediate frequency signal is such that the value close to the peak of the FM intermediate frequency signal can be continuously sampled when it is close to the frequency of In the case of the phase relationship of being separated by a maximum of 45 °, the amplitude becomes maximum (1 / √2) lower in the case of the latter phase relationship. In the present embodiment, the frequency of the FM intermediate frequency signal is set to 1 of the sampling frequency.
Since it is set to / 4, effective value detection in which the level does not fluctuate unstable is more suitable for digital signal processing.

In the received signal level detection circuit 11, the output from the adder 10 is as shown in the equation (5), and F
Input of the shift register 32 when the frequency of the M intermediate frequency signal is deviated within a predetermined frequency range from the center frequency fs / 4 of the pass band of the digital filter 2 and there is no attenuation of the FM intermediate frequency signal by the digital filter 2. The value based on the signal is (Xmax), and the digital filter 2
The value based on the output signal from the shift register 32 when there is no attenuation of the FM intermediate frequency signal due to (Yma
x), the constant α is set so as to satisfy the following expression (9).

[0043]

[Equation 9]

On the other hand, when the center frequency fs / 4 of the pass band of the digital filter 2 and the frequency of the FM intermediate frequency signal match, the attenuation amount of the FM intermediate frequency signal passing through the digital filter 2 is the minimum. Therefore, it is not necessary to correct the received signal level. As the frequency of the FM intermediate frequency signal deviates from the center frequency fs / 4 of the pass band of the digital filter 2, the attenuation amount of the FM intermediate frequency signal passing through the digital filter 2 increases as shown in FIG. It is necessary to correct the received signal level.

Further, as the frequency of the FM intermediate frequency signal deviates from the center frequency fs / 4 of the pass band of the digital filter 2, the delay amount by the shift register 32 is affected as shown in FIG. 2 (b). , The frequency of the FM intermediate frequency signal is the center frequency f of the pass band of the digital filter 2.
When it is equal to s / 4, the delay amount by the shift register 32 is 90 degrees, and the correction of the received signal level is unnecessary.
When the frequency of the FM intermediate frequency signal deviates from the center frequency fs / 4 of the pass band of the digital filter 2 in the decreasing direction, the delay amount decreases from 90 degrees and is shifted to 0 degrees,
When the frequency of the FM intermediate frequency signal deviates in the increasing direction from the center frequency fs / 4 of the pass band of the digital filter 2, the delay amount increases from 90 degrees and is shifted to 180 degrees, and the received signal Level correction is required.

That is, when the frequency deviation between the center frequency fs / 4 of the pass band of the digital filter 2 and the frequency of the FM intermediate frequency signal increases, the FM intermediate frequency signal is attenuated by passing through the digital filter 2. The attenuation amount increases, and the frequency of the FM intermediate frequency signal in the output signal from the adder 7 decreases in accordance with the amount of deviation from the center frequency number fs / 4 of the pass band of the digital filter 2. As the frequency of the FM intermediate frequency signal deviates from 1/4 of the sampling frequency, it becomes necessary to correct the received signal level with a large correction value.

Further, when the center frequency fs / 4 of the pass band of the digital filter 2 and the frequency of the FM intermediate frequency signal match, when the received signal is not FM-modulated or the modulation index is small. , The spread of the occupied band of the FM intermediate frequency signal is small, the attenuation amount by passing through the digital filter 2 is minimum, and the correction of the received signal level is unnecessary. As the modulation index increases, the occupied band of the FM intermediate frequency signal expands, and the amount of attenuation due to passing through the digital filter 2 also increases,
It is necessary to correct the received signal level.

That is, when the received signal is not FM-modulated or the degree of modulation is low, it is not necessary to correct the received signal level. When the received signal is modulated, a large correction value is proportional to the degree of modulation. It is necessary to correct the received signal level by.

On the other hand, the phase characteristic of the shift register 32 is the characteristic shown in FIG. 2B, and when the absolute value of the output signal of the multiplier 33 is taken, it becomes a signal of the correction value | xy | By multiplying the constant α by increasing the constant α as shown by the arrow in FIG. 2C, the frequency fs /
The correction value based on the frequency deviation from 4 will increase. The output signal from the multiplier 9 is | αXY |, and the output signal from the absolute value calculation circuit 8 is as shown on the right side of the equation (9). In FIG. 2B, the broken line shows | αxy | when there is no attenuation, and the solid line shows | αxy when there is attenuation.
| Is shown.

However, the output of the multiplier 33, that is, F
The larger the modulation index, the larger the M demodulation output, and the adder 7 for the frequency deviation amount between the center frequency fs / 4 of the pass band of the digital filter 2 and the frequency of the FM intermediate frequency signal.
The direction of change of the output signal from the multiplier 9 and the direction of change of the output signal from the multiplier 9 are opposite to each other, and the adder 10 adds the output signal from the adder 7 and the output signal from the multiplier 9. As a result, the received signal level can be corrected.

Here, when the frequency of the FM intermediate frequency signal deviates from the center frequency of the pass band of the digital filter 2 within a predetermined frequency range, a constant α (0 <α ) Is set, the frequency of the FM intermediate frequency signal is corrected when the frequency is deviated within a predetermined frequency range from the center frequency of the pass band of the digital filter, and the FM intermediate frequency within the predetermined range from the deviated frequency is set. The fluctuation of the detection level of the received signal with respect to the fluctuation of the frequency of the frequency signal is suppressed within the hysteresis range of the squelch circuit as shown in FIG. Therefore, if the detection level fluctuation width of the reception signal is within the hysteresis range of the squelch circuit, the reception signal output is not turned on / off due to the frequency deviation.

FM within a predetermined frequency range
When the fluctuation of the detection level of the received signal with respect to the frequency fluctuation of the intermediate frequency signal is small and close to 0, the value of the constant α becomes a small value. FM within a predetermined frequency range determined in advance
When the fluctuation of the detection level of the received signal with respect to the frequency fluctuation of the intermediate frequency signal is large, the value of the constant α becomes a large value in proportion to the fluctuation width.

The value of the constant α will be described below. When the detection level of the received signal fluctuates by 20 dB, the center frequency fs / of the pass band of the digital filter 2
Since the deviation of the FM intermediate frequency signal with respect to 4 is large, the modulation index is large, and / or the modulation frequency is high, the distortion of the FM demodulation output becomes so large that it cannot be practically used, and a normal reception sound cannot be obtained. Therefore, when the fluctuation of the detection level of the received signal exceeds 20 dB,
It is not necessary to correct the detection level of the received signal, and it can be assumed that the maximum value of the constant α is when the variation of the detected level of the received signal is 20 dB.

The amplitude when the input signal X of the FM intermediate frequency signal that has passed through the digital filter 2 is X = Asin (2πωx), and the FM intermediate frequency signal that has passed through the digital filter 2 is not attenuated by the digital filter 2. If A is 〃A = 1〃 and the amplitude A when it is attenuated by 20dB is 〃A = 0.1〃, the value on the left side of equation (9) is 0.09 and the value on the right side (αXY) is It is 0.05α and becomes (0.99 = 0.005α) from the equation (9), and α≈198. This is the maximum value that the constant α can take.

In one embodiment of the received signal level detection circuit according to the present invention described above, for example, the frequency deviation is 5 kHz, the modulation frequency is 1 kHz, and the center frequency fs / 4 of the pass band of the digital filter 2 is 455 kHz. When the bandwidth is 12 kHz, the frequency deviation is set to 1 kHz and the constant α is set to “2”. For example, when the reception signal detection level is 0 V to 1 V, the detection level of the reception signal within the frequency range of the FM intermediate frequency signal. Change of 0.02V was suppressed to 0.0089V within the hysteresis width range of 0.01V of the squelch circuit, so that the received signal output was not turned on / off due to frequency deviation.

The output of the shift register 32 and the FM demodulation output constituting the quadrature type digital demodulation circuit 31 can be used for detecting the reception level, and the shift register and (XY) can be used for detecting the reception level. ) It is not necessary to separately provide a multiplier.

Next, another embodiment of the FM receiver according to the present invention will be described. FIG. 3 is a block diagram showing the configuration of the main part of an FM receiver according to another embodiment of the present invention.

Another embodiment of the present invention is an example in which an arc tangent type digital FM demodulation circuit 35 is used instead of the quadrature type FM digital demodulation circuit 31, as shown in FIG. In the present embodiment, the arctangent type digital FM demodulation circuit 35 includes a shift register 36 that delays the output of the digital filter 2 for one sampling period, an output of the digital filter 2 and the shift register 3.
6, a memory 37 that outputs an arctangent value based on the output of the digital filter 2 (the output of the digital filter 2 / the output of the shift register 36), the shift register 38 that delays the output from the memory 37 for one sampling period, and the memory 3
It is composed of an adder 39 for adding the output from 7 and the output of the shift register 38.

In another embodiment of the present invention, the shift register 32 in the reception signal level detection circuit 16 is used.
Of the quadrature type FM digital demodulation circuit 31 using the inputs and outputs of the shift register 36 instead of the inputs and outputs of
Is provided with a multiplier 15 for multiplying the input of the shift register 36 and the output of the shift register 36, and the output of the multiplier 15 is sent to the multiplier 9. It is the same as the detection circuit 11.

The operation of the FM receiver according to another embodiment of the present invention is similar to that of the FM receiver according to one embodiment of the present invention, and the detailed description thereof will be omitted to avoid duplication. . Since the arc tangent type digital FM demodulation circuit 35 has a large AM suppression ratio, the limiter 12 can be omitted and is omitted in other embodiments of the present embodiment.

Even when the arc tangent type digital demodulation circuit 35 is used in place of the quadrature type digital demodulation circuit 31, the output of the arc tangent type digital demodulation circuit 35 is used in place of the output of the multiplier 15. By supplying the output of the arctangent type digital demodulation circuit 35 to the multiplier 9, the multiplier 15 can be omitted, and it is not necessary to separately provide the (XY) multiplier.

[0062]

As described above, according to the FM receiver of the present invention, the signal detection level is corrected by the change of the modulation degree or the modulation frequency of the received signal and the frequency shift of the FM intermediate frequency signal, and the reception is performed. The squelch operation can be stabilized by determining the presence or absence of the received signal based on the signal level.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part showing a configuration of an embodiment of an FM receiver according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment of the FM receiver according to the present invention.

FIG. 3 is a block diagram of a main part showing a configuration of another embodiment of an FM receiver according to the present invention.

FIG. 4 is a block diagram showing a configuration of a main part of a conventional FM receiver.

[Explanation of symbols]

 1 A / D converter 2 Digital filter 5, 6, 9 and 15 Multiplier 7 and 10 Adder 8 Absolute value calculation circuit 11 and 16 Received signal level detection circuit 13 Signal level determination circuit 14 Switch circuit 31 Quadrature digital FM demodulation Circuit 35 Arc Tangent Digital FM Demodulation Circuit

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[Procedure amendment]

[Submission date] May 31, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

4. The FM receiver according to claim 1, wherein the A / D-converted FM intermediate frequency signal input to the digital FM demodulation circuit is sampled at a frequency four times the FM intermediate frequency. Characteristic FM receiver.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction contents]

Conventional example of a method according to the digital signal processing was Satoi the detection method of the received signal level is configured as shown in FIG. In FIG. 3 , the FM intermediate frequency signal is A / D converted by the A / D converter 1, and the digital FM intermediate frequency signal output from the A / D converter 1 is supplied to the digital filter 2 forming a band pass filter. Then, the band is limited, and the band-limited digital FM intermediate frequency signal is supplied to the digital FM demodulation circuit 3 and the reception signal level detection circuit 18. The FM demodulation output output from the digital FM demodulation circuit 3 is sent out via the switch circuit 14.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

[0022] In FM receiver according to the present invention, the digital FM demodulation circuit Kuodorachua digital demodulation circuits
And characterized in that.

[Procedure amendment 4]

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[Document name to be amended] Statement

[Correction target item name] Figure 3

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[Correction contents]

FIG. 3 is a block diagram showing a configuration of a main part of a conventional FM receiver.

[Procedure amendment 10]

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[Correction contents]

[Description of Reference Signs] 1 A / D converter 2 Digital filter 5, 6 and 9 Multiplier 7 and 10 Adder 8 Absolute value calculation circuit 1 1 Received signal level detection circuit 13 Signal level determination circuit 14 Switch circuit 31 Quadrature digital FM demodulation circuit

[Procedure amendment 12]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

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[Fig. 3]

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[Correction method] Deleted

Claims (5)

[Claims] 1. An FM receiver comprising a digital FM demodulation circuit for performing FM demodulation using an A / D converted FM intermediate frequency signal that has passed through a band pass filter for band limitation as an input signal, in the digital demodulation circuit. From the following, a delayed signal obtained by delaying the input signal by 90 degrees is taken out, where X is a value based on the input signal, Y is a value based on the delayed signal, and α is a constant: The frequency of the FM intermediate frequency signal is deviated within a predetermined frequency range from the center frequency of the pass band of the band pass filter, and the FM intermediate frequency signal is attenuated by the band pass filter. When the value based on the input signal when there is no noise is (Xmax), and the value based on the delayed signal when there is no attenuation of the FM intermediate frequency signal by the bandpass filter is (Ymax), ] A constant α (0 <α) is set to satisfy the above condition, the output signal from the calculating means is output as a reception signal level, and the FM demodulation output is turned on / off based on the reception signal level. Receiving machine. 2. The FM receiver according to claim 1, wherein the multiplication value of the value X and the value Y in the calculation of the calculating means is a digital F.
An FM receiver characterized in that it is an output from an M demodulation circuit. 3. The FM receiver according to claim 1 or 2, wherein the digital FM demodulation circuit is a quadrature type digital demodulation circuit. 4. The FM receiver according to claim 1 or 2, wherein the digital FM demodulation circuit is an arc tangent type digital demodulation circuit. 5. The FM receiver according to claim 1, wherein the A / D-converted FM intermediate frequency signal input to the digital FM demodulation circuit is sampled at a frequency four times the FM intermediate frequency. Characteristic FM receiver.