JPH09186314A - Mos field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax a field concentration between a drain and gate and to prevent the deterioration of the current driving capability and withstand voltage of a MOS field-effect transistor from being caused by a method wherein an electrode set at an equal potential with that in a drain electrode is formed in the vicinity of a gate electrode on at least the drain side. SOLUTION: An interlayer insulating film 11 is formed and thereafter, contact holes are formed and with one part of each high-concentration diffused region made to expose, applied electrodes are made to expose. After that, an aluminium film is formed on the entire surface and is patterned. By that, the high-concentration diffused region and the applied electrode, which are located on a drain side, are made to connect with each other and a source electrode 13 is formed simultaneously with the formation of a drain electrode 12, which is set at an equal potential with that in the applied electrode. A MOS FET is completed according to a normal production method. In the MOS FET formed in such a way, it is eliminated that a field concentration is generated only between low-concentration diffused regions and a gate electrode like a conventional MOS FET because an electric field between a drain and a gate is dispersed between the applied electrodes and the gate electrode and between the low-concentration diffused regions and the gate electrode.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an LDD (Lightly
The present invention relates to a MOS type field effect transistor (MOS type FET) having a Doped Drain structure, and particularly to a MOS type FET having a high current drive capability and a high breakdown voltage.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional method for manufacturing an N-channel MOS FET having a high breakdown voltage LDD structure. First, a gate oxide film 2 made of a silicon oxide film is formed on the surface of the semiconductor region 1 in an element formation planned region made of a P type silicon substrate or a P type well region. Ion implantation is performed through the gate oxide film 2 using the photoresist 3 as a mask, and LDD is performed on the surface of the semiconductor region 1 in the source / drain formation planned region.
An N-type low-concentration diffusion region 4 having a structure is formed (FIG. 7A).
After removing the photoresist 3, polysilicon is formed on the entire surface and patterned to form the gate electrode 5.
Here, the gate electrode 5 is formed so as to overlap a part of the low concentration diffusion region 4. As shown in the figure, the gate electrode 5 may be formed on the drain side in an offset structure.
Further, using the gate electrode 5 as a mask, ion implantation is performed through the gate oxide film 2 to form an N-type high-concentration diffusion region 6 in the N-type low-concentration diffusion region 4 (FIG. 7B). According to the usual manufacturing process of the MOS type FET, the extraction electrode and the like are formed to complete the MOS type FET.

[0003]

MO having such a structure
In the S-type FET, the low-concentration diffusion region 4 and the gate electrode 5 are formed so as to partially overlap each other, so that the gate electrode 5 is formed.
When a voltage is applied to the gate electrode, the carrier concentration in the vicinity of the gate electrode is increased, the electric field between the drain and the gate is relaxed, and the generation of hot carriers can be prevented.

However, the voltage between the gate and the drain is 10
There is no problem if the voltage is relatively low as V, but when driving at a higher voltage, even if such a structure is adopted, a high voltage is generated between the low concentration diffusion region 4 on the drain side and the gate electrode 5. It will take intensively. As a result, hot carriers are generated, and the generated hot carriers are trapped in the gate oxide film 2. Due to the hot carriers trapped in the gate oxide film, the low-concentration diffusion region 4 is partially depleted, resulting in an increase in resistance and a reduction in the current driving capability of the FET. In addition, there is a problem that the substrate current increases, causing a breakdown voltage phenomenon of the FET. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, to provide a MOS type FET having a structure that alleviates the electric field concentration between the drain and the gate, and does not cause the deterioration of the current driving capability and the breakdown voltage.

[0005]

In order to achieve the above-mentioned object, the present invention achieves the above object by forming a semiconductor region of one conductivity type and a low-concentration diffusion region of the opposite conductivity type which constitutes a source region and a drain region formed in the semiconductor region. And a high-concentration diffusion region and a gate electrode formed on the semiconductor region between the source and the drain via an oxide film, at least in the vicinity of the drain-side gate electrode, that is,
It is characterized in that an electrode having the same potential as the drain electrode is provided at a position where the electric field strength between the low concentration diffusion region on the drain side and the gate electrode is reduced.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention will be described below.
The channel MOS FET will be described as an example together with the manufacturing process. First, about 500 is formed on the surface of the semiconductor region 1 in a device formation planned region such as a P-type silicon substrate or a P-type well.
An angstrom gate oxide film 2 is formed. After that, a 3500 angstrom polysilicon film is deposited on the gate oxide film 2 by the CVD method, and patterning is performed using a photoresist to form the gate electrode 5.

Next, using the gate electrode 5 as a mask, N-type impurities are ion-implanted through the gate oxide film 2 into the semiconductor region 1 in the regions where the source and drain are to be formed, and the impurity concentration is 1 × 10 ¹⁷ to 1 ×. A low concentration diffusion region 4 of about 10 ¹⁸ cm ^-3 is formed (FIG. 1).

A gate electrode and an insulating film capable of selective etching, for example, a nitride film or an oxide film is formed on the entire surface by a CVD method. Next, anisotropic dry etching is performed to form sidewalls 7 made of a nitride film or an oxide film on the sidewalls of the gate electrode 5 (FIG. 2). Here, the lateral dimension of the sidewall 7 can be formed to a desired thickness depending on the formation thickness of the nitride film or the oxide film, and as will be described later, the dimension is required for the MOS type FET. It is appropriately selected according to the breakdown voltage.

Furthermore, a polysilicon film 8 is formed on the entire surface by 2000.
It is formed by the CVD method to a thickness of about angstrom. Here, for the polysilicon film 8, in order to reduce the resistance, doped polysilicon is used, or a non-doped polysilicon film is formed on the entire surface and then impurities are implanted. A photoresist 9 is patterned and formed on the polysilicon film 8 at the positions of the drain side sidewall 7 and the low concentration diffusion region 4 (FIG. 3).

Using the photoresist 9 as a mask, the polysilicon film 8 is removed by etching to expose the gate electrode 5 and the gate oxide film 2. The photoresist 9 is removed, and the remaining polysilicon film is used as the application electrode 10. Here, the applied electrode 10, the gate electrode 5, and the low concentration diffusion region 4 are electrically insulated by the sidewall 7 and the gate oxide film 2.

N-type impurities are ion-implanted through the gate oxide film 2 into the low-concentration diffusion region 4 using the applying electrode 10, the gate electrode 5 and the sidewall 7 as a mask, and the impurity concentration is 1 × 10 ²⁰ to 1 × 10. ^A high concentration diffusion region 6 of about ²¹ cm ^-3 is formed (FIG. 4). Here, the high-concentration diffusion region 6 is offset-formed by the size of the application electrode 10 formed on the low-concentration diffusion region 4.
During the operation of T, the application electrode 10 becomes conductive with the drain electrode, acts to accumulate majority carriers in the low concentration diffusion region 4 on the drain side, and the drain resistance can be reduced.

After forming the interlayer insulating film 11, a contact hole is formed to expose a part of the high concentration diffusion region 6 and the application electrode 10. After that, aluminum is formed on the entire surface and patterned to connect the high-concentration diffusion region 6 on the drain side and the application electrode 10, and simultaneously form the drain electrode 12 having the same potential as the application electrode 10 and the source electrode 13. (Fig. 5). Hereafter, the MOS type FET is completed according to the usual manufacturing method.

The MOS type FET thus formed is
Since the electric field between the drain and the gate is dispersed between the application electrode and the gate electrode and between the low concentration diffusion region 4 and the gate electrode, it is possible to concentrate the electric field only between the low concentration diffusion region 4 and the gate electrode as in the conventional case. Lost.

FIG. 6 shows a conventional structure and the MOS type FE of the present invention.
Regarding T, the simulation result of the maximum electric field intensity in the semiconductor region on the drain side, which is applied between the drain region and the gate electrode, is shown. In FIG. 6, the conventional process has a structure in which an applying electrode is not provided, and the sidewall 7 of the present invention is used.
Is compared with the electric field strength when the horizontal dimension of is changed. The simulation conditions were such that the gate voltage and the back gate voltage were 0 V, the electric field in the insulating film was ignored, and the drain voltage was variable in the range of 0 to 20 V.

As shown in the figure, the electric field strength increases as the drain-gate voltage (Vds) increases. However, it can be seen that the rate of increase is smaller in the MOS FET having the structure of the present invention. In addition, the lateral dimension of the sidewall 7 is in the range of 0.2 to 0.6 μm,
It can be seen that the electric field strength is relaxed almost equally.

From these results, the MOS type FET of the present invention
It can be seen that can be driven with an operating voltage larger than that of the conventional structure. Further, when the operating voltages are the same, it indicates that the electric field strength is low, so that a high voltage is not concentratedly applied between the drain side low concentration diffusion layer and the gate electrode. Therefore, generation of hot carriers can be prevented, the low-concentration diffusion layer is not partially depleted, and problems such as an increase in resistance and a reduction in current driving capability of the FET can be solved. Furthermore, it was possible to prevent the breakdown voltage from deteriorating as the electric field strength decreased.

In the above embodiment, the application electrode 10 is used.
Shows a structure formed only on the low-concentration diffusion region 4 and the sidewall 7 on the drain side. However, the structure is not limited to such a structure, and the electric field between the low-concentration diffusion region and the gate electrode is relaxed. The position can be changed appropriately. For example, the same effect can be obtained by forming it on the third wall 7 and the gate electrode 5. Further, it may be formed on the low-concentration diffusion region 4, the side wall 7, and the gate electrode 5. In this case, the gate electrode and the application electrode need to have an insulated structure. When forming the high-concentration diffusion region, another mask material may be selected as the ion implantation mask instead of the application electrode.

Although the N-channel MOS type FET has been described above as an example, the present invention is not limited to the above-described embodiment, and can be applied to the P-channel MOS type FET.

[0019]

As described above, according to the MOS type field effect transistor of the present invention, the electric field concentration between the drain and the gate is alleviated, and the generation of hot carriers can be prevented. As a result, depletion of the low-concentration diffusion layer on the drain side and increase in resistance can be prevented, and the current drive capability of the MOS field effect transistor can be improved. Further, since the substrate current does not increase due to the electric field concentration, there is an effect that the breakdown voltage can be prevented from being deteriorated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a MOS field effect transistor of the present invention.

FIG. 2 is a cross-sectional view illustrating the method of manufacturing a MOS field effect transistor of the present invention.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a MOS field effect transistor of the present invention.

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the MOS field effect transistor of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the MOS field effect transistor of the present invention.

FIG. 6 is a graph comparing the electric field strength between the drain and the gate of the present invention and the conventional MOS field effect transistor.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a conventional MOS field effect transistor.

[Explanation of symbols]

 1 semiconductor region 2 gate oxide film 3 photoresist 4 low concentration diffusion region 5 gate electrode 6 high concentration diffusion region 7 sidewall 8 polysilicon film 9 photoresist 10 applying electrode 11 interlayer insulating film 12 drain electrode 13 source electrode

Claims (2)

[Claims] 1. A semiconductor region of one conductivity type, a low-concentration diffusion region and a high-concentration diffusion region of opposite conductivity type which form a source region and a drain region in the semiconductor region, and the semiconductor between the source and the drain. A MOS type field effect transistor having a gate electrode formed on a region through an oxide film, characterized in that an electrode having the same potential as the drain electrode is provided at least near the drain side gate electrode. Field effect transistor. 2. The MOS field effect transistor according to claim 1, wherein the electrode having the same potential as the drain electrode is
It is arranged at a position where the electric field strength between the low concentration diffusion region on the drain side and the gate electrode is reduced.
OS type field effect transistor.