JPH09186310A - Solid-state image sensing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to increase the junction capacity between photodiodes without entailing a rise of a substrate shutter voltage by a method wherein the depth of second conductivity type element isolation layers is formed in a depth of a value larger than that of a depth, Which prevents an inversion layer from being formed in the surfaces of the element isolation layers and is required for performing an element isolation. SOLUTION: An N-type diffused layer 15 constituting a vertical CCD register 102 being adjacent to photodiodes is formed and a P-type diffused layer 16 is formed under the lower part of the layer 15. A P<+> element isolation layer 18 is formed on the periphery of each photodiode excluding a readout gate region 17. An insulating film 14, such as a silicon dioxide film, is formed on one main surface of an N-type silicon substrate 11 and transfer electrodes 20 and 21 consisting of a polysilicon film or the like are formed on the film 19. As the layers 18 are formed in a depth equal with that of an N-type diffused layer 13 for discharging an innate role in an element isolation, the P-N junction capacity between the photodiodes can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a CCD type solid-state image pickup device having a vertical overflow drain structure capable of operating a substrate shutter.

[0002]

2. Description of the Related Art FIG. 3 is a general interline CCD.
It is a schematic block diagram of a solid-state imaging device. Interline C
The CD type solid-state imaging device includes a plurality of photodiodes 101.
And a vertical CCD register 102 that receives and transfers the charge from the photodiode, and a horizontal CCD register 103 that receives and transfers the charge from the vertical CCD register.
And a charge detector 104 for detecting the charges transferred by the horizontal CCD register, and an output amplifier 105. The portion surrounded by the broken line is the unit pixel 106.

4A and 4B are views for explaining the structure of a unit pixel in this conventional solid-state image pickup device. FIG. 4A is a plan view and FIG. 4B is a sectional view taken along line AA in FIG. FIG. 6C is a sectional view taken along line BB in FIG. First,
The configuration of the pixel will be described. N-type silicon substrate 111
A P-type well region 112 is formed on one main surface.
An N-type diffusion layer 113 that constitutes the photodiode 101 and a P ⁺ -type diffusion layer 114 for suppressing the generation of dark current are formed inside the photodiode. Further, an N-type diffusion layer 115 that constitutes the vertical CCD register 102 and a P-type diffusion layer 116 are formed below the N-type diffusion layer 115. A P ⁺ type element isolation layer 118 is formed around each photodiode 101 except for the read gate region 117. Although not shown in the figure, an additional impurity layer may be formed near the substrate surface of the read gate region 117 for adjusting the threshold voltage. An insulating film 119 made of a silicon dioxide film or a silicon nitride film is formed on one main surface of the silicon substrate 111, and a transfer electrode 12 made of a polysilicon film or the like is formed thereon.
0 and 121 are formed. An insulating film 122 made of a silicon dioxide film or the like exists between the transfer electrodes 120 and 121. Further, a light-shielding film (not shown) made of a tungsten film, an aluminum film or the like is formed on the insulating film (not shown) made of a silicon dioxide film or the like. Further thereon, a cover film (not shown) made of a silicon dioxide film or the like is formed.

[0004]

At present, with the increase in the number of pixels and the density of solid-state image pickup devices, the size of the unit pixel 106 is 5
The size is reduced to about μm square. Along with this, the area of the photodiode 101 is reduced, and the sensitivity and capacitance of the photodiode are reduced. In order to improve this, photodiodes have been deeply formed to a depth of 1 μm or more. On the other hand, the depth of the P ⁺ type element isolation layer formed around the photodiode is such that it covers the side surface of the N type diffusion layer 115 of the vertical CCD register 102.
That is, it was formed to a depth of about 0.3 to 0.5 μm.

By the way, in the recent solid-state image pickup device used as an image input device for multimedia equipment, the one which adopts a driving system called sequential scanning is predominant. In this method, since the signal of each pixel is usually read independently, the maximum amount of signal charge corresponds to the photodiode capacitance of one pixel. On the other hand, in the case of the interlaced scanning method in which one transfer stage corresponds to two pixels, two adjacent pixels are arranged in the vertical direction.
Since it was possible to add the signal charges of the photodiodes of the pixels, it was possible to obtain a relatively large amount of signal charges. However, in a camera using a progressive scan type solid-state imaging device, if the standard signal charge amount is set to be the same in order to maintain the same S / N as that of a camera using an interlace scanning type solid-state imaging device, the dynamic range Becomes smaller. To improve this, it is necessary to further increase the photodiode capacitance.

As one method for expanding the photodiode capacitance, there is a method disclosed in Japanese Patent Laid-Open No. 60-1979. The invention described in this publication is
The junction capacitance around the photodiode is increased by locally increasing the impurity concentration of the diffusion layer around the photodiode of the solid-state imaging device using the plasma coupling element. When this idea is applied to the photodiode of FIG. 4, a new P-type diffusion layer is formed around the N-type diffusion layer 113. Here, Japanese Patent Laid-Open Publication No. Sho 6
According to 0-1979, the concentration of the P-type diffusion layer around the photodiode is set to be lower than that of the N-type diffusion layer 113 and higher than that of the P-type well region 112. For example, the concentration of the N-type diffusion layer 113 is 1 × 10 ^16.
cm ⁻³ , and the concentration of the P-type well region around it is 5 × 10
^In the case of ¹⁵ cm ⁻³ , the depletion layer width at the junction is about 0.5 μm. Since the junction capacitance is proportional to the reciprocal of the depletion layer width of the junction, the junction capacitance can be increased by increasing the concentration of the P-type diffusion layer provided around the photodiode.
For example, when the concentration is 1 × 10 ¹⁷ cm ⁻³ ,
The width of the depletion layer at the junction becomes about 0.3 μm, and the junction capacitance further increases. However, at the same time, since the P-type impurity concentration on the bottom surface of the photodiode also increases, the substrate shutter voltage applied to the substrate when sweeping the charges accumulated in the photodiode to the N-type silicon substrate 111 increases.
Alternatively, there is a problem that the substrate shutter itself does not function.

Therefore, an object of the present invention is to provide a solid-state image pickup device capable of increasing the junction capacitance of a photodiode without increasing the substrate shutter voltage.

[0008]

A solid-state image pickup device of the present invention includes a plurality of photodiodes, a vertical CCD register for receiving and transferring charges from the photodiodes,
In a solid-state imaging device including a horizontal CCD register that receives and transfers charges from the vertical CCD register, a charge detection unit that detects charges from the horizontal CCD register, and an output amplifier, the photodiode is of a first conductivity type. A first conductivity type diffusion which is selectively formed on the surface of the second conductivity type region of the surface of the semiconductor substrate and which is partitioned in contact with a second conductivity type element isolation layer having a higher impurity concentration than the second conductivity type region. A layer, and the depth of the second conductivity type element isolation layer is made larger than a value required to prevent formation of an inversion layer on the surface and perform element isolation.

Further, the width of the second conductive type element isolation layer can be made narrower at the bottom than the upper part, and the first conductive type diffusion layer can be made wider at the bottom than the upper part.

Further, the impurity concentration distribution in the depth direction of the second conductivity type element isolation layer can be made uniform by changing the acceleration voltage and performing ion implantation.

Since the second-conductivity-type element isolation layer is deeper than the value originally required for the element-isolation layer, the junction capacitance of the first-conductivity-type diffusion layer of the photodiode in contact therewith can be increased.

[0012]

FIG. 1 is a diagram for explaining the structure of a unit pixel in the first embodiment of the present invention.
FIG. 6A is a plan view, FIG. 6B is a sectional view taken along the line AA of FIG. 6A, and FIG. 6C is a sectional view taken along the line BB of FIG.

In this embodiment, a P-type well region 12 (impurity concentration of 5 × 10 ¹⁴ to 5 × 10 14-) formed on one main surface portion of an N-type silicon substrate 11 having an impurity concentration of about 1 × 10 ¹⁴ cm ^-3.
5 × 10 ¹⁵ cm ⁻³ ). P-type well region 12
N-type diffusion layer 13 (impurity concentration 5 × 10 ¹⁵
5 × 10 ¹⁶ cm ⁻³ and a depth of about 1 μm) are selectively formed to form a photodiode (101 in FIG. 3). In addition, on the surface portion of the N-type diffusion layer 14, the P ⁺ -type diffusion layer 14 (impurity concentration 10 ^17-
10 ¹⁸ cm ⁻³ ) are formed.

Further, a vertical C is provided adjacent to the photodiode.
The N-type diffusion layer 15 having a concentration of about 10 ¹⁶ to 10 ¹⁷ cm ^−3, which constitutes the CD register 102, and 5 below the N-type diffusion layer 15.
A P-type diffusion layer 16 having a concentration of about × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ is formed. Each photodiode 101
Except for the readout gate region 17, 10 ¹⁷
P ⁺ type element isolation layer 1 having a concentration of about 10 ¹⁹ cm ⁻³
8 are formed. Here, the depth of the P ⁺ type element isolation layer 18 is equal to the depth of the N type diffusion layer 13, and for example, 1
It is about μm. An insulating film 19 made of a silicon dioxide film, a nitride film, or the like is formed on one main surface of the N-type silicon substrate 11.
Are formed, and transfer electrodes 20 and 21 (which constitute a vertical CCD register together with the N-type diffusion layer 15) made of a polysilicon film or the like are formed thereon. A light-shielding film (not shown) made of a tungsten film, an aluminum film or the like is also formed between the transfer electrode 20 and the transfer electrode 21 via an insulating film (not shown) made of a silicon dioxide film or the like. Further thereon, a cover film (not shown) made of a silicon dioxide film or the like is formed.

The P ⁺ type element isolation layer 18 has a function of 0.3 to 0.
A depth of about 5 μm is sufficient, but in the present embodiment, it is deeper than that and equal to the depth of the N-type diffusion layer 13. As a result, the PN junction capacitance of the photodiode can be increased. The degree of this capacitance increase depends on the size of the photodiode. When the unit pixel size is 5 μm square and the photodiode area is 2 μm × 3.5 μm, an increase of about 20% can be estimated. If the number of pixels is further increased, the number can be further increased. On the other hand, the bottom of the photodiode is
P-type well region 12 having the same impurity concentration as the conventional one
Therefore, the substrate shutter voltage can be maintained at the same level as the conventional one.

The impurity concentration distribution in the depth direction of the P ⁺ type element isolation layer 18 is desired to be as uniform as possible. For that purpose, when using ion implantation, the acceleration voltage may be changed to perform the implantation. Here, an example of a method of forming the P ⁺ type element isolation layer 18 having a depth of about 1 μm will be described. The P ⁺ type element isolation layer 18 is formed in the same manner as before until just before the photoresist process, and the N type silicon substrate 1 is formed.
It is assumed that a thermal oxide film having a thickness of about 20 nm is formed on the first layer. The resist film having a thickness of about 3 μm coated on the thermal oxide film is patterned, and the resist film is used as a mask to form a mask.
0 keV, 250 keV, 100 keV,
And 10 at an implantation energy of about 30 keV
Boron ion implantation is performed four times at a dose of about ¹³ cm ^-2 and annealing is performed. Ion implantation with different implantation energies is performed a plurality of times in order to obtain a more uniform impurity concentration distribution. As a result, the element isolation layer can have an impurity concentration of at least 10 ¹⁷ cm ⁻³ at a depth of about 1 μm from the substrate surface. Although the case where the ion implantation is performed four times with different implantation energies is shown here, the ion implantation may be performed three times or five times or more. Furthermore, the implantation energy may be changed continuously. By using two times of ion implantation with different implantation energies, the impurity concentration is at least 10 ¹⁷ cm ⁻³ having a depth of about 0.8 μm.
The P ⁺ type element isolation layer 18 can be formed.

The present embodiment can be manufactured in the same manner as in the conventional example, only by modifying the formation process of the P ⁺ type element isolation layer and without changing to other manufacturing processes.

FIG. 2 is a diagram for explaining the structure of a unit pixel according to the second embodiment of the present invention, and FIG.
Is a plan view, FIG. 6B is a sectional view taken along line AA in FIG. 6A, and FIG. 6C is a sectional view taken along line BB in FIG. The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Around each photodiode 101, except for the read gate region 17,
A P ⁺ type element isolation layer 18A and a P ⁺ type element isolation layer 23 are formed. Here, the depth of the P ⁺ -type element isolation layer 18A is about 0.3 to 0.6 μm, and the depth of the P ⁺ -type element isolation layer 23 is equivalent to that of the N-type diffusion layer 13A.
It is about μm. In addition, the P ⁺ type element isolation layer 23 is formed of P ⁺
It is formed in a region farther from the center of the N-type diffusion layer 13A than the mold element isolation layer 18A. The ion implantation region for forming the N-type diffusion layer 13A is the P ⁺ -type element isolation layer 23.
So as to come into contact with the N-type diffusion layer 13 of the first embodiment.
It may be a little wider than the case of forming.

As described above, the P ⁺ type element isolation layers 18A, P ⁺
By forming the type element isolation layer 23 and the N-type diffusion layer 13A, the width of the N-type diffusion layer 13A becomes wider in the depth direction as a result. As a result, not only the junction capacitance can be further increased, but also an NPN transistor (N-type diffusion layer 13A- that conducts when the charge accumulated in the photodiode 101 is swept out to the N-type silicon substrate 11).
Since the current path of the P-type well region 12 (made of the N-type silicon substrate) is widened, the narrow channel effect is alleviated, and there is an advantage that the charge can be swept out with a lower substrate shutter voltage as compared with the first embodiment. is there.

In manufacturing the second embodiment, the P ⁺ -type element isolation layer 23 is formed by, for example, 450 k
Boron ion implantation with a dose amount of 10 ¹⁷ cm ⁻² is performed with an implantation energy of about eV and about 250 keV, and 100 keV is used to form the P ⁺ -type element isolation layer 18A.
And an implant energy of about 30 keV and a dose of 1
Annealing may be performed by implanting boron ions of 10 ¹⁷ cm ^-2 . Needless to say, the masks for both ion implantations are individually used so as to have the implantation widths shown in FIGS. 2B and 2C.

[0021]

According to the present invention, the junction of the photodiodes can be formed by making the depth deeper than is originally necessary to perform the isolation of the second conductivity type element in contact with the side surface of the first conductivity type diffusion layer of the photodiode. The capacity can be increased and the dynamic lens can be improved. In addition, the concentration of the second conductivity type region on the bottom surface of the photodiode can be set lower than that of the element isolation layer by one digit or more as in the conventional example, so that the substrate shutter voltage for extracting electrons to the substrate can be kept low.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1) showing a first embodiment of the present invention;
(A)), a sectional view taken along line AA of FIG. 1 (a) (FIG. 1 (b))
It is a BB line sectional view (FIG.1 (c)).

FIG. 2 is a plan view (FIG. 2) showing a second embodiment of the present invention;
2 (a)) and a sectional view taken along line AA of FIG. 2 (a) (FIG. 2 (b)).
It is a BB line sectional view (FIG. 2 (c)).

FIG. 3 is a schematic configuration diagram of a general interline CCD solid-state imaging device.

FIG. 4 is a plan view showing a conventional solid-state imaging device (see FIG.
(A)), AA line sectional view of FIG. 4 (a) (FIG. 4 (b))
FIG. 4 is a sectional view taken along line BB (FIG. 4C).

[Explanation of symbols]

11,111 N-type silicon semiconductor substrate 12,112 P-type well region 13,13A, 113 N-type diffusion layer 14,14A, 114 P ⁺ -type diffusion layer 15,115 N-type diffusion layer 16,116 P-type diffusion layer 17, 117 Read Gate Area 18, 18A, 23 P ⁺ Type Element Separation Layer 19, 22, 119, 122 Insulating Film 20, 21, 120, 121 Transfer Electrode 101 Photodiode 102 Vertical CCD Register 103 Horizontal CCD Register 104 Charge Detector 105 Output Amplifier 106 Unit pixel

Claims (3)

[Claims] 1. A plurality of photodiodes, a vertical CCD register that receives and transfers charges from the photodiodes, a horizontal CCD register that receives and transfers charges from the vertical CCD register, and a horizontal CCD register from the horizontal CCD register. In a solid-state imaging device including a charge detection unit that detects charges and an output amplifier, the photodiode is selectively formed on a surface portion of a second conductivity type region of a surface portion of a first conductivity type semiconductor substrate, A first conductivity type diffusion layer is formed in contact with the second conductivity type element isolation layer having an impurity concentration higher than that of the conductivity type region, and an inversion layer is formed on the surface of the depth of the second conductivity type element isolation layer. A solid-state image pickup device, characterized in that the junction capacitance of the photodiode is increased by increasing the value larger than a value required for element isolation to prevent the occurrence of damage. 2. The solid-state imaging device according to claim 1, wherein the width of the second-conductivity-type element isolation layer is narrower at the bottom than at the top, and the second-conductivity-type diffusion layer is wider at the bottom than at the top. 3. The solid-state imaging device according to claim 1, wherein the impurity concentration distribution in the depth direction of the second conductivity type element isolation layer is made uniform by changing the acceleration voltage and performing ion implantation.