JPH09186156A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process an insulation film on a region contg. repairing spots of an interconnection at a high accuracy for a short time, using a focused ion beam machine by forming marks for repairing the interconnection. SOLUTION: An interconnection 7 and insulation film 8 covering it are formed on a chip having semiconductor elements formed thereon and marks 9 for repairing the interconnection 7 are formed on a region contg. repairing spots of the interconnection. The mark 9 is, e.g. an elongated groove formed into the surface of the film 8 and deviation of the center position of the mark 8 from that of the repairing spot is previously obtained. After positioning the ion beam of a focused ion beam(FIB) machine on the repairing center of the interconnection 7, utilizing the obtained deviation, a hole 10 is formed into the film 7, using the FIB machine to repair the interconnection 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technology.

[0002]

2. Description of the Related Art LSI (Large Scale Integrated Circu)
Semiconductor integrated circuit devices such as it) have been promoted to have higher integration, higher speed and higher performance.

By the way, the inventor of the present invention has studied the manufacturing technology of semiconductor integrated circuit devices. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in the manufacturing process of a semiconductor integrated circuit device, when a defect of a logic circuit or the like occurs after the formation of wiring, the location of the defective logic circuit is set to FIB (Focused Ion).
Beam, Focused Ion Beam) device is used for processing, and it is conceivable to perform logic repair by connecting appropriate wirings so as to achieve a target logic circuit. The FIB apparatus can be applied to processing for accelerating and focusing ions, which have a heavier mass than that of electrons, for example, for the purpose of repairing a sample such as wiring.

As a document describing the focused ion beam device, for example, December 13, 1988.
Some are described in "Electronic Materials, December 1988, Supplement," p94-p99, published by Japan Industrial Research Institute.

[0006]

However, the aforementioned F
Since the machining positioning accuracy using the IB device depends on the target mark recognition accuracy, the stage accuracy, and the beam deflection accuracy in the FIB device, the total of them is the final positioning accuracy.

In this case, since the FIB device can obtain only the information near the surface of the wafer on which the semiconductor integrated circuit device such as the LSI is formed, the FIB device recognizes the wiring to be processed in the wafer which is flattened. Has become difficult.

Therefore, the processing position of the FIB device is moved to the processing point on the basis of the FIB target pattern formed in advance around the chip on which the semiconductor integrated circuit device such as the LSI is formed on the wafer. However, when the positioning accuracy of the FIB device is insufficient, a region other than the processing location may be machined, resulting in a problem that a machining defect occurs.

Further, since the FIB target pattern is formed on the periphery of the chip, not immediately above the processing position, the distance from the FIB target pattern, which is the origin of the FIB device, to the processing point for irradiating the ion beam. Due to the increase, there is a problem in that throughput is reduced because a long operation time is required until the processing position of the FIB device is determined.

Further, in this case, when adjusting the deviation between the processing position and the processing position of the FIB device by deflecting the beam, there is a problem that the positioning accuracy is lowered due to the adjustment error.

An object of the present invention is to provide a semiconductor integrated circuit device capable of performing processing using the FIB device with high accuracy and in a short time, and a manufacturing technique thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the manufacturing technique of the semiconductor integrated circuit device of the present invention is such that after the wiring and the insulating film are formed on the substrate having a plurality of chips in which a plurality of semiconductor elements are formed, the wiring is repaired. After the step of forming a groove as a mark in the insulating film above the region and the deviation amount between the center position of the mark and the center position of the repair of the wiring are obtained, the position of the ion beam of the FIB device is set to the center of the repair of the wiring. After the alignment is performed using the displacement amount in the position, the wiring repair work is performed using the FIB device.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 10 are views showing manufacturing steps of a semiconductor integrated circuit device according to an embodiment of the present invention.

A semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be specifically described with reference to FIGS.

First, as shown in FIGS. 1 and 2, a plurality of semiconductor elements such as MOSFETs are formed on the main surface of a semiconductor substrate 1 made of, for example, p-type silicon single crystal, and then the semiconductor elements are formed on the semiconductor elements. Form multilayer wiring.

The manufacturing technology of the semiconductor integrated circuit device according to the present embodiment is applied to, for example, an ASIC (Application Specific Intergrated C) having a plurality of functional blocks on the semiconductor substrate 1.
ircuit) and other semiconductor integrated circuit device manufacturing technology,
After the multi-layer wiring is formed, the wiring structure of the multi-layer wiring is repaired using an FIB device.

In the multi-layered wiring of this embodiment, the first-layer wiring 3 is formed on the insulating film 2, and the second-layer wiring 3 is formed on the first-layer wiring 3 with the interlayer insulating film 4 interposed therebetween. The wiring 5 is formed, and the wiring 7 of the third layer is formed on the wiring 5 of the second layer with the interlayer insulating film 6 interposed therebetween. Further, an insulating film 8 as a surface protection film is formed on the third layer wiring 7.

The surface of the insulating film 8 is polished so that the insulating film 8 has a flat surface. The first-layer wiring 3, the second-layer wiring 5, and the third-layer wiring 7 are patterned as wiring by using, for example, a photolithography technique and a selective etching technique after forming an aluminum layer or the like by a sputtering method. ing. The insulating film 2, the interlayer insulating film 4, the interlayer insulating film 6 and the insulating film 8 are, for example, a silicon oxide film, a silicon nitride film, a PSG (Phosph).
o Silicate Glass) film, BPSG (Boro Phospho Silic)
ate glass) film etc. by CVD (Chemical Vapor Depositio)
n) formed by the method.

Through holes are formed in the insulating film 2, the interlayer insulating film 4, and the interlayer insulating film 6 in regions (not shown), and the upper wiring and the lower wiring are electrically connected through the through holes. Connected to each other.

Next, for example, in order to detect the repair position of the wiring 7 that is the target of the logic repair or the like, the area to be repaired is detected by inspection such as analysis by simulation.

Next, as shown in FIG. 3 and FIG.
The device B is used to irradiate the insulating film 8 on the wiring 7 at the repair position with an ion beam, and a part of the insulating film 8 in that region is removed to form a rectangular groove serving as a mark 9. The mark 9 has a long side larger than the wiring width of the wiring 7, and various forms can be adopted as long as it is a long groove.

Next, as shown in FIGS. 5 and 6, the center of the repair position is detected by using a position detecting device such as an optical microscope to detect the amount of deviation between the position of the mark 9 and the center of the repair position. Measure ΔY.

In this case, the deviation amount ΔY is the distance Y1 between the center of the repair position and one short side of the rectangular mark 9 and the distance Y2 between the center of the repair position and the other short side of the mark 9. It can be measured and calculated from the formula Y2- (Y1 + Y2) / 2.

Since the insulating film 8 is a transparent film such as a silicon oxide film, the wiring 7 below the insulating film 8 can be easily observed by the position detecting device.

Next, as shown in FIG. 7 and FIG.
After adjusting the position of the ion beam of the apparatus B to the position of the mark 9, by shifting the position of the ion beam by the amount of deviation ΔY with reference to the mark 9, the position of the ion beam can be accurately adjusted to the center of the repair position. After the alignment, a repair hole 10 is formed in the insulating film 8 using the FIB device.

In this case, since the repair position is directly below the mark 9, the stage accuracy and the beam deflection accuracy in the FIB device can be improved, and the movement of the stage and the beam deflection operation can be reduced.

Further, since the repair position is directly below the mark 9, the repair work can be performed while confirming the repair position by the mark 9, and the machining positioning accuracy of the FIB device can be improved, so that the repair work can be performed. It can be done easily.

Next, as shown in FIGS. 9 and 10, the preliminary wiring 11 made of a conductive material such as tungsten is formed on the insulating film 8 by using, for example, a laser CVD method or the like, so that the electrical conductivity of the wiring 7 is improved. The logical connection is changed to perform logical repair.

In this case, the spare wiring 11 is formed to repair the wiring 7 such as logic repair. However, depending on the purpose of repairing the wiring 7, the area of the hole 10 is formed by using the FIB device. It is also possible to adopt a mode in which the wiring is repaired by cutting the wiring 7.

Next, an inspection such as analysis by simulation is performed to inspect whether or not the repair of the wiring 7 is completely performed.

If the result of the inspection shows that the repair is insufficient, the above-mentioned repair work using the FIB device is performed again to complete the repair.

According to the manufacturing technology of the semiconductor integrated circuit device of this embodiment, the mark 9 used for repairing the wiring 7 is provided on the insulating film 8 above the repairing position of the wiring 7, and the position of the optical microscope or the like is provided. After measuring the amount of deviation ΔY between the position of the mark 9 and the center of the repair position using a detection device, the position of the ion beam of the FIB device is adjusted to the position of the mark 9, and then the position of the ion beam is adjusted to the mark 9 The position of the ion beam is aligned with the center of the repair position with high accuracy by shifting the displacement amount ΔY with reference to, so that the hole 10 for repair can be formed with high accuracy.

As a result, according to the manufacturing technique of the semiconductor integrated circuit device of the present embodiment, the ion beam of the FIB device can be aligned with the repair region because the surface of the insulating film 8 is flattened. Even when it is difficult, the repair work can be performed with high accuracy.

Further, according to the manufacturing technique of the semiconductor integrated circuit device of the present embodiment, when forming the repair hole 10, the groove serving as the mark 9 is used as a part of the hole 10, It is possible to reduce the processing time of the hole 10 for repair, improve the processing accuracy, and reduce the throughput of repair work.

(Embodiment 2) FIG. 11 is a schematic plan view showing a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 12 is a schematic sectional view showing a section taken along the line AA in FIG.

As shown in FIGS. 11 and 12, the feature of the method of manufacturing the semiconductor integrated circuit device of the second embodiment is that the mark 12 is a cross-shaped groove.

The mark 12 according to the second embodiment includes the mark 9 as a rectangular groove (slit-shaped groove) extending in the direction orthogonal to the extending direction of the wiring 7 and the extending direction of the wiring 7. Mark 9 as an existing rectangular groove (slit-shaped groove)
It is formed on the surface of the insulating film 8 by the FIB device as a cross-shaped groove intersecting with a in the vicinity of their center points.

In the step of forming the mark 12 of the second embodiment, the insulating film 8 immediately above the repair position of the wiring 7 is irradiated with an ion beam by using the FIB device, and the insulating film 8 in that region is irradiated.
The groove to be the mark 12 is formed by removing a part of the groove.

In this case, in the formation of the mark 12, a deviation between the mark 9 and the mark 9a and the center of the repair position in the wiring 7 may occur due to variations in the manufacturing technique, but the mark 12 is a means for detecting the repair position. Therefore, there is no problem with the repair work.

In the manufacturing technique of the semiconductor integrated circuit device according to the second embodiment, the manufacturing process other than the manufacturing process for forming the mark 12 described above is almost the same as that of the first embodiment described above. Omit it.

According to the manufacturing technique of the semiconductor integrated circuit device of the second embodiment, by using the mark 12 for repair work, not only the positioning in the direction orthogonal to the extending direction of the wiring 7 to be repaired but also the positioning is performed. Since the positioning in the extending direction can also be performed, the repair work can be performed with higher accuracy.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the semiconductor integrated circuit device having the three-layer wiring structure and the manufacturing technique thereof are applied. However, the semiconductor integrated circuit device having the multilayer wiring structure such as the four-layer wiring structure and the manufacturing technique thereof are applied. it can.

Further, the semiconductor integrated circuit device and the manufacturing technique thereof according to the present invention can be applied to a semiconductor substrate or an SOI (Silicon on
Insulator) substrate and other MOSFETs, CMOS
The present invention can be applied to a semiconductor integrated circuit device having various semiconductor elements such as a BiMOS or BiCMOS structure in which an FET, a bipolar transistor or a MOSFET and a bipolar transistor are combined, and a manufacturing technique thereof.

[0049]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the manufacturing technology of the semiconductor integrated circuit device of the present invention, the position of the ion beam can be determined by providing the mark used for repairing the wiring on the insulating film above the region including the repair position of the wiring. Since the center of the repair position can be aligned with high accuracy, the repair work can be performed with high accuracy.

(2). According to the manufacturing technology of the semiconductor integrated circuit device of the present invention, even when it is difficult to align the ion beam of the FIB device with the repair region because the surface of the insulating film is flattened, Since the ion beam of the FIB device can be accurately aligned with the repair position of the wiring by using the mark, the repair work can be performed with high accuracy.

(3). According to the manufacturing technology of the semiconductor integrated circuit device of the present invention, when the repair hole is formed in the groove region which is the mark when the repair hole is formed by the FIB device, the repair hole is formed. The processing time can be shortened, the processing accuracy can be improved, and the repair work throughput can be reduced.

(4) According to the semiconductor integrated circuit device manufacturing technique of the present invention, the mark as a cross-shaped groove in which two rectangular grooves formed on the surface of the insulating film intersect is used. As a result, not only positioning of the wiring to be repaired in the extending direction but also positioning in the direction orthogonal to the wiring can be performed, so that the repair work can be performed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a section taken along the line AA in FIG. 1;

FIG. 3 is a schematic plan view showing a manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a cross section taken along the line AA in FIG.

FIG. 5 is a schematic plan view showing the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.

6 is a schematic cross-sectional view showing a cross section taken along the line AA in FIG.

FIG. 7 is a schematic plan view showing the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.

8 is a schematic cross-sectional view showing a cross section taken along the line AA in FIG.

FIG. 9 is a schematic plan view showing a manufacturing process of the semiconductor integrated circuit device which is the embodiment of the present invention.

10 is a schematic cross-sectional view showing a cross section taken along the line AA in FIG.

FIG. 11 is a schematic plan view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

12 is a schematic cross-sectional view showing a cross section taken along the line AA in FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3 wiring 4 interlayer insulating film 5 wiring 6 interlayer insulating film 7 wiring 8 insulating film 9 mark 9a mark 10 hole 11 preliminary wiring 12 mark

Front Page Continuation (72) Takako Hashimoto, Inventor Takako Hashimoto, 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hitsuritsu Cho-LS Engineering Co., Ltd. (72) Inventor Toshio Yamada 2326 Imai, Ome-shi, Tokyo Address Hitachi, Ltd. Device Development Center

Claims (9)

[Claims] 1. A wiring and an insulating film covering the wiring are provided on a chip on which a plurality of semiconductor elements are formed, and the wiring is repaired on the insulating film above a region including a repair position of the wiring. A semiconductor integrated circuit device, characterized in that a mark used at the time is provided. 2. The semiconductor integrated circuit device according to claim 1, wherein the mark is a positioning mark for repairing the wiring by using an FIB device. 3. The semiconductor integrated circuit device according to claim 1, wherein the mark is a long groove formed on the surface of the insulating film. 4. The semiconductor integrated circuit device according to claim 1, wherein the mark is a cross-shaped groove in which long grooves formed on the surface of the insulating film intersect. Integrated circuit device. 5. A step of forming a wiring and an insulating film on a substrate having a plurality of chips on which a plurality of semiconductor elements are formed, and a mark on the insulating film above the repaired area of the wiring. A step of forming a groove; a step of obtaining a deviation amount between a center position of the mark and a center position of repair of the wiring; and a step of using an ion beam position of the FIB device as a center position of repair of the wiring. After doing the alignment,
And a step of repairing the wiring by using a FIB device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the mark is a long groove formed on the surface of the insulating film. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the mark is a cross-shaped groove in which long grooves formed on the surface of the insulating film intersect. Manufacturing method of semiconductor integrated circuit device. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein in the step of repairing the wiring using an FIB device, a hole is formed in the insulating film. A method of manufacturing a semiconductor integrated circuit device, comprising: 9. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the repair of the wiring is a step of forming a repair wiring electrically connected to the wiring. Alternatively, a method of manufacturing a semiconductor integrated circuit device, which comprises a step of cutting an area for repairing the wiring.