JPH0918531A - Digital demodulator - Google Patents

Abstract

PURPOSE: To prevent the error rate of demodulated data from increasing because of the use of an A/D converter which does not have sufficient high-frequency characteristics by providing a frequency characteristics correcting means between the A/D converter and a digital processing circuit. CONSTITUTION: Digital orthogonally demodulated signals outputted by A/D converters 25I and 25Q are filtered by frequency characteristic correcting circuits 51I and 51Q according to frequency characteristics reverse to the frequency characteristics that the A/D converters 25I and 25Q have and then supplied to a complex multiplier 26. Namely, the complex multiplier 26 is supplied with the digital orthogonally modulated signals equivalent to those signal in the case wherein conversion is performed by A/D converters having flat frequency characteristics up to a high-frequency range. Therefore, the deterioration in frequency characteristics of the A/D converters 25I and 25Q which is one of causes of the increase in error rate is corrected by the frequency characteristic correcting circuits 51I and 51Q before digital processing for removing frequency detuning, and consequently demodulation performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator provided in, for example, radio equipment for satellite communication or satellite broadcasting, or mobile equipment such as mobile phones.

[0002]

2. Description of the Related Art In a wireless communication system for transmitting a video signal, an audio signal, etc., a digital modulation method is adopted in order to improve transmission quality and frequency utilization efficiency. For example, in the terrestrial microwave circuit, etc.
6-ary quadrature amplitude modulation (16QAM; Quadrature Amplitude)
Modulation) method and 64-value quadrature amplitude modulation (64QA
M) method is used, and in satellite lines and mobile communication lines, two-phase phase modulation (BPSK;
B Phase Shift Keying) and quadrature phase modulation (QPSK;
Quadrature Phase Shift Keying) method is generally used.

FIG. 12 shows an example of the configuration of a demodulator adopting the QPSK system, which is a quadrature quasi-coherent detection type QPSK demodulator. In the figure, a QPSK modulated wave signal supplied from a receiver circuit (not shown) is first input to the quadrature detection circuit 21. The quadrature detection circuit 21 includes multipliers 22I and 22Q, a local oscillator 23, and a distributor 24. The multipliers 22I and 22Q use the QPSK.
Quadrature detection is performed by multiplying the modulated wave signal by a local oscillation signal having a phase difference of 90 °. The local oscillation signal is generated by dividing the fixed frequency generated from the local oscillator 23 into two by the distributor 24 and phase-shifting one of them by 90 °.

The analog demodulated signals output from the multipliers 22I and 22Q are converted into digital signals by the A / D converters 25I and 25Q, and then input to the complex multiplier 26. The complex multiplier 26 performs exactly the same operation as the frequency converter in the intermediate frequency band in the base band, and the complex multiplication result is input to the digital low pass filters (LPF) 27I and 27Q. The digital low-pass filters 27I and 27Q are filters that form transmission characteristics required to prevent intersymbol interference in the transmission of digital data, and are generally called rolls when combined with the filter characteristics on the transmission side. It is designed to obtain off characteristics. Therefore, the digital demodulated signals output from the digital low-pass filters 27I and 27Q are spectrum-shaped so that the eye opening ratio is sufficiently large.

The digital low-pass filter 27I,
The digital demodulated signal output from 27Q is input to the complex multiplier 28. The complex multiplier 28 is a frequency converter for the PLL realized in the baseband. The output of the complex multiplier 28 is branched into four, and the clock recovery circuit 2
9, the data reproduction circuit 30, the phase comparator 31, and the frequency error detection circuit 32, respectively.

In the clock recovery circuit 29, the symbol timing component in the detected signal is extracted, and the recovered clock synchronized with the extraction timing is generated. Then, this reproduced clock is fed back to the A / D converters 25I and 25Q as a sampling clock. The data reproducing circuit 30 reproduces the QPSK data by binarizing the input signal at the symbol timing.

The phase comparator 31 detects the phase difference between the digital demodulated signal and the oscillation output of the numerically controlled oscillator (NCO) 33, and the phase difference information is subjected to the numerical control via the loop filter 34 for carrier regeneration. It is input to the frequency control terminal of the oscillator 33. The numerically controlled oscillator 33 is composed of a cumulative adder that does not detect an overflow, and repeats the adding operation up to its dynamic range according to the value of the phase difference information input to the frequency control terminal. That is, the oscillation operation is performed in a cycle according to the value of the phase difference information. The oscillation output of the numerically controlled oscillator 33 is branched into two and input to the data conversion circuits 35I and 35Q. The data conversion circuits 35I and 35Q respectively convert the oscillation output into oscillation signals having a sine waveform and a cosine waveform and feed them back to the complex multiplier 28.

That is, a digital loop for carrier regeneration is provided by a loop loop that returns from the phase comparator 31 to the complex multiplier 28 via the loop filter 34, the numerically controlled oscillator 33 and the data conversion circuits 35I and 35Q.
L is constructed.

The frequency error detection circuit 32 detects the frequency error Δf between the detection signal and the local oscillation signal. Then, this frequency error signal is smoothed by the AFC loop filter 36 and then supplied to the frequency control terminal of the numerically controlled oscillator (NCO) 37. This numerically controlled oscillator 37
An oscillation signal composed of a sawtooth wave having a frequency corresponding to the smoothed signal having the frequency error Δf is output. This oscillation output is converted into an oscillation signal having a sine waveform and a cosine waveform by the data conversion circuit 38, and then fed back to the complex multiplier 26 as a frequency conversion carrier.

That is, an automatic frequency control (AFC) loop is constructed by a loop loop that returns from the frequency error detection circuit 32 to the complex multiplier 26 via the AFC loop filter 36, the numerically controlled oscillator 37 and the data conversion circuit 38. .

The loop switching control circuit 39 supplies a loop switching signal to the loop filter 34 of the carrier regeneration PLL and the loop filter 36 of the AFC loop. As a result, when the demodulation operation is started, the AFC loop is set to the operating state, the carrier regeneration PLL is set to the non-operating state, and when the AFC loop is set to the hold state after a certain period of time, the carrier regeneration PLL loop is set. PLL for carrier regeneration with the filter 34 set to the operating state
Then, the PLL operation is started.

On the other hand, FIG. 13 shows an example of the construction of an orthogonal synchronous detection type QPSK demodulator which is different from the orthogonal quasi synchronous detection type QPSK demodulator described above. In the figure, the same parts as those in FIG. 12 are designated by the same reference numerals and detailed description thereof will be omitted.

QPS output from a receiver circuit (not shown)
The K modulated wave signal is branched into two and input to the multipliers 22I and 22Q, respectively. In these multipliers 22I and 22Q, the QPSK modulated wave signal is multiplied by the local oscillation signal having a phase difference of 90 °, and thereby quadrature detection is performed.
The analog demodulated signal obtained by this quadrature detection is A /
After being converted into a digital demodulated signal by the D converters 25I and 25Q, a digital low pass filter (LPF)
It is input to 27I and 27Q, and the spectrum is shaped here. Then, the spectrum-shaped digital demodulated signal is input to the complex multiplier 28, frequency-converted therein, and then input to the clock recovery circuit 29, the data recovery circuit 30, the phase comparator 31, and the frequency error detection circuit 32, respectively. .

Further, the AFC loop of this quadrature synchronous detection type QPSK demodulator is constructed as follows. That is,
The digital demodulated signal output from the complex multiplier 28 is
It is input to the frequency error detection circuit 32, where the frequency error Δf between the digital demodulated signal and the local oscillation signal is detected. The detection signal of this frequency error Δf is A
After being smoothed by the FC loop filter 36, it is supplied to the frequency control terminal of the numerically controlled oscillator 37. The numerically controlled oscillator 37 outputs an oscillation signal composed of a sawtooth wave having a frequency corresponding to the smoothed signal having the frequency error Δf, and the oscillation output is input to the frequency multiplication circuit 40.

The frequency multiplication circuit 40 has a data converter 41 for converting the oscillation signal composed of the sawtooth wave output from the numerically controlled oscillator 37 into a sine wave, and the signal converted by the data converter 41 is The digital / analog (D / A) converter 42 converts the analog signal. The output signal of the D / A converter 42 is the phase detector 4
3 is input. The phase detector 43 detects the phase difference between the output signal of the D / A converter 42 and the output signal of the frequency divider 46, and outputs a signal having a voltage corresponding to this phase difference. The signal output from this phase detector 43 is
Voltage controlled oscillator (VCO) after being amplified by amplifier 44
45. The voltage controlled oscillator 45 outputs an oscillation signal having a frequency corresponding to the voltage value of the signal output from the amplifier 44. This oscillating signal is frequency-divided by the frequency divider 46 into 1 / N and then fed back to the phase detector 43. Along with this, the distributor 24 is also used as a local oscillation signal.
Is supplied to the multipliers 22I and 22Q for quadrature detection after being converted into an in-phase (0 °) local oscillation signal and a 90 ° phase-shifted local oscillation signal in the quadrature in the distributor 24. .

As described above, two types of Q that have been conventionally used
The configuration of the PSK demodulator is shown, but in any type of demodulator, digital processing is performed in the data recovery circuit, clock recovery circuit, carrier recovery circuit, AFC loop, etc. Are provided with A / D converters 25I and 25Q.

By the way, recently, a QPSK modulation system having a high bit rate such as a bit rate of 40 MHz or more has been studied in response to a demand for a higher transmission rate. In the QPSK demodulator used in such a system,
A with flat frequency characteristics up to high band area
It is desirable to use a / D converter. However, an A / D converter having a flat frequency characteristic up to a high band region is generally expensive and unsuitable for use in products intended for mass production.

[0018]

As described above, in the conventional QPSK demodulator, digital signal processing is performed in order to improve demodulation performance. Therefore, the analog quadrature demodulated signal is converted into A / D converters 25I and 25Q. Are converted into digital signals with. This A / D converter 25I, 25Q
Considering the use in a high bit rate system, it is necessary to have a flat frequency characteristic up to a high band region. However, A / with flat high frequency characteristics
D converters are generally expensive and unsuitable for use in products intended for mass production.

Further, if an inexpensive A / D converter is used with priority on price, a flat high frequency characteristic is not guaranteed, so that the demodulation data error is caused by the deterioration of the frequency characteristic by the A / D converter. There is a risk that the rate will increase and the demodulation performance will deteriorate.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the error rate of demodulated data due to the use of an A / D converter which does not have sufficient high frequency characteristics. It is an object of the present invention to provide a digital demodulator which is inexpensive, suitable for mass production, and has high demodulation performance by preventing an increase.

[0021]

To achieve the above object, a digital demodulator of the present invention comprises an analog / digital converter provided for supplying an analog demodulated signal to a digital processing circuit, and the digital processing circuit. A frequency characteristic correcting means is provided between the two, and the frequency characteristic correcting means corrects the deterioration of the frequency characteristic by the analog / digital converter.

The present invention also provides a spectrum shaping filter for shaping the spectrum of the digital demodulated signal output from the analog / digital converter between the analog / digital converter and the digital processing circuit. Is characterized in that the function of the frequency characteristic correction means is also used as the spectrum shaping filter.

Each of the following configurations can be considered as the frequency characteristic correcting means. That is, the first configuration is analog /
The correction characteristic is fixedly set in the correction unit that corrects the frequency characteristic of the digital demodulated signal output from the digital converter.

The second configuration is to provide an input means for inputting the correction characteristic and set the correction characteristic input by the input means in the correction section. A third configuration is provided with a correction characteristic storage unit that stores in advance a plurality of correction characteristics corresponding to a plurality of analog / digital converters that are expected to be used, and a specifying unit for specifying the type of the correction characteristics. The correction characteristic designated by the designation means is selectively read from the correction characteristic storage unit and set in the correction unit.

Furthermore, according to the present invention, the frequency characteristic correcting means does not correct the frequency characteristic of the digital demodulated signal output from the analog / digital converter within a predetermined period from the start of reception of the digital modulated wave signal. It is also characterized in that the frequency characteristic of the digital demodulated signal is corrected after the lapse of the predetermined period.

[0026]

As a result, according to the present invention, the deterioration of the frequency characteristic in the analog / digital converter is corrected by the frequency characteristic correcting means. Therefore, even if an analog / digital converter that does not have a flat frequency characteristic is used, it is possible to suppress the data error rate and obtain sufficient demodulation performance, and use an inexpensive analog / digital converter. Therefore, the cost of the product when it is mass-produced can be reduced.

Further, when the spectrum shaping means composed of, for example, a roll-off filter is provided on the subsequent stage side of the analog / digital converter, the function of the frequency characteristic correction means is also used for the spectrum shaping filter.
It is not necessary to provide the frequency characteristic correction unit independently, and thereby the circuit configuration can be downsized and the cost can be reduced.

If the frequency characteristic correction means is constructed so that the correction characteristics are fixedly set in the correction section composed of, for example, a digital filter, the function of controlling the correction characteristics becomes unnecessary. The configuration and control procedure can be simplified. It should be noted that if the correction characteristic is fixed to one, if it is necessary to replace the analog / digital converter after the start of use, it may not be possible to deal with this replacement. If the types are the same and the variation in the frequency characteristics is guaranteed within a certain range, no problem occurs.

Further, when the frequency characteristic correcting means is constituted so that the correcting characteristic can be inputted by the inputting means and the inputted correcting characteristic is set in the correcting portion, it is used both when assembling the product and when exchanging the parts. It is possible to set the optimum correction characteristic each time according to the frequency characteristic of the analog / digital converter. Therefore, the demodulation with the best characteristics can always be obtained by using any analog / digital converter.

Further, the frequency characteristic correction means stores a plurality of correction characteristics corresponding to a plurality of analog / digital converters which are expected to be used in advance in the storage section, and the correction characteristics input and designated by the designating means are described above. If the configuration is such that it is read from the storage unit and set in the correction unit, it is not necessary to input all the correction characteristics of the analog / digital converter each time when assembling a product or replacing parts, which makes it relatively easy and It is possible to set a correction characteristic suitable for the frequency characteristic of the digital converter.

Further, according to the present invention, the frequency characteristic correcting means does not perform the frequency characteristic correcting operation within a predetermined period from the reception start time of the digital modulated wave signal, but the frequency characteristic correcting operation after the predetermined period has elapsed. By doing so, the time required for the demodulator to rise can be shortened.

[0032]

【Example】

(First Embodiment) FIG. 1 shows the QPSK according to this embodiment.
It is a circuit block diagram which shows an example of a structure of the digital mobile telephone apparatus provided with the demodulator.

In FIG. 1, a radio carrier signal sent from a base station (not shown) via a radio channel is received by an antenna 1 and then input to a receiving circuit (RX) 3 via an antenna duplexer (DUP) 2. Then, the received local oscillation signal output from the frequency synthesizer (SYN) 4 is mixed and frequency-converted into a received intermediate frequency signal. The received intermediate frequency signal is QPSK described later.
It is input to the demodulator (DEM) 6. In this QPSK demodulator 6, digital demodulation processing of the received intermediate frequency signal is performed. The demodulated data obtained by this demodulation processing is input to a time division multiple access circuit (TDMA) 7, where the time slots destined for the own device are separated and extracted for each transmission frame.

The demodulated data output from the TDMA circuit 7 is subsequently subjected to an error correction code decoding circuit (CH-COD).
8 and is subjected to error correction decoding processing. The error-correction-decoded demodulated data is input to the voice code decoding circuit (SP-COD) 9 and subjected to voice decoding processing, whereby the digital received signal is reproduced. The digital reception signal is converted into an analog reception signal by the D / A converter 10 and then supplied to the speaker 11 via a voice amplifier (not shown), and the speaker 11 outputs the signal in a loud voice.

On the other hand, the voice transmitted by the speaker is the microphone 1
2 collects the sound, converts it into a transmission signal, further amplifies it to a predetermined level by a transmission amplifier (not shown), and then A
It is input to the / D converter 13. Then, the A / D converter 13 samples the signal at a predetermined sampling period, thereby converting it into a digital transmission signal composed of a sample pulse train. After the acoustic echo is canceled by an echo canceller (not shown), this digital transmission signal is input to the voice code decoding circuit 9 and voice coded there.

The voice-encoded digital transmission signal is input to the error correction code decoding circuit 8 together with the control signal output from the control circuit 17, and is error correction coded there. Then, this error correction coded digital transmission signal is input to the TDMA circuit 7. This TDMA
In the circuit 7, a transmission frame corresponding to the time division multiple access (TDMA) system is generated, and a process for inserting the digital transmission signal in the time slot assigned to the own device in the transmission frame is performed. This TDM
The digital transmission signal output from the A circuit 7 is subsequently input to the QPSK modulator 14.

In this QPSK modulator 14, a transmission intermediate frequency signal digitally modulated by the digital transmission signal is generated, and this transmission intermediate frequency signal is not shown in D.
After being converted into an analog signal by the / A converter, it is input to the transmission circuit (TX) 5. In the transmission circuit 5, the modulated transmission intermediate frequency signal is mixed with the transmission local oscillation signal output from the frequency synthesizer 4, and thereby converted into a radio carrier frequency corresponding to a radio communication channel. Then, this radio carrier signal is controlled to a predetermined transmission power level by a transmission power amplifier (not shown),
The signal is transmitted from the antenna 1 to the base station (not shown) via the antenna duplexer 2.

Reference numeral 18 is an operation input section having dial keys and various function keys, 19 is a display section using a liquid crystal display and a light emitting diode, and these operation input section 18 and display section 19 are on a panel of the apparatus. It is arranged. Also,
Reference numeral 16 is a power supply circuit, which generates a desired operating voltage Vcc based on the output of the battery 15 which is a rechargeable secondary battery, and supplies it to each of the circuits.

By the way, the QPSK demodulator 6 is constructed as follows. This QPSK demodulator 6 is a quadrature quasi-synchronous detection type QPSK demodulator, and FIG. 2 is a circuit block diagram showing its configuration. In the figure, the same parts as those in FIG. 12 are designated by the same reference numerals and detailed description thereof will be omitted.

Frequency characteristic correction circuits 51I and 51Q are provided between the A / D converters 25I and 25Q and the complex multiplier 26. The frequency characteristic correction circuits 51I and 51Q are
This is for correcting the frequency characteristics of the / D converters 25I and 25Q, and is configured as shown in FIG. 3, for example.

That is, the frequency characteristic correction circuits 51I, 5
1Q includes a transversal filter, and includes a shift register in which a plurality of delay units (511 to 515 in the figure) are connected in series, a plurality of multipliers 521 to 525, and an adder 530. The digital quadrature demodulated signals output from the A / D converters 25I and 25Q are input terminals 51
It is serially shifted and input to the shift register through 0. Then, this shift-input digital quadrature demodulation signal is output in parallel from the shift register and input to the multipliers 521 to 525 each time 1-bit shift input is performed. In these multipliers 521 to 525, the digital quadrature demodulated signal is multiplied by tap coefficients T11 to T15 which determine the filter characteristic. Then, the digital quadrature demodulated signals multiplied by the tap coefficients T11 to T15 are combined by the adder 530 and then output terminal 540.
From the output to the complex multiplier 26.

Here, the tap coefficients T11 to T15 are set as follows. That is, assume that the frequency characteristics of the A / D converters 25I and 25Q are such that the gain decreases as the frequency increases as shown in FIG. In this case, the correction characteristics of the frequency characteristic correction circuits 51I and 51Q are such that the A / D converter 25 has a gain of 1.0 as the center.
It may be any line symmetrical with respect to the frequency characteristics of I and 25Q, and is set as shown in FIG. 5, for example. Then, in order to realize this correction characteristic, the tap coefficients T11 to T11
T15 is defined.

The tap coefficients T11 to T15 are
For example, at the time of assembling inspection of a mobile phone device, it is determined by an inspector according to the characteristics of the A / D converters 25I and 25Q,
It is set by directly inputting to the tap input terminal of the transversal filter using an input device such as a ROM.

With such a configuration, the digital quadrature demodulated signals output from the A / D converters 25I and 25Q are output by the frequency characteristic correction circuits 51I and 51Q.
After being filtered in accordance with a frequency characteristic opposite to the frequency characteristic of the A / D converters 25I and 25Q, it is supplied to the complex multiplier 26. That is, the complex multiplier 26 is supplied with a digital quadrature demodulation signal equivalent to the case where the complex multiplier 26 is converted by the A / D converter having a flat frequency characteristic up to the high band region as shown in FIG. Will be.

Therefore, in the QPSK demodulator of this embodiment, the A / D converters 25I and 25Q, which have been one of the causes of the increase in the error rate before the digital processing for removing the frequency detuning, are performed. The deterioration of the frequency characteristic can be corrected by the frequency characteristic correction circuits 51I and 51Q, and thus the demodulation performance can be improved. In addition, an inexpensive A / D converter 25I, 2 which does not have flat high frequency characteristics
Since 5Q can be used as it is, the mass production cost of the QPSK demodulator can be reduced.

(Second Embodiment) This embodiment is based on QPSK.
Quadrature detection circuit 1 and A / D converter 25 of demodulator
When all parts except I and 25Q are integrated, tap coefficient data which is a correction characteristic is input from the operation input unit 18 of the mobile phone device, and the tap coefficient data is input from the control unit 17 in the integrated circuit. The frequency characteristic correction circuit is configured to be transferred and set via the bus of the control unit 17.

FIG. 7 is a circuit block diagram showing the configuration of the frequency characteristic correction circuits 52I and 52Q according to this embodiment. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted.

A bus decode circuit 550 is provided in each of the frequency characteristic correction circuits 52I and 52Q. The bus decoding circuit 550 is used by the control unit 17 to control the data bus 1
The tap coefficient data transferred via 7a is decoded, and the decoded tap coefficients T21 to T25 are supplied to the multipliers 521 to 525.

With such a configuration, the A / D converter 2
Tap coefficient data corresponding to the frequency characteristics of 5I and 25Q can be input and set from the operation input unit 18 of the mobile phone device. Therefore, the tap coefficient can be set by a simple operation not only during the assembly inspection of the mobile phone device but also when the A / D converters 25I and 25Q are replaced after the start of use for repair or the like. be able to.

Although the tap coefficient data is input from the operation input unit 18 in the second embodiment, the following modification may be considered. That is, a memory including a ROM or a RAM for storing tap coefficient data is provided in the control unit 17 or attached to the transversal filter, and the frequency characteristics of a plurality of types of A / D converters that are expected to be used are provided. The tap coefficient data is stored in the memory in advance. Then, the inspector or the maintenance person operates the operation input unit 1
When the type data of the A / D converter is input from 8, the tap coefficient data corresponding to the type data is selectively read from the memory and supplied to the bus decoding circuit 550 of the transversal filter.

With this configuration, the inspector or the maintenance person can perform A / D conversion when inputting and setting the tap coefficient data.
It is only necessary to input one or two digits of the type data of the converter, which simplifies the setting operation.

(Third Embodiment) This embodiment is based on QPSK.
In the case where the digital processing circuit including all parts other than the quadrature detection circuit 1 of the demodulator, that is, the A / D converter and the frequency characteristic correction circuit are integrated as one LSI, the frequency characteristic correction circuit A tap coefficient fixed storage unit is provided inside, and a tap coefficient corresponding to the frequency characteristic of the A / D converter is fixedly stored in advance in the tap coefficient fixed storage unit and stored in the tap coefficient fixed storage unit. The tap coefficient is given to each multiplier.

FIG. 8 is a circuit block diagram showing the configuration of the frequency characteristic correction circuits 53I and 53Q according to this embodiment. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted.

A tap coefficient fixed storage unit 560 is provided in each of the frequency characteristic correction circuits 53I and 53Q. The tap coefficient fixed storage unit 560 stores a tap coefficient value T3 corresponding to the frequency characteristic of the A / D converter incorporated in the LSI.
1 to T35 are stored in advance. When the use is started, the tap coefficient values T31 to T35 stored in the storage unit 560 are fixedly provided to the multipliers 521 to 525, respectively.

In such a configuration, the A / D converter has the LS
Since it is built in I, it cannot be replaced.
Therefore, fixing the tap coefficient value does not cause any problem. Further, since the tap coefficient values T31 to T35 can be fixed, it is not necessary to change the tap coefficient value after starting the use of the apparatus, and the configuration of the frequency characteristic correction circuit can be simplified.

(Fourth Embodiment) FIG. 9 is a circuit block diagram showing the structure of a quadrature synchronous detection type QPSK demodulator according to the fourth embodiment of the present invention. In the figure, the same parts as those in FIG. 13 are designated by the same reference numerals and detailed description thereof will be omitted.

Between the A / D converters 25I and 25Q and the complex multiplier 26, correction / low-pass filters 62I and 62 are provided.
Q is provided. These correction / low pass filters 62
I and 62Q are transversal filters, and have a function of correcting the frequency characteristics of the A / D converters 25I and 25Q in addition to the function as a roll-off filter.

That is, the correction / low pass filter 62
The filter characteristics of I and 62Q are the same as the roll-on characteristics that form the transmission characteristics required to prevent intersymbol interference in digital data transmission, and the A / D converters 25I and 25
It is set to a combination of correction characteristics for correcting the Q frequency characteristics. For example, if the roll-off characteristic is as shown in FIG. 10, the roll-off characteristic is set to the filter characteristic shown in FIG. 11, which is obtained by adding the correction characteristic shown in FIG.

With such a configuration, the digital quadrature demodulated signals output from the A / D converters 25I and 25Q are filtered by the roll-off characteristic in the correction / low pass filters 62I and 62Q as in the conventional case. At the same time, after being filtered in accordance with the correction characteristic set to correct the frequency characteristic of the A / D converters 25I and 25Q, it is supplied to the complex multiplier 28. That is, deterioration of the frequency characteristics of the A / D converters 25I and 25Q is eliminated and the digital quadrature demodulation signal spectrally shaped only by the roll-off characteristics is input to the complex multiplier 28.

Therefore, in the QPSK demodulator of the present embodiment, the digital quadrature demodulated signal equivalent to the case of being converted by the A / D converter having the flat frequency characteristic up to the high band region is used in the digital processing circuit section. Can be supplied to. Therefore, the demodulation performance can be improved without being affected by the deterioration of the frequency characteristics of the A / D converters 25I and 25Q, which is one of the causes of the increase in the error rate. Also, an inexpensive A / that does not have flat high-frequency characteristics
Since the D converters 25I and 25Q can be used as they are, the mass production cost of the QPSK demodulator can be reduced.

Further, the characteristic deterioration of the A / D converters 25I and 25Q is corrected by combining the correction characteristic with the filter characteristic of the existing roll-off filter.
Therefore, it is not necessary to newly provide a correction circuit, which has the advantage that it can be realized with a simple configuration without adding any hardware.

The correction / low-pass filter 62
Regarding the configurations of I and 62Q, as described in the second embodiment, the tap coefficient data that is the correction characteristic is input from the operation input unit 18 of the mobile phone device, and this tap coefficient data is input from the control circuit 17 to the above. Correction / low pass filter 62
I / 62Q transfer via data bus for correction /
The low pass filters 62I and 62Q may be configured to be decoded by a bus decoder and applied to each multiplier.

Further, as described in the third embodiment,
All parts other than the quadrature detection circuit 1 of the QPSK demodulator, that is, the digital processing circuits including the A / D converters 25I and 25Q and the correction / low-pass filters 62I and 62Q are integrated as one LSI. In this case, the correction / low-pass filters 62I and 62Q are provided with tap coefficient fixed storage sections, and the A / D converters 25I and 25I
The tap coefficient corresponding to the frequency characteristic of Q may be fixedly stored in advance in the tap coefficient fixed storage section, and the tap coefficient stored in the tap coefficient fixed storage section may be given to each multiplier. .

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the frequency correction circuit is always set to the operating state. However, the frequency correction operation is not performed for a certain period immediately after the start of reception and the through state is set, and the frequency correction operation is performed after the reception state becomes stable. The frequency correction circuit may be controlled to perform. This makes it possible to prevent the time constant of the frequency correction circuit from adversely affecting the reception start-up operation, thereby preventing an increase in the time required for the reception start-up.

In each of the above-described embodiments, the case where the QPSK demodulator of the present invention is provided in the portable telephone device has been described as an example. However, a video receiving device for receiving and displaying a digitally modulated video signal and a personal / personal The digital demodulator of the present invention may be applied to an information terminal device such as a computer or a workstation, a wireless LAN terminal device, or the like.

In addition, a frequency characteristic correction circuit and correction /
The specific circuit configuration of the transversal filter used as a low-pass filter, the number of taps, the setting method of the correction characteristic, the configuration for setting, the type of the digital modulation method, etc. are within the scope of the present invention. Can be modified in various ways.

[0067]

As described above in detail, according to the present invention, the frequency characteristic correction is performed between the analog / digital converter provided for supplying the analog demodulated signal to the digital processing circuit and the digital processing circuit. By providing a means for correcting the deterioration of the frequency characteristic by the analog / digital converter by the frequency characteristic correcting means, even if an A / D converter which does not have a sufficient high frequency characteristic is used, It is possible to prevent an increase in the error rate of demodulated data due to, and thereby to provide a digital demodulator that is inexpensive, suitable for mass production, and has high demodulation performance.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an example of a configuration of a digital mobile phone device including a QPSK demodulator according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing the configuration of an orthogonal quasi-coherent detection QPSK demodulator according to the first embodiment of the present invention.

3 is a circuit block diagram showing a configuration of a frequency characteristic correction circuit provided in the demodulator shown in FIG.

FIG. 4 is a diagram showing an example of frequency characteristics of an A / D converter.

FIG. 5 is a diagram showing an example of a correction characteristic set in a frequency characteristic correction circuit.

FIG. 6 is a diagram showing frequency characteristics after correction.

FIG. 7 is a circuit block diagram showing a configuration of a frequency characteristic correction circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit block diagram showing a configuration of a frequency characteristic correction circuit according to a third embodiment of the present invention.

FIG. 9 is a circuit block diagram showing a configuration of a quadrature synchronous detection type QPSK demodulator according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing an example of roll-off characteristics.

FIG. 11 is a diagram showing a filter characteristic obtained by adding a correction characteristic to a roll-off characteristic.

FIG. 12 is a circuit block diagram showing an example of the configuration of a conventional quadrature quasi-coherent detection QPSK demodulator.

FIG. 13 is a circuit block diagram showing an example of the configuration of a conventional quadrature synchronous detection QPSK demodulator.

[Explanation of symbols]

1 ... Antenna 2 ... Antenna duplexer (DUP) 3 ... Reception circuit (RX) 4 ... Frequency synthesizer (SYN) 5 ... Transmission circuit (TX) 6 ... QPSK demodulator (DEM) 7 ... Time division multiple access circuit (TDMA) 8 ... Error correction code decoding circuit (CH-COD) 9 ... Voice code decoding circuit (SP-COD) 10 ... D / A converter 11 ... Speaker 12 ... Microphone 13 ... A / D converter 14 ... QPSK modulator 15 ... Battery 16 ... Power supply circuit 17 ... Control circuit 18 ... Operation input section 19 ... Display section 21 ... Quadrature detection circuit 22I, 22Q ... Quadrature detection multiplier 23 ... Quadrature detection local oscillator 24 ... Distributor 25I, 25Q ... A / D converter 26, 28 ... Complex multiplier 27I, 27Q ... Digital low-pass filter (LP
F) 29 ... Clock regeneration circuit 30 ... Data regeneration circuit 31 ... Phase comparator 32 ... Frequency error detection circuit 33 ... Numerically controlled oscillator (NCO) 34 ... Carrier regeneration loop filter 35I, 35Q, 38 ... Data conversion circuit 36 ... AFC loop filter 37 ... Numerically controlled oscillator (NCO) 39 ... Loop switching control circuit 40 ... Frequency multiplication circuit 41 ... Data converter 42 ... Digital / analog (D / A) converter 43 ... Phase detector 44 ... Amplifier 45 ... Voltage Control oscillator (VCO) 46 ... Divider 51I, 51Q ... Frequency characteristic correction circuit 510 ... Input terminal of frequency characteristic correction circuit 511-515 ... Delay device 521-525 ... Multiplication for multiplying tap coefficient 530 ... Adder 540 ... Output terminal of frequency characteristic correction circuit 550 ... Bus decoding Circuit 560 ... tap coefficient fixed storage unit 62I, 62Q ... correction / low pass filter

Claims (6)

[Claims] 1. A digitally modulated wave signal is subjected to quadrature detection, an analog demodulated signal obtained thereby is converted into a digital signal by an analog / digital converter, and then a predetermined digital signal required for digital demodulation by a digital processing circuit. In a digital demodulator for performing signal processing, frequency characteristic correction means for correcting deterioration of frequency characteristic due to the analog / digital converter is provided between the analog / digital converter and the digital processing circuit. And a digital demodulator. 2. A spectrum shaping filter for spectrum shaping the digital demodulated signal output from the analog / digital converter is provided between the analog / digital converter and the digital processing circuit. 2. The spectrum shaping filter also has a function of frequency characteristic correction means, wherein the spectrum shaping filter is also used.
The described digital demodulator. 3. The frequency characteristic correcting means corrects the frequency characteristic of the digital demodulated signal output from the analog / digital converter and outputs the corrected characteristic, and the correction characteristic is fixedly set to the correcting section. 3. The digital demodulator according to claim 1, further comprising a correction characteristic setting unit. 4. The frequency characteristic correcting means includes a correcting portion for correcting and outputting the frequency characteristic of the digital demodulated signal outputted from the analog / digital converter, an input means for inputting the correcting characteristic, and an input means for inputting the correcting characteristic. 3. The digital demodulator according to claim 1, further comprising a correction characteristic setting unit that sets the correction characteristic input by the means to the correction unit. 5. The frequency characteristic correction means includes a correction unit for correcting and outputting the frequency characteristic of the digital demodulated signal output from the analog / digital converter, and a plurality of analog / digital converters expected to be used. A correction characteristic storage unit that stores a plurality of corresponding correction characteristics in advance, a designation unit for designating the type of the correction characteristic, and a correction characteristic designated by the designation unit is selectively read from the correction characteristic storage unit. 3. The digital demodulator according to claim 1, further comprising a correction characteristic setting unit which is set in the correction unit. 6. The frequency characteristic correction means does not perform a frequency characteristic correction operation on the digital demodulated signal output from the analog / digital converter within a predetermined period from the start of reception of the digital modulated wave signal, 3. The digital demodulator according to claim 1, wherein a frequency characteristic correction operation for the digital demodulated signal is performed after the lapse of the predetermined period.