JPH09185132A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to detect the inversion of a reading-out address and a writing address by comparing the data read out in trial with the test data and emitting an error signal if the data are not equal. SOLUTION: This data processor has an image input section 101, an FIFO memory 12 and a printing control section 103. An LD modulating section 104 modulates and drives an LD 105. A synchronous detector 106 for detecting the laser beam emitted from this LD 105 is connected to the printing control section 103 and a phase shifting circuit 107. A test data generating circuit 108 is connected to the data writing section of the FIFO memory 102 and a data comparator circuit 109 to the data reading out section of the FIFO memory 102. The error signal output of the data comparator circuit 109 is connected to a CPU. The reading-out data outputted from the reading-out image data output terminal Dout of the FIFO memory 102 is compared with an expected value in the period when the reading-out enable signal XFRE is active in the data comparator circuit 109. The error signal is emitted in case the data do not coincide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital copying machine,
The present invention relates to a data processing device used in fields such as printers and facsimiles.

[0002]

2. Description of the Related Art A digital copying machine which is an example of a conventional data processing apparatus is shown in FIG. FIG. 16 is a block diagram of a conventional digital copying machine.
The digital copying machine 1601 is roughly divided into an image reading unit 1602 for reading and inputting a print image of a document (not shown).
A signal processing unit 1603 that executes various processes on the image data input by the image reading unit 1602;
3 and an image printing unit 1604 that prints out the image data output from the printer 3 on a printing paper (not shown), and has a structure in which these are sequentially connected.

Specifically, the image reading section 1602 has a first scanning unit 1608 consisting of a line light source 1606 elongated in the main scanning direction and a reflection mirror 1607, and a pair of reflection mirrors 1609, 1 under a contact glass 1605.
The second scanning unit 1611 composed of 610 is movably supported in the sub-scanning direction so that the speed ratio becomes 2: 1, and the image forming optical system 1612 and the CCD (Charge Couple).
ed Device) sensor 1613 is sequentially arranged.

The signal processing section 1603 includes an amplifier 1 connected to the CCD sensor 1613 of the image reading section 1602.
614, A / DC (Analog / Digital
1616, an image processing unit 1616 that executes various processes on image data, a buffer memory 1617 that temporarily stores the image data, a print control unit 1618 that controls the start timing of data reading, and an image printing unit 1604 based on the image data. LD (Lase for drive control)
r Diode) modulator 1619 and the like are sequentially connected.

Further, the image printing unit 1604 is connected to the LD modulation unit 1619 of the signal processing unit 1603 and the LD 16
A reflecting surface of a polygon mirror 1623 which is rotatable in the main scanning direction via a collimator lens 1621 and a cylindrical lens 1622 is located in the outgoing optical path of 20, and the fθ lens 1624 and the reflecting mirror in the main scanning direction of the polygon mirror 1623. The structure is such that the surface to be scanned of the photosensitive drum 1626 that is rotatable in the sub-scanning direction via 1625 is positioned.

The image printing unit 1604 is provided with a synchronous detector 1 including a photo sensor at a position immediately before the main scanning light of the polygon mirror 1623 enters the photosensitive drum 1626.
627 is arranged, and the output terminal of the synchronization detector 1627 is feedback-connected to the print control unit 1618 of the signal processing unit 1603.

With the above arrangement, the digital copying machine 16
Reference numeral 01 is for reading and inputting image data from a document by the image reading unit 1602 and printing out on a printing paper by the image printing unit 1604. In this process, the image data is temporarily stored by the signal processing unit 1603 and the image The input speed of the reading unit 1602 and the output speed of the image printing unit 1604 are arbitrated.

More specifically, the conventional digital copying machine 16
In 01, the image reading unit 1602 reads and scans the print image of the document placed on the contact glass 1605 in the sub-scanning direction by the first scanning unit 1608 and the second scanning unit 1611, and the CCD optical sensor 1612 scans the image. An image is formed at 1613. Therefore, the CCD sensor 161
Reference numeral 3 denotes the signal processing unit 16 for each line of the image data of the dot matrix as main scanning lines continuous in the sub-scanning direction.
03 is output.

At this time, the CCD sensor 1613 outputs the image data of one line one by one in the main scanning direction at a predetermined image clock after resetting the address by the line synchronization signal LSYNC. , First scanning unit 1608, second scanning unit 16
The signal is output line by line to the signal processing unit 1603 at a predetermined line cycle due to the scanning speed of 11 and the reading cycle of the CCD sensor 1613.

Therefore, in the signal processing unit 1603, the image data input line by line is amplified by the amplifier 1614 and converted from an analog value to a digital value by the A / DC 1615, and the image processing unit 1616 performs brightness correction processing and scaling. Buffer memory 1 after executing various processing such as processing and editing processing
Input to 617. After that, as will be described in detail later, since the print control unit 1618 outputs a timing control signal to the buffer memory 1617, the image data in the buffer memory 1617 is read by the print control unit 1618 in accordance with this timing control signal.

Therefore, the print control unit 1618 outputs various image data to the LD modulation unit 1619 after performing various processes such as range limitation and pattern composition.
619 outputs a drive current that is modulated according to the image data to the LD 1620 of the image printing unit 1604.

In the image printing unit 1604, the light emitted from the LD 1620 driven in accordance with the image data is converged by the collimator lens 1621 and the cylindrical lens 1622, deflected and scanned by the polygon mirror 1623, and the scanning light is scanned. The photosensitive drum 162 is corrected by the fθ lens 1624.
An image is formed on the surface to be scanned 6 which moves in the sub-scanning direction. Therefore, since an electrostatic latent image of a dot matrix is formed on the surface to be scanned of the photosensitive drum 1626, the image is printed by developing it with toner (not shown) and transferring it to a printing paper.

Here, in the image printing unit 1604, the synchronization detector 1627, which the main scanning light of the polygon mirror 1623 enters immediately before the photosensitive drum 1626, is synchronized with the synchronization detection signal DEP.
Since T is output, the signal processing unit 160 to which this is input
The print control unit 1618 of No. 3 outputs the timing control signal to the buffer memory 1617. By doing so, the image data temporarily stored in the buffer memory 1617 of the signal processing unit 1603 can be stored in the image printing unit 1.
The printouts of 604 are sequentially read at appropriate timing.

Incidentally, such a digital copying machine 1601
To continuously write image data from the image reading unit 1602 to the signal processing unit 1603 and read image data from the signal processing unit 1603 to the image printing unit 1604, the buffer memory of the signal processing unit 1603. 1617 has two systems so that two lines of image data can be input and output separately for each line. Therefore, while one line of image data is being written in one buffer memory 1617, the other buffer memory 1617
The image data of one line written in advance is read out, and such data reading and data writing are alternately executed by the two systems of buffer memory 1617.

However, in the digital copying machine 1601,
Since the data reading is set to be completed before the data writing switching timing, there is an inconvenience that it is impossible to cope with the case where the data reading speed is slower than the data writing.

Therefore, as a conventional data processing device that solves this problem, there is one disclosed in Japanese Patent Laid-Open No. 4-170857. According to the data processing device disclosed in Japanese Patent Laid-Open No. 4-170857, the buffer memory has two systems of FIF.
As an O (First In First Out) memory, data writing and data reading are started asynchronously so that they can be executed in the same cycle, and data reading is faster than data writing.

By doing so, even when data writing and data reading are simultaneously performed in one buffer memory, the data reading is faster than the data writing, so that the write address can catch up with or overtake the read address. There is nothing.

Further, since the phases of the write timing and the read timing to the buffer memory are made relatively variable, one system of FIFO having a storage capacity of one line is provided.
Therefore, a device that can realize a buffer memory has been proposed.

There is also proposed a system of FIFO having a storage capacity of less than one line, which can realize a buffer memory.

[0020]

However, according to the conventional data processing device using the FIFO, the length of the FIFO is theoretically the length of the image data of one line, that is, the write clock and the read clock. The length obtained by multiplying the frequency difference ratio by the number of clocks required for writing and reading of the FIFO may be used. However, the shorter the memory capacity of the FIFO is for one line of image data, the more the clock is used. There is a problem that the read address catches up with the write address and the address inversion occurs, and the data cannot be correctly transferred, because the margin becomes smaller as the frequency is farther away.

Further, the amount of changing the phase of the writing timing and the reading timing is set by software in accordance with the pixel density and the paper size, but the image delay amount of the image input section largely changes, and there is a margin of inversion. If the time is exceeded, there will be a problem that reverse rotation will occur and correct data transfer will not be possible.

In addition, when the pixel density and the paper size increase, there is a problem that the table of set values must be increased or the calculation must be performed.

Further, there is a problem that there is no method for detecting the reverse rotation even if the setting is mistaken when the pixel density and the paper size are increased.

The present invention has been made in view of the above, and it is an object of the present invention to provide a data processing device capable of detecting a reverse address of a read address and a write address.

Further, the present invention has been made in view of the above, and it is an object of the present invention to provide a data processing device in which a read address and a write address are not reversed.

[0026]

In order to achieve the above object, a data processor according to a first aspect of the present invention provides a data write corresponding to a write address with a write clock of a predetermined cycle and the write clock. Storage means capable of simultaneously performing data reading corresponding to a read address with a read clock of an independent predetermined cycle; and data writing means for starting the data writing to the storage means by inputting a write start signal. , The data read means for starting the data read from the storage means by inputting a read start signal, and the phases of the read start signal of the data read means and the write start signal of the data write means are relatively variable Start signal phase varying means, test write data generating means for generating test data to be written to the storage means on a trial basis, and data read on a trial basis from the storage means. Compared to experimental data, and includes comparison means for generating an error signal if not equal, a.

A data processing apparatus according to claim 2 is
The test write data generating means changes the generated test data line by line.

A data processing apparatus according to claim 3 is
The test write data generating means changes the generated test data every time the write address of the storage means returns to 0.

The data processing apparatus according to claim 4 is
Storage means capable of simultaneously executing data writing corresponding to a write address with a write clock of a predetermined cycle and data reading corresponding to a read address with a read clock of a predetermined cycle independent of the write clock; Data writing means for starting the data writing to the means by inputting a write start signal, data reading means for starting the data reading from the storage means by inputting a read start signal, and the data reading means Start signal phase changing means for relatively changing the phases of the read start signal and the write start signal of the data writing means; and test write data generating means for generating test data to be written in the storage means on a trial basis. Comparing the data read out from the storage means on a trial basis with the test data and generating an error signal if they are not equal,
The start signal phase changing means changes the phase change amount based on the comparison result of the comparing means.

The data processing apparatus according to claim 5 is
The operation of the test write data generating means and the phase change of the start signal phase changing means are performed when the print paper width or the pixel density is changed.

A data processing apparatus according to claim 6 is
The start signal phase changing means gradually changes the phase change amount, changes the phase until no error signal is generated in the comparing means, and changes the phase if the comparison result of the comparing means is equal. The amount of phase change is stopped and determined.

A data processing device according to claim 7 is
The start signal phase varying means determines the phase change amount according to the timing at which the error signal is generated by the comparing means.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION A data processing device of the present invention is applied to a digital copying machine as an example, and will be described in detail with reference to the drawings.

FIG. 1 is an overall block diagram of the digital copying machine of this embodiment. The digital copying machine of this embodiment includes an image input unit 101 as a data writing unit, a FIFO memory 102 as a storage unit, and a print control unit 103 as a data reading unit.

Further, the print control unit 103 includes the LD modulation unit 1
The LD modulator 104 drives the LD 105 for modulation. A synchronization detector 106 that detects a laser beam emitted from the LD 105 is connected to the print control unit 103 and a phase changing circuit 107 as a start signal phase changing unit, and the phase changing circuit 107 includes an image input unit. 1
01 is connected.

Further, the test data generating circuit 108 as the test writing data generating means is provided in the data writing portion of the FIFO memory 102 and the data comparing circuit 109 as the comparing means.
Is connected to the data reading section of the FIFO memory 102, and the error signal output of the data comparison circuit 109 is the CPU.
(Not shown).

The image input section 101 starts reading of image data of one line and image processing in response to the polygon motor synchronization signal XPMSYNC. Then, after a predetermined processing time, a write start signal XLSYNC is generated, the write address is sequentially incremented by a write clock WCLK of a predetermined cycle, data writing of image data to the FIFO memory 102 is started, and one line is started. Image data of the above is written in the FIFO memory 102. Therefore, there is a phase difference between the polygon motor synchronization signal XPMSYNC and the writing start signal XLSYNC. Since the processing time of image processing varies depending on the system and mode, the phase difference between the polygon motor synchronization signal XPMSYNC and the writing start signal XLSYNC changes depending on the system and mode and is not constant.

The FIFO memory 102 has a storage capacity of less than one line or more than one line of the image data in the main scanning direction, and writes data corresponding to the write address by the write clock WCLK of a predetermined cycle and its writing. Embedded clock WCL
Data read corresponding to the read address is simultaneously executed by the read clock RCLK having a predetermined cycle independent of K.

This FIFO memory 102 has a write data input terminal Din, a read image data output terminal Dout, write enable and read enable input terminals XWE, X.
RE, reset input terminals XWRES and XRRES, and clock input terminals WCLK and RCLK are provided, respectively. The X at the beginning of each letter represents active low, and the letter name of each terminal is the signal name.

Further, the FIFO memory 102 has a write address pointer and a read address pointer built therein, and each pointer has a reset signal XWRES, XRR.
ES will reset the pointer address value to 0,
When the enable signals XWE and XRE are active, the pointer address value is incremented by the clock signals WCLK and RCLK. When each address pointer reaches the final address corresponding to the storage capacity of the FIFO memory 102, each address pointer returns to 0 and is further incremented.

The print control unit 103 receives the synchronization detection signal XDE
A read start signal XRRES generated by PT causes a read clock R having a predetermined cycle independent of the image input unit 101.
Read address is sequentially incremented by CLK and FIF
Data reading of image data from the O memory 102 is started. The read start signal XRRES is the synchronization detection signal XDEP.
Since it is a signal that only T is shaped, the synchronization detection signal XD
There is almost no phase difference between the EPT and the read start signal XRRES.

The phase change circuit 107 has a synchronization detection signal XD.
When the EPT is input, its synchronization detection signal XD
The EPT phase is output in different states. The signals having different phases are input to the XPMSSYNC terminal of the image input unit 101. Here, the signal at the terminal XPMSSYNC is referred to as a polygon motor synchronization signal XPMSSYNC.

The write start signal XLSYNC is generated after a predetermined processing time of the polygon motor synchronization signal XPMSYNC. On the other hand, the synchronization detection signal XDEPT is input to the XDETP terminal of the print control unit 103. Here, the synchronization detection signal XDEPT is shaped so that the read start signal XRRES
Becomes Therefore, the read start signal XRRES has the same phase as the synchronization detection signal XDEPT, but is relatively different from the phase of the write start signal XLSYNC. In this case, by using the write start signal XLSYNC and the read start signal XRRES whose phases are relatively different from each other, it is controlled so that writing and reading of image data can be alternately accessed to an arbitrary address of the FIFO memory 102. It

That is, the image input unit 101 writes the image data into the FIFO memory 102 using the write start signal XLSYNC generated after a predetermined processing time of the input polygon motor synchronization signal XPMSYNC as the write reset signal, and the print control unit 101. 103 is a synchronization detection pulse signal XDE
Image data is read from the FIFO memory 102 by using PT (hereinafter, the synchronization detection signal XDEPT is referred to as a synchronization detection pulse signal XDEPT) as a read start signal XRRES.
Since the data writing and the data reading of the FIFO memory 102 are independently performed by the clocks having the different cycles, the chaotic execution of the data causes the addresses of the data writing and the data reading to cross each other, resulting in an error. Will occur.

The image input section 101 has a structure in which an image printing section 113 is connected to the image reading section 110 via an amplifier 111 and an A / D converter 112, and as shown in FIG. A clock generation circuit 114 for generating an input pixel clock SCLK which is a write clock WCLK of the memory 102 is provided. FIG.
5 is an explanatory diagram showing input / output of the image input unit 101. FIG.

Further, the image input section 101 receives an input terminal for the polygon motor synchronization signal XPMSYNC, an output terminal for image data to be written in the FIFO memory 102, and a main scanning effective area signal XLGATE which is a write enable signal XWE for the FIFO memory 102. It is provided with an output terminal, an output terminal of a write start signal XLSYNC which is a write reset signal XWRES of the FIFO memory 102, and the like.

The print control unit 103 includes a FIFO memory 10
2, an input terminal for image data to be read from 2, an output terminal for an XRE signal serving as a read enable signal XRE for the FIFO memory 102, and a read reset signal X for the FIFO memory 102.
Output terminal of XRRES signal which becomes RRES, output terminal which becomes read clock RCLK of FIFO memory 102, L
An output terminal for transmitting image data to the image printing unit 113 via the D modulation unit 104, and a print pixel clock P for transmitting image data to the image printing unit 113 via the LD modulation unit 104.
CLK output terminal, image printing unit 11 serving as a read start signal
It is provided with an input terminal for the synchronous detection pulse signal XDEPT and the like.

Therefore, a detailed description of each part of the digital copying machine will be sequentially described below together with its operation. FIG.
FIG. 4 is an explanatory diagram showing the timing of each signal of the digital copying machine. First, in the image printing unit 113 of the digital copying machine, the rotation speed of the polygon mirror 115 is set as the following equation.

[0049]

[Equation 1]

Therefore, such a polygon mirror 115
Forms a main scan by deflecting and scanning the emitted light of the LD 105. Since this emitted light enters the synchronous detector 106 immediately before entering the photosensitive drum 116, the synchronous detector 1 at this time
Reference numeral 06 outputs a synchronization detection pulse signal XDEPT to the print control unit 103 in response to light reception. That is, the synchronization detection pulse signal XDEPT is output once for each main scan of one line of the image printing unit 113, and its cycle is the same as the line cycle of image printing. Therefore, this line period is given by the following equation.

[0051]

[Equation 2]

Then, the synchronization detection pulse signal XDEPT output by the image printing unit 113 in such a line cycle is
The read start signal is input to the print control unit 103.

Therefore, as shown in FIG. 4, the print control unit 103 sends the sync detection pulse signal XD from the image printing unit 113.
The clock generation circuit 114 is connected to the clock synchronization circuit 117 to which the EPT is input.
14 outputs the print pixel clock PCLK. FIG. 4 is an explanatory diagram showing the output of the print pixel clock PCLK. Here, the print pixel clock PCLK
Is also the LD printing frequency and is given by the following equation.

[0054]

(Equation 3)

The effective scanning period ratio is usually 70 to 80 (%) in the case of a laser printer. Therefore, in the print control unit 103, the clock synchronizing circuit 117 outputs the print pixel clock PCLK generated by the clock generating circuit 114 as described above in synchronization with the input timing of the synchronization detection pulse signal XDEPT. The clock generation circuit 114 may use a crystal or ceramic oscillator, but a PLL (Phase Locked)
Since the frequency can be changed by using a Loop frequency synthesizer, it is possible to deal with a change in pixel density or linear velocity.

Further, as shown in FIG. 1, the image printing unit 1
Since the synchronization detection pulse signal XDEPT output by 13 is also input to the phase changing circuit 107, the phase changing circuit 1
07, the phase is changed without changing the cycle of the synchronization detection pulse signal XDEPT, and the polygon motor synchronization signal XP is changed.
It is output to the image input unit 101 as MSYNC.

Here, in the image input section 101, the input pixel frequency of the input pixel clock SCLK generated by the clock generation circuit 114 is obtained by the following equation.

[0058]

(Equation 4)

The effective image rate is calculated from the period generated due to the invalid elements existing in the CCD sensor 118. Since this invalid period requires only a few% of the whole,
The effective image rate is close to 100 (%). Then, in the image input unit 101, the input polygon motor synchronization signal X
Synchronize PMSYNC to the input pixel clock SCLK,
It outputs to CCD sensor 118 as a shift pulse.

Therefore, in the CCD sensor 118, the built-in shift register (not shown) is reset by the shift pulse, and the effective CCD image data is successively output to the invalid CCD pixels. Is executed in the image input unit 101 and then written in the FIFO memory 102. At this time, in the image input unit 101, data transmission is delayed by several lines in the sub-scanning direction and tens to hundreds of dots in the main scanning direction due to various processes.
The main scanning effective area signal XLGATE becomes active at the effective first pixel corresponding to this delay amount.

The main scanning effective area signal XLGAT
E indicates an effective image area in the main scanning direction, and the write start signal XLSYN is output a predetermined number of clocks before it becomes active.
C is output. Therefore, as described above, the FIFO memory 102 to which the main scanning effective area signal XLGATE and the write start signal XLSYNC are input from the image input unit 101.
The image data is sequentially stored using the input pixel clock SCLK of the image input unit 101 as the write clock WCLK.

Therefore, the print control unit 103 has a function of reading the image data written in the FIFO memory 102 from the image input unit 101 as described above and transmitting the image data from the LD modulation unit 104 to the image printing unit 113, and the FIFO memory. And a function of controlling data reading of the data.

First, as shown in FIG. 4 and described above, the print pixel clock generated by the clock generation circuit 114 has a phase at the input timing of the synchronization detection pulse signal XDEPT input from the image printing unit 113 in the clock synchronization circuit 117. Synchronized to become PCLK, and XDETP becomes synchronized with PCLK to become an XDETP1 signal having a predetermined pulse width.
Therefore, XDETP output by the clock synchronization circuit 117
One signal is the XRRES signal, which is the FIFO memory 102.
Is output to the FIFO memory 102 and the read address is reset by the read reset signal XRRES in the FIFO memory 102.

The XDETP1 signal output from the clock synchronization circuit 117 is also output to the reset terminal of the main scanning counter 119 which is a read counter, and the main scanning counter 119 is also reset.

Here, the main scanning counter 119 uses the XDE
A binary counter that is reset by the TP1 signal and incremented by PCLK is used to determine the main scanning position of the laser beam from the count value.
The main scanning counter 119 has a bit number that does not overflow during the scanning of one line. At this time, the image printing unit 113 prints an image at 800 dpi on an A3 size printing paper which is vertically fed. If you do 1
4 bits are required.

The main scanning counter 119 is connected with three comparators 120, 121, 122, and the first comparator 120 has an L level for detecting synchronization.
The forced drive signal of D105 is generated.
Therefore, to the first comparator 120, a CPU 123, which is a numerical value setting means for variably setting a numerical value, is connected via the I / F register 124, and the count value A of the main scanning counter 119 and the CPU 123 are connected. The value is variably compared with a preset value B, and when the count value A exceeds the set value B, the output becomes active. Therefore, this output is BD (Beam Detect)
t) signal is logically ORed with the image data by a logical OR gate 125 which is a logical OR means, and this output causes the LD 105
Is forcibly driven to emit light.

At this time, the timing of forced driving of the LD 105 must be set after the main scanning light passes through the effective printing area and before the next main scanning light reaches the synchronous detector 106. Since it is necessary to prevent it, it is usually set several (mm) to ten and several (mm) before the sync detector 106. When the main scanning light of the LD 105 that is forcibly driven as described above enters the synchronization detector 106, the synchronization detection pulse signal XDEPT output from the synchronization detector 106 becomes active and the main scanning counter 11
9 is reset. Therefore, when the main scanning counter 119 is reset, the counting is restarted, and this counting is repeated every line cycle of the image printing unit 113.

The second comparator 121 is provided for defining the print timing of the image data and the effective print area, and has two numerical values C and D (C <C <which are variably set by the CPU 123 in advance. D) is compared with the count value A of the main scanning counter 119. When the count value A exceeds the set numerical value C, the output signal X
When RGATE becomes active and the count value A exceeds the set numerical value D, the output signal XRGATE becomes negative. This output signal XRGATE is an inversion signal, and the inversion and the image data read from the FIFO memory 102 are logically ANDed by the AND gate 126 so that the image data is selectively masked and is located outside the effective print area. Positional image data is blocked. Further, the output signal XRGATE is output to the FIFO memory 102 as an XREF signal, and this FIFO memory 102 becomes a read enable signal XRE to enable the read operation. That is, since the set position of the image data determines the start position of the main scan of the image data and the set value of D determines the end position of the main scan, these values are changed according to the width of the printing paper and the conveyance position. It is also used to adjust the mechanical error.

Further, the third comparator 122 has a C
The numerical value E variably set by the PU 123 is compared with the count value A of the main scanning counter 119, and if they match, a pulse signal is generated, and the image input unit outputs the polygon mirror synchronization pulse signal XPMSYNC as a writing start signal. 101 is input.

The comparator 120 as described above,
Numerical values B, C, D and E set by 121 and 122 are CPUs
It can be variably set by 123.

The test data generation circuit 108 is a FIFO
It is connected to the data writing section of the memory 102, and the write start signal XLSYNC, the main scanning effective area signal XLGATE, and the write clock WCLK are input. The test data generation circuit 108 generates test data while the main scanning effective area signal XLGATE is active, and the test data is FI.
It is output to the write data input terminal Din of the FO memory 102.

The test data may be multi-bit data, but may be 1-bit data in the case of data described later. In that case, only one bit of the write data input terminal Din of the FIFO memory 102 is connected.

The data comparison circuit 109 is connected to the data read section of the FIFO memory 102, and has a read start signal XRR.
ES, read enable signal XRE, read clock RCL
Read image data output terminal D of K, FIFO memory 102
The read data output from out is input.

In the data comparison circuit 109, the FIFO memory 10 is activated while the read enable signal XRE is active.
The read data output from the second read image data output terminal Dout is compared with the expected value, and if they do not match, an error signal is generated. The bits of the data connected from the read image data output terminal Dout of the FIFO memory 102 to the data comparison circuit 109 are the same as the bits of the test data. The error signal is connected to the CPU (not shown),
The CPU can detect whether the data transfer can be performed correctly.

FIG. 5 shows an embodiment of the data comparison circuit 109. Read start signal XRRES, read enable signal X
The second test data generation circuit 128, to which RE and the read clock RCLK are connected, receives the write start signal XLSYN.
C, main scanning effective area signal XLGATE, write clock W
The above-mentioned test data generation circuit 108 to which CLK is connected
The same test data as that output by the test data generating circuit 108 at the timing of the control signal on the reading side is output as the expected value. This expected value is connected to the comparator 129.

On the other hand, the data read from the FIFO memory 102 is also connected to the comparator 129 and compared with the above-mentioned expected value. If they do not match, a mismatch signal is output. The mismatch signal is input to the AND gate 137, and a signal obtained by inverting the read enable signal XRE by the inverter 138 is connected to the other input of the AND gate 137,
The mismatch signal is output from the AND gate 130 only while the read enable signal XRE is active.

This output signal is input to a latch circuit (not shown) composed of an OR gate 131 and a D flip-flop 132 and output as an error signal. The error signal is connected to the CPU (not shown), and the CPU can detect whether the data transfer can be performed correctly.
Also, CP is connected to the reset terminal of the D flip-flop 132.
The reset signal from U is connected and the error signal can be released.

When the storage capacity of the FIFO memory 102 is one line or more, the present invention can be realized by a very simple method. Approximately 5k when printing an image at 400 dpi on A3 size printing paper that the image printing unit 113 feeds vertically
A case where the FIFO memory 102 having a word line length is used will be described with reference to FIGS. The number of effective print pixels in this case is calculated by the following equation and is 4677.

[0079]

(Equation 5)

On the other hand, a 5 kword FIFO memory 102
If the number of words is 5048 dots, the FIFO
The memory 102 has more than the number of effective print pixels.

FIG. 6 shows an embodiment of the test data generating circuit 108. The J and K inputs of the JK flip-flop 133 are fixed to high level. The output terminal Q is 1 of the write data input terminal Din of the FIFO memory 102.
Connected to a bit. The JK flip-flop 133 is
Write start signal XLSY connected to clock input terminal C
Toggle operation by NC. Then, 0s and 1s are alternately written into the FIFO memory 102 every other line.
There is no change in data within one line.

FIG. 7 shows an embodiment of the data comparison circuit 109. 1 bit of the read image data output terminal Dout of the FIFO memory 102 is the first D flip-flop 1
The D input terminal of 34 and the exclusive OR (exclusive OR) 135 are input to the test data generating circuit 1 described above.
At 08, the data written in the FIFO memory 102 is read.

Since the read clock RCLK is connected to the clock input terminal C of the first D flip-flop 134, the data delayed by one pixel is output from the output of the first D flip-flop 134. Since the output is input to the input terminal of the exclusive OR 135, when the adjacent pixels in the main scanning direction are different, the exclusive OR 1
The output of 35 goes high.

That is, when the read data of the FIFO memory 102 changes from 0 or 1, or from 1 to 0, the signal becomes active. This becomes the above-mentioned mismatch signal. Since the read enable signal XRE is connected to the D input terminal of the second D flip-flop 136 and the read clock RCLK is connected to the clock input terminal C, the second D flip-flop 136 is connected.
The read enable signal XRE is inverted and output from the XQ output terminal of the flip-flop 136 with a delay of one pixel.

This output and the output of the exclusive OR 135 are input to the AND gate 137, and the AND gate 13 is operated only while the read enable signal XRE is active.
An inconsistency signal is output from 7.

Since the test data written in the FIFO memory 102 does not change during one line, it means that the mismatch signal becomes active.
Therefore, the data could not be read correctly. The output signal is OR gate 139 and D flip-flop 140.
Is input to the latch circuit configured by and is output as an error signal.

The error signal is connected to the CPU (not shown), and the CPU can detect whether the data transfer can be performed correctly. A reset signal from the CPU is connected to the reset terminal of the D flip-flop 140 so that the error signal can be released. The error signal is also input to the clock input terminal C of the third D flip-flop 141. The output of the main scanning counter 119 is connected to the input terminal D of the third D flip-flop 141, and the value of the main scanning counter 119 is latched at the timing when the error signal becomes active. By making the output of the third D flip-flop 141 readable by the CPU, the CPU can know the main scanning position where the error occurred. Knowing the main scanning position means that FI
The address of the FO memory 102 can be easily known. It is also possible to control the amount of phase change with this value.

Here, a graph in which the vertical axis is the address of the image data in the FIFO memory 102 and the horizontal axis is the main scanning position of the image printing of the image printing unit 113 is shown in FIGS. . In these graphs, the broken line means the write address of the image data to be written in the FIFO memory 102, and the solid line shows F.
The read address of the image data read from the IFO memory 102 is meant. Further, these graphs show the case of the maximum size printing paper. Further, although these graphs exemplify the case where the frequency of the write clock WCLK for data writing is lower than the frequency of the read clock RCLK for data reading, the frequency of the write clock WCLK for data writing is Read clock RCL for data read
Even if the frequency is higher than K, the same configuration can be used.

Therefore, when the print control unit 103 reads one line of image data from the FIFO memory 102,
First, the read address is reset by the read reset signal XRRES, then image data is read at the read address according to the read clock RCLK while the read enable signal XRE is active, and the read address is incremented every time this read operation is executed. . Then, the read address pointer is incremented while the read enable signal XRE is active. In the case of reading 4677 pixels, which is the number of pixels corresponding to 400 dpi on the short side of A3 size, in this example, the read address pointer is 4677.
Is incremented until is reached.

Here, the read enable signal XRE controls the start and end timings corresponding to the width of the printing paper in the main scanning direction. Therefore, when the printing paper has the maximum size, the read enable signal XRE shown in FIGS. As shown in, the signal becomes active at the beginning of the effective scanning period and becomes negative at the end. Also,
When the printing paper is small in size, the timings of active and negative are adjusted so that the main scanning operation and the center of the photosensitive drum 116 coincide with each other. Therefore, when the printing paper has a small size, the number of pixels of the image to be read is small, and the active time of the read enable signal XRE is short.

On the other hand, when writing one line of image data in the FIFO memory 102, the write address is set after the write address is reset by the write reset signal XWRES generated by delaying the sync detection pulse signal XDEPT. , The FIFO memory 10 according to the write clock WCLK while the write enable signal XWE is active.
Image data is written in No. 2, and the write address is incremented every time this write operation is executed. Then, the write address pointer is incremented while the write enable signal XWE is active. In the case of writing 4677 pixels, which is the number of pixels corresponding to 400 dpi on the short side of A3 size, in this example, the write address pointer is 467.
It is incremented until it reaches 7.

Here, the write enable signal XWE is active for a period corresponding to the width of the printing paper in the main scanning direction, like the read enable signal XRE. When the printing paper is large size, the number of pixels of the image data to be written increases, so the active period of the write enable signal XWE becomes long, and when the printing paper is small size, the number of pixels of the image to be read out is small. Therefore, the write enable signal XWE
Will have less active time.

When the data writing and data reading of the FIFO memory 102 as described above are expressed by addresses, the graphs of FIGS. 8 and 9 are obtained. In these illustrated graphs,
When the frequency of the write clock WCLK is the lowest, the image input unit 10
Since the effective image of No. 1 is close to 100 (%), the illustrated inclination of the write address is the slowest, as illustrated by the broken line. That is, since the slope of the write address is determined by the ratio of the write frequency fw and the read frequency fr, for example, the slope of the write address gradually increases as the write frequency fw increases.

In the graphs of FIGS. 8 and 9, the FIF
If the broken line indicating the write operation of the O memory 102 and the solid line indicating the read operation do not intersect with each other, data writing and data reading that are independently executed at the same time do not interfere with each other.

FIG. 8 shows a case where there is almost no phase change, and the broken line indicating the write operation and the solid line indicating the read operation intersect. As described above, the write test data is toggled by the write reset signal XWRES. In the case of this figure, 0 is written over 1 line in the left write cycle, and 1 is written from 1 line in the right write cycle. It is 1 in the previous write cycle that is out of the range of this figure.
Is writing 1 line. Before the write operation and the read operation intersect, the write operation precedes the read operation.
After the read operation and the write operation and the read operation intersect, the read operation precedes the write operation, so that the data 1 of the previous line can be read.

That is, the read data changes in the read cycle of one line. Then, since the error signal becomes active, the CPU can detect that the data transfer by the FIFO memory 102 has caused an error. Further, as described above, since the main scanning position where the error has occurred can be known, it is also possible to control the phase change amount by this value.

FIG. 9 is a time chart when the phase is changed by the phase change circuit 107 so that the broken line showing the write operation and the solid line showing the read operation do not intersect. The control on the writing side is the same as in FIG. Since the write operation and the read operation do not intersect and the read operation precedes the write operation, in the read cycle on the left side of the figure, the data 1 of the previous line can be read over the read period of one line. That is, the read data does not change in the read cycle of one line. Therefore, the error signal remains negative, so CP
U can detect that the data transfer by the FIFO memory 102 has been performed correctly.

Next, the image printing unit 113 feeds A3 vertically.
A case of printing an image at 800 dpi on a printing paper of a size and using the FIFO memory 102 having a line length of about 5 k words will be described with reference to graphs and time charts. In this case, the number of effective print pixels is calculated by the following equation and becomes 9354.

[0099]

(Equation 6)

On the other hand, a 5 kword FIFO memory 102
If the number of words is 5048 dots, the FIFO
The memory 102 has a line length which is a little more than ½ of the number of effective print pixels.

10 and 11 are graphs with the time axis of the address of the image data in the FIFO memory 102 as the vertical axis and the horizontal axis of the main scanning position of the image printing of the image printing unit 113 as characteristic charts together with the time chart. . In addition,
The one cycle T on the horizontal axis of these graphs indicates that
Corresponds to the line period of the line, and is determined by the pixel density in the sub-scanning direction and the line speed. The maximum value APmax on the vertical axis of these graphs is determined by the number of words in the FIFO memory 102, that is, the maximum value of the address pointer. The maximum value of the address pointer is a FIFO with 5048 words.
In this example using the memory 102, the number is 5047.

In these graphs, the broken line indicates FIF.
This means the write address of the image data to be written in the O memory 102, and the solid line means the read address of the image data read from the FIFO memory 102. Further, these graphs show the case of the maximum size printing paper. Further, the graph of FIG. 10 exemplifies a case where the frequency of the write clock WCLK for data writing is lower than the frequency of the read clock RCLK for data reading.
The graph of 1 illustrates the case where the frequency of the write clock WCLK for data writing is higher than the frequency of the read clock RCLK for data reading.

Therefore, when the print control unit 103 reads the image data of the nth line from the FIFO memory 102, the read address is first reset by the read reset signal XRRES, and then the read enable signal XRE is read in the active state. The image data is read at the read address according to the clock RCLK, and the read address is incremented each time the read operation is executed. And
When the read address reaches the maximum value of the read address pointer of the FIFO memory 102, in this example, at the next read clock RCLK when the read address becomes 5047, the read address pointer returns to "0" and further increment. to continue. Then, the read address pointer is incremented while the read enable signal XRE is active. In the case of reading 9354 pixels, which is the number of pixels corresponding to 800 dpi on the short side of A3 size, in this example, the read address pointer is incremented until it reaches 4305.

Here, the read enable signal XRE controls the start and end timings corresponding to the width of the print sheet in the main scanning direction. Therefore, when the print sheet has the maximum size, the read enable signal XRE shown in FIGS. As shown in, the signal becomes active at the beginning of the effective scanning period and becomes negative at the end. When the printing paper is small, the timings of active and negative are adjusted so that the main scanning operation and the center of the photosensitive drum 142 coincide with each other. Therefore, when the printing paper has a small size, the number of pixels of the image to be read is small, and the active time of the read enable signal XRE is short.

On the other hand, when the image data of the nth line is written in the FIFO memory 102, the write address is n-
After the write address is reset by the write reset signal XWRES, which is generated by delaying the synchronization detection pulse signal XDEPT on the first line, the write enable signal XWE is incremented according to the write clock WCLK in the active state. .

The write address is the FIFO memory 1
When the maximum value of the write address pointer 02 is reached, in this example, the write address pointer returns to “0” at the next write clock WCLK when the write address becomes 5047, and the increment is further continued. . Then, the write address pointer is incremented while the write enable signal XWE is active. 8 on the short side of A3 size
In the case of writing 9354 pixels, which is the number of pixels corresponding to 00 dpi, it is incremented until the write address pointer reaches 4305.

Here, the write enable signal XWE is active for a period corresponding to the width of the printing paper in the main scanning direction, like the read enable signal XRE. When the printing paper is large size, the number of pixels of the image data to be written increases, so the active period of the write enable signal XWE becomes long, and when the printing paper is small size, the number of pixels of the image to be read out is small. Therefore, the write enable signal XWE
Will have less active time.

When the data writing and data reading of the FIFO memory 102 as described above are expressed by addresses, the graphs of FIGS. 10 and 11 are obtained. In the graph illustrated in FIG. 10, since the frequency of the write clock WCLK is the lowest and the effective image of the image input unit 101 is close to 100 (%), this is as illustrated by the broken line in FIG. The slope of the write address shown is the slowest. That is, since the slope of the write address is determined by the ratio of the write frequency fw and the read frequency fr, for example, the slope of the write address gradually increases as the write frequency fw increases. A case where the writing frequency fw is higher than the reading frequency fr is illustrated in FIG.

In the graphs of FIGS. 10 and 11, in the writing operation of one line, the FIFO memory 102 is shown between the broken line showing the first writing operation and the broken line showing the second writing operation. If the solid line indicating the first read operation of 102 does not cross and the solid line indicating the second read operation does not cross after the broken line indicating the second write operation. It is possible to write new data to the same address that has been read once and read new image data at the time of the second read operation, so that data writing and data reading that are independently executed at the same time do not interfere with each other. Therefore, the output timing of the write reset signal XWRES is adjusted appropriately so that the FIFO memory 102 can be easily confirmed from the figure.
It is possible to prevent the data reading from catching up with the data writing.

It is necessary to take this into consideration because it actually takes some time from the writing of data to the reading of data in the FIFO memory 102.

10 and 11 show the phase changing circuit 10
7 shows the case where the setting of 7 is made proper and the reading of the image data is performed correctly. The operations of the test data generation circuit 108 and the data comparison circuit 109 in order to correctly set the phase changing circuit 107 will be described with reference to the time charts of FIGS. 12 to 15.

12 to 15 show the case where the write frequency fw is lower than the read frequency fr under the same conditions as in FIG. 10, and the FIFO memory 102 is rotated twice for one line. In the write test data, the first write data in the writing of one line is set to 0, and the FIFO memory 1
The second write data after the write address of 02 makes one round and returns to 0 is set to 1. If the reading is correctly performed by this, the read data should be 0 at the beginning of reading one line and become 1 from the second time when the storage capacity of the FIFO memory 102 is exceeded. Therefore, the comparison data of the data comparison circuit 109 is generated as such.

FIG. 12 shows a case where there is almost no phase change amount. In the first read cycle and the first write cycle, the broken line showing the write operation and the solid line showing the read operation intersect. Before the write operation and the read operation intersect, the write operation precedes the read operation, so 0 can be read, and after the write operation and the read operation intersect, the read operation precedes the write operation. The second write data 1 on the previous line can be read.

Since the second writing is performed only up to the address 4035, the data 0 written in the previous first writing can be read after the address 4036 in the first reading. Further, in the second reading, the data written in the first reading can be read, so that 0 can be read. The read data is compared with the comparison data, and if they do not match, the error signal becomes active there, so that the CPU can detect that the data transfer by the FIFO memory 102 has caused an error. In the case of this example, the error signal becomes active at the timing when the write operation and the read operation intersect.

In FIG. 13, the phase change amount of the phase change circuit 107 is made larger than that in FIG. 12, and the broken line showing the write operation and the solid line showing the read operation intersect in the first read cycle and the first write cycle. This shows the case where the control is performed so as not to. However, between the broken line showing the first write operation of the FIFO memory 102 and the broken line showing the second write operation, F
Since the solid line indicating the first read operation of the IFO memory 102 is not included and the second read operation of the FIFO memory 102 is included, correct transfer cannot be performed. Since the first read operation of the FIFO memory 102 precedes the first write operation, the second write data 1 of the previous line can be read. Further, as in the case of FIG. 12, 0 can be read after the address 4036 in the first read, and 0 can be read in the second read. In the case of this example, the error signal becomes active when 1 can be read in the first reading.

FIG. 14 shows a broken line showing a write operation and a read operation in the first write cycle and the second read cycle when the phase change amount of the phase change circuit 107 is made larger than that in FIG. The case where the solid lines intersect is shown.
Similar to FIG. 13, since the first read operation of the FIFO memory 102 precedes the first write operation, the second write data 1 of the previous line can be read. Further, as in the case of FIG. 12, 0 can be read after the address 4036 of the first read, and the write operation precedes the read operation even before the crossing of the write operation and the read operation in the second read. Therefore, 0 of the first writing can be read, and after the writing operation and the reading operation intersect, the reading operation precedes the writing operation, so that the second writing data 1 of the previous line can be read. In this example, as in the case of FIG. 13, the error signal becomes active when 1 can be read in the first read.

FIG. 15 shows a case where the amount of phase change of the phase change circuit 107 is made larger than that of FIG. 14, and when data transfer is performed correctly, that is, in the write operation of one line, the first time of the FIFO memory 102. Between the broken line showing the write operation and the broken line showing the second write operation, the FIF
A case is shown in which the solid line indicating the first read operation of the O memory 102 is prevented from crossing, and the solid line indicating the second read operation is not crossed after the broken line indicating the second write operation. There is. Since the write operation and the read operation are alternately performed, the same data as the comparison data can be read. In this case, since the error signal remains negative, the CPU can detect that the data transfer by the FIFO memory 102 has been correctly performed.

As shown in FIGS. 12 to 15, the phase change amount of the phase change circuit 107 is gradually changed, the phase is changed until the data comparison circuit 109 does not generate an error signal, and the data comparison circuit 109 changes the phase. If the same result is obtained, the phase change can be stopped and the appropriate amount of phase change can be determined.

Up to now, the case where the width of the printing paper is maximum has been described, but as described above, the timing of the start and end of the read enable signal XRE to the FIFO memory 102 corresponding to the width of the printing paper in the main scanning direction. When the width of the printing paper in the main scanning direction is small, the start timing of the read enable signal XRE is delayed and the end timing thereof is advanced. In this case, unless the write start timing to the FIFO memory 102 is also delayed, the write address and the read address may cross each other and an error may occur. Therefore, the timing of the write start signal is adjusted according to the width of the printing paper in the main scanning direction.

The writing and reading of the test data, the detection of the error, and the setting of the phase change amount are executed between print jobs, that is, when the print paper width or pixel density between papers is changed.

In this embodiment, a digital copying machine is exemplified as the data processing device, and the image input unit 101 for writing the image data optically input by the CCD sensor 118 into the FIFO memory 102 is exemplified as the data writing means. ，
The print control unit 103, which prints out the image data read out from the FIFO memory 102 by the image printing unit 113, is exemplified as the data reading unit, but the present invention is not limited to the above embodiment. For example, a DTP (Desk Top Publicity) equipped with a device for writing image data received from a host computer to the FIFO memory 102 and a device for displaying and outputting image data read out from the FIFO memory 102 on a display.
ng) system or the like can also be realized as a data processing device.

[0122]

As described above, according to the data processor of the present invention (claim 1), the data write corresponding to the write address by the write clock of a predetermined cycle and the write clock are independent. Storage means capable of simultaneously performing data read corresponding to a read address with a read clock of a predetermined cycle; data writing means for starting the data writing to the storage means by inputting a write start signal; Data read means for starting the data read from the storage means by inputting a read start signal, and start for relatively varying the phases of the read start signal of the data read means and the write start signal of the data write means The signal phase varying means, the test write data generating means for generating test data to be written in the storage means on a trial basis, and the test data read out from the storage means as the test data. The data writing means writes the test data generated by the test write data generating means in the storage means, and the data reading means reads it out. Further, the comparison means compares, so that the reverse of the address of the storage means can be detected.

Further, according to the data processor of the present invention (claim 2), the test write data generating means changes the generated test data for each line, so that the storage capacity of one line or more is required. It is possible to detect the reversal of the address of the image data of the storage means that it has.

According to the data processor of the present invention (claim 3), the test write data generating means changes the generated test data every time the write address of the storage means returns to 0. Therefore, it is possible to detect the inversion of the address of the image data of the storage means having the storage capacity of less than one line.

Further, according to the data processor of the present invention (claim 4), the data write corresponding to the write address with the write clock of the predetermined cycle and the read clock of the predetermined cycle independent of the write clock. Storage means capable of simultaneously performing data reading corresponding to the read address, data writing means for starting the data writing to the storage means by inputting a write start signal, and the data from the storage means Data read means for starting reading by inputting a read start signal; start signal phase varying means for relatively varying the phases of the read start signal of the data reading means and the write start signal of the data writing means; The test write data generating means for generating test data to be written in the storage means on a trial basis is compared with the test read data from the storage means and the test data is equalized. If so, the start signal phase changing means changes the phase change amount based on the comparison result of the comparing means, so that the data writing means tests the storage means. By writing the test data generated by the write data generating means, reading it by the data reading means, and comparing it by the comparing means, it is possible to detect the inversion of the address of the storing means, and at the same time write Since the read phase is controlled, it is possible to prevent the address inversion of the storage means from occurring.

Further, according to the data processor of the present invention (claim 5), the operation of the test write data generating means and the phase change of the start signal phase changing means are performed when the print paper width or the pixel density is changed. Therefore, the phase can be properly set so that the inversion of the address of the storage means does not occur, so that the inversion of the address of the storage means can be prevented.

Further, according to the data processor of the present invention (claim 6), the start signal phase varying means gradually changes the phase change amount, and the comparing means does not generate an error signal. If the result of comparison by the comparing means is equal, the change is stopped and the amount of phase change is determined, that is, the amount of phase change of the start signal phase changing means is gradually changed, and the error signal is compared by the comparing means. The phase is changed until no longer occurs, and if the comparison means obtains an equal result, the change is stopped and the amount of phase change is determined. Therefore, no calculation is performed. In other words, the address reversal of the storage means is easily reversed. The phase can be set properly so that it does not occur.

According to the data processor of the present invention (claim 7), the start signal phase varying means determines the phase change amount according to the timing at which the error signal is generated by the comparing means. That is, since the start signal phase varying means determines the phase change amount in accordance with the timing at which the comparing means generates an error signal, the phase should be properly set so that the inversion of the address of the storage means does not occur in a fast operation. You can

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an entire data processing device of an embodiment.

FIG. 2 is an explanatory diagram showing input / output of an image input unit.

FIG. 3 is an explanatory diagram showing the timing of each signal of the data processing device.

FIG. 4 is an explanatory diagram showing an output of a print pixel clock PCLK.

FIG. 5 is a configuration diagram showing an embodiment of a data comparison circuit.

FIG. 6 is a configuration diagram showing an embodiment of a test data generating circuit.

FIG. 7 is a configuration diagram showing an embodiment of a data comparison circuit.

FIG. 8 is an explanatory diagram showing a case where a broken line indicating a write operation and a solid line indicating a read operation intersect each other when there is almost no phase change amount.

FIG. 9 is an explanatory diagram showing a time chart when the phase is changed by the phase changing circuit so that the broken line showing the write operation and the solid line showing the read operation do not intersect.

FIG. 10 is an explanatory diagram showing a case where the frequency of the write clock WCLK for data writing is lower than the frequency of the read clock RCLK for data reading.

FIG. 11 is an explanatory diagram showing a case where the frequency of the write clock WCLK for data writing is higher than the frequency of the read clock RCLK for data reading.

FIG. 12 is an explanatory diagram showing a case where there is almost no phase change amount.

FIG. 13 is a control for increasing the phase change amount of the phase change circuit as compared with FIG. 12 so that the broken line showing the write operation and the solid line showing the read operation do not intersect in the first read cycle and the first write cycle. It is explanatory drawing which showed the case.

14 is a diagram illustrating a case in which the phase change amount of the phase change circuit is made larger than that in FIG. 13, the broken line indicating the write operation and the solid line indicating the read operation intersect in the first write cycle and the second read cycle. It is explanatory drawing which showed the case.

FIG. 15 is an explanatory diagram showing a case where the amount of phase change of the phase change circuit is made larger than that in FIG. 14, a case where data transfer is performed correctly, and a case where data transfer is performed correctly.

FIG. 16 is a block diagram of a conventional digital copying machine.

[Explanation of symbols]

101 image input unit 102 FIFO memory 103 print control unit 107 phase change circuit 108, 128 test data generation circuit 109 data comparison circuit 110 image reading unit 113 image printing unit 114 clock generation circuit 117 clock synchronization circuit PCLK print pixel clock RCLK read clock SCLK Input image clock WCLK Write clock XWE Write enable signal XRE Read enable signal XWRES Write reset signal XRRES Read start signal or read reset signal XDEPT Sync detection signal or sync detection pulse signal XLSYNC Write start signal XLGATE Main scan effective area signal XRGATE Output signal XPMSYNC Polygon motor sync signal or polygon mirror sync pulse signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 3/12 G06F 3/12 K H04N 1/00 H04N 1/00 E 1/19 1/21 1 / 21 1/387 1/387 1/04 103Z

Claims (7)

[Claims] 1. A memory capable of simultaneously executing data writing corresponding to a write address with a write clock of a predetermined cycle and data reading corresponding to a read address with a read clock of a predetermined cycle independent of the write clock. Means, data writing means for starting the data writing to the storage means by inputting a write start signal, and data reading means for starting the data reading from the storage means by inputting a read start signal, Start signal phase changing means for relatively changing the phases of the read start signal of the data reading means and the write start signal of the data writing means, and a test document for generating test data to be written in the storage means on a trial basis. Embedded data generating means and comparing means for comparing the data read experimentally from the storage means with the test data and generating an error signal if they are not equal. A data processing device characterized by the following. 2. The data processing apparatus according to claim 1, wherein the test write data generating means changes the generated test data for each line. 3. The data processing apparatus according to claim 1, wherein the test write data generating means changes the generated test data every time the write address of the storage means returns to 0. 4. A memory capable of simultaneously executing data writing corresponding to a write address with a write clock of a predetermined cycle and data reading corresponding to a read address with a read clock of a predetermined cycle independent of the write clock. Means, data writing means for starting the data writing to the storage means by inputting a write start signal, and data reading means for starting the data reading from the storage means by inputting a read start signal, Start signal phase changing means for relatively changing the phases of the read start signal of the data reading means and the write start signal of the data writing means, and a test document for generating test data to be written in the storage means on a trial basis. Embedded data generating means and comparing means for comparing the data read experimentally from the storage means with the test data and generating an error signal if they are not equal, A data processing device, wherein the start signal phase varying means changes the phase change amount based on a comparison result of the comparing means. 5. The data processing apparatus according to claim 4, wherein the operation of the test write data generating means and the phase change of the start signal phase changing means are performed when the print paper width or the pixel density is changed. 6. The start signal phase changing means gradually changes the phase change amount and changes the phase until an error signal is not generated in the comparing means, and if the comparison result of the comparing means is equal. 5. The data processing apparatus according to claim 4, wherein the phase change amount is determined by stopping the phase change. 7. The data processing apparatus according to claim 4, wherein the start signal phase varying means determines the phase change amount according to the timing at which the error signal is generated by the comparing means.