JP2002152475A - Image data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable moving of an image to the left side in a main scanning direction without restriction in movement with a simple constitution. SOLUTION: A start position of an image data effective signal XLGATE output from an image input unit 30 is delayed in response to the amount of shift of an image position in the left direction by a start position changing circuit 33 as a write enable signal XWE of a line buffer memory. The start signal of the XWE signal is delayed by M clocks from the image data effective signal XLGATE, and image data of a (M+1)-th pixel is written at address '0' of the buffer memory. Since the reading side of the line buffer memory 31 is sequentially read from the address '0', a print start pixel of the image becomes the (M+1)-th image data, and a printed image shifted by M pixels in an optical beam detector direction (left direction) is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus such as a digital copying machine for writing and reading image data to and from a line memory.

[0002]

2. Description of the Related Art As a conventional example of an image data processing apparatus, a digital copying machine will be described below with reference to FIG. First,
The digital copying machine 1 includes an image reading unit 2 that reads and inputs a print image of a document (not shown), and a signal processing unit 3 that performs various processes on image data input by the image reading unit 2.
And an image printing unit 4 for printing out image data to be output from the signal processing unit 3 on printing paper (not shown).

More specifically, an image reading unit 2 includes a first scanning unit 8 including a line light source 6 elongated in the main scanning direction and a reflecting mirror 7 under a contact glass 5, and a pair of reflecting mirrors 9 and 10. And a second scanning unit 11 comprising
The imaging optical system 12 and a CCD (Charge Coupled Device) are supported so as to be movable in the sub-scanning direction so that the speed ratio becomes 2: 1.
The sensor 13 and the sensor 13 are sequentially arranged.

[0004] The signal processing unit 3 is provided with a C
A / DC is supplied to the amplifier 14 connected to the CD sensor 13.
(Analog / Digital Converter) 15, an image processing unit 16 for performing various processes on image data, a line buffer memory 17 for temporarily storing image data, a print control unit 18 for controlling the start timing of data reading, (Laser Diode) that drives and controls the image printing unit 4
The modulation section 19 and the like are sequentially connected.

Further, the image printing section 4 includes a polygon mirror rotatable in the main scanning direction via a collimator lens 21 and a cylindrical lens 22 on an emission optical path of the LD 20 connected to the LD modulation section 19 of the signal processing section 3. 23 is positioned on the main scanning optical path of the polygon mirror 23.
The scanning surface of the photosensitive drum 26 that is rotatable in the sub-scanning direction via the θ lens 24 and the reflection mirror 25 is positioned. In the image printing section 4, a synchronization detector 27 composed of a photo sensor is disposed at a position immediately before the main scanning light of the polygon mirror 23 is incident on the photosensitive drum 26. The output terminal of the synchronization detector 27 is a signal. It is feedback connected to the print control unit 18 of the processing unit 2.

In such a configuration, the digital copying machine 1 is configured to read and input image data from a document by the image reading unit 2 and print out the image data on printing paper by the image printing unit 4. The image data is temporarily stored in the signal processing unit 3, and the input speed of the image reading unit 2 and the output speed of the image printing unit 4 are arbitrated.

More specifically, in the digital copying machine 1, the image reading section 2 reads a print image of a document placed on the contact glass 5 in the sub-scanning direction by the first and second scanning units 8, 11. Since the image is scanned and formed on the CCD sensor 13 by the imaging optical system 12, the CCD sensor 13 outputs dot matrix image data to the signal processing unit 3 line by line as main scanning lines that are continuous in the sub-scanning direction. . At this time, the CCD sensor 13 outputs one line of image data one pixel at a time in the sub-scanning direction at a predetermined pixel clock after resetting the address by the line synchronization signal LSYNC. -The signals are output line by line to the signal processing unit 3 at a predetermined line cycle due to the scanning speed of the second scanning units 8 and 11, the reading cycle of the CCD sensor 13, and the like.

The signal processing unit 3 amplifies the image data input line by line by an amplifier 14 and converts the amplified image data into an A / A signal.
The DC 15 converts the analog value into a digital value, and the image processing unit 16 executes various processes such as a brightness correction process, a scaling process, and an editing process, and then inputs the processed value to the line buffer memory 17. Then, as described later, the print control unit 18 outputs a timing control signal to the line buffer memory 17, and the image data in the line buffer memory 17 is read out to the print control unit 18 according to the timing control signal. The print control unit 18 outputs image data on which various processes such as range limitation and pattern synthesis have been performed to the LD modulation unit 19, and the LD modulation unit 19 outputs a drive current modulated in accordance with the image data to the LD 20 of the image printing unit 4. Output to

In the image printing section 4, the light emitted from the LD 20 driven in accordance with the image data is converged by the various lenses 21 and 22 and deflected by the polygon mirror 23 for scanning. To form an image on the surface to be scanned of the photosensitive drum 26 that moves in the sub-scanning direction. Then, since an electrostatic latent image of a dot matrix is formed on the surface to be scanned of the photosensitive drum 26, the image is developed by developing the image with toner (not shown) and transferring the image to printing paper.

Here, in the image printing section 4, a synchronization detector 27 on which the main scanning light of the polygon mirror 23 is incident immediately before the photosensitive drum 26 outputs a synchronization detection signal DETP, and receives the synchronization detection signal DETP. Print control unit 18 of signal processing unit 3
Outputs a timing control signal to the line buffer memory 17. In this way, the image data temporarily stored in the line buffer memory 17 of the signal processing unit 3 is sequentially read at a timing appropriate for the print output of the image printing unit 4.

The digital copying machine 1 continuously writes image data from the image reading unit 2 to the signal processing unit 3 and reads image data from the signal processing unit 3 to the image printing unit 4. For the purpose of efficient execution, the line buffer memory 17 of the signal processing section 3 has two systems so that two lines of image data can be input and output separately for each line. Therefore, one line of image data written in advance is read from the other line buffer memory 17 at the time when one line of image data is being written to one line buffer memory 17. And writing are alternately performed by the two line buffer memories 17.

Here, the applicant of the present invention disclosed in Japanese Unexamined Patent Publication No. Hei 8-9119.
In this publication, a method of arbitrating between the input speed of the image reading unit and the output speed of the image printing unit using a one-line FIFO memory is shown. Further, this publication describes that the print start position of the data in the main scanning direction is changed by changing the output timing of the read enable signal of the FIFO memory. That is, by changing the timing at which the image data is read from the FIFO memory, it is possible to print the image while moving it in the main scanning direction on the transfer paper.

[0013]

However, in this conventional method, the printing start position in the main scanning direction can be moved in the direction to delay the timing, but there is a problem that the direction to advance the timing is restricted. . The read enable signal is generated by a main scanning counter which starts counting from the output of the light beam detection signal of the beam detection means provided before the effective printing area of the light writing beam of the light beam writing means in the main scanning direction. Since the signal is a signal, it cannot be generated at a timing before the light beam detection signal, and the movement of the printing position in a direction to advance the timing is restricted. For example, in an image forming apparatus that scans rightward from a beam detection unit,
When output of an image from the position is the default, the movement of the image in the main scanning direction is not shifted more than 10 mm to the left side, which is a direction to advance the timing.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described conventional problems, and has as its object to provide an image data processing apparatus capable of moving an image in the main scanning direction to the left without any restriction with a simple configuration.

Another object of the present invention is to provide an image data processing apparatus capable of moving the image in the main scanning direction to the right without any restriction with a simple configuration.

[0016]

In order to achieve the above object, a first means has a storage capacity of one or more lines of image data of a dot matrix, and writes and reads image data corresponding to a write address. Storage means capable of simultaneously and independently reading the corresponding image data, write enable signal generation means for generating a write enable signal by delaying a line synchronization signal in accordance with the shift of the image position to the left, When the write enable signal generated by the write enable signal generating means becomes active, the write address is initialized, and during the period when the write enable signal is active,
A write unit for sequentially incrementing a write address by a first clock of a predetermined period and writing image data to the storage unit; and setting a read address to an initial state when a read enable signal becomes active; Reading means for reading out image data from the storage means by sequentially incrementing a read address by a second clock having a predetermined cycle independent of the data writing means during the period.

The second means is to achieve the above object.
A storage means having a storage capacity of at least one line of dot matrix image data and capable of simultaneously and independently writing image data corresponding to a write address and reading image data corresponding to a read address, and a write enable signal being active Writing means for writing the image data to the storage means by sequentially incrementing the writing address by a first clock of a predetermined period while the write enable signal is active, and Initial read address setting means for setting an initial read address of the storage means in accordance with the amount of shifting to the left, and an initial read address set by the initial read address setting means when a read enable signal becomes active. The day The write means, characterized in that a reading means for reading the image data from the storage means and sequentially incremented by a second clock independent predetermined period.

A third means is that, in the first and second means, the read enable signal is provided by a beam detecting means provided in front of an effective printing area of the light writing beam of the light beam writing means in the main scanning direction. The second clock is a print pixel clock, which is a signal generated by a main scanning counter that starts counting from the output of the beam detection signal.

The fourth means is characterized in that the read enable signal is delayed according to the shift of the image position to the right in the first to third means.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of an image data processing apparatus according to the present invention, FIG. 2 is a timing chart showing main signals when the start position changing circuit in FIG. 1 does not change the start position, and FIG. 5 is a timing chart showing main signals when the start position changing circuit changes the start position.

FIG. 1 shows a digital copying machine 28 exemplified as an image data processing apparatus in the present embodiment. The same parts as those of the digital copying machine 1 described above as a conventional example are described in detail using the same names and reference numerals. Detailed description is omitted. First, as shown in FIG. 1, the digital copying machine 28 has a configuration in which a signal processing unit 29 and an image printing unit 4 are connected, and the signal processing unit 29 includes an image input unit 30 serving as image data writing means. , A line buffer memory 31 and a print control unit 32 as image data reading means are sequentially connected. Further, the synchronization detector 27 of the image printing unit 4 is connected to the image input unit 30 together with the print control unit 32.

An image data valid signal XLGATE output from the image input section 30 is applied to the start position changing circuit 33. The output signal of the start position changing circuit 33 is a write enable signal to the line buffer memory 31. XW
Applied as E. The image input unit 30 receives the synchronization detection signal XDETP from the synchronization detector 27 as a polygon motor synchronization signal XPMSYNC signal, and outputs the line synchronization signal XLSYN at a timing synchronized with the polygon motor synchronization signal XPMSYNC.
C as write reset signal XWRES in buffer memory 3
Output to 1. The delay time between the polygon motor synchronizing signal XPMSYNC signal and the line synchronizing signal XLSYNC varies depending on the processing in the image input unit, and is several tens to several hundreds of clocks.

The image data valid signal XL is delayed by a fixed number of clocks after the pulse of the line synchronization signal XLSYNC is output.
GATE becomes active. Image data valid signal XLGATE
Is a signal that is active during the valid period of the image data output from the image input unit 30, and the image data is output from the first pixel after this signal becomes active.

Here, in the digital copying machine 28, the line buffer memory 31 has a storage capacity of one line or more of the dot matrix image data, and corresponds to the data write corresponding to the write address and the read address. Data reading is simultaneously and independently performed. The image input unit 30 writes the image data in the line buffer memory 31 by sequentially incrementing the write address with a write clock of a predetermined period after the write enable signal XWE becomes active, and writing the image data into the line buffer memory 31. The read data is read from the line buffer memory 31 by sequentially incrementing the read address after the read enable signal becomes active at a read clock of a predetermined cycle independent of the image input unit 30.

More specifically, the line buffer memory 31
Are input terminals for image data Din to be written, output terminals for image data Dout to be read, input terminals for a write enable signal XWE, input terminals for a read enable signal XRE, input terminals for a write reset signal XWRES, and inputs for a read reset signal XRRES. Terminal, write clock WCL
A K input terminal, a read clock RCLK input terminal, a write address pointer (not shown) pointing to a write address, a read address pointer (not shown) pointing to a read address, and the like are provided.

Here, an input terminal of the line buffer memory 31 having a leading X means that the signal is active low. Then, the write address pointed by the write address pointer is reset to “0” by the write reset signal XWRES, and is incremented by the write clock WCLK when the write enable signal XWE is active. Similarly, the read address pointed by the read address pointer is reset to “0” by the read reset signal XRRES, and the read enable signal XR
It is incremented by the read clock RCLK when E is active.

Therefore, when image data is written in the line buffer memory 31, as shown in FIG.
After the write address is first reset by the write reset signal XWRES, when the write clock WCLK (SCLK) transitions from low to high while the write enable signal XWE is active, the line buffer memory 31 stores the write address WCLK (SCLK) with the write address WCLK (SCLK). Image data Din is written. Each time the write operation is performed, the write address is incremented, so that the image data Din
Is the write address “0” in the line buffer memory 31
Are written in order.

FIG. 2 shows a timing chart when the image data valid signal XLGATE output from the image input unit 30 is not delayed and the write enable XWE of the line buffer memory 31 is used. In this case, the data is stored in the line buffer memory 31 in order from the head pixel of the line. That is, the image data Din of the first pixel is written to the address 0 of the line buffer memory. When the image data Dout is read from the line buffer memory 31, after the read address is first reset by the read reset signal XRRESF, when the read clock RCLK transitions from low to high while the read enable signal XREF is active. The image data Dout is read from the line buffer memory 31 at the read address. Since the read address is incremented each time the read operation is performed, the image data Dout is sequentially read from the address 0 of the line buffer memory 31.

Since the generation timing of the read enable signal XREF is generated by the main scanning counter of the print control unit 32, the generation timing is changed by paper size or mechanical adjustment. The printing position in the main scanning direction can be changed according to the timing at which this signal is generated. The main scanning counter starts counting from the output of the light beam detection signal of the beam detection means provided before the effective printing area of the light writing beam of the light beam writing means in the main scanning direction.
The read enable signal XREF cannot be generated at a timing before the light beam detection signal, and therefore, the movement of the printing position in a direction to advance the timing is restricted.

The line buffer memory 31 has two lines of memory capacity of at least one readable and writable line. When one line memory is being written, it is read out from the other line memory. In the case of a toggle buffer system in which writing and reading are alternately repeated alternately, written data is read out with a delay of one line as shown in FIG. Alternatively, it can be realized by a one-line FIFO memory disclosed in JP-A-8-9119.

FIG. 3 is a timing chart in the case where the start position of the image data valid signal XLGATE signal output from the image input unit 30 is delayed by the start position changing circuit 33 to become the write enable signal XWE of the line buffer memory. In a system in which one pixel is transferred by one clock (SCLK), the start position of the XWE signal is determined by the image data valid signal X
If M clocks are delayed from LGATE, the image data of the (M + 1) th pixel is written to the address 0 of the buffer memory. Since the reading side of the line buffer memory 31 is sequentially read from address 0, the printing start pixel of the image is M +
This is the first image data. That is, a print image shifted by M pixels in the light beam detector direction (left direction) as compared with the case of FIG. 2 is obtained.

Direction away from light beam detector (rightward)
Can be moved by changing the generation timing of the read enable signal XRE, so that the combination of changing the generation timing of the write enable signal XWE signal and the generation timing of the read enable signal XRE The image can be moved to the left as well.

<Second Embodiment> A second embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing a second embodiment of the image data processing apparatus according to the present invention. FIG. 5 is a timing chart showing main signals when the initial read address by the initial read address setting circuit in FIG. 4 is 0. 6 is a timing chart showing main signals when the initial read address by the initial read address setting circuit in FIG. 4 is not 0.

In the second embodiment, the start position changing circuit 33 in FIG. 1 is omitted, and an initial read address setting circuit 33a is provided for the line buffer memory 31 instead. Then, the initial read address setting circuit 33a sets an address initialized by the XRRES signal of the image data Dout read from the buffer memory 31.

As shown in FIG. 5, when the image data Din is written into the line buffer memory 31, the write address is first reset by the write reset signal XWRES, and then the write clock is turned on while the write enable signal XWE is active. When WCLK (SCLK) transitions from low to high, the image data Din is written to the line buffer memory 31 at the write address. Since the write address is incremented each time this write operation is performed, the image data Din is written to the line buffer memory 31 in order from the write address “0”.

FIG. 5 shows an initial read address setting circuit 33.
A timing chart when the address specified by a is address 0, the image data of one line is M bytes, that is, the final address is M is shown. In this case, the data is stored in the line buffer memory 31 in order from the head pixel of the line. That is, the image data Din of the first pixel is written to the address 0 of the line buffer memory 31.

When the image data Dout is read from the line buffer memory 31, after the read address is first reset by the read reset signal XRRESF, the read clock RCLK is changed from low to high while the read enable signal XREF is active. , The image data Dout is read from the line buffer memory 31 at the read address. Since the read address is incremented each time the read operation is performed, the image data Dout is sequentially read from the address designated by the initial read address setting circuit 33a of the line buffer memory 31, in this case, from address 0.

Since the generation timing of the read enable signal XREF is generated by the main scanning counter of the print control unit, the generation timing is changed by paper size or mechanical adjustment. The printing position in the main scanning direction can be changed according to the timing of generation of this signal. The main scanning counter is
Since the counting is started from the output of the light beam detection signal of the beam detection means provided before the effective printing area of the light writing beam of the light beam writing means in the main scanning direction, the read enable signal XREF is set before the light beam detection signal. , The movement of the printing position in the direction to advance the timing is restricted.

The line buffer memory is readable and writable.
A toggle buffer system that has two lines of memory capacity equal to or more than one line and reads from the other line memory while writing to one line memory, and each memory alternately writes and reads one line at a time. For example, as shown in FIG. 5, the written data is read with a delay of one line. Or JP-A-8
As described in Japanese Patent Application Laid-Open No. 9119, it is also possible to realize with a one-line FIFO memory.

In FIG. 6, the initial read address setting circuit 3
A timing chart when the address designated by 3a is address L and the input image data of one line is M bytes, that is, the final address is M is shown. In the case of a system in which one byte has one pixel, the initial read address setting circuit 33
If the address designated by a is designated as address L, image data is read from address L of the line buffer memory and output to the print control unit. Line buffer memory 3
Since the writing side of 1 is written in order from address 0,
The print start pixel of the image is the L-th image data. That is, a print image shifted by L pixels in the direction of the light beam detector (leftward) as compared with the case shown in FIG. 5 is obtained.

The direction away from the light beam detector (rightward)
Can be moved by changing the timing of the generation of the read enable signal XRE, so by changing the initial read address and changing the timing of the generation of the read enable signal XRE, The image can be moved.

<Modifications and Application> Although not shown, there is also a system in which a plurality of pixels are transferred with one write clock SCLK in order to suppress the memory configuration and the frequency of the transfer clock. For example, in a system in which eight pixels are transferred by one clock, eight pixels are allocated to one address of the memory. In that case, the unit of movement by changing the generation timing of the write enable signal XWE signal is one clock, that is, eight pixels. In this case as well, the generation timing of the read enable signal XRE can usually be changed in units of the print pixel clock PCLK.
The image can be moved in pixel units.

In the above embodiment, the digital copying machine 28 is exemplified as a data processing device, and the image input section 30 for writing image data optically input by the CCD sensor 13 to the line buffer memory 31 is illustrated as data writing means. The print control unit 32 that prints out image data to be read out from the line buffer memory 31 by the image printing unit 4 is illustrated as the data reading unit.
The present invention is not limited to the above embodiment. For example, a DTP (Desk Top Publishing) system including a data writing unit for writing image data received from a host computer to a line buffer memory and a data reading unit for displaying and outputting image data to be read from the line buffer memory on a display Can be realized as a data processing device.

[0044]

As described above, according to the first aspect of the present invention, the write enable signal for writing to the line buffer memory is delayed by the line synchronization signal in accordance with the shift of the image position to the left. Therefore, the image can be moved in the main scanning direction to the left without any restriction with a simple configuration.

According to the second aspect of the present invention, the initial address of the read address read from the line buffer memory is made variable in accordance with the amount by which the image position is shifted to the left. The movement can be moved to the left without any restrictions.

According to the third aspect of the present invention, since the circuit for generating the read enable signal for reading out the line buffer uses the main scanning counter of the print control unit, the movement of the image of the image forming apparatus in the main scanning direction is performed. It can be realized with a simple configuration.

According to the present invention, both the write enable signal for writing to the line buffer memory or the initial address of the read address read from the line buffer memory and the timing of the read enable signal for reading the line buffer are controlled. By doing so, it is possible to move the image in both the right and left directions with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image data processing device according to the present invention.

FIG. 2 is a timing chart showing main signals when the start position changing circuit in FIG. 1 does not change the start position.

FIG. 3 is a timing chart showing main signals when the start position changing circuit of FIG. 1 changes the start position.

FIG. 4 is a block diagram showing a second embodiment of the image data processing device according to the present invention.

5 is a timing chart showing main signals when the initial read address by the initial read address setting circuit of FIG. 4 is 0. FIG.

FIG. 6 is a timing chart showing main signals when the initial read address by the initial read address setting circuit in FIG. 4 is not 0;

FIG. 7 is a block diagram showing a digital copying machine to which the image data processing device according to the present invention is applied.

[Explanation of symbols]

 Reference Signs List 30 image input unit (image data writing unit) 31 line buffer memory 32 print control unit 32 (image data reading unit) 33 start position changing circuit 33a initial read address setting circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 1/23 103 H04N 1/23 103Z 5C074 1/387 1/387 5C076 F term (reference) 2C087 BB10 BC01 BC05 BC07 5B047 AA01 BB02 CA21 CB25 EA07 EB13 5B057 AA11 BA02 CA12 CA16 CB12 CB16 CC01 CD02 CH11 5C072 AA05 BA02 EA05 HA02 HA13 UA12 XA05 5C073 AA03 BB07 CE04 5C074 AA10 BB03 H04A03 H03H04A02

Claims (4)

[Claims] 1. A storage means having a storage capacity of at least one line of image data of a dot matrix and capable of simultaneously and independently writing image data corresponding to a write address and reading image data corresponding to a read address. A write enable signal generating means for generating a write enable signal by delaying a line synchronizing signal in accordance with a shift of an image position to the left; and when a write enable signal generated by the write enable signal generating means becomes active. Initially, the write address is set to the initial state, and during the period in which the write enable signal is active, the write address is set to the first
Writing means for sequentially writing the image data in the storage means by incrementing the clock by the clock of (i), setting a read address to an initial state when a read enable signal is activated, and setting the read address to the data while the read enable signal is active. A reading means for reading out image data from the storage means by sequentially incrementing at a second clock having a predetermined cycle independent of the writing means. 2. A storage means having a storage capacity of one or more lines of dot matrix image data, and capable of simultaneously and independently writing image data corresponding to a write address and reading image data corresponding to a read address. When the write enable signal becomes active, the write address is initialized, and during the period in which the write enable signal is active, the write address is sequentially incremented by a first clock of a predetermined period to write image data into the storage means. Means, an initial read address setting means for setting an initial read address of the storage means in accordance with a shift of an image position to the left, and setting by the initial read address setting means when a read enable signal becomes active. Initial read address A reading means for sequentially reading out image data from the storage means by sequentially incrementing the address by a second clock having a predetermined period independent of the data writing means. 3. The main scanning which starts counting from an output of a light beam detection signal of a beam detection unit provided before an effective printing area of a light writing beam of a light beam writing unit in a main scanning direction. 3. The image data processing device according to claim 1, wherein the signal is a signal generated by a counter, and the second clock is a print pixel clock. 4. The data processing apparatus according to claim 1, wherein the read enable signal is delayed according to a shift of the image position to the right.