JPH09181711A - Clock pulse phase control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the clock pulse phase control circuit controlling a data signal and a clock pulse so as to have a proper phase relation at all times by absorbing a phase fluctuation or the like due to an ambient temperature change of the circuit and a power supply fluctuation or the like without employing an expensive component and a complicated temperature compensation circuit. SOLUTION: The clock signal phase control circuit has a means that detects a phase difference between a frame pulse given to a frame pulse input terminal 4 and a clock pulse given to a clock pulse input terminal 7 and controls a phase of the clock pulse depending on the phase difference. The means controlling the phase of the clock pulse includes a flip-flop 5, a delay circuit 8, a buffer 9, flip-flop circuits 11, 12, a low pass filter 13 and an operational amplifier 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit applied to a digital signal processing device, and in particular,
The present invention relates to a clock pulse phase control circuit that controls a phase between a data signal and a clock pulse signal.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional clock pulse phase control circuit. Referring to FIG. 4, this clock pulse phase control circuit has data signal input terminals 51-1 to 51-1.
-N and flip-flop (F / F except for a part
52-1 to 52-n and the data signal output terminal 5
3-1 to 53-n, a frame pulse (hereinafter, referred to as FP except for a part) input terminal 54, an F / F 55, and an FP
It has an output terminal 56, a clock pulse input terminal 57, a delay circuit 58, and a buffer 59.

The n data signals input to the data signal input terminal 51-n are input to the data input terminal of the F / F 52-n. In the F / F 52-n, the input data signals are retimed by clock pulses having the same phase, and n data signals that have been identified and reproduced are output to the data signal output terminals 53-n. Similarly, F
The FP input to the P input terminal 54 is also retimed by the clock pulse having the same phase as that of the F / F 52-n in the F / F 55 and output to the FP output terminal 56. The clock pulse input to the clock pulse input terminal 57 passes through a delay circuit 58 including a coaxial cable, a distributed constant type delay line, etc.
Clock pulses of the same phase are supplied to / F52-n and 55.

In the prior art, the phase between the data signal input to each F / F and the FP and the clock pulse is adjusted to the optimum phase by first setting the delay amount of the delay circuit 58. .

[0005]

In the above-mentioned conventional example, since the phase of the clock pulse is first set and then the clock pulse is operated at this set value, all the phase fluctuations due to changes in the ambient temperature of the circuit, fluctuations in the power supply, etc. The input phase margin of F / F had to be absorbed. Therefore, in order to suppress the phase fluctuation of each circuit as much as possible, expensive components and complicated temperature compensation circuits may be required. However, even if such a method is used, the phase variation cannot be completely suppressed because the open loop control is performed.

An object of the present invention is to absorb phase fluctuations due to changes in the ambient temperature of the circuit, fluctuations in power supply, etc. without using expensive parts or complicated temperature compensating circuits, and always optimize the phase of data signals and clock pulses. (EN) Provided is a clock pulse phase control circuit which can be controlled to be related.

[0007]

According to the present invention, in an interface circuit for inputting a data signal, a frame identification pulse signal, and a clock pulse and retiming the data signal and the frame pulse, the interface pulse of the frame pulse and the clock pulse is A clock pulse phase control circuit is obtained which has means for detecting a phase difference between them and controlling the phase of a clock pulse according to this phase difference.

Further, according to the present invention, the means for controlling the phase of the clock pulse, the delay circuit for changing the phase of the input clock pulse according to the control voltage, and the delayed clock pulse are input, the mutual phase Generate two kinds of clock pulses of positive phase and negative phase different by 180 degrees, and use the positive phase clock as a clock for retiming the data signal and the frame pulse, while the negative phase clock retiming only the input frame pulse To be used as a clock for re-timing the frame pulse retimed by the negative phase clock by the frame pulse retimed by the positive phase clock, and the waveform of the retimed frame pulse. A low-pass filter that removes high-frequency components,
There is provided the clock pulse phase control circuit including means for applying negative feedback to the control input of the delay circuit so that the output of the low pass filter becomes constant. In addition, the first to retime the frame pulse by the positive phase clock
Flip-flop, a second flip-flop for retiming only an input frame pulse by a reverse-phase clock, and a frame pulse retimed by the second flip-flop for the frame retimed by the first flip-flop. A clock pulse phase control circuit is obtained having a third flip-flop that is retimed by a pulse.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock pulse phase control circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a clock pulse phase control circuit according to an embodiment of the present invention. FIG.
(G) is a figure which shows the example of a waveform of each part in this clock pulse phase control circuit, (a) is a data signal, (b) is
Is a frame pulse, and (c) and (d) are CLK described later.
1, CLK2, (e) to (g) indicate the outputs of three flip-flops described later. FIG. 3 is a diagram showing a characteristic example of the clock pulse phase control circuit.

In FIG. 1, the present clock pulse phase control circuit includes data signal input terminals 1-1 to 1-n, flip-flops (F / F) 2-1 to 2-n, and a data signal output terminal 3-. 1-3-n, the frame pulse (FP) input terminal 4, the F / F 5, the FP output terminal 6, the clock pulse input terminal 7, the delay circuit 8, the buffer 9, and the F / F.
F11 and 12 and low pass filter (LPF) 13
And an operational amplifier 14 and a reference voltage 15.

Referring to FIGS. 1 to 3, the n data signals input to the data signal input terminal 1-n are F / F52.
-N is input to the data input terminal. Data input 1-n
And FP are retimed in the F / Fs 2-n and 5 and output to the data signal output terminal 3-n and the FP output terminal 6.

The clock for retiming the F / F2-n and FP is the clock input from the clock pulse input terminal 7 supplied through the delay circuit 8 and the buffer 9. This clock is referred to as CLK1. . Also, a clock pulse having a phase difference of 180 degrees with respect to CLK1 is output from the buffer 9 as well.
K2.

In the F / F 11, the F input to the F / F 5
The same FP as P is retimed by CLK2 (FIG. 2 (e)). The output of the F / F 11 is retimed again by the output FP of the F / F 5 in the F / F 12. Here, paying attention to the operations of the F / F5 and F / F11, the two F / Fs are input with the same FP, and retiming is performed based on the clock pulses CLK1 and CLK2 whose phase relationships are different by 180 degrees. doing. Therefore, when the F / F5 operates at the phase optimum point, the F / F11 operates at the worst phase point, and conversely, when the F / F5 operates at the phase optimum point, the worst case phase occurs at the F / F11. Will work in points.

FIG. 2 shows the case where the F / F 5 operates at the phase optimum point, but the F / F 11 operates at the phase worst point, and the output waveform is as shown in FIG. An uncertain place occurs for one clock. This indeterminate portion for one clock is extended by the output FP of F / F5, and F / F12
A waveform as shown in FIG. F / F1
When 1 is in the worst state of phase, the output of this F / F 12 appears at the H level and the L level almost equal to each other.
The output voltage of the PF 13 is as shown in FIG. And L
The operational amplifier 14 is arranged so that the output of the PF 13 becomes the optimum point.
And the negative feedback is applied to the delay circuit 8 via the reference voltage 15.

[0016]

The clock pulse phase control circuit according to the present invention has means for detecting the phase difference between the frame pulse and the clock pulse and controlling the phase of the clock pulse according to this phase difference. The data signal and the clock pulse are controlled so as to always have the optimum phase relationship, and the phase fluctuations of the data and the clock due to temperature fluctuations, power supply voltage fluctuations, aging fluctuations, etc. are absorbed, and the optimum phase relationship is maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a clock pulse phase control circuit according to an embodiment of the present invention.

2 (a) to (g) are diagrams showing waveform examples of respective parts in the clock pulse phase control circuit shown in FIG.

FIG. 3 is a characteristic example in the clock pulse phase control circuit shown in FIG.

FIG. 4 is a diagram showing a conventional clock pulse phase control circuit.

[Explanation of symbols]

 1-1 to 1-n data signal input terminal 2-1 to 2-n flip-flop (F / F) 3-1 to 3-n data signal output terminal 4 frame pulse (FP) input terminal 5 F / F 6 FP Output terminal 7 Clock pulse input terminal 8 Delay circuit 9 Buffer 11, 12 F / F 13 Low pass filter (LPF) 14 Operational amplifier 15 Reference voltage

Claims (3)

[Claims] 1. A data signal, a frame identification pulse signal,
In the interface circuit for inputting the clock pulse and the clock pulse and retiming the data signal and the frame pulse, a means for detecting the phase difference between the frame pulse and the clock pulse and controlling the phase of the clock pulse according to the phase difference is provided. A clock pulse phase control circuit having. 2. The means for controlling the phase of the clock pulse, the delay circuit for changing the phase of the input clock pulse according to the control voltage, and the delayed clock pulse are input, the positive phase different from each other by 180 degrees. Phase and reverse phase 2
Means for generating different types of clock pulses, using the positive-phase clock as a clock for retiming the data signal and the frame pulse, while using the negative-phase clock as a clock for retiming only the input frame pulse; A means for retiming the frame pulse retimed by the negative phase clock by the frame pulse retimed by the positive phase clock, and a low-pass filter for removing high frequency components of the waveform of the retimed frame pulse, The clock pulse phase control circuit according to claim 1, further comprising means for applying negative feedback to the control input of the delay circuit so that the output of the low pass filter becomes constant. 3. A first flip-flop for retiming a frame pulse with a positive-phase clock, a second flip-flop for retiming only an input frame pulse with a negative-phase clock, and a retiming by the second flip-flop. 3. The clock pulse phase control circuit according to claim 2, further comprising a third flip-flop for retiming the generated frame pulse with the frame pulse retimed by the first flip-flop.