JP4481884B2 - PLL circuit and semiconductor device including PLL circuit - Google Patents

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit and a semiconductor device including the PLL circuit, and more particularly to a PLL circuit for generating jitter and a semiconductor device including the PLL circuit.

  In recent years, the transfer rate of data between devices has been increased, and transmission at a high data rate has been realized. In such a high data rate transmission, in parallel transmission, it becomes difficult to secure a skew between parallel signals as the speed increases, and thus the limit of the transfer speed has become apparent. For this reason, serial transmission is gradually being used for high-speed transmission. Jitter characteristics are important in high-speed serial transmission. The fluctuation of the signal, which was not a problem in the low-speed transmission, becomes obvious as the transmission error increases as the speed increases. When this jitter increases to some extent, data transmission cannot be performed normally.

  When a certain amount of jitter is present in the transmitter, the jitter generated by the signal line frequency characteristics and ISI (Inter Symbol Interference) is superposed along with the signal transmission. In the receiver, it is necessary to receive a signal in which jitter generated in the transmitter and jitter superimposed during transmission are added, and to reproduce the original digital signal to be transmitted. Therefore, it is required to measure the jitter tolerance of the receiver in the transmission system.

  One method of measuring jitter tolerance is to add a jitter component to the data. In this case, the data is phase-modulated or FM-modulated and the data is sent to the serial I / F device to test whether the device CDR (Clock and Data Recovery) can receive it normally. In this test, it is necessary to create a measurement environment for applying jitter components by modulating data.

  On the other hand, there is a method of putting a jitter component on the clock side supplied to the CDR. Receiving normal data using a CDR that operates with a clock modulated with jitter is the same as receiving data modulated with jitter with a CDR that operates with a normal clock, and the same test is possible. It becomes. Even in this test method, a measurement environment must be established.

  By the way, in a transmission system, a PLL circuit is often used to generate a transmission / reception timing clock. The PLL circuit is a circuit that inputs a reference clock and outputs a clock having a frequency multiplied by the reference clock. In such a PLL circuit, it is common to generate a clock having a frequency multiplied by a voltage controlled oscillator (VCO). A technique is known in which a modulation signal generator is attached immediately before this voltage controlled oscillator, the frequency of the output signal output from the voltage controlled oscillator is fluctuated, and a clock including a jitter component is generated (for example, a patent). Reference 1).

  In the PLL circuit described in Patent Document 1, a signal output at a frequency corresponding to the voltage of the control signal from the voltage controlled oscillator is frequency-divided by a frequency divider, and this frequency-divided signal and the reference signal output from the reference signal generator The signal is input to a phase frequency comparator. An error signal corresponding to the phase difference between the divided signal and the reference signal is extracted from the output signal of the phase frequency comparator by a low-pass filter, and the error signal and the modulation signal output from the modulation signal generator are added by an adder. to add. The added signal is input to the voltage controlled oscillator as a control signal. The modulation signal generator outputs to the adder a modulation signal having a frequency corresponding to the specified jitter frequency and having an amplitude corresponding to the specified jitter amount. Thus, the output signal output from the voltage controlled oscillator has a fluctuation in frequency, and a clock including a jitter component is generated.

JP 2000-230953 A (FIG. 2)

  Conventionally, a device reception test is performed by putting a jitter component on data or a clock, but a device corresponding to a measuring instrument for performing jitter modulation on the clock generator or the data generator is required. For example, according to the technique described in Patent Document 1, a controllable modulation signal generator is required. However, with such a configuration, there is a concern that the circuit scale may increase, especially considering that a clock with jitter is easily generated by being incorporated in an LSI or the like.

A PLL circuit according to an aspect of the present invention that solves the above-described problem is a phase comparator that compares the phase of an input reference signal and the output signal of a frequency divider to be fed back and outputs an output signal corresponding to the phase difference A filter unit that passes a low-frequency component of the output signal of the phase comparator, a voltage-controlled oscillator that generates an oscillation signal having an oscillation frequency controlled based on the output voltage of the filter unit, and the oscillation signal A PLL circuit comprising: the frequency divider that circulates and outputs to the phase comparator; and a wiring unit that induces noise from outside, and a noise signal induced by the wiring unit is added to the output signal of the filter unit The wiring portion includes a wiring that is wired close to at least one of a power supply line and a ground line in the semiconductor device .

  According to the present invention, since a wiring section for inducing noise from the outside is simply added to the conventional PLL circuit, the circuit scale is small and a clock including a jitter component can be easily generated.

  FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention. In FIG. 1, the PLL circuit includes a phase comparator 11, a filter unit 12, a voltage controlled oscillator 13, a frequency divider 14, and a wiring unit 15. The phase comparator 11 compares the phase of the input reference clock signal CKR and the signal fed back from the frequency divider 14 and outputs an output signal corresponding to the phase difference to the filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 and outputs it to the voltage controlled oscillator 13. The voltage controlled oscillator 13 generates an oscillation signal having an oscillation frequency controlled based on the output voltage of the filter unit 12 as an output signal CKF. The frequency divider 14 divides the output signal CKF and outputs it to the phase comparator 11. The wiring unit 15 connects one end Q of the wiring of the wiring unit 15 to the output P of the filter unit 12 so as to induce noise from the outside and add it to the output signal of the filter unit 12.

  In the PLL circuit configured as described above, noise induced from the outside is added to the output signal of the filter unit 12 and input to the voltage controlled oscillator 13, so that the oscillation frequency of the output signal CKF generated by the voltage controlled oscillator 13 Fluctuates due to noise. That is, a jitter component due to noise is added to the output signal CKF.

  According to such a PLL circuit, the jitter tolerance test is performed by supplying the output signal CKF, which is a clock subjected to jitter modulation, to the CDR or the like without creating a measurement environment in which jitter is applied to the data and the clock. It can be done easily. At this time, it is possible to generate a clock with jitter with a simple circuit configuration without the need for a modulation signal generator in the prior art. Since the circuit configuration is extremely simple, it is particularly suitable for incorporation in a semiconductor device.

  FIG. 2 is a block diagram showing the configuration of the PLL circuit according to the embodiment of the present invention. The PLL circuit of FIG. 2 includes a phase comparator 11a, a voltage controlled oscillator 13, a frequency divider 14, a wiring unit 15, a charge pump 16, and a low-pass filter 12a. The basic operation is the same as that of the PLL circuit of FIG. is there. 2, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted. The output of the phase comparator 11 a is input to the charge pump 16, and the output of the charge pump 16 is connected to one end P of the low-pass filter 12 a, the input of the voltage controlled oscillator 13, and one end Q of the wiring unit 15. The phase comparator 11a compares the phases of the input reference clock signal CKR and the signal fed back from the frequency divider 14, and outputs an up signal or a down signal with a pulse width corresponding to the comparison result. The charge pump 16 outputs a positive or negative current pulse according to the up signal or the down signal. These current pulses are integrated by the low-pass filter 12a and output to the voltage controlled oscillator 13 as a control signal from which the high frequency component has been cut. This control signal includes fluctuations due to the noise signal induced by the wiring section 15. become. The voltage controlled oscillator 13 generates an oscillation signal having an oscillation frequency based on the control signal as an output signal CKF. Since the control signal includes fluctuation due to the noise signal, the output signal CKF includes a jitter component.

  Next, details of the wiring section 15 will be described. The wiring unit 15 is disposed in the vicinity of the wiring 21 that generates noise. The wiring 21 that generates noise is preferably a power line 22 as shown in FIG. 3 or a GND line 23 as shown in FIG. The power supply line 22 or the GND line 23 is, for example, a power supply line or a GND line in a semiconductor device in which a PLL circuit is built, and is a wiring that generates noise in accordance with the operation of the semiconductor device. Further, as shown in FIG. 5, the wiring part may be branched into a wiring part 15 a and a wiring part 15 b, and each may be arranged close to the power supply line 22 and the GND line 23.

  As described above, by arranging the wiring portion 15 in the vicinity of the wiring 21 that generates noise (the power supply line 22, the GND line 23, etc.), noise is not generated in the wiring portion 15 by capacitive coupling and / or electromagnetic induction. Inductively connected. The induced noise becomes a jitter component at the oscillation frequency of the output signal CKF of the voltage controlled oscillator 13. In addition, if it is set as a structure as shown in FIG. 5, a bigger noise can be induced | guided | derived.

  The wiring unit 15 includes switch units 20a to 20n. The wiring in the wiring section 15 is divided according to the number of switch sections, and the switch section 20a is arranged between the divided wirings so that the effective length of the wiring (the length of the wiring that induces noise) can be adjusted. ~ 20n are inserted respectively. And opening / closing of the switch parts 20a-20n is each controlled by a control signal not shown. If the switch portions 20a, 20b,... 20n are arranged from the side closer to one end Q of the wiring of the wiring portion 15, the length of the wiring is the shortest when all the switch portions are opened, and the switch portions 20a, 20b,. By closing 20n in order, the length of the wiring is sequentially increased. In this way, the length of the wiring is changed by opening and closing the switch units 20a to 20n, and the amplitude of the induced noise is controlled. By controlling the amplitude of noise, the jitter amount of the output signal output from the voltage controlled oscillator 13 can be made variable.

  Next, the configuration of the switch unit will be described. FIG. 6 is a diagram illustrating a configuration of the switch unit 20i (i = a to n). The switch unit 20i includes switch elements SW1, SW2, and SW3. The switch elements SW1 and SW2 are inserted in cascade between one end N1 of the wiring and one end N2 of the other wiring. The switch element SW3 is connected between the connection point of the switch elements SW1 and SW2 and the ground or the power supply (in FIG. 6, it is connected to the ground). The switch elements SW1 and SW2 and the switch element SW3 perform reverse opening / closing operations. That is, when the switch elements SW1 and SW2 are “ON” as shown in FIG. 6A, the switch element SW3 is “OFF”, and as shown in FIG. 6B, the switch elements SW1 and SW2 are “OFF”. ", The switch element SW3 is controlled to be" ON ".

  When the switch unit is shown in FIG. 6B, the switch element SW3 is turned on so that the switch elements SW1 and SW2 are not completely cut off due to capacitive coupling or the like. Thereby, the connection point of the switch elements SW1 and SW2 is connected to the GND potential, and noise transmitted by capacitive coupling of the open switch elements SW1 and SW2 can be cut off.

  Next, a specific circuit configuration of the switch unit will be described. FIG. 7 is a diagram illustrating a specific circuit configuration of the switch unit 20i (i = a to n). The switch elements SW1, SW2, and SW3 in FIG. 6 are configured by NMOS transistors MN1, MN2, and MN3, respectively. Further, a control signal CNT for controlling opening / closing of the switch unit is applied to the gates of the NMOS transistors MN1 and MN2, and a signal obtained by inverting the control signal CNT by the inverter INV is applied to the gate of the NMOS transistor MN3. The NMOS transistors MN1 and MN2 and the NMOS transistor MN3 are controlled to open and close by the control signal CNT. Since this switch section can be easily configured with three NMOS transistors and one inverter, the circuit scale can be reduced.

  Further, as shown in FIG. 8, the switch elements SW1, SW2, and SW3 in FIG. 6 may be configured by PMOS transistors MP1, MP2, and MP3, respectively. In this case, the connection point of the PMOS transistors MP1, MP2, and MP3 is connected to the power supply VDD. A control signal CNT for controlling opening / closing of the switch unit is applied to the gate of the PMOS transistor MP3, and a signal obtained by inverting the control signal CNT by the inverter INV is applied to the gates of the PMOS transistors MP1 and MP2. The PMOS transistors MP1 and MP2 and the PMOS transistor MP3 are controlled to be opened and closed by the control signal CNT. Since this switch section can be easily configured with three PMOS transistors and one inverter, the circuit scale can be reduced.

  Further, as shown in FIG. 9, the switch elements SW1, SW2, and SW3 in FIG. 6 are transferred by respective transfer gates including the NMOS transistor MN4 and the PMOS transistor MP4, the NMOS transistor MN5 and the PMOS transistor MP5, and the NMOS transistor MN6 and the PMOS transistor MP6. It may be configured. The gates of the NMOS transistors MN4, MN5, and the PMOS transistor MP6 are supplied with a control signal CNT that controls the opening and closing of the switch unit. The gates of the NMOS transistors MN6, PMOS transistors MP4, and MP5 are inverted by the inverter INV. Signal is given. The NMOS transistors MN4 and MN5, the PMOS transistors MP4 and MP5, and the NMOS transistor MN6 and the PMOS transistor MP6 are controlled to open and close by the control signal CNT. By adopting a transfer gate configuration, it is possible to reliably perform on / off control over a wide input range.

It is a block diagram which shows the structure of the PLL circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the PLL circuit which concerns on the Example of this invention. It is a figure which shows the example of arrangement | positioning of a wiring part. It is a figure which shows other examples of arrangement | positioning of a wiring part. It is a figure which shows the further another example of arrangement | positioning of a wiring part. It is a figure which shows the structure of a switch part. It is a circuit diagram of the switch part comprised by the NMOS transistor. It is a circuit diagram of the switch part comprised by the PMOS transistor. It is a circuit diagram of the switch part comprised by the transfer gate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 11a Phase comparator 12 Filter part 12a Low pass filter 13 Voltage control oscillator 14 Frequency divider 15, 15a, 15b Wiring part 16 Charge pump 20a-20n Switch part 21 Wiring 22 Power supply line 23 GND line INV Inverter MN1-MN6 NMOS transistor MP1 to MP6 PMOS transistors SW1 to SW3 Switch elements

Claims (6)

A phase comparator that compares the phase of the input reference signal and the output signal of the divider to be fed back and outputs an output signal corresponding to the phase difference, and a filter that passes the low-frequency component of the output signal of the phase comparator A voltage controlled oscillator that generates an oscillation signal having an oscillation frequency controlled based on an output voltage of the filter unit, and the frequency divider that divides the oscillation signal and outputs the divided signal to the phase comparator. In the PLL circuit provided,
It has a wiring part that induces noise from outside,
The noise signal induced in the wiring unit is configured to be added to the output signal of the filter unit ,
The PLL circuit according to claim 1, wherein the wiring portion includes a wiring that is wired close to at least one of a power supply line and a ground line in the semiconductor device .   The PLL circuit according to claim 1, wherein one end of a wiring included in the wiring unit is connected to an input terminal of the voltage controlled oscillator. The wiring section, PLL circuit according to claim 1, wherein it contains one or more of the switch unit which allows adjusting the effective length of the wiring. The switch unit is connected between the first and second switch elements connected in cascade between the wirings, and a connection point between the first and second switch elements and a ground or a power source. 4. The PLL circuit according to claim 3 , further comprising a third switch element that performs an opening / closing operation opposite to the first and second switch elements. 5. The PLL circuit according to claim 4 , wherein the first, second and third switch elements are MOS transistors whose opening and closing are controlled by a control signal applied to a gate. A semiconductor device comprising: a PLL circuit according to any one of claims 1-5.

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