JPH09181343A - Photoelectric conversion device - Google Patents

Photoelectric conversion device

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Publication number
JPH09181343A
JPH09181343A JP7339774A JP33977495A JPH09181343A JP H09181343 A JPH09181343 A JP H09181343A JP 7339774 A JP7339774 A JP 7339774A JP 33977495 A JP33977495 A JP 33977495A JP H09181343 A JPH09181343 A JP H09181343A
Authority
JP
Japan
Prior art keywords
amorphous silicon
silicon layer
type
thickness
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7339774A
Other languages
Japanese (ja)
Inventor
Kouichirou Shinraku
浩一郎 新楽
Hideki Shiroma
英樹 白間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7339774A priority Critical patent/JPH09181343A/en
Publication of JPH09181343A publication Critical patent/JPH09181343A/en
Pending legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/545Microcrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

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  • Photovoltaic Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To optimize the thickness of thickness silicon layers and to improve a voltage-current characteristic especially in low illuminance by providing a back electrode layer on one main face side of a substrate constituted of crystal silicon and sequentially stacking first and second amorphous silicon layers with specified thickness, and light-receiving electrode layer on the other main face. SOLUTION: The back electrode layer 8 is provided on one main face side of the substrate 1 constituted of p-type or n-type crystal silicon, and the i-type first amorphous silicon layer 2, the p-type or n-type second amorphous silicon layer 3 and the light-receiving electrode layer 4 are sequentially stacked on the other main face of the substrate 1. The thickness of the first amorphous silicon layer 2 is set to be less than 400Å, and the thickness of the second amorphous silicon layer 3 is set to be less than 100Å. Especially, the thickness of the second amorphous silicon layer 3 is set to be optimum one for suppressing the absorption of light. Thus, the voltage-current characteristic becomes satisfactory especially in low illuminance, and the photoelectric conversion device S of the solar battery superior in high efficiency and the optical sensor superior in the characteristic can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、光センサや太陽電
池等に用いられる光電変換装置に関し、特に結晶系シリ
コン上に非晶質シリコン層を積層させた光電変換装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device used for photosensors, solar cells, and the like, and more particularly to a photoelectric conversion device in which an amorphous silicon layer is laminated on crystalline silicon.

【0002】[0002]

【従来技術とその問題点】従来より、結晶シリコン(多
結晶シリコンもしくは単結晶シリコン)から成る基板上
に非晶質シリコンを積層し、高い変換効率が得られるヘ
テロ接合光電変換装置に関する研究が盛んに行われてい
る。
2. Description of the Related Art Conventionally, much research has been done on a heterojunction photoelectric conversion device in which amorphous silicon is laminated on a substrate made of crystalline silicon (polycrystalline silicon or single crystalline silicon) to obtain high conversion efficiency. Has been done in.

【0003】例えば、図6に示すように、結晶シリコン
基板51の一主面(裏面)に、金−アンチモンから成る
金属膜52を設け、この結晶シリコン51の他の主面
(受光面)に非晶質のシリコンカーバイド膜53を設
け、このシリコンカーバイド膜53上に透明導電膜54
を設けた光電変換装置Jが知られている(例えば、Jpn.
J. Appl. Phys. 23 (1984) 515.を参照)。
For example, as shown in FIG. 6, a metal film 52 made of gold-antimony is provided on one main surface (rear surface) of a crystalline silicon substrate 51, and the other main surface (light receiving surface) of this crystal silicon 51 is provided. An amorphous silicon carbide film 53 is provided, and a transparent conductive film 54 is formed on the silicon carbide film 53.
A photoelectric conversion device J provided with is known (for example, Jpn.
J. Appl. Phys. 23 (1984) 515.).

【0004】また、結晶のシリコン基板の上にi型非晶
質シリコン層及びn型微結晶質シリコン層、透明電極層
を順次積層させたような光電変換装置において、n型の
非晶質シリコン層を100 Å以上の厚さに積層し、しかも
不純物濃度を非常に高くしたものも知られている(例え
ば、12TH EUROPEAN PHOTOVOLTAIC SOLAR ENERGY CONF.
11-15 APRIL 1994. 705-708 を参照)。
In a photoelectric conversion device in which an i-type amorphous silicon layer, an n-type microcrystalline silicon layer, and a transparent electrode layer are sequentially stacked on a crystalline silicon substrate, an n-type amorphous silicon layer is used. It is also known that the layers are laminated to a thickness of 100 Å or more and the impurity concentration is extremely high (for example, 12TH EUROPEAN PHOTOVOLTAIC SOLAR ENERGY CONF.
11-15 APRIL 1994. 705-708).

【0005】しかしながら、このようなヘテロ接合光電
変換装置においては、ダイオード特性を向上させるため
に、不純物をドーピングさせた層(p型もしくはn型の
層)が厚く(例えば200 Å以上)、さらに不純物濃度も
高いために、入射光が光電流に変換可能な領域に到達す
る前に、この層において吸収されてしまう割合が大きか
った。このため、変換効率の向上が期待できないという
問題を有している。
However, in such a heterojunction photoelectric conversion device, in order to improve the diode characteristics, the impurity-doped layer (p-type or n-type layer) is thick (for example, 200 Å or more), and the impurity is further increased. Due to the high concentration, a large proportion of incident light is absorbed in this layer before it reaches the region where it can be converted into photocurrent. Therefore, there is a problem that improvement in conversion efficiency cannot be expected.

【0006】そこで、このような従来の光電変換装置の
諸問題を解消し、結晶シリコンに積層させる非晶質シリ
コン層の厚さを最適化して、特に低照度における電圧−
電流特性の優れた光電変換装置を提供することを目的と
する。
Therefore, various problems of the conventional photoelectric conversion device are solved, and the thickness of the amorphous silicon layer to be laminated on the crystalline silicon is optimized so that the voltage-especially at low illuminance.
It is an object to provide a photoelectric conversion device having excellent current characteristics.

【0007】[0007]

【課題を解決するための手段】上記目的を達成する光電
変換装置は、p型もしくはn型の結晶シリコンから成る
基板の一主面側に裏面電極層を設けるとともに、前記基
板の他主面上に、厚さが400 Å以下のi型の第1非晶質
シリコン層、p型もしくはn型で且つ厚さが100 Å以下
の第2非晶質シリコン層、及び受光面電極層を順次積層
させて成る。
A photoelectric conversion device which achieves the above object is provided with a back electrode layer on one main surface side of a substrate made of p-type or n-type crystalline silicon and on the other main surface of the substrate. In addition, an i-type first amorphous silicon layer having a thickness of 400 Å or less, a second amorphous silicon layer of p-type or n-type having a thickness of 100 Å or less, and a light-receiving surface electrode layer are sequentially laminated. It will be done.

【0008】ここで、特に低照度域での変換効率を向上
させるために、第1非晶質シリコン層の厚さはより好適
には50〜200 Åがよく、また第2非晶質シリコン層の厚
さはより好適には40〜90Åがよい。すなわち、第1非晶
質シリコン層はこのように最適化することにより、光電
流の取り出しに支障が無くなり(第1非晶質シリコン層
が厚すぎると結晶シリコン側で発生した光生成キャリア
が光電流として取り出しにくくなる)、第2非晶質シリ
コン層は光の吸収を抑制し、かつ適度なダイオード特性
が得られる。
Here, in order to improve the conversion efficiency particularly in the low illuminance region, the thickness of the first amorphous silicon layer is more preferably 50 to 200Å, and the second amorphous silicon layer is more preferable. The thickness is more preferably 40 to 90Å. That is, by optimizing the first amorphous silicon layer in this way, there is no hindrance to the extraction of photocurrent (if the first amorphous silicon layer is too thick, the photo-generated carriers generated on the crystalline silicon side are exposed to light). It becomes difficult to take out as a current), and the second amorphous silicon layer suppresses absorption of light, and an appropriate diode characteristic is obtained.

【0009】なお、p型もしくはn型の非晶質シリコン
層は完全な非晶質でなくともよく、微結晶が混入された
いわゆる微結晶層であってもよい。
The p-type or n-type amorphous silicon layer does not have to be completely amorphous, and may be a so-called microcrystalline layer in which microcrystals are mixed.

【0010】[0010]

【発明の実施の形態】本発明に係る実施例について図面
に基づき詳細に説明する。図1に示す光電変換装置S
は、照明灯が蛍光灯や白熱灯等の光の波長が種々のもの
であっても、変換効率を高く維持することが可能な太陽
電池であり、その理想的な基本構造は以下に示す通りで
ある。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to the drawings. Photoelectric conversion device S shown in FIG.
Is a solar cell that can maintain high conversion efficiency even when the illumination light has various wavelengths of light such as fluorescent light and incandescent light. Its ideal basic structure is as shown below. Is.

【0011】図1に示すように、光電変換装置Sは、p
型もしくはn型の結晶シリコンの基板1の一主面(裏
面)1b側に裏面電極層8が設けられ、基板1の他主面
(受光面)1a上に、i型の第1非晶質シリコン層2、
p型もしくはn型で且つ基板1の他主面の面積より狭い
被着面積の第2非晶質シリコン層3、及び受光面電極層
4を順次積層させて成る。
As shown in FIG. 1, the photoelectric conversion device S has p
-Type or n-type crystalline silicon is provided with a back surface electrode layer 8 on the one main surface (back surface) 1b side of the substrate 1, and on the other main surface (light receiving surface) 1a of the substrate 1, the i-type first amorphous Silicon layer 2,
The second amorphous silicon layer 3 having a deposition area smaller than the area of the other main surface of the p-type or n-type substrate 1 and the light-receiving surface electrode layer 4 are sequentially laminated.

【0012】具体的には、導電型がp型の多結晶シリコ
ンから成る基板1の受光面1a側には、基板1の受光面
1aのほぼ全面に導電型がi型の第1非晶質シリコン層
2が設けられ、この第1非晶質シリコン層2上には、周
縁部がパターニング除去され、被着面積が基板1の受光
面1aの面積より狭く、導電型がn型の第2非晶質シリ
コン層3が設けられ、この第2非晶質シリコン層3上に
は、さらに周縁部がパターニングされたITO(酸化イ
ンジウム・スズ)から成り、第2非晶質シリコン層3よ
り被着面積が狭い受光面電極層4が設けられ、この受光
面電極層4上には導電ペースト,導電ペースト+半田,
もしくは金属膜などから成る出力の取り出し電極5が設
けられている。
Specifically, on the light-receiving surface 1a side of the substrate 1 made of polycrystalline silicon having a p-type conductivity, the first amorphous material having the i-type conductivity is formed on almost the entire light-receiving surface 1a of the substrate 1. A silicon layer 2 is provided, and a peripheral portion is patterned and removed on the first amorphous silicon layer 2, and a deposition area is smaller than an area of the light receiving surface 1a of the substrate 1 and a second conductivity type is an n type. An amorphous silicon layer 3 is provided, and the second amorphous silicon layer 3 is made of ITO (indium tin oxide) whose peripheral portion is patterned, and is covered by the second amorphous silicon layer 3. A light-receiving surface electrode layer 4 having a small mounting area is provided, and a conductive paste, a conductive paste + solder,
Alternatively, an output extraction electrode 5 made of a metal film or the like is provided.

【0013】また、基板1の裏面1b側には、基板1の
裏面1bのほぼ全面にi型の第3非晶質シリコン層6が
設けられ、この第3非晶質シリコン層6上には、周縁部
がパターニングされ、被着面積が基板1の裏面1bの面
積より狭く、導電型がp型の第4非晶質シリコン層7が
設けられ、この第4非晶質シリコン層7上には、周縁部
がパターニングされ、被着面積が第4非晶質シリコン層
7より狭いアルミニウムから成る裏面電極層8が設けら
れている。
On the back surface 1b side of the substrate 1, an i-type third amorphous silicon layer 6 is provided on almost the entire back surface 1b of the substrate 1, and on the third amorphous silicon layer 6. A peripheral portion is patterned, a deposition area is narrower than the area of the back surface 1b of the substrate 1, and a fourth amorphous silicon layer 7 having a conductivity type of p is provided, and on the fourth amorphous silicon layer 7. Is provided with a back surface electrode layer 8 made of aluminum whose peripheral area is patterned and whose deposition area is narrower than that of the fourth amorphous silicon layer 7.

【0014】次に、上記構成の光電変換装置Sの製造方
法について説明する。まず、基板1の受光面1a側を成
膜する。すなわち、プラズマCVD法により基板1の受
光面1aのほぼ全面にi型の水素化非晶質シリコン層で
ある第1非晶質シリコン層2を厚さ400 Å以下、すなわ
ち20〜400 Å程度に成膜する。ここで、第1非晶質シリ
コン層2の厚さはより好適には50〜200 Åとする。この
厚さにすることにより光電流の取り出しに支障が無くな
る。そして、この第1非晶質シリコン層2の上面のほぼ
全面に同様な方法にて、非晶質シリコン形成用ガスに不
純物ドープ用ガスであるホスフィン等を所定の比率で
(不純物濃度が約0.2 〜2 at.%となるように)混合
して、厚さ30〜100 Å程度に成膜してn型の第2非晶質
シリコン層3を形成する。次いで、この第2非晶質シリ
コン層3の上面のほぼ全面にスパッタ法によりITOか
ら成る受光面電極層4を厚さ700 〜1000Å程度に成膜す
る。
Next, a method of manufacturing the photoelectric conversion device S having the above configuration will be described. First, a film is formed on the light receiving surface 1a side of the substrate 1. That is, the first amorphous silicon layer 2, which is an i-type hydrogenated amorphous silicon layer, is formed on substantially the entire light receiving surface 1a of the substrate 1 by plasma CVD to a thickness of 400 Å or less, that is, about 20 to 400 Å. Form a film. Here, the thickness of the first amorphous silicon layer 2 is more preferably 50 to 200 Å. With this thickness, there is no hindrance to the extraction of photocurrent. Then, phosphine, which is an impurity doping gas, is added to the amorphous silicon forming gas at a predetermined ratio (impurity concentration of about 0.2%) on substantially the entire upper surface of the first amorphous silicon layer 2. ˜2 at.%) And mixed to form a film having a thickness of about 30 to 100 Å to form the n-type second amorphous silicon layer 3. Then, a light-receiving surface electrode layer 4 made of ITO is formed on the almost entire upper surface of the second amorphous silicon layer 3 by a sputtering method so as to have a thickness of about 700 to 1000Å.

【0015】また、基板1の裏面1b側は、まず、基板
1の裏面1bのほぼ全面に、上記と同様にi型の水素化
非晶質シリコンを厚さ0 〜200 Å程度に成膜してi型の
第3非晶質シリコン層6を形成する。そして、この第3
非晶質シリコン層6の上面のほぼ全面に同様な方法に
て、非晶質シリコン形成用ガスに不純物ドープ用ガスで
あるジボランガス等を所定の比率で混合して、厚さ約0
〜200 Å程度にp型の第4非晶質シリコン層7を形成す
る。そして、この第4非晶質シリコン層7の上面のほぼ
全面に蒸着やスパッタ法等によりアルミニウムから成る
裏面電極層8を厚さ3000Å程度に形成する。
On the back surface 1b side of the substrate 1, first, i-type hydrogenated amorphous silicon is formed to a thickness of about 0 to 200 ° on almost the entire back surface 1b of the substrate 1 in the same manner as described above. Then, an i-type third amorphous silicon layer 6 is formed. And this third
The amorphous silicon forming gas is mixed with a gas for impurity doping such as diborane gas at a predetermined ratio in a similar manner on substantially the entire upper surface of the amorphous silicon layer 6 to have a thickness of about 0.
The p-type fourth amorphous silicon layer 7 is formed to about 200 Å. Then, the back surface electrode layer 8 made of aluminum is formed on almost the entire upper surface of the fourth amorphous silicon layer 7 by a vapor deposition method or a sputtering method to have a thickness of about 3000 Å.

【0016】次に、まず、受光面電極層4及び裏面電極
層8の所定領域をレジストで覆いマスクする。そして、
フッ酸,硝酸,及び水を混合させた混酸を用いて、第2
非晶質シリコン層3,受光面電極層4,第4非晶質シリ
コン層7,及び裏面電極層8の周縁部をエッチングす
る。ここで、第1非晶質シリコン層2及び第3非晶質シ
リコン層6はほとんどエッチングされない。ここで、エ
ッチングレイトを調節するために、混酸における硝酸の
量を多くしてエッチングレイトを下げたり、水の量を多
くしてエッチングレイトを下げたりする。また、稀フッ
酸(2 %) を用いても、第1非晶質シリコン層2と第2
非晶質シリコン3とのエッチングレイトの差を実現でき
目的の構造をすることができる。なお、第3非晶質シリ
コン6と第4非晶質シリコン7も同様である。
Next, first, predetermined regions of the light-receiving surface electrode layer 4 and the back surface electrode layer 8 are covered with a resist and masked. And
Using a mixed acid that is a mixture of hydrofluoric acid, nitric acid, and water,
The peripheral portions of the amorphous silicon layer 3, the light-receiving surface electrode layer 4, the fourth amorphous silicon layer 7, and the back surface electrode layer 8 are etched. Here, the first amorphous silicon layer 2 and the third amorphous silicon layer 6 are hardly etched. Here, in order to adjust the etching rate, the amount of nitric acid in the mixed acid is increased to lower the etching rate, or the amount of water is increased to lower the etching rate. Even if dilute hydrofluoric acid (2%) is used, the first amorphous silicon layer 2 and the second amorphous silicon layer 2
A difference in etching rate from the amorphous silicon 3 can be realized and a target structure can be formed. The same applies to the third amorphous silicon 6 and the fourth amorphous silicon 7.

【0017】さらに、受光面電極層4及び裏面電極層8
をエッチングする場合には、例えば塩酸もしくは臭化水
素でもってエッチングする。
Further, the light-receiving surface electrode layer 4 and the back surface electrode layer 8
Is etched with hydrochloric acid or hydrogen bromide, for example.

【0018】そして、スクリーン印刷,半田ディップ,
もしくは蒸着法等により取り出し電極5を形成して、図
1に示す光電変換装置Sを作製することができる。な
お、基板1上に多数個の素子領域を作製している場合に
は、上記のようにして素子を作製した後に、素子どうし
を分離するためにレーザー,ダイシング,もしくはダイ
ヤモンドスクライブ等によりカッティングを行う。
Then, screen printing, solder dip,
Alternatively, the extraction electrode 5 can be formed by a vapor deposition method or the like to manufacture the photoelectric conversion device S shown in FIG. When a large number of element regions are formed on the substrate 1, after the elements are formed as described above, cutting is performed by laser, dicing, diamond scribe or the like to separate the elements. .

【0019】なおここで、基板1は単結晶シリコンでも
よく、基板1の導電型はn型でもよい(この場合には、
基板1の受光面側に設けるn型の非晶質シリコン層の代
わりに、p型の非晶質シリコン層を設けるとよい。)。
また、第2非晶質シリコン層3や第4非晶質シリコン層
7は完全な非晶質でなくともよく、いわゆる微結晶層で
あってもよい。また、基板1の裏面側には裏面電極層だ
けを形成するようにしてもよい。また、受光面電極層4
は酸化亜鉛(ZnO)等でもよい。また、第1非晶質シ
リコン層2及び/又は第3非晶質シリコン層6の周縁部
をパターニング除去するようにしてもよい。
Here, the substrate 1 may be single-crystal silicon, and the conductivity type of the substrate 1 may be n-type (in this case,
Instead of the n-type amorphous silicon layer provided on the light receiving surface side of the substrate 1, a p-type amorphous silicon layer may be provided. ).
Further, the second amorphous silicon layer 3 and the fourth amorphous silicon layer 7 do not have to be completely amorphous, and may be so-called microcrystalline layers. Alternatively, only the back surface electrode layer may be formed on the back surface side of the substrate 1. In addition, the light-receiving surface electrode layer 4
May be zinc oxide (ZnO) or the like. Further, the peripheral portions of the first amorphous silicon layer 2 and / or the third amorphous silicon layer 6 may be patterned and removed.

【0020】なおまた、光電変換装置S全体の耐湿性等
の信頼性向上のために、裏面電極層8上には保護膜が形
成されるとより好適である。例えば、樹脂を周知の印刷
手法を用いて保護膜として形成し、さらに、例えば導電
性樹脂を周知の印刷手法を用いて取り出し電極部分が形
成される。また、この上に後工程の実装時の半田づけ性
を良好とするため、半田材料を形成しておくとよい。こ
れは、導電性樹脂表面が長時間放置によって酸化され、
後の実装時の半田づけ性に悪影響を及ぼす可能性を未然
に防ぐためである。
It is more preferable that a protective film is formed on the back electrode layer 8 in order to improve the reliability such as the moisture resistance of the photoelectric conversion device S as a whole. For example, a resin is formed as a protective film using a known printing method, and further, for example, a conductive resin is extracted using a known printing method, and an electrode portion is formed. In addition, a solder material may be formed thereon in order to improve the solderability at the time of mounting in a later step. This is because the conductive resin surface is oxidized by leaving it for a long time,
This is to prevent the possibility of adversely affecting the solderability during later mounting.

【0021】次に、上記光電変換装置Sの特性について
説明する。受光面積が約0.5 cm2 の場合の光電変換装置
Sの電圧−電流特性は、図2に実線で示す通りであっ
て、開放電圧は約0.4 Vであり、電圧−電流特性が非常
に良好であった。さらに、順バイアス0.3 Vにおける暗
電流も2 ×10-6A/cm2 以下であった。このように、光
電変換装置Sでは特に半導体接合部における表面経由を
長くすることにより暗電流の発生を極力抑えることがで
き、低照度における電圧−電流特性を従来より大幅に向
上させることができた。
Next, the characteristics of the photoelectric conversion device S will be described. The voltage-current characteristics of the photoelectric conversion device S when the light-receiving area is about 0.5 cm 2 are as shown by the solid line in FIG. 2, and the open-circuit voltage is about 0.4 V, indicating that the voltage-current characteristics are very good. there were. Further, the dark current at a forward bias of 0.3 V was also 2 × 10 −6 A / cm 2 or less. As described above, in the photoelectric conversion device S, the generation of dark current can be suppressed as much as possible by lengthening the length of the surface of the semiconductor junction, and the voltage-current characteristics at low illuminance can be significantly improved as compared with the related art. .

【0022】次に、受光面積が約0.42cm2 , 蛍光灯の照
度が250 ルクス, 室温の測定条件で、第2非晶質シリコ
ン層3の厚さと短絡電流値との関係を示した図を図3に
示す。この図から明らかなように、第2非晶質シリコン
層3の厚さが薄ければ薄いほど短絡電流値が増加するこ
とがわかる。
Next, a diagram showing the relationship between the thickness of the second amorphous silicon layer 3 and the short circuit current value under the measurement conditions of a light receiving area of about 0.42 cm 2 , an illuminance of a fluorescent lamp of 250 lux and room temperature. As shown in FIG. As is apparent from this figure, the thinner the second amorphous silicon layer 3 is, the larger the short-circuit current value is.

【0023】また、第2非晶質シリコン層3の厚さと短
絡電流値との関係を示した図を図4に示す。この結果
は、上記と同様な測定条件により測定した。この図から
明らかなように、順バイアス0.3 Vにおける明電流との
第2シリコン層3の厚さとの関係から、好適な第2シリ
コン層3の厚さは40〜90Åであり、約60〜70Å付近にピ
ークがあるものと思われる。これは、光吸収の抑制の度
合いとダイオード特性との兼ね合いにより最適厚さが存
在するものと思われる。第2非晶質シリコン3の厚さが
薄すぎて特性が低下するのはダイオード特性が低下する
ためであるが、より詳しくは接合部の拡散電位が不十分
になるためと思われる。
FIG. 4 is a diagram showing the relationship between the thickness of the second amorphous silicon layer 3 and the short circuit current value. This result was measured under the same measurement conditions as above. As is clear from this figure, from the relationship between the bright current at a forward bias of 0.3 V and the thickness of the second silicon layer 3, the preferable thickness of the second silicon layer 3 is 40 to 90Å, and about 60 to 70Å. It seems that there is a peak in the vicinity. It is considered that the optimum thickness exists due to the balance between the degree of suppression of light absorption and the diode characteristics. The reason that the characteristics of the second amorphous silicon 3 are too thin and the characteristics are deteriorated is that the diode characteristics are deteriorated. More specifically, it is considered that the diffusion potential of the junction is insufficient.

【0024】なお、図5に示すように、p型もしくはn
型の多結晶シリコンの基板31の裏面に裏面電極層34
を設け、p型もしくはn型の多結晶シリコンの基板31
の受光面側に、周縁部をパターニングして、被着面積が
基板31の受光面より狭い、2層以上(i型や他の導電
型の層が複数積層された層構成をなす)の非晶質シリコ
ン層32を積層し、この非晶質シリコン層32上に、周
縁部をパターニングして、被着面積が非晶質シリコン層
32より狭い受光面電極層33を積層した構造の光電変
換装置S3としてもよい。このような光電変換装置S3
においても第1非晶質シリコン層2と第2非晶質シリコ
ン3とに、上述の実施例と同様な厚さの最適範囲がある
ことが判明した。なお、図5において基板31の取り出
し電極等は省略している。また、図中C3はレーザーや
ダイシング等によりカッティングして素子分離を行う箇
所を示す。
As shown in FIG. 5, p-type or n-type
Of the rear surface electrode layer 34 on the rear surface of the substrate 31 of the polycrystalline silicon of the mold
And a p-type or n-type polycrystalline silicon substrate 31
The light receiving surface of the substrate 31 is patterned to have a peripheral edge portion, and the deposition area is narrower than the light receiving surface of the substrate 31. Photoelectric conversion having a structure in which a crystalline silicon layer 32 is stacked, and a peripheral portion is patterned on the amorphous silicon layer 32 to stack a light-receiving surface electrode layer 33 having a deposition area narrower than that of the amorphous silicon layer 32. It may be the device S3. Such a photoelectric conversion device S3
Also in the above, it was found that the first amorphous silicon layer 2 and the second amorphous silicon 3 have the same optimum range of thickness as in the above embodiment. Note that, in FIG. 5, the extraction electrode and the like of the substrate 31 are omitted. In addition, C3 in the figure indicates a portion where element isolation is performed by cutting with laser or dicing.

【0025】このとき使用するエッチャントは、非晶質
シリコン層32と受光面電極層33とが共にエッチング
されるエッチャント(例えば、混酸)を用い、共にエッ
チングされるようにし、さらに、受光面電極層33のみ
エッチングされるように塩酸などのエッチャントを用い
て受光面電極層33のサイドエッチングするようにする
とよい。
The etchant used at this time is an etchant (for example, mixed acid) in which the amorphous silicon layer 32 and the light-receiving surface electrode layer 33 are both etched, and is etched together. Side etching of the light-receiving surface electrode layer 33 may be performed using an etchant such as hydrochloric acid so that only 33 is etched.

【0026】[0026]

【発明の効果】以上説明したように、本発明の光電変換
装置は、p型もしくはn型の結晶シリコンから成る基板
の一主面側に裏面電極層を設けるとともに、基板の他主
面上にi型の第1非晶質シリコン層、p型もしくはn型
の第2非晶質シリコン層、及び受光面電極層を順次積層
させて成る。そして、第 1非晶質シリコン層の厚さを40
0 Å以下とし、第2非晶質シリコン層の厚さを100 Å以
下とし、特に、第2非晶質シリコン層における光吸収を
抑える最適の厚さとしたので、特に特に低照度において
電圧−電流特性が良好となり、高効率の優れた太陽電池
や特性の優れた光センサなどの光電変換装置を提供する
ことができる。
As described above, in the photoelectric conversion device of the present invention, the back electrode layer is provided on one main surface side of the substrate made of p-type or n-type crystalline silicon, and the other main surface of the substrate is provided. The i-type first amorphous silicon layer, the p-type or n-type second amorphous silicon layer, and the light-receiving surface electrode layer are sequentially stacked. Then, increase the thickness of the first amorphous silicon layer to 40
The thickness of the second amorphous silicon layer is set to 0 Å or less, and the thickness of the second amorphous silicon layer is set to 100 Å or less. It is possible to provide a photoelectric conversion device such as a solar cell having excellent characteristics and high efficiency and an optical sensor having excellent characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る一実施例の光電変換装置の要部断
面図。
FIG. 1 is a sectional view of a main part of a photoelectric conversion device according to an embodiment of the present invention.

【図2】光電変換装置の電圧−電流特性を示す特性図。FIG. 2 is a characteristic diagram showing voltage-current characteristics of a photoelectric conversion device.

【図3】第2非晶質シリコン層の厚さと短絡電流値との
関係を示す図。
FIG. 3 is a diagram showing a relationship between a thickness of a second amorphous silicon layer and a short circuit current value.

【図4】第2非晶質シリコン層の厚さと短絡電流値との
関係を示す図。
FIG. 4 is a diagram showing a relationship between a thickness of a second amorphous silicon layer and a short circuit current value.

【図5】本発明に係る他実施例の光電変換装置の要部断
面図。
FIG. 5 is a cross-sectional view of a main part of a photoelectric conversion device according to another embodiment of the present invention.

【図6】従来の光電変換装置の一例を示す要部断面図。FIG. 6 is a cross-sectional view of a main part showing an example of a conventional photoelectric conversion device.

【符号の説明】[Explanation of symbols]

1 ・・・ 基板 2 ・・・ 第1非晶質シリコン層 3 ・・・ 第2非晶質シリコン層 4 ・・・ 受光面電極層 8 ・・・ 裏面電極層 S ・・・ 光電変換装置 1 ... Substrate 2 ... 1st amorphous silicon layer 3 ... 2nd amorphous silicon layer 4 ... Light-receiving surface electrode layer 8 ... Back surface electrode layer S ... Photoelectric conversion device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 p型もしくはn型の結晶シリコンから成
る基板の一主面側に裏面電極層を設けるとともに、前記
基板の他主面上に、厚さが400 Å以下のi型の第1非晶
質シリコン層、p型もしくはn型で且つ厚さが100 Å以
下の第2非晶質シリコン層、及び受光面電極層を順次積
層させて成る光電変換装置。
1. A back electrode layer is provided on one main surface side of a substrate made of p-type or n-type crystalline silicon, and an i-type first substrate having a thickness of 400 Å or less is provided on the other main surface of the substrate. A photoelectric conversion device comprising an amorphous silicon layer, a p-type or n-type second amorphous silicon layer having a thickness of 100 Å or less, and a light-receiving surface electrode layer, which are sequentially stacked.
JP7339774A 1995-12-26 1995-12-26 Photoelectric conversion device Pending JPH09181343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7339774A JPH09181343A (en) 1995-12-26 1995-12-26 Photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7339774A JPH09181343A (en) 1995-12-26 1995-12-26 Photoelectric conversion device

Publications (1)

Publication Number Publication Date
JPH09181343A true JPH09181343A (en) 1997-07-11

Family

ID=18330687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7339774A Pending JPH09181343A (en) 1995-12-26 1995-12-26 Photoelectric conversion device

Country Status (1)

Country Link
JP (1) JPH09181343A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781669B2 (en) 2005-02-25 2010-08-24 Sanyo Electric Co., Ltd. Photovoltaic cell
JP2013042126A (en) * 2011-07-21 2013-02-28 Semiconductor Energy Lab Co Ltd Photoelectric conversion device
WO2013069324A1 (en) * 2011-11-10 2013-05-16 三菱電機株式会社 Solar cell, method for manufacturing same, and solar cell module
JP2015095648A (en) * 2013-11-08 2015-05-18 財團法人工業技術研究院Industrial Technology Research Institute Hetero-junction type solar battery structure
WO2020059204A1 (en) * 2018-09-21 2020-03-26 株式会社カネカ Solar battery cell, solar battery device, and solar battery module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781669B2 (en) 2005-02-25 2010-08-24 Sanyo Electric Co., Ltd. Photovoltaic cell
USRE45872E1 (en) 2005-02-25 2016-01-26 Panasonic Intellectual Property Management Co., Ltd. Photovoltaic cell
JP2013042126A (en) * 2011-07-21 2013-02-28 Semiconductor Energy Lab Co Ltd Photoelectric conversion device
WO2013069324A1 (en) * 2011-11-10 2013-05-16 三菱電機株式会社 Solar cell, method for manufacturing same, and solar cell module
JPWO2013069324A1 (en) * 2011-11-10 2015-04-02 三菱電機株式会社 SOLAR CELL, ITS MANUFACTURING METHOD, SOLAR CELL MODULE
JP2015095648A (en) * 2013-11-08 2015-05-18 財團法人工業技術研究院Industrial Technology Research Institute Hetero-junction type solar battery structure
WO2020059204A1 (en) * 2018-09-21 2020-03-26 株式会社カネカ Solar battery cell, solar battery device, and solar battery module

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