JPH09179745A - Composite computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a more inexpensive and faster composite computer system. SOLUTION: A server 1 has a microprocessor 11 to be driven by its own server OS, a memory 12 to which the server OS is loaded, an internal bus control circuit 14 for connecting an internal bus 3 and controlling data transfer and interruption, and an interruption controller 15 for controlling an interruption in the sever 1. A client 2 has a microprocessor 21 to be driven by its own client OS, a memory 22 to which the client OS is loaded, an interruption register 23a, an interruption generating circuit 26 for generating an interruption at the time of recognizing writing in the register 23a, an internal bus control circuit 24 for connecting the bus 3 and controlling data transfer, and an interruption controller 25 for controlling an interruption in the client 2. An interruption is generated in the client 2 by allowing the server 1 to execute writing operation in the register 23a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite computer system, and more particularly to a system form of a client / server system, which is one form of the composite computer system, which is inexpensive and high speed.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a typical configuration example of a conventional client / server system. As shown in FIG. 9, it is a general system form that one server and a plurality of clients are connected to a LAN, and a plurality of clients access a shared database on a disk connected to the server. Since the server is required to respond at high speed to access requests from a plurality of clients, a high performance computer is used. In other words, the client is realized by an inexpensive and general-purpose personal computer, while the server is realized by a dedicated server computer or office computer.

[0003]

When it is constructed by a plurality of computers and communication is performed among the computers as represented by the client / server system, it would be desirable to construct the system at a lower cost. It is desired to speed up access between computers.

The present invention has been made to solve the above problems, and an object thereof is to provide a cheaper and faster complex computer system.

[0005]

In order to achieve the above-mentioned objects, a composite computer system according to the present invention comprises a host processor, a first storage means on which a host operating system is loaded, an internal bus. And a host computer having a first internal bus control unit for controlling data transfer and interrupt control, a guest processor, a second storage unit in which a guest operating system is loaded, and an internal bus. One or a plurality of guest computers having a second internal bus control means for performing data transfer control and interrupt control, and connecting the guest computer and each host computer by an internal bus. .

Further, the guest computer is characterized by performing a predetermined process in response to a write operation from the host computer.

Further, the guest computer has an interrupt register and an interrupt generating means for generating an interrupt when recognizing a write to the interrupt register, and an interrupt is generated by the host computer writing to the interrupt register. Is generated.

Further, the guest computer has a factor register indicating a factor of interrupt generation, and the factor of interrupt generation is obtained by writing to the factor register by the host computer.

Further, the guest computer is characterized in that an interrupt is generated by recognizing writing to the factor register.

Further, the guest computer has a data information storage means for causing the host computer to write transfer data information, and the guest computer receives data from an input / output device internally connected based on the written transfer data information. It is characterized by performing output.

Further, the host computer is characterized in that an interrupt is generated in the guest computer, and input / output is performed with respect to an input / output device connected to the guest computer which generated the interrupt.

Further, the guest computer is characterized by having an interrupt-disabled state holding means for holding that the guest computer is in the interrupt-disabled state.

Further, the guest computer is characterized by having interrupt-disabled state holding means for holding the interrupt-disabled state and abnormal state holding means for holding the internal abnormal state.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a diagram showing a basic configuration of a complex computer system according to the present invention. In this embodiment, a client / server system, which is one form of the composite computer system, will be described. This system is composed of one server 1 as a host computer, a plurality of clients 2 as guest computers, and an internal bus 3 connecting the server 1 and each client 2. In a typical client / server system, a server and a client are connected by a LAN, and each client / server system is constructed as a separate computer mounted in a separate casing. The present embodiment is characterized in that the server 1 and the client 2 are connected to each other via the internal bus 3 and are mounted in, for example, one casing. This internal bus 3 is also generally called a system bus. In the present embodiment, by using the PCI bus as the internal bus 3, it is possible to mutually access the memory and the register group between the server and the client.

The server 1 includes a microprocessor 11 as a host processor that operates in a server operating system, a memory 12 as a first storage unit in which the server operating system is loaded,
An internal bus control circuit 14 as a first internal bus control means for connecting the first register group 13 which is a temporary storage means and the internal bus 3 to perform data transfer control and interrupt control, an IO device in the server 1 and the like. An interrupt controller 15 that arbitrates the interrupt from 1 to extract one interrupt and notifies the microprocessor 11 of the interrupt. A data line, an address line, and a control line are connected to each component as needed. Since the server 1 needs to have high performance as described above, it is realized by an office computer or the like. Therefore, the server 1 is equipped with the microprocessor 11 unique to the office computer which is realized by the office computer board and operates in the operating system for the office computer adopted as the host operating system.

On the other hand, the client 2 includes a microprocessor 21 as a guest processor which operates in a client operating system, a memory 22 as a second storage means in which the client operating system is loaded, and a second register group. 23 and an internal bus control circuit 24 as a second internal bus control means for connecting the internal bus 3 and performing data transfer control and interrupt control.
And an interrupt controller 25 that arbitrates an interrupt from the IO device or the like in the own client 2 to extract one interrupt and notify the microprocessor. A data line, an address line, and a control line are connected to each component as needed. Each client 2 can be realized with the same configuration. The client 2 is realized by an inexpensive personal computer or the like as described above. Therefore, client 2
A microprocessor 21 which is realized by a personal computer board and operates in a personal computer operating system adopted as a guest operating system is mounted.

The host computer means one or a plurality of computers that can serve as hosts in a system constructed by a plurality of computers. A guest computer is a computer that is not a host computer, and unless otherwise specified, a general independent computer is constructed.

As shown in FIG. 1, since the server 1 and the client 2 are represented in the same structure, the multi C
Seems almost like a PU computer. Of course, in connection with the internal bus, interrupt control, etc., the control method between CPUs in a multi-CPU computer, data transfer method, internal bus usage method, address line, data line usage method, etc. Has the same place. However, the system according to the present embodiment differs from a general multi-CPU computer in that the server 1 and the client 2 operate with different operating systems.

As described above, the characteristic feature of this embodiment is that the server 1 and the client 2 are connected to each other using the internal bus 3. As a result, an integrated client / server system can be constructed, so that an inexpensive and high-speed system can be provided as compared with a client / server system constructed using a general LAN or the like. Detailed operations such as interrupt control based on this system will be described in the following embodiments.

In the above example, the server 1 is used as the host computer and the client 2 is used as the guest computer. However, the server 1 is used as the guest computer and the client 2 is used.
May be the host computer. The same applies to the following embodiments.

Embodiment 2. FIG. 2 is a configuration diagram showing a second embodiment of the composite computer system according to the present invention. Note that the same elements as those in FIG. The same applies below. Unless otherwise specified, the client a is described as a representative.

In the present embodiment, as shown in FIG. 2, the interrupt register 23a in the register group 23 and the interrupt generation as an interrupt generation means for generating an interrupt when the writing to the interrupt register 23a is recognized. The circuit 26 is newly provided. A feature of the present embodiment is that the server 1 is caused to perform an interrupt operation by causing the client 2 to perform a write operation to the interrupt register 23a.

In a general client / server system, for example, when a server requests some access from a client, there is usually no concept of interruption, and the server sends a packet to issue a communication request. Then, the client receives the packet from the server and refers to the contents of the packet to know the request of the server. In the present embodiment, the internal bus 3 is used for connection so that the configuration is somewhat similar to that of a multi-CPU computer. However, with this configuration, an interrupt can be generated, so the server 1
Can inform the client 2 of an intention such as an access request.

In a general multi-CPU computer, an interrupt dedicated line wired to an internal bus is used to generate an interrupt to another CPU. But,
When the number of CPUs is increased, the number of peculiar interrupt signal lines running between the internal buses is increased, which is complicated, and it is not only not possible to flexibly cope but also expensive. Therefore, in the present embodiment, since the server 1 can cause an interrupt to the client 2 with the above configuration, it is not necessary to wire an interrupt dedicated line to the internal bus 3. Therefore, according to the present embodiment, in the client / server system, by using the internal bus, it is possible to access the client at a higher speed, and at the same time, it is possible to provide a system that is inexpensive and has excellent expandability. can do.

Next, an interrupt procedure from the server 1 to the client 2 in this embodiment will be described.

First, each device installed in the server 1 and the client 2 has a unique address set therein, but the client 2 also has a unique address set in the interrupt register 23a. Here, the server 1 sends the address information of the interrupt register 23a of the client 2 to the internal bus 3. The address information is the address of the device to be written to, the address of a register, etc., the information about the data such as the address of the data storage destination in the case of data transfer or the data itself, and the interrupt if a response is required depending on the type of interrupt Addresses and the like are included as appropriate.
The address information in this case includes the address of the interrupt register 23a.

Next, when the internal bus control circuit 24 of the client 2 receives the address information from the server 1 and recognizes that it is addressed to itself, it occupies the bus in the client 2 and stores the data in the interrupt register 23a. Write. In the case of this example, since it is sufficient to inform only that an interrupt has occurred, the operation is to set only a specific bit in the interrupt register 23a. And
The internal bus control circuit 24 releases the bus in the client 2.

When there is a write in the interrupt register 23a, the interrupt generation circuit 26 recognizes the High / Low level of the signal line assigned to the interrupt register 23a by hardware and generates an interrupt. When the interrupt controller 25 detects an interrupt from the interrupt generating circuit 26, the interrupt controller 25 arbitrates with an interrupt from another device. As a result, the interrupt generation circuit 2
When the interrupt from 6 is selected, the microprocessor 2
1 will generate an interrupt in response to a request from the server 1.

As described above, since the server 1 can generate an interrupt only by writing to the interrupt register 23a of the client 2, it is possible to flexibly cope with an increase in the number of clients 2. it can. Then, after the interruption, each processing shown in the embodiments described below can be performed.

In the above example, the client 2 is equipped with the interrupt register 23a and the interrupt controller 25, and the client 2 generates an interrupt in response to an interrupt request from the server 2, but the reverse and vice versa. You may make it have the structure of. When there are a plurality of clients 2, the address information can be applied by including information for specifying the interrupt generation destination.

Embodiment 3. In the above embodiment, the server 1 simply causes the client 2 to generate an interrupt, but there are various types of interrupts, that is, reasons (factors). For example, an abnormality in the state of the server 1 and a request for IO or the like are factors. The present embodiment is characterized in that the factor is also notified.

FIG. 3 is a block diagram showing a third embodiment of the composite computer system according to the present invention. What is characteristic of the present embodiment is the factor register 23b representing the factor of interrupt generation. Is provided in the register group 23. By causing the server 1 to write a factor into the factor register 23b, the client 2 can obtain the factor of the interrupt occurrence.

Next, the operation of this embodiment will be described. Although FIG. 3 shows an example of the factor register 23b, 1 bit is assigned to each factor as shown in FIG.

The server 1 has already described sending address information when causing an interrupt to the client 2, but the setting information (hereinafter referred to as "factor information") to the factor register 23b is added to this address information. Will be done. The internal bus control circuit 24 uses the interrupt register 23a.
However, before that, the factor register 23b is operated based on the factor information. For example, server 1
Is an interrupt when it is desired to use the input / output device connected to the client 2, the fact is added to the address information as factor information. Therefore, the internal bus control circuit 24
Operates a predetermined bit of the factor register 23b.

In this way, the client 2 causes the server 1 to determine the cause of the interrupt of the server 1 by the cause register 23.
By writing to b, it is possible to easily know the cause of the interrupt of the server 1.

For example, when the server 1 wants to access the disk connected to the client 2, the server 1 writes IO in the factor register 23b of the client 2. Since the client 2 can determine that the server 1 has interrupted for the disk access, it can execute a routine such as releasing the disk or setting up the disk in advance.

In this way, by notifying the cause of interruption, it is possible to efficiently use the entire system in which the client / server system is integrated.

As in the above case, the server 1 and the client 2 may have an inverse relationship or both may have the same configuration. If there are multiple clients 2,
The address information can be applied by including information for specifying the interrupt generation destination.

Embodiment 4 FIG . FIG. 4 is a diagram showing the main parts of the register group 23 and the interrupt controller 25 of the client 2 according to the present embodiment. What is characteristic of the present embodiment is that all outputs of the factor register 23b are
By connecting to the R circuit 27, the generation of an interrupt is recognized. As a result, it is possible to detect the occurrence of an interrupt by recognizing the writing to the factor register 23b without having the interrupt register or the interrupt generation circuit in the above embodiment.

Embodiment 5. FIG. 5 is a configuration diagram showing a fifth embodiment of the composite computer system according to the present invention. The client 2 in the present embodiment is equipped with an IO control unit 28, and a disk 4 as an input / output device is connected to the end of the IO control unit 28 via an IO bus.

By the way, when the server 1 transfers data to the client 2, for example, the server 1 transfers the data to the client 2.
The client 2 can specify the transfer data by notifying the start address of the data to be transferred on the memory 12 and the number of transfer bytes. In the present embodiment,
As a data information storage unit for writing transfer data information including a start address of data to be transferred on the memory 12 and the number of transfer bytes, the register group 23 is provided with a data pointer register 23c and a data count register 23d. There is. The operation of this embodiment in this configuration will be described below.

In the third embodiment, when the cause of the interrupt from the server 1 is IO, that is, when the cause of the interrupt is data transfer, the factor register 23b is subjected to the IO in the above-described procedure. Before writing, the server 1 writes the start address and the number of transfer bytes of the data to be transferred to the data pointer register 23c and the data count register 23d, respectively. That is,
The server 1 will issue an interrupt request after the data transfer is ready.

When the client 2 recognizes the interrupt from the server 1, the client 2 refers to the factor register 23b to obtain the I
Recognize O request. Then, referring to the data pointer register 23c and the data count register 23d, the data in the memory 12 is independently fetched and directly output to the disk 4 connected inside.

In this way, the server 1 writes the transfer data information of the data to be transferred to the client 2 and outputs it to the disk 4 connected to the client 2 without using its own microprocessor 11. it can. The process in which the client 2 receives data from the server 1 is performed by the internal bus control circuit 14 in the server 1 operating independently of the microprocessor 11.

According to the present embodiment, since the internal bus 3 is used, the above processing can be performed at high speed, but the data to be output is directly output to the disk 4 without temporarily storing it in the memory 22. Therefore, it can be processed at a higher speed.

By the way, in the above description, the server 1 outputs to the disk of the client 2 as an example.
Of course, it is possible to input, but since such access is possible, there are the following advantages. That is, the client 2 is usually realized by a personal computer or the like, and the input / output device such as a disk connected thereto is also relatively cheaper than the server 1 realized by the office computer. The personal computer has high performance in accordance with recent technological innovation, and the input / output device thereof is also being increased in capacity, performance, and price. Therefore, it is cheaper to store the data in the client / server system on the personal computer side than to store the data on the office computer side. However, according to the present embodiment, the internal bus 3
It is possible to construct a system at a lower cost by using the disk of the personal computer in the office computer while achieving high speed by using.

In this embodiment described above, the register group 23 is used as the data information storage means and the data pointer register 23c and the data count register 23d are provided, but they may be provided in the memory 2. Also,
The transfer data information handled is not limited to the start address and the number of transfer bytes, and may be information that can specify the data to be transferred, for example, the start address and the end address. This is not the subject of the present invention. Further, in the above description, an example of output to the disk 4 has been described, but the same applies to other peripheral devices.

Further, as in the above-mentioned embodiment, the data pointer register 23c and the data count register 23d.
May be provided in the server 1.

Embodiment 6 FIG . In the fifth embodiment, the client takes the initiative to take out the data in the memory of the server and directly output the data to the disk. Therefore, the server has previously written the transfer data information to the client. The present embodiment is characterized in that the server takes the initiative in outputting to the disk connected to the client. This is done as follows.

That is, in FIG. 5, since the server 1 knows the address of the disk 4 of the client 2, this information is added to the above-mentioned address information to interrupt the client 2. Of course, factor information is also added. Based on this address information, the internal bus control circuit 24 performs a write operation on the interrupt register 23a and factor register 23b to generate an interrupt. Then server 1
Directly outputs to the disk 4 via the internal bus control circuit 24. At this time, the microprocessor 21 of the client 2 is not used.

In this way, the server 1 can take the initiative in outputting to the disk 4 connected to the client 2. This can be realized without using the data information storage means shown in FIG. Of course, the input process can be performed, and the server 1 and the client 2 can be reversed to realize the same.

Embodiment 7. FIG. 6 is a block diagram showing a sixth embodiment of the composite computer system according to the present invention. The present embodiment is characterized in that the client 2 is provided with a status register 23e in the register group 23 as an interrupt disabled state holding means for holding that the current client is in the interrupt disabled state.

Next, the operation of this embodiment will be described.

For example, when the client 2 receives an access request from another client, it sets the status register 23e by itself. As a result, the client 2 holds that the interrupt disabled state has been entered. It should be noted that in the present embodiment, since only interrupts are enabled or disabled, it can be represented by only one bit in the status register 23e.

When the server 1 interrupts the client 2 to issue a data transfer request or the like as described above, the setting contents of the status register 23e are referred to in advance. If the status register 23e is set and the client 2 is busy transferring data with others, the server 1 once cancels the data transfer request to the client 2 and performs other processing. Run. Then, after a while, an interrupt for making a data transfer request or the like is sent again.

As described above, according to the present embodiment, since the status register 23e is provided, the server 1 can know the status of the client 2 in advance, and it is possible to perform efficient communication without wasteful access. It can be performed.

In the above description, only the client 2 has the status register 23e.
The server 1 and all other clients may have it. In addition, the status register 2 is provided as an interrupt-disabled state holding means.
Although 3e is provided, it may be provided in the memory 22.

Embodiment 8. FIG. 7 is a block diagram showing the eighth embodiment of the composite computer system according to the present invention. In FIG. 7, the client 2 is provided with the same interrupt register 23a and factor register 23b as in FIG. 3 in the register group 23, and the server 1 has the interrupt disabled state described in the seventh embodiment. A status register 13e as a holding means is provided in the register group 13.

By the way, in the third embodiment,
It has been described that the factor register 23b is provided to notify the client 2 of the factor of the interrupt in the server 1. In addition, in the above-described seventh embodiment, the status register 23e is provided to hold that the interrupt is disabled. The present embodiment is characterized in that the server 1 is provided with the status register 13e as described above, and is used not only as the interrupt-disabled state holding means but also as an abnormal state holding means for holding an internal abnormal state. Further, it is characterized in that the factor register 23b is provided with a factor of "abnormal" for notifying the client 2 of any abnormality in the server 1.
Here, the abnormal state of the server 1 means that some abnormality is internally detected, for example, when an abnormality of a connected peripheral device is detected, or when a temperature sensor installed therein detects that the server 1 has an abnormally high temperature. However, it means a state in which normal processing using the internal bus 3 can be performed. Not only the presence / absence of an abnormality but also the type of abnormality is written in the status register 13e. Status register 1
It has been described above that 3e needs only one bit as the interrupt disabled state holding means, but the rest can be used as the abnormal state holding means. Of course, if the number of bits is insufficient, an abnormal state holding means may be provided separately.

The operation of this embodiment will be described below.

When the server 1 detects any of the above-mentioned abnormalities, it first writes that fact in the status register 13e. Then, the factor information "abnormal" is added to the address information to the client 2 and is sent to be written in the factor register 23b.

When an interrupt occurs due to an interrupt request from the server 1, the client 2 first causes the cause register 23.
By referring to the contents of b, it is known that the factor of "abnormal" is set. Then, the client 2 can know the type of abnormal state of the server 1 by referring to the status register 13e of the server 1. This allows, for example,
When detecting an abnormality that the disk connected to the server 1 cannot be used, the client 2 does not have to send an access request to the server 1 to the server 1. In this way, useless access can be prevented in advance.

In the above description, the case of the abnormality by the server 1 has been described, but the same can be applied to the client 2.

Ninth Embodiment In each of the above-described embodiments, the server and each client are connected using the internal bus in order to reduce the cost and increase the speed of the system. As a result, the client was able to perform the predetermined processing as described above in each embodiment at high speed in response to the write operation from the server. Then, the server can provide an inexpensive system by using the client device. Furthermore, by adopting a configuration that does not use an interrupt dedicated line like a multi-CPU computer, it is possible to provide a system excellent in expandability.

FIG. 8 is a block diagram showing the ninth embodiment of the composite computer system according to the present invention. In the present embodiment, the system is composed of only the server 1 and one client 2. Has been done. As in the present embodiment,
In the case of configuring with a small number of clients 2, it may be cheaper to use the interrupt dedicated line 5 as in the conventional case by degrading the device function of the server 1 constructed by the office computer. For example, the internal bus control circuit 16 of the server 1 in this embodiment is a slave type circuit. Therefore, the server 1 cannot access each client 2 via the internal bus 3. However, by wiring the interrupt dedicated line 5 between the internal bus control circuit 16 and the internal bus control circuit 24 of the client 2. , So that an interrupt can be generated from the server 1 to the client 2.

That is, although the use of the interrupt dedicated line 5 is very limited in expandability and costs much, the cheaper the internal bus control circuit 16 of the server 1 is to keep the whole system cheaper. May be possible. The processing speed is the same as that of each of the above-mentioned embodiments, and is sufficiently high compared with the conventional client / server system.

Conventionally, processing such as data transmission / reception could be performed only after issuing an access request via the LAN, but according to each of the above embodiments, the server and the client are connected by the internal bus 3. By adopting the integrated client / server system, it is possible to provide a faster and cheaper system.

It is also possible to connect this system to a LAN to provide a more expanded system without installing all the clients in the composite computer system shown in each of the above embodiments.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a complex computer system according to the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of a complex computer system according to the present invention.

FIG. 3 is a configuration diagram showing a third exemplary embodiment of a composite computer system according to the present invention.

FIG. 4 is a configuration diagram showing essential parts of a register group and an interrupt controller of a client in a fourth embodiment of the multi-function computer system according to the present invention.

FIG. 5 is a configuration diagram showing a fifth exemplary embodiment of a composite computer system according to the present invention.

FIG. 6 is a configuration diagram showing a seventh exemplary embodiment of a composite computer system according to the present invention.

FIG. 7 is a configuration diagram showing an eighth exemplary embodiment of a composite computer system according to the present invention.

FIG. 8 is a configuration diagram showing a ninth exemplary embodiment of a composite computer system according to the present invention.

FIG. 9 is a diagram showing a typical configuration example of a conventional client / server system.

[Explanation of symbols]

1 server, 2 client, 3 internal bus, 4 disk, 5 interrupt dedicated line, 11,21 microprocessor, 12,22 memory, 13,23 register group,
13e, 23e Status register, 14, 16, 2
4 internal bus control circuit, 15, 25 interrupt controller, 23a interrupt register, 23b cause register, 2
3c data pointer register, 23d data count register, 23e status register, 26 interrupt generation circuit, 27 OR circuit, 28IO control unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Iwa ▲ Zaki ▼ Yasuo Marunouchi 2-3-3, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Inventor Koichi Hirose 2--2 Marunouchi, Chiyoda-ku, Tokyo 3 In Sanryo Electric Co., Ltd. (72) Inventor Kenichi Nakano 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd.

Claims (9)

[Claims] 1. A host processor and a first host operating system is loaded.
And a first internal bus control means for connecting an internal bus to perform data transfer control and interrupt control, a host computer having a guest processor, and a guest operating system loaded with a second operating system.
Storage means and second internal bus control means for connecting an internal bus to perform data transfer control and interrupt control, and one or a plurality of guest computers, the guest computer and the host computers. A computer system characterized by connecting to each other via an internal bus. 2. The composite computer system according to claim 1, wherein the guest computer performs a predetermined process according to a write operation from the host computer. 3. The host computer according to claim 2, wherein the guest computer includes: an interrupt register; and an interrupt generation unit that generates an interrupt when recognizing writing to the interrupt register. A compound computer system characterized in that an interrupt is generated by writing to the interrupt register by a computer. 4. The complex computer system according to claim 2, wherein the guest computer has a factor register indicating a factor of interrupt generation, and the factor of interrupt generation is obtained by writing to the factor register by the host computer. A computer system characterized by. 5. The complex computer system according to claim 4, wherein the guest computer generates an interrupt by recognizing a write to the factor register. 6. The complex computer system according to claim 2, wherein the guest computer has a data information storage unit that causes the host computer to write transfer data information, and the guest computer internally stores the transfer data information based on the written transfer data information. A complex computer system that performs input / output to / from a connected input / output device. 7. The complex computer system according to claim 3, wherein the host computer causes an interrupt to the guest computer, and an input / output device connected to the guest computer that has generated the interrupt. A complex computer system characterized by inputting and outputting data. 8. The multi-computer system according to claim 1, wherein the guest computer has an interrupt-disabled state holding unit that holds that the guest computer is in the interrupt-disabled state. 9. The complex computer system according to claim 3, wherein the guest computer holds an interrupt-disabled state holding unit for holding that the guest computer is in an interrupt-disabled state, and an abnormality for holding the internal abnormal state. A composite computer system comprising: a state holding unit;