JPH09178800A - Method for evaluating insulation layer - Google Patents

Method for evaluating insulation layer

Info

Publication number
JPH09178800A
JPH09178800A JP34168595A JP34168595A JPH09178800A JP H09178800 A JPH09178800 A JP H09178800A JP 34168595 A JP34168595 A JP 34168595A JP 34168595 A JP34168595 A JP 34168595A JP H09178800 A JPH09178800 A JP H09178800A
Authority
JP
Japan
Prior art keywords
dielectric breakdown
field strength
insulating layer
electric field
ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34168595A
Other languages
Japanese (ja)
Other versions
JP3147758B2 (en
Inventor
Kazuhiro Yamamoto
一弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP34168595A priority Critical patent/JP3147758B2/en
Publication of JPH09178800A publication Critical patent/JPH09178800A/en
Application granted granted Critical
Publication of JP3147758B2 publication Critical patent/JP3147758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Relating To Insulation (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To evaluate dielectric breakdown with the same degree as that of the TDDB(time dependent dielectric breakdown) method quickly in any case. SOLUTION: A dielectric breakdown field strength is obtained for all insulation layers 2 to be evaluated, each dielectric breakdown field strength is compared with a threshold field strength, for example, 8MV/cm, a ratio (conforming ratio) where the dielectric breakdown field strength is equal to or more than a threshold field strength is calculated, and the ratio is determined as a primary conforming ratio. When the calculation of the primary conforming ratio is completed, it is judged whether the calculation of the conforming rate is performed for a specific number of times or not, the operation until the calculation of the conforming ratio is repeated until it is judged that the calculation of the conforming ratio has been performed for a specific number of times, and a secondary conforming ratio, a third conforming ratio,... are determined. Then, an insulation layer 2 is evaluated based on the primary conforming ratio, the secondary conforming ratio,....

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子に設け
てある絶縁層の耐電圧及び耐久性,又は絶縁層の良・不
良等を評価する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating the withstand voltage and durability of an insulating layer provided on a semiconductor element, or the quality of an insulating layer.

【0002】[0002]

【従来の技術】半導体基板に形成したMOSキャパシタ
の酸化層又はトランジスタのゲート酸化層等,半導体素
子に設けられた絶縁層は、半導体素子の高密度化に伴い
その厚みが減じられている一方、電源電圧を低くするこ
とは困難であるため、絶縁層は高い電界強度の下で使用
されている。従って、半導体素子の信頼性を確保する上
で、絶縁層を詳細に評価することが重要である。
2. Description of the Related Art An insulating layer provided on a semiconductor element such as an oxide layer of a MOS capacitor or a gate oxide layer of a transistor formed on a semiconductor substrate is reduced in thickness as the density of the semiconductor element increases. Since it is difficult to reduce the power supply voltage, the insulating layer is used under high electric field strength. Therefore, it is important to evaluate the insulating layer in detail in order to secure the reliability of the semiconductor element.

【0003】そのような評価方法に絶縁破壊耐圧測定法
がある。この方法では、半導体基板に形成した複数の半
導体素子の絶縁層それぞれに印加する電圧を段階的に昇
圧し、所定の電流が検出されたときの電圧を絶縁破壊電
圧とする。(絶縁破壊電圧/絶縁層の厚み)で表される
絶縁破壊電界強度が所定の値以上,例えば8MV/cm
以上である絶縁層を良とし、そうでないものを不良とす
る。そして、印加した総数に対する良であった数の割合
に基づいて、絶縁層の優劣を評価する。しかし、このよ
うな絶縁破壊耐圧測定法は、短時間で評価を行うことは
できるものの、半導体素子の使用状態に応じた評価,即
ち経時的な評価を行うことができないという問題があっ
た。
As such an evaluation method, there is a dielectric breakdown voltage measuring method. In this method, the voltage applied to each of the insulating layers of the plurality of semiconductor elements formed on the semiconductor substrate is stepwise increased, and the voltage when a predetermined current is detected is used as the dielectric breakdown voltage. The breakdown electric field strength represented by (dielectric breakdown voltage / thickness of insulating layer) is not less than a predetermined value, for example, 8 MV / cm.
The above insulating layers are regarded as good, and those not so are regarded as defective. Then, the superiority or inferiority of the insulating layer is evaluated based on the ratio of the good number to the total applied voltage. However, although such a dielectric breakdown voltage measuring method can perform evaluation in a short time, it has a problem that it cannot perform evaluation according to a usage state of a semiconductor element, that is, evaluation with time.

【0004】そのため、絶縁層に一定の電圧を連続的に
印加し続け、所定の時間間隔で電流を検出して経時的な
変化を求め、絶縁破壊に至るまでの時間,その経過等を
詳細に評価するTDDB(Time Dependent Dielect
ric Breakdown)法が開発されており、このTDDB法
の改良方法として、印加する電圧を段階的に昇圧すると
共にChen −Holland−Hu モデルを適用する方法が特
開平 6-34704号公報に記載されている。
Therefore, a constant voltage is continuously applied to the insulating layer, a current is detected at a predetermined time interval to obtain a change over time, and the time until the dielectric breakdown and its progress are described in detail. TDDB (Time Dependent Dilect)
The ric breakdown method has been developed, and as an improved method of the TDDB method, a method of stepwise boosting the applied voltage and applying the Chen-Holland-Hu model is disclosed in Japanese Patent Laid-Open No. 6-34704. There is.

【0005】図6は、その評価方法の実施に使用する装
置の構成を示すブロック図であり、図中11は導電性の基
板である。基板11上には絶縁層12が形成してあり、該絶
縁層12上には電極13が形成してある。電極13は印加する
電圧の大きさを段階的に変化し得る可変電源15の一端子
に接続してあり、可変電源15の他端子は電流計14を介し
て基板11に接続してある。そして、可変電源15は0V近
傍の所定の電圧から段階的に昇圧し、絶縁破壊が生じる
まで複数回,所定時間ずつ絶縁層12に印加するようにな
っている。
FIG. 6 is a block diagram showing the structure of an apparatus used for carrying out the evaluation method, and 11 in the drawing is a conductive substrate. An insulating layer 12 is formed on the substrate 11, and an electrode 13 is formed on the insulating layer 12. The electrode 13 is connected to one terminal of a variable power source 15 that can change the magnitude of the applied voltage stepwise, and the other terminal of the variable power source 15 is connected to the substrate 11 via an ammeter 14. Then, the variable power source 15 is stepwise boosted from a predetermined voltage near 0 V and is applied to the insulating layer 12 a plurality of times for a predetermined time until dielectric breakdown occurs.

【0006】電流計14の検出電流Iは比較器17に与えら
れる。また、比較器17には、その値を越えた場合は絶縁
破壊が生じたと判断する閾値電流を発生する閾値電流発
生装置18から、印加した電界強度が6MV/cm以下の
場合は閾値電流JCR1 が、また印加した電界強度が6M
V/cmを越える場合は閾値電流JCR2 (JCR1 <J
CR2 )が与えられるようになっており、比較器17は閾値
電流JCR1 又は閾値電流JCR2 と検出電流Iとを比較す
る。その結果、印加電圧が6MV/cm以下であり、J
CR1 <Iである場合、その絶縁破壊は絶縁層12に存在す
るピンホール等の初期不良又は絶縁層12のムラ等の欠陥
によって生じたと判断する。一方、印加した電圧が6M
V/cmを越えており、JCR2 <Iである場合、その絶
縁破壊は欠陥のない絶縁層において耐電圧を越えたこと
によって生じたと判断する。
The detection current I of the ammeter 14 is supplied to the comparator 17.
It is. If the value exceeds that value, the comparator 17
Threshold current generation that generates a threshold current that determines that breakdown has occurred
The electric field strength applied from the raw device 18 is 6 MV / cm or less.
If the threshold current JCR1However, the applied electric field strength is 6M
Threshold current J when V / cm is exceededCR2(JCR1<J
CR2) Is given, the comparator 17
Current JCR1Or threshold current JCR2And the detection current I
You. As a result, the applied voltage was 6 MV / cm or less, and
CR1<I, the breakdown is in the insulating layer 12
Initial defects such as pinholes or defects such as unevenness of the insulating layer 12
It is judged that it was caused by. On the other hand, the applied voltage is 6M
V / cm is exceeded, JCR2<If I
Edge breakdown exceeded withstand voltage in a defect-free insulating layer
It is judged that it was caused by.

【0007】そして、絶縁破壊に至るまでの印加回数,
印加時間,及び印加した電界強度を用い、Chen −Hol
land−Hu モデルに基づいて絶縁層破壊寿命を求め、求
めた絶縁層破壊寿命にワイブル分布を適用してTDDB
曲線を算出し、算出したTDDB曲線に基づいて絶縁層
12の経時的な絶縁破壊を評価する。このように段階的に
印加電圧を高くすることによって、いわゆる加速度試験
を実施してTDDB曲線を計算によって求めるため、前
述した従来のTDDB法よりは短い時間でTDDB曲線
を得ることができる。
Then, the number of application times until dielectric breakdown,
Using the applied time and the applied electric field strength, Chen-Hol
The insulation layer breakdown life is obtained based on the land-Hu model, and the Weibull distribution is applied to the obtained insulation layer breakdown life to obtain TDDB.
A curve is calculated, and an insulating layer is calculated based on the calculated TDDB curve.
Evaluate 12 breakdowns over time. Since the so-called acceleration test is carried out and the TDDB curve is calculated by increasing the applied voltage stepwise as described above, the TDDB curve can be obtained in a shorter time than the conventional TDDB method described above.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
評価方法にあっては、Chen −Holland−Hu モデルに
基づいて計算によってTDDB曲線を求めているため、
該モデルに適合しない絶縁破壊、特に初期不良領域が存
在する場合については正確なTDDB曲線が得られず、
評価の信頼性が低いという問題があった。本発明はかか
る事情に鑑みてなされたものであって、その目的とする
ところは印加する電圧を段階的に昇圧して絶縁破壊電界
を検出する操作を同じ半導体素子の絶縁層に対して複数
回行うことによって、いかなる場合でも短時間でTDD
B法と同程度に絶縁破壊を評価し得る絶縁層の評価方法
を提供することにある。
However, in the conventional evaluation method, the TDDB curve is obtained by calculation based on the Chen-Holland-Hu model.
An accurate TDDB curve cannot be obtained in the case of dielectric breakdown that does not conform to the model, especially in the case where an initial defective region exists.
There was a problem that the reliability of evaluation was low. The present invention has been made in view of the above circumstances, and an object thereof is to perform an operation of stepwise increasing an applied voltage to detect a dielectric breakdown electric field a plurality of times with respect to an insulating layer of the same semiconductor element. By doing, TDD can be done in a short time in any case.
An object of the present invention is to provide a method for evaluating an insulating layer, which can evaluate dielectric breakdown to the same extent as the method B.

【0009】[0009]

【課題を解決するための手段】第1発明に係る絶縁層の
評価方法は、半導体素子に設けてある絶縁層に印加する
電圧を段階的に昇圧して絶縁破壊電界強度を検出し、検
出した絶縁破壊電界強度に基づいて絶縁層を評価する方
法において、前記絶縁破壊電界強度の検出を同じ半導体
素子の絶縁層に対して複数回行うことを特徴とする。
According to a first aspect of the present invention, there is provided an insulating layer evaluation method, wherein a voltage applied to an insulating layer provided on a semiconductor element is stepwise increased to detect a dielectric breakdown electric field strength. In the method of evaluating an insulating layer based on the breakdown electric field strength, the detection of the breakdown electric field strength is performed a plurality of times for the insulating layer of the same semiconductor element.

【0010】第2発明に係る絶縁層の評価方法は、半導
体基板に形成した複数の半導体素子に設けてある絶縁層
に印加する電圧を段階的に昇圧して絶縁破壊電界強度を
検出し、検出した絶縁破壊電界強度に基づいて絶縁層を
評価する方法において、複数の半導体素子の絶縁層に対
して前記絶縁破壊電界強度をそれぞれ検出するステップ
と、検出した各絶縁破壊電界強度と予め定めた閾値とを
それぞれ比較するステップと、前記半導体素子の数に対
する、絶縁破壊電界強度が閾値を越えた半導体素子の数
の比率を算出するステップとを備え、これらの各ステッ
プを複数回数繰り返し、算出した複数の比率に基づいて
絶縁層を評価することを特徴とする。
According to a second aspect of the present invention, there is provided an insulating layer evaluation method in which a voltage applied to an insulating layer provided on a plurality of semiconductor elements formed on a semiconductor substrate is stepwise increased to detect a dielectric breakdown electric field strength. In the method for evaluating an insulation layer based on the insulation breakdown electric field strength, the step of respectively detecting the insulation breakdown electric field strength with respect to the insulation layers of a plurality of semiconductor elements, each detected insulation breakdown electric field strength and a predetermined threshold value. And a step of calculating the ratio of the number of semiconductor elements whose dielectric breakdown field strength exceeds a threshold value with respect to the number of semiconductor elements, and repeating each of these steps a plurality of times It is characterized in that the insulating layer is evaluated based on the ratio of.

【0011】本発明にあっては、印加する電圧を段階的
に昇圧して絶縁破壊電界強度を検出する操作を、同じ半
導体素子の絶縁層に対して複数回行うことによって、絶
縁層に過大なストレスを反復して負荷する。これによっ
て、電圧を長時間印加した場合に絶縁破壊を生じさせる
ような僅かな歪み又は不均一な部分等が絶縁層に存在す
る場合、一度目の負荷では所定の絶縁破壊電界強度を有
していても、過大ストレスの反復負荷によって、それら
が欠陥にまで拡大され、絶縁破壊電界強度の急激な低下
として検出される。このように計算によってではなく実
測値に基づいて評価を行うため、いかなる場合であって
もTDDB法と同等の評価を短時間で行うことができ
る。
In the present invention, the operation of stepwise increasing the applied voltage and detecting the dielectric breakdown electric field strength is performed a plurality of times on the insulating layer of the same semiconductor element, so that an excessive amount of voltage is applied to the insulating layer. Repeat stress. As a result, when the insulating layer has a slight distortion or a non-uniform portion that causes dielectric breakdown when a voltage is applied for a long time, the first load has a predetermined dielectric breakdown electric field strength. However, due to repeated overstressing, they are expanded to defects and detected as a sharp drop in the dielectric breakdown field strength. Since the evaluation is performed based on the actual measurement value instead of the calculation as described above, the evaluation equivalent to the TDDB method can be performed in a short time in any case.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて具体的に説明する。図1は本発明に係る評価
方法の実施に使用する装置の構成を示す模式図であり、
図中1は基板である。基板1上には絶縁層2,2,…及
び電極3,3,…を備える複数の半導体素子が所定パタ
ーンになるように形成してある。電極3には前後左右移
動自在に支持されているプローブ7の下端が接触してあ
り、プローブ7の移動は制御装置8によって制御される
ようになっている。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a schematic diagram showing the configuration of an apparatus used for carrying out the evaluation method according to the present invention,
In the figure, reference numeral 1 denotes a substrate. A plurality of semiconductor elements having insulating layers 2, 2, ... And electrodes 3, 3, ... Are formed in a predetermined pattern on the substrate 1. The lower end of a probe 7 supported so as to be movable back and forth and right and left is in contact with the electrode 3, and the movement of the probe 7 is controlled by a controller 8.

【0013】プローブ7の上端は、印加電圧の大きさを
段階的に変化させ得る可変電源5の一端子に接続してあ
り、可変電源5の他端子は基板1に接続してある。この
可変電源5のオン・オフは制御装置8によって制御され
ている。また、可変電源5の印加電圧を測定する電圧計
6が並列接続してあり、プローブ7と可変電源5との間
には電流計4が介装してある。この電流計4及び電圧計
6の測定値は制御装置8に与えられる。
The upper end of the probe 7 is connected to one terminal of the variable power source 5 which can change the magnitude of the applied voltage stepwise, and the other terminal of the variable power source 5 is connected to the substrate 1. The control device 8 controls the on / off of the variable power source 5. Further, a voltmeter 6 for measuring the applied voltage of the variable power source 5 is connected in parallel, and an ammeter 4 is interposed between the probe 7 and the variable power source 5. The measured values of the ammeter 4 and the voltmeter 6 are given to the controller 8.

【0014】図2は図1に示した制御装置8の要部構成
を示すブロック図である。図中82は前述したプローブ7
(図1参照)の移動を制御するプローブ制御部、83は絶
縁破壊電界強度を検出する検出部、84は可変電源のオン
・オフを制御する電源制御部であり、これらの動作は中
央制御部81によって制御されている。また、中央制御部
81には検出部83が検出した絶縁破壊電界強度を記憶する
第1メモリ85と、第1メモリ85に記憶された絶縁破壊電
界強度と予め設定された閾値電界強度とを比較して、絶
縁破壊電界強度が閾値電界強度以上であったものの割合
(良品率)を算出する算出部86と、算出部86が算出した
良品率を記憶する第2メモリ87とが接続してあり、中央
制御部81はこれらの動作も制御している。
FIG. 2 is a block diagram showing a main configuration of the control device 8 shown in FIG. In the figure, 82 is the probe 7 described above.
(See FIG. 1) A probe control unit that controls movement, 83 a detection unit that detects the dielectric breakdown electric field strength, and 84 a power supply control unit that controls on / off of a variable power supply. These operations are performed by a central control unit. Controlled by 81. Also, the central control unit
In 81, a first memory 85 that stores the dielectric breakdown electric field strength detected by the detection unit 83 is compared with the dielectric breakdown electric field strength stored in the first memory 85 and a preset threshold electric field strength, The calculation unit 86 for calculating the ratio (non-defective product rate) of the electric field strength equal to or higher than the threshold electric field strength and the second memory 87 for storing the non-defective product ratio calculated by the calculation unit 86 are connected to each other, and the central control unit 81 Also controls these actions.

【0015】プローブ制御部82には、所定のパターンに
形成された半導体素子の絶縁層2,2,…の内,絶縁破
壊電界強度を検出する半導体素子の部位及び検出順が設
定してあり、プローブ制御部82は、中央制御装置81から
の指令に従って、絶縁層2の絶縁破壊電界強度の検出が
終了すると次の絶縁層2の部位にプローブ7を移動し、
該絶縁層2上に形成された電極3に接触させる。プロー
ブ7が電極3に接触されると、電源制御部84は可変電源
5をオンし、電圧の低い側から高い側へ所定時間ずつ電
圧を印加させる。
In the probe control unit 82, the position and the detection order of the semiconductor element for detecting the dielectric breakdown electric field strength among the insulating layers 2, 2, ... Of the semiconductor element formed in a predetermined pattern are set, In accordance with a command from the central controller 81, the probe controller 82 moves the probe 7 to the next site of the insulating layer 2 when the detection of the dielectric breakdown field strength of the insulating layer 2 is completed,
The electrode 3 formed on the insulating layer 2 is contacted. When the probe 7 is brought into contact with the electrode 3, the power supply control unit 84 turns on the variable power supply 5 to apply a voltage from the low voltage side to the high voltage side for a predetermined time.

【0016】検出部83には絶縁層2,2,…の厚み及び
閾値電流が予め設定されており、検出部83は電流計4の
検出電流と閾値電流とを比較し、前者が後者を越えたと
き絶縁破壊が生じたと判断して、そのときの電圧計6の
検出電圧及び絶縁層2,2,…から絶縁破壊電界強度を
求め、それを第1メモリ85に記憶させる。また、検出部
83によって絶縁破壊が生じたと判断されると、電源制御
部84は可変電源5をオフにする。このような操作を所定
部位の絶縁層2,2,…全てに対して行う。そして、前
同様の操作を所定回数だけ繰り返す。
The thickness of the insulating layers 2, 2, ... And the threshold current are preset in the detection unit 83. The detection unit 83 compares the detection current of the ammeter 4 with the threshold current, and the former exceeds the latter. At this time, it is determined that the dielectric breakdown has occurred, the dielectric breakdown electric field strength is obtained from the detected voltage of the voltmeter 6 and the insulating layers 2, 2, ... At that time, and stored in the first memory 85. Also, the detection unit
When it is determined by 83 that the dielectric breakdown has occurred, the power supply control unit 84 turns off the variable power supply 5. Such an operation is performed for all the insulating layers 2, 2, ... Then, the same operation as before is repeated a predetermined number of times.

【0017】算出部86は前述した操作が1回行われる都
度、第1メモリ85に記憶された各絶縁破壊電界強度と、
予め設定された閾値電界強度とを比較して良品率を算出
し、それを第2メモリ87に記憶させる。そして、出力部
88は第2メモリ87に記憶された複数の良品率をプリンタ
又はモニタ等に出力する。
Each time the above-mentioned operation is performed once, the calculation unit 86 calculates each dielectric breakdown electric field strength stored in the first memory 85,
The non-defective rate is calculated by comparing with a preset threshold electric field strength and stored in the second memory 87. And the output section
Reference numeral 88 outputs the plurality of non-defective product rates stored in the second memory 87 to a printer, a monitor, or the like.

【0018】図3は本発明に係る評価方法による絶縁層
の評価手順を示すフローチャートである。プローブ7を
所定の電極3に接触させ(ステップS1)、可変電源5
を作動させて電圧の印加を開始し(ステップS2)て、
絶縁層2に流れる電流の値を電流計4で検出する(ステ
ップS3)。所定時間だけ電圧を印加する間に検出され
た検出電流と予め設定した閾値電流,例えば1μAとを
比較し(ステップS4)、検出電流が閾値電流以下であ
れば、ステップS2に戻って一段高い電圧を印加する。
そして、検出電流が閾値電流を越えた場合、電圧の印加
を停止し(ステップS5)、そのときの電圧及び予め測
定した絶縁層2の厚みから絶縁破壊電界強度を求める
(ステップS6)。
FIG. 3 is a flow chart showing an insulating layer evaluation procedure according to the evaluation method of the present invention. The probe 7 is brought into contact with the predetermined electrode 3 (step S1), and the variable power source 5
To start applying voltage (step S2),
The value of the current flowing through the insulating layer 2 is detected by the ammeter 4 (step S3). The detected current detected while the voltage is applied for a predetermined time is compared with a preset threshold current, for example, 1 μA (step S4). If the detected current is less than or equal to the threshold current, the process returns to step S2 and the voltage is increased by one step. Is applied.
Then, when the detected current exceeds the threshold current, the voltage application is stopped (step S5), and the breakdown electric field strength is obtained from the voltage at that time and the thickness of the insulating layer 2 measured in advance (step S6).

【0019】絶縁破壊電界強度が求まると、当該電極3
が検出対象の最後の絶縁層2に係る電極であるか否かを
判断し(ステップS7)、そうであると判断されるま
で、ステップS1〜ステップS7までの操作を繰り返
す。そして、評価対象である全ての絶縁層2について絶
縁破壊電界強度をそれぞれ求めると、各絶縁破壊電界強
度と閾値電界強度,例えば8MV/cmとを比較し(ス
テップS8)、良品率を算出し(ステップS9)、それ
を一次良品率とする。
When the breakdown electric field strength is obtained, the electrode 3
Is the electrode related to the last insulating layer 2 to be detected (step S7), and the operations from step S1 to step S7 are repeated until it is determined that this is the case. Then, when the dielectric breakdown electric field strength is obtained for all the insulating layers 2 to be evaluated, each dielectric breakdown electric field strength is compared with the threshold electric field strength, for example, 8 MV / cm (step S8), and the non-defective rate is calculated ( In step S9), it is set as the primary non-defective rate.

【0020】一次良品率の算出が終了すると、良品率の
算出を所定回数だけ行ったか否かを判断し(ステップS
10)、そうであると判断されるまでステップS1〜ステ
ップS10までの操作を繰り返し、それぞれ二次良品率,
三次良品率,…とする。そして、一次良品率,二次良品
率,…に基づいて絶縁層2を評価する(ステップS1
1)。このように、段階的に高い電圧を印加して絶縁破
壊電界を検出する操作を、同じ絶縁層2に対して複数回
行うことによって、絶縁層2に過大なストレスを反復し
て加え、電圧を長時間印加した場合に絶縁破壊を生じさ
せるような僅かな歪み又は不均一な部分等が絶縁層に存
在する場合、それらを欠陥にまで拡大して絶縁破壊とし
て検出する。従って、前述したTDDB法と同等の評価
を短時間で行うことができる。
When the calculation of the primary non-defective rate is completed, it is judged whether or not the non-defective rate has been calculated a predetermined number of times (step S
10), the operations from step S1 to step S10 are repeated until it is determined that they are, and the secondary non-defective rate,
The third-order non-defective rate, ... Then, the insulating layer 2 is evaluated based on the primary non-defective rate, the secondary non-defective rate, ... (Step S1
1). In this way, the operation of applying a high voltage stepwise to detect the dielectric breakdown electric field is performed a plurality of times on the same insulating layer 2, thereby repeatedly applying excessive stress to the insulating layer 2 to apply a voltage. When there are slight strains or non-uniform portions in the insulating layer that cause dielectric breakdown when applied for a long time, these are expanded to defects and detected as dielectric breakdown. Therefore, the same evaluation as the above-mentioned TDDB method can be performed in a short time.

【0021】[0021]

【実施例】次に、比較試験を行った結果について説明す
る。図4は本発明方法による測定結果を示すグラフであ
り、図5は従来のTDDB法による測定結果を示すグラ
フである。試料には、チョクラルスキ(CZ)法によっ
て得たウェハの表面を、A〜Eの互いに異なる組成の溶
液で洗浄した後、600個のMOSキャパシタを形成し
たものと、対照として洗浄を行うことなく同数のMOS
キャパシタを形成したもの(F)を用いた。また、エピ
タキシャル(Epi)成長させたウェハの表面を、A組
成で洗浄した後に600個のMOSキャパシタを形成し
たもの、及び対照として洗浄を行うことなく同数のMO
Sキャパシタを形成したものも用いた。
EXAMPLES Next, the results of comparison tests will be described. FIG. 4 is a graph showing the measurement result by the method of the present invention, and FIG. 5 is a graph showing the measurement result by the conventional TDDB method. For the sample, the surface of the wafer obtained by the Czochralski (CZ) method was washed with solutions having different compositions of A to E, and then 600 MOS capacitors were formed. MOS
What formed the capacitor (F) was used. In addition, the surface of an epitaxially grown wafer was cleaned with the composition A and then 600 MOS capacitors were formed, and as a control, the same number of MO capacitors was used without cleaning.
The thing which formed the S capacitor was also used.

【0022】図4に示した本発明方法にあっては、MO
Sキャパシタを200個ずつ3つのグループにわけ、各
グループに対して二次良品率まで検出しており、図中、
○は一次良品率を、また●は二次良品率をそれぞれ表し
ている。図5に示した従来のTDDB法にあっては、2
00個のMOSキャパシタについて11MV/cmとな
るように電圧を印加し、累積破壊率を対数時間に対して
プロットしてある。
In the method of the present invention shown in FIG.
The S capacitors are divided into three groups of 200 each, and the secondary non-defective rate is detected for each group.
○ indicates the primary non-defective product rate, and ● indicates the secondary non-defective product ratio. In the conventional TDDB method shown in FIG.
A voltage was applied so that 00 MV capacitors had a voltage of 11 MV / cm, and the cumulative breakdown rate was plotted against logarithmic time.

【0023】図5から明らかな如く、従来のTDDB法
による評価結果は、CZウェハについてはE≒C≒D>
A>B>Fであり、EpiウェハについてはA<Fであ
った。また、ウェハの比較では、CZウェハ≪Epiウ
ェハであった。一方、図3から明らかな如く、本発明に
よる評価結果は、CZウェハについてはC≒D≒E>A
>B>Fであり、EpiウェハについてはA<Fであ
り、ウェハの比較では、CZウェハ≪Epiウェハであ
った。このように、本発明方法によってTDDB法と同
様な評価を行うことができることが分かる。
As is apparent from FIG. 5, the evaluation result by the conventional TDDB method shows that for a CZ wafer, E≈C≈D>
A>B> F, and A <F for the Epi wafer. In comparison of wafers, CZ wafer << Epi wafer. On the other hand, as is apparent from FIG. 3, the evaluation results according to the present invention show that CZ wafers have C≈D≈E> A.
>B> F, A <F for the Epi wafer, and a CZ wafer << Epi wafer in the wafer comparison. As described above, it is understood that the method of the present invention can perform the same evaluation as the TDDB method.

【0024】[0024]

【発明の効果】以上詳述した如く、本発明に係る絶縁層
の評価方法にあっては、TDDB法と同程度に詳細な評
価を短時間で行うことができ、また、計算モデルによら
ないため、絶縁層のいかなる不良をも正確に評価するこ
とができる等、本発明は優れた効果を奏する。
As described above in detail, in the method for evaluating an insulating layer according to the present invention, it is possible to perform a detailed evaluation in the same time as the TDDB method in a short time, and it does not depend on a calculation model. Therefore, the present invention has excellent effects such that any defect in the insulating layer can be accurately evaluated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る評価方法の実施に使用する装置の
構成を示す模式図である。
FIG. 1 is a schematic diagram showing a configuration of an apparatus used for carrying out an evaluation method according to the present invention.

【図2】図1に示した制御装置の要部構成を示すブロッ
ク図である。
FIG. 2 is a block diagram showing a main configuration of a control device shown in FIG.

【図3】本発明に係る評価手順を示すフローチャートで
ある。
FIG. 3 is a flowchart showing an evaluation procedure according to the present invention.

【図4】本発明方法による測定結果を示すグラフであ
る。
FIG. 4 is a graph showing the measurement results by the method of the present invention.

【図5】従来のTDDB法による測定結果を示すグラフ
である。
FIG. 5 is a graph showing measurement results by a conventional TDDB method.

【図6】従来の評価方法の実施に使用する装置の構成を
示すブロック図である。
FIG. 6 is a block diagram showing a configuration of an apparatus used for implementing a conventional evaluation method.

【符号の説明】[Explanation of symbols]

1 基板 2 絶縁層 3 電極 4 電流計 5 可変電源 7 プローブ 1 substrate 2 insulating layer 3 electrode 4 ammeter 5 variable power supply 7 probe

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子に設けてある絶縁層に印加す
る電圧を段階的に昇圧して絶縁破壊電界強度を検出し、
検出した絶縁破壊電界強度に基づいて絶縁層を評価する
方法において、 前記絶縁破壊電界強度の検出を同じ半導体素子の絶縁層
に対して複数回行うことを特徴とする絶縁層の評価方
法。
1. A voltage applied to an insulating layer provided in a semiconductor element is stepwise increased to detect a dielectric breakdown electric field strength,
A method for evaluating an insulating layer based on the detected dielectric breakdown field strength, wherein the dielectric breakdown field strength is detected a plurality of times with respect to the insulating layer of the same semiconductor element.
【請求項2】 半導体基板に形成した複数の半導体素子
に設けてある絶縁層に印加する電圧を段階的に昇圧して
絶縁破壊電界強度を検出し、検出した絶縁破壊電界強度
に基づいて絶縁層を評価する方法において、 複数の半導体素子の絶縁層に対して前記絶縁破壊電界強
度をそれぞれ検出するステップと、 検出した各絶縁破壊電界強度と予め定めた閾値とをそれ
ぞれ比較するステップと、 前記半導体素子の数に対する、絶縁破壊電界強度が閾値
を越えた半導体素子の数の比率を算出するステップとを
備え、 これらの各ステップを複数回数繰り返し、算出した複数
の比率に基づいて絶縁層を評価することを特徴とする絶
縁層の評価方法。
2. A dielectric breakdown electric field strength is detected by stepwise increasing a voltage applied to an insulating layer provided on a plurality of semiconductor elements formed on a semiconductor substrate, and the insulating layer is based on the detected dielectric breakdown electric field strength. In the method for evaluating the above, a step of detecting the dielectric breakdown electric field strengths for insulating layers of a plurality of semiconductor elements, a step of comparing the respective detected dielectric breakdown electric field strengths with a predetermined threshold value, and the semiconductor A step of calculating a ratio of the number of semiconductor elements whose dielectric breakdown electric field intensity exceeds a threshold value to the number of elements, repeating each of these steps a plurality of times, and evaluating the insulating layer based on the calculated plurality of ratios. A method for evaluating an insulating layer, comprising:
JP34168595A 1995-12-27 1995-12-27 Evaluation method of insulation layer Expired - Fee Related JP3147758B2 (en)

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Application Number Priority Date Filing Date Title
JP34168595A JP3147758B2 (en) 1995-12-27 1995-12-27 Evaluation method of insulation layer

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Application Number Priority Date Filing Date Title
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Publication Number Publication Date
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JP3147758B2 JP3147758B2 (en) 2001-03-19

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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010066250A (en) * 2008-08-11 2010-03-25 Mitsubishi Electric Corp Semiconductor testing device and semiconductor test method
US8680883B2 (en) 2010-05-11 2014-03-25 Samsung Electronics Co., Ltd. Time dependent dielectric breakdown (TDDB) test structure of semiconductor device and method of performing TDDB test using the same
CN111812196A (en) * 2020-07-16 2020-10-23 浙江云联智能制造研究院有限公司 Gas pipe electric spark detection equipment with gas pipe insulating layer electric leakage
WO2021039501A1 (en) * 2019-08-23 2021-03-04 デンカ株式会社 Insulating-material withstand-voltage-characteristic evaluation method and withstand-voltage-characteristic measurement device
CN112946428A (en) * 2019-11-26 2021-06-11 杭州通产机械有限公司 Detection method
GB2616875A (en) * 2022-03-23 2023-09-27 Megger Instruments Ltd Measurement apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010066250A (en) * 2008-08-11 2010-03-25 Mitsubishi Electric Corp Semiconductor testing device and semiconductor test method
US8680883B2 (en) 2010-05-11 2014-03-25 Samsung Electronics Co., Ltd. Time dependent dielectric breakdown (TDDB) test structure of semiconductor device and method of performing TDDB test using the same
WO2021039501A1 (en) * 2019-08-23 2021-03-04 デンカ株式会社 Insulating-material withstand-voltage-characteristic evaluation method and withstand-voltage-characteristic measurement device
CN112946428A (en) * 2019-11-26 2021-06-11 杭州通产机械有限公司 Detection method
CN111812196A (en) * 2020-07-16 2020-10-23 浙江云联智能制造研究院有限公司 Gas pipe electric spark detection equipment with gas pipe insulating layer electric leakage
GB2616875A (en) * 2022-03-23 2023-09-27 Megger Instruments Ltd Measurement apparatus
WO2023180738A1 (en) * 2022-03-23 2023-09-28 Megger Instruments Ltd Measurement of insulation resistance of an electrical insulator

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