JPH09178785A - Pulse counting circuit and fv conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the responsivity of a pulse counting circuit. SOLUTION: A pulse counting circuit 11 counts input signals by an input signal counter 16, latches the signals with a latch 17 for each counting period which is set by a timer signal (B) from a timer circuit 15 for setting count period gives the storage value of the latch 17 to a D/A conversion circuit 12, and performs FV conversion to a voltage value from frequency. A comparator 19 compares the count value of the input signal counter 16 with the stored value of the latch 17 and selects a value which is not smaller by a selector 20 and feeds it to the D/A conversion circuit 12. When the frequency of an input signal rapidly increases, the count value of the input signal counter 16 is derived as a direct pulse count value, thus improving the response when the input signal rapidly increases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse counting circuit for counting the number of various pulse signals input per predetermined time, and an FV conversion circuit for converting the frequency of various input signals into a voltage using the pulse counting circuit. Regarding

[0002]

2. Description of the Related Art A typical configuration of a conventional pulse counting circuit and FV converting circuit is shown in FIG. The input signal is counted by the pulse counting circuit 1 as the number of pulses per predetermined time and converted into a digital value, and the D / A conversion circuit 2 converts the digital value into a signal representing an analog value.
The FV conversion circuit 3 including the pulse counting circuit 1 and the D / A conversion circuit 2 detects the frequency of the input signal as the number of pulses within a unit time and derives an analog output having a voltage level corresponding to the detected number of pulses. .

In the pulse counting circuit 1, a waveform shaping circuit 4 for shaping the waveform of various input signals and converting it into a pulse wave, and a timer signal for determining a counting period T which is a predetermined time for counting the pulse wave are output. Counting period setting timer 5
And an input signal counter 6 that counts the number of output pulses from the waveform shaping circuit 4 that enters during the count period T with an N-bit digital value, and an output value of the input signal counter 6 at the end of the count period by a timer signal. Latch 7 to hold
And a delay circuit 8 that delays the timer signal from the count period setting timer 5 for a fixed time to clear the input signal counter 6. The D / A conversion circuit 2 converts the digital output from the latch 7 into an analog output.

FIG. 21 shows a signal waveform of a main part of the pulse counting circuit 1 of FIG. Counting period setting timer 5
The timer signal output from is supplied to the clock input CK of the latch 7 and the input of the delay circuit 8 as a latch signal shown in (b). The delay circuit 8 outputs the timer signal to the time Δt.
After that, the clear signal shown in (c) is applied to the clear input CL of the input signal counter 6. When the reset input shown in (a) is released, the count period setting timer 5 derives the timer output as the latch signal (b) at the count cycle T. At the time when the latch signal (b) rises at time t1, the count value m of the input signal counter 6 immediately before that is taken in and held in the latch 7. Input signal counter 6
The counter value is cleared to zero by the clear signal in (c), and the input pulse signal shown in (d) is output from the waveform shaping circuit 4 and is counted again. If the input pulse signal (d) rises n times during the counting period T up to the time t2, the latch output indicated by (f) from the latch 7 changes from m to n after the time t2.

[0005]

In the pulse counting circuit 1 described with reference to FIGS. 20 and 21, the count period T is constant, and the digital output of the latch and the D / A conversion circuit 2 are provided.
The output value of the analog output from does not change unless the latch signal (b) for each count period T is input, and therefore the conversion response is also determined in the count period T. Therefore, in the case of FV converting a signal in a wide frequency range, the count period T must be made long in accordance with the low frequency side, the responsiveness deteriorates, and the frequency changes in the high frequency range. You will not be able to follow.

The pulse counting circuit 1 and the FV conversion circuit 3 shown in FIG. 20 are used in various fields. For example, in order to detect the engine speed of an automobile and smoothly perform various controls according to the speed, it is necessary to be able to measure an accurate speed at all times with good responsiveness.

An object of the present invention is to provide a pulse counter circuit having a good responsiveness capable of following a wide range change of a pulse generation period, and an FV having a good responsiveness capable of following a wide range change of a frequency of an input signal. It is to provide a conversion circuit.

[0008]

SUMMARY OF THE INVENTION The present invention is a pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, wherein a counting period is set and a counting period is set for each counting period. A timer that derives a clock signal, a counter that is cleared by the clock signal from the timer, counts the pulse signals that are input, derives a signal that represents the count value, and a counter that is immediately before being cleared by the clock signal from the timer. In response to the signal from the counter and the latch that stores the count value and derives the signal that represents the stored value, compare the count value and the stored value, and derive the signal that represents the value that is not smaller as the pulse count value. And a comparison means for performing the pulse counting circuit. According to the present invention, the counter counts the pulse signal input within the counting period set by the clock signal from the timer, and the count value of the preceding counting period is stored in the latch.
The comparing means compares the count value of the counter with the stored value of the latch, and derives a signal representing the value which is not smaller as the pulse count value. If the cycle of the input pulse signal is shortened and the count value of the counter becomes larger than the stored value of the latch within the count period, the count value of the counter is directly derived as the pulse count value in the remaining count period. . Therefore, the generation period of the input pulse signal can be shortened, the followability when the frequency of the input signal increases such that the number of pulses increases, and the response can be improved.

Furthermore, the present invention is a pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, wherein a counting period is set and a clock signal is derived for each counting period. In response to the timer and the clock signal from the timer, the select signal is derived for each selection period of a value obtained by dividing the counting period corresponding to the cycle of the clock signal by one selected value selected from a plurality of predetermined integers. A selector, a counter that is cleared by a select signal from the selector, counts the pulse signals that are input, and derives a signal that represents the count value, and responds to the signal from the counter by counting the count value of the counter and the selected value. Multiplying means for deriving a signal representing a multiplication value and a signal from the multiplying means immediately before the counter is cleared by the select signal from the selector. And stores the multiplication value of the multiplication means and derives a signal representing the stored value as a pulse count value, and compares the pulse count value with a plurality of preset reference values in response to the signal from the latch. , And a comparing means for controlling the selector according to the result thereof. According to the present invention, the counter counts the input pulse signal for each selection period obtained by dividing the counting period by one selection value selected from a plurality of integers predetermined by the selector. Since the count value of the counter is multiplied by the selection value, it is possible to perform pulse counting in the selection period, which is almost equivalent to the counting period. If the count value of the counter is divided by the selected value and multiplied by the same selected value again, it may not be the same as the original count value, but if the original count value is relatively large, the result of division and multiplication The error of is small. When the count value of the counter is equal to or larger than one reference value, the comparing means selects an integer of a larger value as a selection value for further division and multiplication, shortens the selection period, and outputs the pulse signal input at high frequency. The trackability when the number increases can be improved. When the number of pulses of the input signal decreases, if the coefficient value is less than or equal to one reference value, an integer with a smaller value is selected as a selection value for division and multiplication. Therefore, the selection period is lengthened to prevent an increase in error. You can

In the present invention, the comparison means converts the digital signal representing the pulse count value from the latch into an analog signal, compares the analog signal with a reference level corresponding to the first and second reference values, and compares the result. The selector is controlled so as to select the selection value according to the above. According to the invention, the comparing means compares the analog signal obtained by converting the pulse count value with the reference levels corresponding to the first and second reference values, and selects an integer value for division and multiplication.
When an analog signal such as a conversion circuit is easily obtained, the response can be improved especially at high frequencies.

The present invention further comprises an input detecting means for detecting the presence / absence of an input pulse signal, and the comparing means responds to the output from the input detecting means, and the counter is cleared by the select signal from the selector. When the pulse signal is not input up to, the selector is controlled so as to select a value smaller than the value selected at that time as the selection value without clearing the counter. According to the present invention, when the input pulse signal sharply decreases, the selection period can be switched to a long time to prevent an increase in error.

In the present invention, the comparison means does not clear the counter when the count value until the counter is cleared by the select signal from the selector in response to the signal from the counter is less than a predetermined reference value. The selector is controlled so as to select a value smaller than the value selected at that time as the selected value.
According to the present invention, when the number of pulses of the input signal counted by the counter is small, the selection value for dividing the counting period is selected to be small, and the count value of the counter is used as it is to continue counting pulses. It is possible to improve the responsiveness when the number of pulses of the input signal changes in the decreasing direction, as compared with the case of starting counting again.

Further, according to the present invention, the selector selects the maximum integer in the initial state. According to the present invention, since the maximum integer is selected by the selector in the initial state, it is possible to sufficiently follow up even if a high frequency input signal is input at the start of counting, and it is possible to improve responsiveness.

Further, in the present invention, the comparison means responds to a signal from the counter, and when the count value until the counter is cleared by the select signal from the selector is equal to or more than a predetermined reference value, the comparison value is set as the selected value. The selector is controlled so as to select a value larger than the value selected at the time point. According to the present invention, when the number of pulses sharply increases such that the frequency of the input signal sharply increases, the count value until the counter is cleared becomes equal to or greater than a predetermined reference value. Control and select an integer value greater than the value currently selected. As a result, it is possible to improve the follow-up property when the frequency suddenly rises and improve the responsiveness.

In the present invention, the selector selects the smallest integer value in the initial state. According to the present invention, since the selection value selected by the selector is the smallest integer in the initial state, a sufficient selection period is set for an input signal having a long frequency of a pulse signal and a low frequency, and accurate counting is performed. It can be carried out. When the number of input pulses is large, the selection value selected by the selector becomes large, so that it is possible to improve the followability to the high frequency side.

Further, the present invention is a pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, wherein a counting period is set and a clock signal is derived for each counting period. Of the plurality of timers, each timer derives a clock signal at each time point divided by a division cycle corresponding to a value obtained by dividing the counting period by the number of timers, and each timer is provided with each timer. A pulse signal that is cleared by a clock signal and is input is counted, a signal that represents the count value is derived, and in response to the plurality of counters, the timers, and the signals from the counters, the pulse counts are calculated for each division cycle. And a latch means for storing a count value from a counter whose count value is cleared at a time point and deriving a signal representing the stored value as a pulse count value. It is a circuit. According to the present invention, the plurality of sets each including one timer and one counter count the input signals in the counting periods of the same length and different timings, and the latch means sequentially latches the signals. Since the counting of input signals and the timing of latching are different for each set,
The latch means can obtain the count value from the different counter for each divided period at a time interval shorter than the time required for counting.

Further, the present invention is a pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, wherein a counting period is set and a clock signal is derived for each counting period. Of the plurality of timers, each timer derives a clock signal at each time point divided by a division cycle corresponding to a value obtained by dividing the counting period by the number of timers, and each timer is provided with each timer. Immediately before being cleared by the clock signal from each timer, which is cleared by the clock signal, counts the input pulse signal, derives the signal indicating the count value, is provided for each of the plurality of counters and each timer The counter for storing the count value of the counter and deriving a signal representing the stored value, and in response to the signals from each latch and each timer, the combination is switched at each division cycle. For example, while a pulse counting circuit, which comprises an average calculating means for averaging the counts from the number of latches predetermined derives a signal representative of the average value as the pulse count. According to the present invention, a plurality of combinations each including one timer, one counter, and one latch are used, and clock signals deviated from each timer by a division cycle of an integer fraction, which is the number of combinations, in the same counting cycle. Is derived, and pulses are counted by each counter and latch. The averaging means averages the count values from a predetermined latch while switching the combination for each division cycle and derives a signal representing the average value as a pulse count value. Therefore, even if the count value of the counter fluctuates greatly, the error with respect to the pulse count value from the final averaging means can be reduced and the responsiveness to the true input signal can be improved.

Furthermore, the present invention is characterized by including a pulse counting circuit having the above characteristics, and D / A conversion means for responding to a signal from the pulse counting circuit and converting the pulse count value into an analog value. It is an FV conversion circuit. In the FV conversion circuit that converts the frequency of the input signal into an analog value,
Since the analog value obtained by converting the count value from the pulse counting circuit that improves the response when the frequency changes is used,
It is possible to obtain an FV conversion circuit having excellent responsiveness.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic electrical configuration of a first embodiment of the present invention. The pulse counting circuit 11 is
The number of pulses corresponding to the frequency of the input signal is counted, and a signal representing the pulse count value is given to the D / A conversion circuit 12. D /
The A conversion circuit 12 converts the input digital signal representing the pulse count value into an analog signal. Pulse counting circuit 1
1 and FV conversion circuit 13 including D / A conversion circuit 12
Converts the frequency of the input signal into a corresponding analog signal, eg a voltage level proportional to the frequency. The input signal is waveform-shaped by the waveform shaping circuit 14 and converted into a pulse wave having a constant amplitude. The counting period is set by the cycle of the clock signal derived from the counting period setting timer 15. Within this counting period, the input signal counter 16
Counts the pulse number of the input signal as an N-bit digital value, stores and holds the counted value by the latch 17, and adjusts the timing at which the latch 17 records the counted value and the timing at which the input signal counter 16 is cleared. Therefore, the delay circuit 18 is used. The comparator 19 compares the count value of the input signal counter 16 with the stored value of the latch 17, and derives the value which is not smaller as the pulse count value.

FIG. 2 shows the operation of the pulse counting circuit 11 of FIG. Control is started from step a1 and then step a2
Then, the count of the input signal counter 16, that is, the counting operation is started. At step a3, the input signal counter 1
The count value E1 of 6 and the stored value E2 of the latch 17 are compared. If E1 is larger than E2, step a4
Then, the selector 20 selects the count value E1 of the input signal counter 16. When E2 is larger than E1 in step a3, the selector 20 selects the stored value E2 of the latch 17 in step a5. Next, in step a6, it is determined whether or not the counting period has ended. The end of the counting period is determined by whether or not the latch timing is the rising edge of the clock signal. When it is determined that the process is not completed, the process returns to step a3, and when it is completed, the process proceeds to step a7. At step a7, the count value E1 of the input signal counter 16 is latched in the latch 17 and stored and retained in the latch 17
Input signal counter 16 until the stored value E2 of
The count value E1 of is substituted. Then, in step a8, the input signal counter 16 is cleared, and the process returns to step a2.

FIG. 3 shows the operation timing of the pulse counting circuit of FIG. The clock signal (B) from the counting period setting timer circuit 15 is derived for each counting period T.
From the waveform shaping circuit 14 to the clock input CK of the input signal counter 16 during the counting period from time t10 to t11,
When four pulse signals are input as shown in (D),
The count value E1 of the input signal counter 16 increases and the latch 1
The stored value E2 of 7 remains the initial value, for example, zero. The output of the comparator 19 becomes a high level indicating that E1 is larger than E2 after time t10a when the input pulse is first applied. At time t11 when the next counting period starts, the input signal counter 16 receives the clear signal from the delay circuit 18 at the clear input CL, and the count value becomes zero. On the other hand, the latch 17 receives the clock signal at the clock input CK and receives the input signal counter 1
Since the count value "4" of 6 is stored, "4" is held as the count value in the counting period from time t11. Time t11
In the counting period from, the count value of the input signal counter 16 becomes larger than the stored value “4” of the latch 17 after the time t11b. Therefore, the output (G) of the comparator 19 also becomes high level after the time t11b, and the selector 20 derives the output (E1) from the input signal counter 16 as a pulse count value. In the counting period after time t12, the storage value “7” is held in the latch 17, and the input signal counter 1
Until the count value of 6 exceeds 7, the value stored in the latch 17 (E
2) is selected by the selector 20. Therefore, the pulse count value (F) selected by the selector 20 and input to the D / A conversion circuit 12 becomes a signal as indicated by a thick line.

FIG. 4 shows a schematic electrical configuration of the second embodiment of the present invention. In this embodiment, parts corresponding to those in the first embodiment are designated by the same reference numerals, and description thereof will be omitted. Pulse counting circuit 21, D / A conversion circuit 12, and comparison means 22
Constitute the FV conversion circuit 23. Pulse counting circuit 21
A selector 24, a count period setting circuit 25 and a multiplication circuit 26 are included in the inside. The comparator 22 includes two comparators 27 and 28. Selector 24
Is the counting period T derived from the counting period setting circuit 25, its half period T / 2, and further 1
One is selected from the clock signals respectively representing T / 4 during the divided period of / 2 and is given to the latch 17 and the delay circuit 18 as a select signal shown in (B). The multiplication circuit 26 has a multiplication value P = n obtained by multiplying the count value n of the input signal counter 16 by α.
Derive xα as the output (E). The value of the multiplication value α that is the selection value is selected so that the period represented by the selection signal selected by the selector 24 is T / α. Comparator 2
7, 28 are digital memory values P held by the latch 17.
Are respectively compared with the first prescribed value R1 and the second prescribed value R2, and signals G1 and G2 representing the comparison results are given to the selector 24 and the multiplication circuit 26, respectively, to control the selection of the value of α.

FIG. 5 shows the operation of the pulse counting circuit 21 and the comparing means 22 of FIG. The operation is started from step b1, and in step b2, the input value P to the D / A conversion circuit 12 is compared with the specified values R1 and R2. P is R1 and R
When it is smaller than 2, t = T is selected as the count period in step b3, and 1 is set to the multiple α in step b4. When N is greater than or equal to R1 and less than R2,
In step b5, t = T / 2 is selected as the count period, and in step b6, the multiple α is set to 2. N is R1
And R2 or more, t = T / 4 is selected as the count period in step b7, and the multiple α = 4 is set in step b8. Next, when the count value n of the input signal counter 16 is obtained in step b9, step b1
At 0, the multiplication circuit 26 calculates P = n × α,
At step b11, the value of P is stored in the latch 17. At step b12, the input signal counter 16 is cleared,
Return to step b2.

FIG. 6 shows the operation timing of the pulse counting circuit 21 of FIG. When the reset input of (A) rises, three clock signals of three types are derived from the count period setting circuit 25 in the cycles of T, T / 2, and T / 4, respectively. The selector 24 selects the clock signal as shown in (B) and causes the input signal counter 16 to count the input signal as shown in (D). In the first counting period, the output (F) of the latch 17 is zero, and the comparator 2
Since the outputs (G1) and (G2) of 7, 28 are also zero, the clock signal T and the multiple α = 1 are selected, respectively.
If the reference value R1 = 8 and the reference value R2 = 16, T / 2 is selected as the next clock signal, and the multiple α = 2. Further, T / 4 is selected as the next clock signal, and the multiple α = 4. Since the number of pulses of the input signal (D) decreases in that period, it returns to the clock signal T / 2 in the next counting period, and the multiple α = 2 is set.

FIG. 7 shows the electrical construction of the third embodiment of the present invention. In the present embodiment, parts corresponding to those in the first and second embodiments are designated by the same reference numerals, and description thereof will be omitted. The selection in the selector 24 and the multiplication circuit 26 in the pulse counting circuit 21 is performed by the outputs (G1) and (G2) from the analog comparators 31 and 32 in the comparison means 30. The signals input to the comparators 31 and 32 are analog signals from the D / A conversion circuit 12. The comparators 31 and 32 include reference voltages V1 and V2 corresponding to the first and second reference values and the D / A conversion circuit 12 respectively.
The analog output of the second embodiment is compared, and the same switching as in the second embodiment is performed according to the comparison result. The operation of the third embodiment is similar to the operation of the second embodiment.

FIG. 8 shows a schematic electrical configuration of a fourth embodiment of the present invention. In the present embodiment, parts corresponding to those in the first to third embodiments are designated by the same reference numerals, and description thereof will be omitted. In the present embodiment, the comparison means 40 and the pulse counting circuit 4
1, the FV conversion circuit 43 is configured to include the input signal detection circuit 42 and the D / A conversion circuit 12. The pulse counting circuit 41 includes a selector 24 and an input signal detecting circuit 42.
An AND gate 44 responsive to the output from is included. In the comparison means 40, a calculation signal generation circuit 45 responsive to the outputs from the selector 24 and the input signal detection circuit 42,
And an arithmetic circuit 46 responsive to the outputs from the comparators 27, 28.

A counter 4 is provided in the input signal detection circuit 42.
7 and comparator 48 are included. Comparator 4
Reference numeral 8 compares the count value ni of the counter 47 with a preset setting value m, and derives a signal representing the comparison result.

FIG. 9 shows the operations of the comparing means 40, the pulse counting circuit 41 and the input signal detecting circuit 42 shown in FIG. The operation starts from step c1 and steps c2 to c8 are the same as the operations of the steps b2 to b8 in FIG. 5, respectively. Step c
At 9, the count value ni of the counter 47 in the input signal detection circuit 42 is detected. At step c10, the comparator 48 in the input signal detection circuit 42 makes the count value ni
And the set value m are compared. When ni is larger than m, operations similar to those in steps b10 to b12 in FIG. 5 are performed in steps c11 to c13. Count value n in step c10
When i is determined to be equal to or smaller than the set value m, it is determined in step c14 whether the count period t is equal to T or not. If they are equal, the counting period cannot be lengthened any further, and therefore the process proceeds to step c11. Step c
When the count period t is not equal to T in 14, the count period t is doubled in Step c15, and Step c16
The value of the multiple α is halved, and the process returns to step c9. The counter 47 in the input signal detection circuit 42 only needs to determine the presence or absence of an input signal when the set value m is zero, and can be replaced with a flip-flop or the like to simplify the circuit configuration. Further, instead of the counter 47, the count value from the input signal counter 16 may be compared.

FIG. 10 shows operation timings of the comparing means 40 and the pulse counting circuit 41 of FIG. From the count period setting circuit 25, three types of clock signals T, T / 2 and T / 4 are derived after the reset signal (A) rises. A clock signal as shown in (B) is selected by the selector 24, and is ANDed as a select signal.
It is applied to the latch 17 and the delay circuit 18 via the gate 44. During the period when the input signal of (D) is interrupted, the output from the input signal detection circuit 42 remains at the low level,
While the clock signal is not given to the latch 17 and the delay circuit 18, a 2-bit output (G3) is derived from the arithmetic signal generation circuit 45. The outputs (g1) and (g2) from the comparators 27 and 28 are the comparator 2 of FIG.
Outputs (G1) and (G2) given from the arithmetic circuit 42 to the selector 24 and the multiplication circuit 26 are derived from the arithmetic signal generation circuit 45, though they are derived in the same manner as (G1) and (G2) from 7 and 28. After the output (G3) is derived, α
Is increased and the count period t is changed to be longer.

FIG. 11 shows a partial structure of a fifth embodiment of the present invention. The other parts of this embodiment are the same as those of the embodiment shown in FIG. The output of the initial state setting circuit 50 is set to O
An R gate (AND gate is also possible, but in that case, the logics of (g1) and (g2) are reversed) 51 and 52, and the outputs (g1) and (g2) of the comparators 27 and 28 are set to the initial state. It is forcibly converted to a constant value and given to the arithmetic circuit 46.

FIG. 12 shows a partial structure of the sixth embodiment of the present invention. The configuration of other parts is similar to that of FIG.
The comparator 55 compares the count value of the input signal counter 16 with a preset value b set in advance, and executes step c7 of FIG.
To start the operation. As outputs (g1) and (g2), analog comparators 31 and 3 as shown in FIG.
The output from 2 can also be used.

As a seventh embodiment of the present invention, FIG.
It is also possible to perform the operation as shown in FIG. 13 by using the configuration of No. 2. Steps d1 to d9 in FIG. 13 are the same as the steps b1 to b9 in FIG. 5, respectively. In step d10, it is determined whether the count value n of the input signal counter 16 is smaller than the set value b. When it is determined that it is not smaller, the count period t is halved in step d11, the multiple α is doubled in step d2, and the process returns to step d9.
When it is determined in step d10 that n is smaller than b, the same operations as steps d13 to d15 and steps b10 to b12 in FIG. 5 are performed.

FIG. 14 shows the electrical construction of the eighth embodiment of the present invention. The pulse counting circuit 100 includes a shift register 101 and a selector 102, and constitutes an FV conversion circuit 103 together with the D / A conversion circuit 12. In the pulse counting circuit 100, the first edge detection circuit 1
04, 114, 124, counting period timer counter 1
05, 115, 125, 135, input signal counter 10
6, 116, 126, 136, latches 107, 117,
127, 137, delay circuits 108, 118, 128, 1
38, and AND gates 113, 123, 133.

FIG. 15 shows the operation of the configuration of FIG. Control is started from step e1, and in step e2, the count period timer counter 105 starts counting. In step e3, it is determined whether the time T / k has elapsed. In this embodiment, the number of combinations k = 4
The description will be made assuming the case. After the time T / k has elapsed, the count period timer counter 1 at step e4
Start counting fifteen. At step e5, 2T /
It is determined whether or not the time of k has elapsed. The same procedure is repeated thereafter, and the counting of the k-th, that is, the fourth counting period timer counter 135 is started in step e6, and it is determined in step e7 whether kT / k time, that is, T time has elapsed. When T time has elapsed, in step e8,
Latches the count value of the input signal counter 106 of
Store in 7. In step e9, it is determined whether (k + 1) T / k time has elapsed. When that time elapses, the output (F) from the selector 102 is changed to the output from the latch 117 which latches the count value from the input signal counter 116 in step e10. Step e11 below
Up to k times, the output from the latch 107 is again derived, and the process returns to step e8.

FIG. 16 shows operation waveforms of the circuit of FIG. Each counting period timer counter 105, 115, 1
25, 135 outputs (B1), (B2), (B
3) and (B4) derive the timer signal that represents the count period of T by shifting for each divided period. The first edge of each timer signal is set to the first edge detection circuit 104, 11
AND gate 113, 123, 1
Counting period timer counters 115, 12
5, 135 are respectively reset, and counting is performed with the counting period shifted. Each count period timer counter 10
The outputs from 5, 115, 125, and 135 are given to the selector 102 via the shift register 101, and the count values Y1, Y2, Y3, and Y4 obtained by shifting the count period are selected by the selector 1
By switching at 02, the output (F) corresponds to the change of the input signal (D) and can respond in a period shorter than the counting period T.

FIG. 17 shows a partial structure of the ninth embodiment of the present invention. The configuration of the remaining part of this embodiment is shown in FIG.
Same as 4. In the averaging means 200, the adder circuits 201, 211, 221, 231 and the divider circuit 20 are included.
2, 212, 222, and 232 are provided, respectively. The 5T / 4 progress detection circuit 240 after reset release in response to the output from the shift register 101 is also added between the selector 102 and the circuit.

FIG. 18 shows the operation of this embodiment. The operation starts from step f1 and the count period timer counter 105 starts counting in step f2. When it is determined in step f3 that T / k time has elapsed, the counting period timer counter 1 in step f4
Start counting fifteen. 2T / k at step f5
It is determined whether or not the time has elapsed, and the count of the next count period timer counter is started. Similarly, the count of the next count period timer counter is sequentially started every T / k time, and the count of the last k-th count period timer counter 135 is started in step f6. In step f7, it is determined whether or not the time of (k + 1) T / k has elapsed. When the time has passed, the process proceeds to step f8, and the output of the input signal counter 106 is stored in the latch 107.
In step f9, the 5T / 4 progress detection circuit 240 is activated after reset release, and in step f10, the selector 102 is activated.
To output the output Y2 from the latch 117.
In step f11, it is determined whether (k + 2) T / k has elapsed. When it is determined that the time has passed, step f1
At 2, the selector 102 outputs the output Y3 from the latch 127. Thereafter, the selector 102 is switched at every T / k time, and at step f13, steps f7 to f
After substituting k + k for the parameters k up to 11, the process returns to step f7.

FIG. 19 shows the operation of the embodiment of FIG. Selector 102 from 5T / 4 hours after reset
(F) is derived, and an averaged output is obtained by the adder circuit and the divider circuit. Each addition circuit 201,211,2
21, 231 are two latches 137, 107; 107,
117; 117, 127; 127, 137 outputs are added, and subsequent division circuits 202, 212, 222, 2 are added.
Although the average value of 1/2 is calculated in 32, it is possible to average a larger number.

In each of the above-described embodiments, a representative example has been described for the number of comparators, the count period and the set values of multiples, the number of combinations, and the number of k, but other values may be used. It is possible.

[0040]

As described above, according to the present invention, since the count value of the counter and the stored value of the latch are compared and the value which is not smaller is derived as the pulse count value, when the input signal suddenly increases. The followability can be improved and the responsiveness can be improved.

Further, according to the present invention, since the period for counting by the counter can be shortened when the number of pulses of the input signal rapidly increases, the responsiveness can be improved.

According to the present invention, the increase in the pulse number of the input signal is compared with the level of the converted analog signal of the signal representing the output pulse count value, and the response can be improved when the pulse number is increased. it can. This can improve the response when the frequency of the input signal sharply increases in the FV conversion circuit or the like.

Further, according to the present invention, when the input pulse signal becomes small, the input signal is not detected in a short period, the counting result up to that point is continued to the next counting as it is, and the counting period is increased. The response on the low frequency side can be improved.

Further, according to the present invention, even in the case where the counter counts only up to the count value less than the predetermined reference value in the short count period, the responsiveness to the one in which the count period is increased and the frequency is lowered is obtained. Can be improved.

Further, according to the present invention, since the selection value for dividing the counting period is maximum in the initial state, the pulse count value is derived in a short time even if a large number of pulses are suddenly input, and the response is improved. Can be made.

According to the present invention, when the count value becomes equal to or larger than the predetermined reference value during counting of pulses, the selection value selected by the selector is made larger than the selection value selected at that time, and the input signal It is possible to improve the responsiveness when the number of pulses is increased.

Further, according to the present invention, since the selector selects the smallest integer in the initial state, it is possible to count with sufficient accuracy even if a small number of pulse signals having a low frequency are input at the beginning.

Further, according to the present invention, since pulse signals whose generation state is fluctuating can be accurately counted in a short period of time, the responsiveness can be improved.

Further, according to the present invention, even if the input signal has noise or missing pulse, a signal representing a pulse count value with few abnormalities is derived from the averaging means to improve the responsiveness to the true input signal. be able to.

Furthermore, according to the present invention, it is possible to obtain an FV conversion circuit having an improved response to an input signal with a simple structure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

FIG. 3 is a time chart illustrating an operation of the embodiment of FIG. 1;

FIG. 4 is a block diagram showing a schematic electrical configuration of a second embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of the embodiment of FIG. 4;

FIG. 6 is a time chart showing the operation of the embodiment of FIG.

FIG. 7 is a block diagram showing a schematic electrical configuration of a third embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic electrical configuration of a fourth embodiment of the present invention.

9 is a flowchart showing the operation of the embodiment of FIG.

FIG. 10 is a time chart illustrating the operation of the embodiment in FIG. 8;

FIG. 11 is a block diagram showing a partial electrical configuration of a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a partial electrical configuration of a sixth embodiment of the present invention.

13 is a flowchart showing the operation of the embodiment of FIG.

FIG. 14 is a block diagram showing an electrical configuration of an eighth embodiment of the present invention.

FIG. 15 is a flowchart showing the operation of the embodiment of FIG.

16 is a time chart showing the operation of the embodiment of FIG.

FIG. 17 is a block diagram showing a partial electrical configuration of a ninth embodiment of the present invention.

FIG. 18 is a flowchart showing the operation of the embodiment of FIG.

FIG. 19 is a time chart showing the operation of the embodiment of FIG.

FIG. 20 is a block diagram showing an electrical configuration of a prior art.

FIG. 21 is a time chart showing the operation of the prior art of FIG. 20.

[Explanation of symbols]

22, 30, 40 Comparison means 11, 21, 41, 100 Pulse counting circuit 12 D / A conversion circuit 13, 23, 33, 43, 103 FV conversion circuit 14 Waveform shaping circuit 15 Count period setting timer 16, 106, 116 , 126, 136 Input signal counter 17, 107, 117, 127, 137 Latch 19, 27, 28, 31, 32, 48, 55 Comparator 24, 102 Selector 25 Count period setting circuit 42 Input signal detection circuit 45 Calculation signal generation Circuit 46 Calculation circuit 50 Initial state setting circuit 101 Shift register 104, 114, 124 First edge detection circuit 105, 115, 125, 135 Count period timer counter 200 Average calculation means 201, 211, 221, 231 Adder circuit 202, 212, 222,232 division A road

Claims (11)

[Claims] 1. A pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, the timer having a counting period set and deriving a clock signal for each counting period, The counter value that is cleared by the clock signal from the timer, counts the input pulse signal, and derives the signal that represents the count value, and the counter value immediately before being cleared by the clock signal from the timer are stored. And a comparator that is responsive to the signal from the counter and the latch to compare the count value and the stored value and to derive the signal that represents the lesser value as the pulse count value. Characteristic pulse counting circuit. 2. A pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, comprising a timer having a counting period set and deriving a clock signal for each counting period, A selector that responds to the clock signal from the timer and derives a select signal for each selection period of a value obtained by dividing a counting period corresponding to the cycle of the clock signal by one selected value selected from a plurality of predetermined integers; A counter that is cleared by the select signal from the selector, counts the pulse signals that are input, and derives a signal representing the count value; and, in response to the signal from the counter, multiplies the count value of the counter by the selection value, In response to the signal from the multiplication means for deriving a signal representing the multiplication value and the multiplication means immediately before the counter is cleared by the select signal from the selector, The latch that stores the multiplication value of, and derives the signal that represents the stored value as the pulse count value, and the pulse count value that is responsive to the signal from the latch, compares the pulse count value with a plurality of preset reference values. A pulse counting circuit, comprising: a comparator that controls the selector according to the pulse counting circuit. 3. The comparing means converts a digital signal representing the pulse count value from the latch into an analog signal, compares it with a reference level corresponding to a plurality of reference values, and selects the selection value according to the comparison result. 3. The pulse counting circuit according to claim 2, wherein the selector is controlled so as to carry out. 4. An input detection means for detecting the presence or absence of an input pulse signal is provided, and the comparison means responds to an output from the input detection means and outputs a pulse until the counter is cleared by a select signal from a selector. 4. The pulse counting circuit according to claim 2, wherein when the signal is not input, the selector is controlled so as to select a value smaller than the value currently selected as the selected value without clearing the counter. . 5. The comparing means responds to a signal from a counter, and when a count value until the counter is cleared by a select signal from a selector is equal to or less than a predetermined reference value, the selection is performed without clearing the counter. 4. The pulse counting circuit according to claim 2, wherein the selector is controlled so as to select a value smaller than a value selected at that time. 6. The pulse counting circuit according to claim 2, wherein the selector selects the largest integer in the initial state. 7. The comparing means is responsive to a signal from a counter, and when a count value until the counter is cleared by a select signal from a selector is equal to or greater than a predetermined reference value, the comparison value is set as the selection value at that time. 4. The pulse counting circuit according to claim 2, wherein the selector is controlled so as to select a value larger than the selected value. 8. The pulse counting circuit according to claim 7, wherein the selector selects a minimum integer value in an initial state. 9. A pulse counting circuit for counting the number of input pulse signals and deriving a signal representing a pulse count value, wherein the pulse counting circuit has a plurality of counting periods and a clock signal is derived for each counting period. Each timer is a timer that derives a clock signal at each time point divided by a division cycle corresponding to a value obtained by dividing the counting period by the number of timers, and a timer that is provided for each timer and that uses the clock signal from each timer. The number of pulse signals that are cleared and input is counted, a signal that represents the count value is derived, and in response to the counters provided by the plurality of timers and the signals from the timers and the counters, the counting is performed at each point of time in each of the division cycles. A pulse counting circuit, comprising: latching means for storing a count value from a counter whose numerical value is cleared and deriving a signal representing the stored value as a pulse count value. 10. The number of input pulse signals is counted,
A pulse counting circuit for deriving a signal representing a pulse count value, comprising a plurality of timers each having a counting period set and deriving a clock signal for each counting period, each timer dividing the counting period by its number. A timer that derives a clock signal at each time point that is shifted by a division cycle corresponding to the value, and a timer that is provided for each timer and that is cleared by the clock signal from each timer and that is input, is counted and the count value is displayed. A signal is derived, and the count value of the counter, which is provided for each of the plurality of timers and each timer, and immediately before being cleared by the clock signal from each timer, is stored,
Responsive to the signals from each latch and each timer that derives the signal representing the stored value, while switching the combination for each division cycle, average the count values from the predetermined number of latches, and calculate the average value. A pulse counting circuit comprising: an averaging means for deriving a signal represented as a pulse count value. 11. A pulse counting circuit according to any one of claims 1 to 10, and D / A converting means for responding to a signal from the pulse counting circuit and converting the pulse counting value into an analog value. Characteristic FV conversion circuit.