GB1583855A - Analogue-to-digital converters - Google Patents

Description

(54) ANALOGUE-TO-DIGITAL CONVERTERS (71) We, SMITHS INDUSTRIES LIMITED, a British Company of Cricklewood, London NW2 6JN, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it iS to be performed, to be particularly described in and by the following statement: This invention relates to analogue-todigital converters.

An analogue-to-digital converter may be used, for example, in controlling a digital speedometer in accordance with the frequency of an oscillatory signal representative of the speed of a craft. It has been found that in these circumstances there may be an undesirable flicker of the digital display between successive digital representations.

The flickering often arises because, for example, the frequency of the oscillatory signals may not be truly constant even when the speed of the craft is apparently constant, but instead may vary rapidly within a very limited range about a mean value. If this mean value corresponds to a threshold value at which the digital display changes from one digital representation to an adjacent digital representation, the frequency of the oscillatory signal repeatedly crosses the threshold value, thereby causing repeated changes in the displayed digit or digits.

It is an object of this invention to provide an analogue-to-digital converter which may be used, for example, to control a digital speedometer without such flickering.

According to one aspect of the present invention there is provided an analogue-todigital converter for providing a digital signal in accordance with the frequency of occurrence of a characteristic of an input signal comprises means to generate a train of timing signals, means to count the occurrences of the said characteristics for the duration of each timing signal, and means to detect proximity in time of the' termination of a said timing signal and an occurrence of the said characteristic and thereupon to cause the said generating means to effect change in the duration of at least the next timing signal provided by the generating means. In the case of a digital display, the risk of display flicker only arises when the characteristic being counted is at or close to coincidence with the end of a timing signal.

Thus a change in the duration of the succeeding timing signal eliminates the possibility of flicker by removing the coincidence.

When the frequency of the input signal has changed sufficiently, the duration of subsequent timing signals can be restored to the original value until the characteristic being counted and the end of a timing signal are again in proximity.

The said input signal may be an oscillatory input signal.

The said characteristic of the input signal may be a voltage characteristic.

The said detection means may be arranged to detect proximity of the termination of a said timing signal and an occurrence of the counted characteristic by detecting a voltage excursion of the input signal at or before the termination of a said timing signal if the frequency of the input signal is rising, and at or after the termination of a said timing signal if the frequency is falling.

The input signal may be a pulse-waveform signal.

The said detection means may be arranged to cause the said generating means to increase the duration of a timing signal when proximity of the termination of a previous timing signal and an occurrence of the counted characteristic is detected as the frequency of the input signal rises, and to decrease the duration of a timing signal when such proximity is detected as the frequency falls.

The duration of each timing signal may be controlled by selectively delaying a signal having a constant duration.

The said input signal may have a second characteristic which occurs alternately with the first-mentioned said characteristic, and the said detection means is arranged to detect proximity of the termination of a timing signal and an occurrence of the said second characteristic and thereupon cause the said generating means to effect change in the duration of at least the next timing signal in a sense opposite to that of the firstmentioned change therein.

The said characteristics of the input signal may be voltage changes of opposite senses to one another.

The first-mentioned said characteristic may be a positive-going voltage change and the second characteristic may be a negative-going voltage change.

According to another aspect of the present invention there is provided speed measuring apparatus including an analogue-to-digital converter in accordance with the said one aspect of the present invention.

The speed measuring apparatus may be a speedometer or tachometer.

The speed measuring apparatus may include means to derive the said input signal.

An analogue-to-digital converter in accordance with this invention, for operating a vehicle speedometer or tachometer, will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic circuit diagram of the converter; Figure 2 is a waveform diagram of signals in the converter; and Figure 3 is a circuit diagram of a variable-delay circuit forming part of the converter.

The analogue-to-digital converter to be described provides a digital signal in accordance with the pulse repetition frequency of a pulse-waveform input signal. This signal may itself be generated in such a manner that its repetition frequency is dependent upon, for example, the speed of rotation of a vehide's roadwheels or of an engine crankshaft. Under these circumstances the converter would provide a signal for driving a digital speedometer or tachometer respectively.

Referring to Figure 1, the input signal is supplied to a pulse shaper 11 which removes noise and other spurious signals and improves the rise and fall times of the input pulses. The pulses from the pulse shaper 11 are supplied to one input of a two-input NAND-gate 12, the output of which is coupled via an inverter 13 to the input of a counter 14. The output of the counter 14 is connected to a latch circuit 15 which in turn supplies the output signal of the analogueto-digital converter.

The counter 14 derives the required digital signal by cyclically counting the pulses which are supplied to it for a predetermined interval of time within each cycle. The pulses are supplied to the counter 14 via the NAND-gate 12 under the control of a bistable circuit 16, the Q output of which is coupled to an input of the NAND-gate 12.

The Q output of the bistable circuit 16 is coupled to one input of a two-input NAND-gate 17, the other input of which is connected to the output of the pulse shape 11. The output of the NAND-gate 17 is connected to the clock input of the bistable circuit 16.

The 5 output of the bistable circuit 16 is also connected to the input of a monostable circuit 18 which is coupled to a second monostable circuit 19 via an inverter 20 and a variable-delay circuit 21. The output of the monostable circuit 19 is coupled to the reset input of the bistable circuit 16 and to one input of a two-input NAND-gate 22, the other input of which is connected to the output of the NAND-gate 12.

The output of the NAND-gate 22 is connected to a monostable circuit 23, which supplies a strobe signal to the latch circuit 15 and triggers another monostable circuit 24 to supply a reset signal to the counter 14.

The duration of the predetermined interval in which the counter 14 counts input pulses is determined by the duration of the quasi-stable state of the monostable circuit 18 and by the delay introduced by the variable-delay circuit 21.

This delay is controlled by a bistable circuit 25, the Q output of which is coupled to the variable-delay circuit 21. The set and reset inputs of the bistable circuit 25 are coupled to the outputs of respective twoinput AND-gates 26 and 27. One input of each of these AND-gates 26 and 27 is coupled to the output of another two-input AND-gate 28, which has one of its inputs coupled directly to the output of the inverter 20 and the other coupled to the same point via a delay circuit 29.

The second input of the AND-gate 26 receives signals from the output of a twoinput NOR-gate 30, the inputs of which are coupled, respectively, to the output of the pulse shaper 11, and to the Q output of the bistable circuit 16. Another two-input NOR-gate 31 supplies signals to the second input of the AND-gate 27, and has its inputs connected, respectively, to the output of the pulse shaper 11 via an inverter 32, and to the Q output of the bistable circuit 16.

As mentioned earlier, the input pulses are passed by the NAND-gate 12 to the counter 14 under the control of the bistable circuit 16, the NAND-gate 12 being open when the Q output of the bistable circuit 16 is at high potentiaSsee Figure 2 (a), (d) and (f).

After each counting cycle, the U output of the bistable circuit 16 is at high potential, so the NAND-gate 17 is open. Thus, provided no signal is present on the reset input of the bistable circuit 16, the next negative-going edge of the input signal produces a positive-going signal at the clock input of the bistable circuit 16, as shown in Figure 2 (c), thereby setting the bistable circuit 16, opening the NAND-gate 12 and initiating a counting cycle and the counting interval within that cycle. The Q output of the bistable circuit 16 goes to low potential (Figure 2 (e) ), thus closing the NAND-gate 17 and blocking the passage of any more pulses to the clock input.

The change of state of the Q output of the bistable circuit 16 also triggers the monostable circuit 18 which is arranged to produce a pulse 420.74 milliseconds in duration, shown, after inversion by the inverter 20, in Figure 2 (g). The termination of this pulse is delayed in the variable-delay circuit 21 by either 0.2 or 3.4 milliseconds, depending upon the signal supplied by the bistable circuit 25, so the monostable circuit 19 is triggered either 420.94 or 424.14 milliseconds respectively after the commencement of the pulse generated by the monostable circuit 18. These pulse durations define the counting interval and are suitable for the use of the converter in a digital speedometer with the input signal being generated by a 12-pole gearbox-mounted electromagnetic generator which produces a signal with a pulse repetition frequency of 142 Hz at 60 m.p.h. It should be noted that, at this frequency, 60 pulses are generated in a period of 422.54 milliseconds (the mean of 420.94 and 424.14 milliseconds), that is, one pulse for each mile-per-hour.

The monostable circuit 19, upon being triggered by the delayed trailing edge of the pulse from the monostable circuit 18, produces a pulse 5 milliseconds long, shown in Figure 2 (i). This pulse is applied to the reset input of the bistable circuit 16, resetting it and thereby terminating the counting of the input pulses. The closing of the NAND-gate lakes its output go to high potential (Figure 2 (f)), thus opening the NANDgate 22 to allow the reset pulse from the monostable circuit 19 to trigger the monostable circuit 23.

The output pulse from the monostable circuit 23 enables the latch circuit 15, so that the count in the counter 14 is stored, and also triggers the monostable circuit 24 to reset the counter 14 to zero. The relevant pulses are shown in Figure 2 (j) and (k).

After the end of the 5-millisecond reset pulse, another counting cycle commences upon the occurrence of the next negativegoing edge of the input signal. While the counter 14 is counting, the latch circuit 15 provides a steady output signal to drive a display device associated with the converter.

The duration of the delay provided by the variable-delay circuit 21 is changed whenever necessary to avoid coincidence between the end of a counting interval and a positive-going edge of the input signal. If such coincidence were not inhibited, it would be possible for the display to flicker between two successive numbers when the input signal had a 'steady' pulse repetition frequency. This is because such a 'steady' signal representing, for example, the speed of a vehicle in fact varies in frequency over a narrow range centred on the apparent steady frequency. Thus the time of occurrence of a positive-going edge of the input signal at the end of a counting interval could repeatedly. change from being just before the end of the interval (when it would be counted) to being just after the end of the interval (when it would not be counted) and back again. This would cause the count in the counter 14 to repeatedly rise and fall by one, so producing the flickering of the display.

In a converter according to this invention, such rapid variations in the count, and the distracting flickering of the display that they cause, are avoided by detecting proximity of a positive-going edge of the input signal and the end of the counting interval, and then varying the duration of the next interval slightly to reduce the proximity. The waveforms in Figure 2 illustrate the operation of the circuit of Figure 1 for the situation in which the repetition frequency of the input signal (Figure 2 (a) ) is steadily falling.

Four successive counting cycles, labelled I to IV, are shown, with four particular instants labelled A to D, at which certain circuit operations occur at the end of each cycle, being indicated by broken lines.

The trailing edge of the pulse generated by the monostable circuit 18 is delayed for 3.5 milliseconds by the delay circuit 9. The delayed signal, shown in Figure 2 (1), is then gated by the AND-gate 28 with the pulse from the monostable circuit 18 to produce a pulse having a duration of 3.5 milliseconds and starting at time A. This pulse, shown in Figure 2 (m), is Supplied to the AND-gates 26 and 27 which control the state of the bistable circuit 25 and thus the duration of the delay provided by the variable-delay circuit 21. Since the AND-gates 26 and 27 can each only provide an output to change the state of the bistable circuit 25 when both their inputs are at high potential, such a change of state can only occur during the 3.5-millisecond pulse from the AND-gate 28. Thus, this pulse defines a period at the end of each counting cycle in which proximity of the end of the counting interval and a positive-going edge of the input signal can be detected and acted upon.

The proximity is sensed by the NOR-gate 30 which supplies an output signal whenever both the input signal (Figure z (a)) and the Q output (Figure 2 (d) of the bistable circuit 16 are at low potential. In the counting cycle I of Figure 2, this situation never occurs, so there is no output from the NOR-gate 30--see Figure 2 (n). The bistable circuit 25 has previously been reseiby a signal from the AND-gate 27, so its Q output is at high potential, as shown in Figure 2 (r). This causes the variable-delay circuit 21 to provide its longer delay, shown in Figure 2 doh).

At the beginning of counting cycle II, the NOR-gate 30 does produce an output pulse, but since this does not coincide with the 3.5-millisecond pulse from the AND-gate 28, no pulse is supplied by the AND-gate 26see Figure 2 (p).

However, by the end of counting cycle II, the repetition frequency of the input signal has fallen to such an extent that a positivegoing edge is occurring just after time C, which marks the end of the counting interval within counting cycle lI-see Figure 2 (d).

Thus the NOR-gate 30 generates a pulse starting at time C and ending as the input signal goes to high potential. This pulse occurs within the 3.5-millisecond pulse from the AND-gate 28, so the AND-gate 26 generates a pulse (Figure 21p) ) which sets the bistable circuit 25. The Q output of the bist- able circuit 25 goes to low potential, so the variable-delay circuit 21 now generates its shorter delay, as shown in the counting cycle III in Figure 2.

It can be seen that the counting interval now terminates 3.2 milliseconds earlier at time B. Thus, even if the input signal's repetition frequency were to remain at such a value that a positive-going edge continued to occur just after time C, the proximity of that edge and the end of the counting interval has been eliminated. Consequently, the number of pulses counted in each interval remains at a single, unambiguous value, thus precluding the possibility of flickering of the display between successive numbers.

In the situation where the input signal is steadily falling in repetition frequency, it is necessary for the delay introduced by the variable-delay circuit 21 to revert to its longer value before another positive-going edge of the input signal approaches coincidence with the end of a timing interval, so that the delay can thereupon be decreased again.

To this end, the degree of proximity of a negative-going edge of the input signal and the end of a shorter timing interval is monitored. The input signal is inverted by the inverter 32 (see Figure 2 (b)) and supplied to the NOR-gate 31 which provides an output when both the inverted input signal and the Q output of the bistable circuit 16 are at low potential--see Figure 2 (o). This signal is gated with that from the AND-gate 28, by the AND-gate 27, to provide the reset pulse for the bistable circuit 25, as shown in Figure 2 (q).

Thus, at the end of counting cycle I, the counting interval of which is of the longer duration, the NOR-gate 31 produces signals during the 3.5-millisecond pulse from the AND-gate 28, and these are passed to the bistable circuit 25 to maintain it in its reset condition.

At the end of counting cycle III, a negative-going edge of the input signal has not quite reached time A, so there is no signal from the NOR-gate 31. However, at the end of counting cycle IV, a negativegoing edge occurs between time A and time B. Since the Q output of the bistable circuit 16 remains at low potential at least until time B, the NOR-gate 31 produces an output signal at the beginning of the 3.5millisecond pulse supphed by the AND-gate 28, so the bistable circuit 25 is reset. The pulse from the monostable circuit 18 is immediately subject to the longer delay of the variable-delay circuit 21, as shown in Figure 2. In the particular circumstances illustrated in Figure 2, another pulse is produced by the NOR-gate 30 between time C and time See Figure 2 (thus setting the bistable circuit 25 again. However, as the input signal continues to decrease in repetition frequency, the negative-going edge of the input signal will eventually occur after time D, whereupon the bistable circuit 25 will remain in its reset condition ready for the detection of impending coincidence between another positive-going edge and the end of a counting interval.

When the input signal is rising in frequency, a similar sequence of operation occurs, except that the positive-going edges are detected as they sweep across time B towards time A, by the NOR-gate 31, and the negative-going edges are detected as they sweep across time D towards time C, by the NOR-gate 30. Thus the counting interval is lengthened when proximity of its termination with a positive-going edge is detected, and shortened again in response to the succeeding negative-going edge.

The variable-delay circuit 21 is shown in detail in Figure 3. The signal from the inverter 20 is applied to to both inputs of a twoinput NAND-gate 41 (which thus acts as an inverter), and also to the anode of a diode 42. The cathode of the diode 42 is coupled by a resistor 43 to an earth line 44, and is also connected to one electrode 45a of a capacitor 45. The other electrode 45b of the capacitor 45 is coupled to the earth line 44 by a resistor 46 and to one input of a twoinput NOR-gate 47. The resistor 46 is shunted by a resistor 48, a diode 49 and a switch 50 connected in series. The switch 50 represents the Q output stage of the bistable circuit 25.

The output of the NAND-gate 41 is coupled to the earth line 44 by a capacitor 51 and is also connected to the second input of the NOR-gate 47. The output of the NOR gate 47 is coupled to the monostable circuit 19 via a two-input NAND-gate 52 coupled to act as an inverter.

While the output of the inverter 20 is at high potential, the output of the NANDgate 41 is at low potential. Any charge on the electrode 45b of the capacitor 45 will flow to the earth line 44 via the resistor 46, so both inputs of the NOR-gate 47 are at low potential. Consequently its output will be at high potential, and the output from the NAND-gate 52 will be at low potential. The electrode 45a of the capacitor 45 is fully charged from the input via the diode 42.

When the output from the inverter 20 goes to low potential (at the start of a counting interval), the output of the NAND-gate 41 goes to high potential, with a slight increase in rise-time owing to the capacitor 51. Thus one output of the NOR-gate 47 goes to high potential, so its output goes to low potential and the output from the variable-delay circuit 21 goes to high potential. At the same time, the capacitor 45 supplies a negative-going pulse to the other input of the NOR-gate 47 (since the voltage across a capacitor cannot change instantaneously), and the electrode 45b of the capacitor 45 then discharges via the resistor 46.

At the end of the pulse from the inverter 20, the output of the NAND-gate 41 goes to low potential, but with a slight delay because of the capacitor 51. Meanwhile, the positive-going pulse from the input is applied by the capacitor 45 to the NOR-gate 47, thus maintaining its output at low potential and the output of the NAND-gate 52 at high potential. The capacitor 45 then recharges via the resistor 46 (and via the resistor 48 if the switch 50 is closed) so that eventually the associated input of the NOR-gate 47 goes to low potential as the voltage on the electrode 45b falls. Thereupon the output of the NOR-gate 47 goes to high potential and the output of the NAND-gate 52 goes to low potential.

The duration of the delay provided as the capacitor 45 re-charges depends on whether the switch 50 is open or closed, and also on the values of the resistors 46 and 48. For the speedometer application described above, and with a capacitor 45 of 0.01 microfarads, the resistor 46 has a value of 680 kilohms and the resistor 48 a value of 10 kilohms.

When the switch 50 is open (which corres onds to the Q output of the bistable circuit 5 being at high potential), the capacitor 45 can only re-charge via the resistor 46, and the delay is then 3.4 milliseconds. Hoover, if the switch 50 is closed (that is, the Q output is at low potential), the capacitor 45 can also re-charge via the resistor 48, and the delay drops in duration to 0.2 milliseconds.

A similar circuit to that shown in Figure 3 may be used for the delay circuit 29, but without the resistor 48 and the diode 49, since the delay circuit 29 is not required to provide a variable delay.

Although the above description has referred to a digital display, the converter may equally well be used to operate a display comprising a series of display devices arranged in a linear array (straight or otherwise), the magnitude of the parameters to be displayed being indicated by the number of display devices which are energised. Such a display is operable by a digital control signal even though it provides a quasi-analogue display.

WHAT WE CLAIM IS: 1. An analogue-to-digital converter for providing a digital signal in accordance with the frequency of occurrence of a characteristic of an input signal comprises means to generate a train of timing signals, means to count the occurrences of the said characteristics for the duration of each timing signal, and means to detect proximity in time of the termination of a said timing signal and an occurrence of the said characteristic and thereupon to cause the said generating means to effect change in the duration of at least the next timing signal provided by the generating means.

2. An analogue-to-digital converter according to Claim 1, wherein the said input signal is an oscillatory input signal.

3. An analogue-to-digital converter according to Claim 1 or Claim 2, wherein the said characteristic of the input signal is a voltage characteristic.

4. An analogue-to-digital converter according to Claim 3, wherein the said detection means is arranged to detect proximity of the termination of a said timing signal and an occurrence of the counted characteristic by detecting a voltage excursion of the input signal at or before the termination of a said timing signal if the frequency of the input signal is rising, and at or after the termination of a said timing signal if the frequency is falling.

5. An analogue-to-digital converter according to any one of the preceding claims, wherein the input signal is a pulsewaveform signal.

6. An analogue-to-digital converter according to any one of the preceding claims, wherein the said detection means is arranged to cause the said generating means to increase the duration of a timing signal when proximity of the termination of a previous timing signal and an occurrence of the counted characteristic is detected as the frequency of the input signal rises, and to decrease the duration of a timing signal when such proximity is detected as the frequency falls.

7. An analogueto-digital converter

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (17)

**WARNING** start of CLMS field may overlap end of DESC **. gate 47 is coupled to the monostable circuit 19 via a two-input NAND-gate 52 coupled to act as an inverter. While the output of the inverter 20 is at high potential, the output of the NANDgate 41 is at low potential. Any charge on the electrode 45b of the capacitor 45 will flow to the earth line 44 via the resistor 46, so both inputs of the NOR-gate 47 are at low potential. Consequently its output will be at high potential, and the output from the NAND-gate 52 will be at low potential. The electrode 45a of the capacitor 45 is fully charged from the input via the diode 42. When the output from the inverter 20 goes to low potential (at the start of a counting interval), the output of the NAND-gate 41 goes to high potential, with a slight increase in rise-time owing to the capacitor 51. Thus one output of the NOR-gate 47 goes to high potential, so its output goes to low potential and the output from the variable-delay circuit 21 goes to high potential. At the same time, the capacitor 45 supplies a negative-going pulse to the other input of the NOR-gate 47 (since the voltage across a capacitor cannot change instantaneously), and the electrode 45b of the capacitor 45 then discharges via the resistor 46. At the end of the pulse from the inverter 20, the output of the NAND-gate 41 goes to low potential, but with a slight delay because of the capacitor 51. Meanwhile, the positive-going pulse from the input is applied by the capacitor 45 to the NOR-gate 47, thus maintaining its output at low potential and the output of the NAND-gate 52 at high potential. The capacitor 45 then recharges via the resistor 46 (and via the resistor 48 if the switch 50 is closed) so that eventually the associated input of the NOR-gate 47 goes to low potential as the voltage on the electrode 45b falls. Thereupon the output of the NOR-gate 47 goes to high potential and the output of the NAND-gate 52 goes to low potential. The duration of the delay provided as the capacitor 45 re-charges depends on whether the switch 50 is open or closed, and also on the values of the resistors 46 and 48. For the speedometer application described above, and with a capacitor 45 of 0.01 microfarads, the resistor 46 has a value of 680 kilohms and the resistor 48 a value of 10 kilohms. When the switch 50 is open (which corres onds to the Q output of the bistable circuit 5 being at high potential), the capacitor 45 can only re-charge via the resistor 46, and the delay is then 3.4 milliseconds. Hoover, if the switch 50 is closed (that is, the Q output is at low potential), the capacitor 45 can also re-charge via the resistor 48, and the delay drops in duration to 0.2 milliseconds. A similar circuit to that shown in Figure 3 may be used for the delay circuit 29, but without the resistor 48 and the diode 49, since the delay circuit 29 is not required to provide a variable delay. Although the above description has referred to a digital display, the converter may equally well be used to operate a display comprising a series of display devices arranged in a linear array (straight or otherwise), the magnitude of the parameters to be displayed being indicated by the number of display devices which are energised. Such a display is operable by a digital control signal even though it provides a quasi-analogue display. WHAT WE CLAIM IS:

1. An analogue-to-digital converter for providing a digital signal in accordance with the frequency of occurrence of a characteristic of an input signal comprises means to generate a train of timing signals, means to count the occurrences of the said characteristics for the duration of each timing signal, and means to detect proximity in time of the termination of a said timing signal and an occurrence of the said characteristic and thereupon to cause the said generating means to effect change in the duration of at least the next timing signal provided by the generating means.

2. An analogue-to-digital converter according to Claim 1, wherein the said input signal is an oscillatory input signal.

3. An analogue-to-digital converter according to Claim 1 or Claim 2, wherein the said characteristic of the input signal is a voltage characteristic.

4. An analogue-to-digital converter according to Claim 3, wherein the said detection means is arranged to detect proximity of the termination of a said timing signal and an occurrence of the counted characteristic by detecting a voltage excursion of the input signal at or before the termination of a said timing signal if the frequency of the input signal is rising, and at or after the termination of a said timing signal if the frequency is falling.

5. An analogue-to-digital converter according to any one of the preceding claims, wherein the input signal is a pulsewaveform signal.

6. An analogue-to-digital converter according to any one of the preceding claims, wherein the said detection means is arranged to cause the said generating means to increase the duration of a timing signal when proximity of the termination of a previous timing signal and an occurrence of the counted characteristic is detected as the frequency of the input signal rises, and to decrease the duration of a timing signal when such proximity is detected as the frequency falls.

7. An analogueto-digital converter

according to any one of the preceding claims, wherein the duration of each timing signal is controlled by selectively delaying a signal having a constant duration.

8. An analogue-to-digital converter according to any one of the preceding claims, wherein the said input signal has a second characteristic which occurs alternately with the first-mentioned said characteristic, and the said detection means is arranged to detect proximity of the termination of a timing signal and an occurrence of the said second characteristic and thereupon cause the said generating means to effect change in the duration of at least the next timing signal in a sense opposite to that of the first-mentioned change therein.

9. An analogue-to-digital converter according to Claim 8, wherein the said characteristics of the input signal are voltage changes of opposite senses to one another.

10. An analogue-to-digital converter according to Claim 8 or Claim 9, wherein the first-mentioned said characteristic is a positive-going voltage change and the second characteristic is a negative-going voltage change.

11. An analogue-to-digital converter substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

12. An analogue-to-digital converter substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.

13. An analogue-to-digital converter substantially as hereinbefore described with reference to the accompanying drawings.

14. Speed measuring apparatus including an analogue-to-digital converter as claimed in any one of the preceding claims.

15. Speed measuring apparatus according to Claim 14, wherein the apparatus is a speedometer.

16. Speed measuring apparatus according to Claim 14, wherein the apparatus is a tachometer.

17. Speed measuring apparatus according to any one of Claims 14 to 16, including means to derive the said input signal.