JPH0917358A - Electron source substrate and its manufacture and image forming device - Google Patents

Electron source substrate and its manufacture and image forming device

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Publication number
JPH0917358A
JPH0917358A JP16217095A JP16217095A JPH0917358A JP H0917358 A JPH0917358 A JP H0917358A JP 16217095 A JP16217095 A JP 16217095A JP 16217095 A JP16217095 A JP 16217095A JP H0917358 A JPH0917358 A JP H0917358A
Authority
JP
Japan
Prior art keywords
electron
thin film
contact hole
wiring
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16217095A
Other languages
Japanese (ja)
Inventor
Kazuo Koyanagi
和夫 小▲柳▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP16217095A priority Critical patent/JPH0917358A/en
Publication of JPH0917358A publication Critical patent/JPH0917358A/en
Pending legal-status Critical Current

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  • Cold Cathode And The Manufacture (AREA)

Abstract

PURPOSE: To reduce characteristic dispersion of a surface conduction type electron emitting element by continuing a contact hole formed in a position separate from upper wiring with the element in the direction for crossing lower wiring. CONSTITUTION: X directional wiring (lower wiring) 72 is formed on an insulating substrate 11 cleaned by a detergent, pure water and an organic solvent by a conductive material such as Cr and Au by a vacuum film forming process or the like. Next, an inter-layer insulating layer 111 of an insulating film is formed by a vacuum evaporation method or the like. Next, a photoresist pattern is formed so that respective element parts continue with each other in the direction for crossing the lower wiring 7, and the inter-layer insulating layer 111 is etched by using this as a mask, and a contact hole is formed. Next, element electrodes 76 and 77 are formed by a vacuum evaporation method or the like, and a connecting part 114 in which the contact hole is embedded is formed by a printing method or the like, and Y directional wiring (upper wiring) 73 is formed by a vacuum film forming process or the like, and after an organic metallic complex or the like is accumulated, an electron emitting thin film having a thin film containing an electron emitting part is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子源およびその応用
である表示装置等の画像形成装置にかかわり、特に微粒
子を電子放出部に用いた表面伝導型放出素子を多数個備
える電子源基板、電子源基板の製造方法、およびその応
用である表示装置等の画像形成装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron source and an image forming apparatus such as a display device, which is an application of the electron source, and more particularly, to an electron source substrate provided with a large number of surface conduction electron-emitting devices using fine particles as electron-emitting portions, The present invention relates to a method of manufacturing an electron source substrate and an image forming apparatus such as a display device that is an application thereof.

【0002】[0002]

【従来の技術】従来、電子放出素子として熱電子源と冷
陰極電子源の2種類が知られている。冷陰極電子源には
電界放出型(以下、FE型と略す)、金属/絶縁層/金
属型(以下、MIM型と略す)や表面伝導型電子放出素
子(以下、SCEと略す)等がある。
2. Description of the Related Art Conventionally, two types of electron emitting devices, a thermionic electron source and a cold cathode electron source, are known. Cold cathode electron sources include field emission type (hereinafter abbreviated as FE type), metal / insulating layer / metal type (hereinafter abbreviated as MIM type), surface conduction type electron emission devices (hereinafter abbreviated as SCE), and the like. .

【0003】FE型の例としてはW.P.Dyke &
W.W.Dolan、”Field emissio
n”、Advance in Electron Ph
ysics、8、89(1956)あるいはC.A.S
pindt、”PHYSICAL Propertie
s of thin−film field emis
sion cathodes with molybd
enium cones”、J.Appl.Phy
s.、47、5248(1976)等が知られている。
MIM型の例としてはC.A.Mead、”The t
unnel−emission amplifier、
J.Appl.Phys.、32、646(1961)
等が知られている。SCE型の例としては、M.I.E
linson、Radio Eng. Electro
n Phys.、10(1965)等がある。SCE型
は基板上に形成された小面積の薄膜に、膜面に平行に電
流を流すことにより、電子放出が生ずる現象を利用する
ものである。この表面伝導型電子放出素子としては、前
記エリンソン等によるSnO2 薄膜を用いたもの、Au
薄膜によるもの[G.Dittmer:”Thin S
olid Films”、9、317(1972)]、
In23 /SnO2 薄膜によるもの[M.Hartw
ell and C.G.Fonstad:”IEEE
Trans. ED Conf.”、519(197
5)]、カーボン薄膜によるもの[荒木久 他:真空、
第26巻、第1号、22頁(1983)]等が報告され
ている。
As an example of the FE type, W. P. Dyke &
W. W. Dolan, "Field Emissio"
n ", Advance in Electron Ph
ysics, 8, 89 (1956) or C.I. A. S
pindt, "PHYSICAL Property"
s of thin-film field emis
sion cathodes with mollybd
enium cones ", J. Appl. Phy
s. , 47, 5248 (1976) and the like are known.
Examples of the MIM type include C.I. A. Mead, "The t
unnel-emission amplifier,
J. Appl. Phys. , 32, 646 (1961)
Etc. are known. Examples of the SCE type include: I. E
Linson, Radio Eng. Electro
n Phys. 10 (1965) and so on. The SCE type utilizes a phenomenon in which electron emission occurs when a current flows through a small-area thin film formed on a substrate in parallel with the film surface. As the surface conduction electron-emitting device, a device using the SnO 2 thin film by the above-mentioned Erinson, Au,
Thin film [G. Dittmer: "Thin S
old Films ", 9, 317 (1972)],
In 2 O 3 / SnO 2 thin film [M. Hartw
ell and C.I. G. FIG. Fonstad: "IEEE
Trans. ED Conf. 519 (197
5)], using a carbon thin film [Hisashi Araki et al .: Vacuum,
26, No. 1, p. 22 (1983)].

【0004】これらの表面伝導型電子放出素子の典型的
な素子構成として前述のM.ハートウェルの素子構成を
図4に示す。同図において1は絶縁性基板である。4は
導伝性薄膜で、H型形状のパターンに、スパッタで形成
された金属酸化物薄膜等からなり、後述のフォーミング
と呼ばれる通電処理により電子放出部3が形成される。
4は電子放出部を含む薄膜と呼ぶことにする。尚、図中
のL1は、0.5〜1mm、Wは、0.1mmで設定さ
れている。
As a typical element structure of these surface conduction electron-emitting devices, the above-mentioned M. The Hartwell device configuration is shown in FIG. In FIG. 1, reference numeral 1 denotes an insulating substrate. Reference numeral 4 denotes a conductive thin film, which is composed of a metal oxide thin film or the like formed by sputtering on an H-shaped pattern, and the electron emitting portion 3 is formed by an energization process called forming described later.
Reference numeral 4 denotes a thin film including an electron-emitting portion. In the figure, L1 is set to 0.5 to 1 mm and W is set to 0.1 mm.

【0005】従来、これらの表面伝導型電子放出素子に
おいては、電子放出を行う前に電子放出部形成用薄膜4
を予めフォーミングと呼ばれる通電処理によって電子放
出部3を形成するのが一般的であった。即ち、フォーミ
ングとは前記電子放出部形成用薄膜4の両端に電圧を印
加通電し、電子放出部形成用薄膜を局所的に破壊、変形
もしくは変質せしめ、電気的に高抵抗な状態にした電子
放出部3を形成することである。尚、電子放出部3は電
子放出部形成用薄膜4の一部に亀裂が発生し、その亀裂
付近から電子放出が行われる。以下、フォーミングによ
り形成した電子放出部を含む電子放出部形成用薄膜4を
電子放出部を含む薄膜4と呼ぶ。前記フォーミング処理
をした表面伝導型電子放出素子は、上述の電子放出部を
含む薄膜4に電圧を印加し、素子に電流を流すことによ
り、上述の電子放出部3より電子を放出せしめるもので
ある。
Conventionally, in these surface conduction electron-emitting devices, the electron-emitting portion forming thin film 4 is formed before the electron emission.
It was general that the electron emitting portion 3 was formed in advance by an energization process called forming. That is, forming means that a voltage is applied to both ends of the electron-emitting-portion forming thin film 4 to locally destroy, deform or alter the electron-emitting-portion forming thin film so that the electron emission is in a high resistance state. To form part 3. In the electron emitting portion 3, a crack is generated in a part of the electron emitting portion forming thin film 4, and electrons are emitted from the vicinity of the crack. Hereinafter, the electron emitting portion forming thin film 4 including the electron emitting portion formed by forming is referred to as a thin film 4 including an electron emitting portion. The surface-conduction electron-emitting device that has undergone the forming process is one in which electrons are emitted from the electron-emitting device 3 described above by applying a voltage to the thin film 4 including the electron-emitting device described above and passing a current through the device. .

【0006】上述の表面伝導型放出素子は、構造が単純
で製造も容易であることから、大面積にわたって多数の
素子を配列形成できる利点がある。そこで、この特徴を
生かせるようないろいろな応用が研究されている。例え
ば、荷電ビーム源、表示装置等があげられる。多数の表
面伝導型放出素子を配列形成した例としては、並列に表
面伝導型電子放出素子を配列し、個々の素子の両端を配
線にてそれぞれ結線した行を多数行配列した電子源基板
があげられる。(例えば、特開平1−031332号公
報) また、本出願人による特開平06−342636号公報
に、素子行を選択する選択手段と偏重信号を印加する変
調波とを有する表面伝導型電子放出素子を行列状に配置
した電子源、および画像形成装置がある。この行列上に
配列されたそれぞれの表面伝導型電子放出素子の構成を
図5に示す。図において、51は絶縁性基板、59は素
子配線電極、50は絶縁層、52、53は素子電極、5
4は電子放出部である。
The above-mentioned surface conduction electron-emitting device has an advantage that a large number of devices can be arrayed over a large area because it has a simple structure and is easy to manufacture. Therefore, various applications that make use of this feature are being studied. For example, a charged beam source, a display device, and the like can be given. An example of an array of a large number of surface conduction electron-emitting devices is an electron source substrate in which surface conduction electron-emitting devices are arranged in parallel and a large number of rows in which both ends of each element are connected by wiring are arranged. To be (For example, Japanese Unexamined Patent Publication No. 1-031332) Further, in Japanese Unexamined Patent Publication No. 06-342636 by the present applicant, a surface conduction electron-emitting device having a selection means for selecting a device row and a modulation wave for applying a biased signal. There are an electron source and an image forming apparatus in which are arranged in a matrix. The structure of each surface conduction electron-emitting device arranged in this matrix is shown in FIG. In the figure, 51 is an insulating substrate, 59 is an element wiring electrode, 50 is an insulating layer, 52 and 53 are element electrodes, 5
4 is an electron emission part.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来例では、コンタクトホールが上配線に囲まれそれぞれ
の素子について独立しているため、電子放出部も上配線
に囲まれてしまい、ラングミュア・ブロジェット法(L
B法)による有機金属錯体、もしくは有機金属とLB法
を用いて堆積するのに好適な両親媒性材料(バインダ
ー)とを混合したものを導伝性膜として堆積する際に、
前記上配線による段差の影響で、導伝性膜の分布が悪く
なり、これにより素子特性のばらつきが起こるという問
題があった。以上の欠点に鑑み、本発明は上記の問題を
除去するためになされたものである。
However, in the above-mentioned conventional example, since the contact hole is surrounded by the upper wiring and each element is independent, the electron emitting portion is also surrounded by the upper wiring, and the Langmuir-Blodgett is also present. Law (L
(B method), or a mixture of an organic metal and an amphipathic material (binder) suitable for deposition using the LB method is deposited as a conductive film,
Due to the influence of the step due to the upper wiring, there is a problem that the distribution of the conductive film is deteriorated, which causes variations in device characteristics. In view of the above drawbacks, the present invention has been made to eliminate the above problems.

【0008】[0008]

【課題を解決するための手段】すなわち、上記の目的を
達成すべく成なされた本発明は、絶縁性基板上に多数個
の表面伝導型電子放出素子を行列状に配列した電子源基
板において、上配線とコンタクトホールとを離れた位置
に形成し、該コンタクトホールを下配線と交差する方向
の素子に連続させることを特徴とする電子源基板であ
る。
That is, the present invention made to achieve the above object is to provide an electron source substrate in which a large number of surface conduction electron-emitting devices are arranged in a matrix on an insulating substrate. The electron source substrate is characterized in that the upper wiring and the contact hole are formed apart from each other and the contact hole is continuous with the element in a direction intersecting with the lower wiring.

【0009】本発明は更に、a.)絶縁性基板を洗浄し
たのち、該基板上に真空プロセス、フォトリソプロセス
または印刷プロセスにより導電性材料で下配線を形成
し、b.)真空蒸着法、印刷法またはスパッタ法により
層間絶縁層として絶縁膜を形成し、c.)a.において
形成した下配線と交差する方向に各素子部が連続になる
ようにコンタクトホールを形成するためのフォトレジス
トパターンを形成し、これをマスクとして層間絶縁層を
エッチングし、d.)真空蒸着法、印刷法、スパッタ法
フォトグラフィ技術、エッチングの何れかを用いて素子
電極を形成し、e.)印刷法、フォトリソ技術と真空成
膜法を用いてコンタクトホールを埋め込む接続部を形成
し、a.と同様にして上配線を形成し、f.)導電性薄
膜をラングミュア・ブロジェト法により、有機金属錯
体、もしくは有機金属錯体と両親媒性材料との混合物を
堆積し、焼成して電子放出用薄膜を形成する電子源基板
の製造方法を提供するものである。
The present invention further comprises: a.) Cleaning an insulating substrate, and then forming a lower wiring with a conductive material on the substrate by a vacuum process, a photolithography process or a printing process, and b.) A vacuum vapor deposition method, a printing process. An insulating film as an interlayer insulating layer by a sputtering method or a sputtering method, and c.) A. A photoresist pattern for forming a contact hole is formed so that each element portion is continuous in a direction intersecting the lower wiring formed in step d.) The interlayer insulating layer is etched using this as a mask, and d.) Vacuum evaporation method , A printing method, a sputtering method, a photography technique, or etching is used to form an element electrode, and e.) A printing method, a photolithography technique, and a vacuum film formation method are used to form a connection portion for filling a contact hole. . The upper wiring is formed in the same manner as in f.) The conductive thin film is deposited by the Langmuir-Broggett method to deposit an organometallic complex or a mixture of an organometallic complex and an amphipathic material, followed by firing to deposit a thin film for electron emission. The present invention provides a method for manufacturing an electron source substrate for forming a substrate.

【0010】本発明は、前記電子源基板を用いて作成さ
れた画像形成装置をも提供するものである。
The present invention also provides an image forming apparatus produced by using the electron source substrate.

【0011】本発明では、上記の構成とすることによ
り、電子放出部を含む薄膜を形成する部分と下配線と交
差する方向において、上配線による段差はなくなり、従
来の構造に比べ、LB法を用いて電子放出部を形成する
際の段差によって生じる膜厚分布を減らし、これにより
素子特性の分布を減少させることができる。
According to the present invention, with the above structure, the step due to the upper wiring is eliminated in the direction intersecting the lower wiring with the portion forming the thin film including the electron emitting portion, and the LB method is used as compared with the conventional structure. It is possible to reduce the film thickness distribution caused by the step when the electron emitting portion is formed by using it, and thereby reduce the distribution of device characteristics.

【0012】以下、本発明の後述する実施例1および2
に係わる本発明の電子放出素子の構造を図2に示し、図
3に従って以下にその作成手順を示す。 工程−a 絶縁性基板11を洗剤、純水および有機溶剤により洗浄
後、基板11上に真空成膜プロセス、フォトリソプロセ
ス、印刷プロセス等により、Cr、Au、Ti、Cu等
の導伝性材料で下配線72を形成する。(図3の
(ア)) 絶縁性基板としては、石英ガラス、Na等の不純物含有
量の少ないガラス、青板ガラス、SiO2 を表面に形成
したガラス基板およびアルミナ等のセラミック基板が用
いられる。 工程−b つぎに、層間絶縁層111として、絶縁膜を真空蒸着
法、印刷法、スパッタ法などを用いて形成する。 工程−c 次に、本発明の特徴となるコンタクトホールを、工程−
aにおいて形成した下配線と交差する方向に各素子部が
連続になるような本発明の特徴であるコンタクトホール
113であるが、フォトレジストパターンを形成しこれ
をマスクとして、層間絶縁層111をエッチングするこ
とにより形成する。(図3の(イ)) 工程−d 次に、素子電極76、77を真空蒸着法、印刷法、スパ
ッタ法フォトグラフィ技術、エッチング技術等を用いて
形成する。(図3の(ウ)) なお、素子電極の材料としては、導電性を示すものであ
ればどのようなものであっても構わないが、例えば、N
i、Cr、Au、Mo、W、Ti、Al、Cu、Pd等
の金属や、Pd、Ag、Au、RuO2 、Pd−Ag等
の金属あるいは金属酸化物とガラス等から構成される印
刷導体、In23 −SnO2 等の透明導電体およびポ
リシリコン等の半導体材料等があげられる。 工程−e 印刷法、フォトリソ技術と真空成膜法等を用いてコンタ
クトホールを埋め込む接続部を形成する。次に工程−a
と同様にして、上配線73を形成する。(図3の
(エ)) 工程−f 次に、導電性薄膜4をLB法を用いて、有機金属錯体、
もしくは有機金属錯体と好適な両親媒性材料とを混合し
たものを堆積させたのち、これを焼成することにより形
成された電子放出部を含む薄膜を有する電子放出用薄膜
を形成する。
Hereinafter, Examples 1 and 2 of the present invention, which will be described later, will be described.
FIG. 2 shows the structure of the electron-emitting device of the present invention according to FIG. 2, and the manufacturing procedure thereof is shown below in accordance with FIG. Step-a After cleaning the insulating substrate 11 with a detergent, pure water, and an organic solvent, a conductive material such as Cr, Au, Ti, or Cu is formed on the substrate 11 by a vacuum film forming process, a photolithography process, a printing process, or the like. The lower wiring 72 is formed. ((A) in FIG. 3) As the insulating substrate, quartz glass, glass with a low content of impurities such as Na, soda lime glass, a glass substrate having SiO 2 formed on its surface, and a ceramic substrate such as alumina are used. Step-b Next, an insulating film is formed as the interlayer insulating layer 111 by a vacuum evaporation method, a printing method, a sputtering method, or the like. Process-c Next, the contact hole, which is a feature of the present invention, is processed by the process-
The contact hole 113, which is a feature of the present invention such that each element portion is continuous in a direction intersecting the lower wiring formed in a, is formed by forming a photoresist pattern and etching the interlayer insulating layer 111 using this as a mask. To be formed. ((A) of FIG. 3) Step-d Next, the device electrodes 76 and 77 are formed by using a vacuum evaporation method, a printing method, a sputtering method photography technique, an etching technique, or the like. ((C) of FIG. 3) The material of the element electrode may be any material as long as it exhibits conductivity.
A printed conductor composed of a metal such as i, Cr, Au, Mo, W, Ti, Al, Cu, Pd, a metal such as Pd, Ag, Au, RuO 2 , Pd-Ag or a metal oxide and glass. , Transparent conductive materials such as In 2 O 3 —SnO 2 and semiconductor materials such as polysilicon. Step-e A connection part to be embedded in the contact hole is formed by using a printing method, a photolithography technique and a vacuum film forming method. Next step-a
Similarly, the upper wiring 73 is formed. ((D) of FIG. 3) Step-f Next, the conductive thin film 4 was formed by using the LB method, an organometallic complex,
Alternatively, a mixture of an organometallic complex and a suitable amphipathic material is deposited and then fired to form an electron emission thin film having a thin film including an electron emission portion.

【0013】以上の工程によりコンタクトホールを下配
線と交差する方向の素子に連続させることにより表面伝
導型電子放出素子を行列状に配列した電子源基板は、電
子放出部形成用薄膜の膜厚分布を減少したことにより、
通電フォーミングをおこなった後のそれぞれの素子の特
性のばらつきを、従来に比べ減少することができる。以
下に実施例を述べる。
The electron source substrate in which the surface conduction electron-emitting devices are arranged in a matrix by connecting the contact holes to the devices in the direction intersecting the lower wiring by the above steps, has a film thickness distribution of the thin film for forming the electron-emitting portion. By reducing
It is possible to reduce variations in the characteristics of the respective elements after conducting the energization forming, as compared with the related art. Examples will be described below.

【0014】[0014]

【実施例】【Example】

実施例1 本実施例では、コンタクトホールを下配線と交差する方
向の素子に連続させた表面伝導型電子放出素子を行列状
に配列した電子源基板の作成例を示す。
Example 1 This example shows an example of producing an electron source substrate in which surface conduction electron-emitting devices in which contact holes are connected to devices in a direction intersecting a lower wiring are arranged in a matrix.

【0015】工程−a 有機溶剤を用いて洗浄した青板ガラス上に、フォトレジ
スト(RD−2001N−41、日立化成社製)により
パターンを形成し、真空蒸着により厚さ100AのT
i、厚さ6000AのAu、厚さ300AのCrを順次
積層した後、フォトレジストパターンを有機溶剤で溶解
し、Cr/Au/Tiの堆積膜をリフトオフし、所望の
形状の下配線を作成した。
Step-a A pattern is formed by a photoresist (RD-2001N-41, manufactured by Hitachi Chemical Co., Ltd.) on soda lime glass washed with an organic solvent, and a 100 A thick T film is formed by vacuum evaporation.
i, Au with a thickness of 6000 A, and Cr with a thickness of 300 A were sequentially laminated, and then the photoresist pattern was dissolved with an organic solvent, and the Cr / Au / Ti deposited film was lifted off to form a lower wiring of a desired shape. .

【0016】工程−b 次に厚さ1.2umのシリコン酸化膜からなる層間絶縁
層をRFスパッタ法により堆積した。
Step-b Next, an interlayer insulating layer made of a silicon oxide film having a thickness of 1.2 μm was deposited by RF sputtering.

【0017】工程−c フォトレジストを用いて下配線と交差する方向の素子に
ついて連続なコンタクトホールを形成するためのパター
ンを形成し、CF4 とH2 ガスを用いてRIE(Rea
ctive Ion Etching)法により、絶縁
層をエッチングしてコンタクトホールを形成した。
Step-c A pattern for forming a continuous contact hole is formed in the device in a direction intersecting with the lower wiring using a photoresist, and RIE (Rea) is performed using CF 4 and H 2 gas.
The contact layer was formed by etching the insulating layer by the active ion etching method.

【0018】工程−d スパッタ法により厚さ50AのTi、厚さ300AのP
tを順次堆積した。
Step-d: Ti having a thickness of 50 A and P having a thickness of 300 A are formed by the sputtering method.
t were sequentially deposited.

【0019】次に、素子電極と素子電極間ギャップとか
らなるパターンをフォトレジスト(AZ1370、ヘキ
スト社製)で形成し、ドライエッチングを行った。ドラ
イエッチングはPtをHBr/Arの混合ガスでTiを
HBr/BCl3 の混合ガスでそれぞれ行った。ドライ
エッチング終了後フォトレジストは有機溶剤にて除去し
た。なお、素子電極間は3ミクロンとし、素子電極の幅
を300ミクロンとした。
Next, a pattern consisting of element electrodes and a gap between the element electrodes was formed with a photoresist (AZ1370, manufactured by Hoechst) and dry etching was performed. The dry etching was performed by using Pt as a mixed gas of HBr / Ar and Ti as a mixed gas of HBr / BCl 3 . After completion of dry etching, the photoresist was removed with an organic solvent. The distance between the device electrodes was 3 μm, and the width of the device electrodes was 300 μm.

【0020】工程−e この上に、上配線、およびコンタクトホールを埋め込む
電極となるべきパターンをフォトレジスト(RD−20
00N−41、日立化成社製)で形成し、真空蒸着によ
り厚さ300AのTi、厚さ1.0umのAuを順次積
層した後、フォトレジストパターンを有機溶剤で溶解
し、リフトオフにより不要の部分を除去して、所望の形
状の上配線およびコンタクトホールの埋め込み電極を作
成した。 工程−f 基板表面に、酢酸パラジウム塩アルキルアミン錯体とド
コサン酸の混合物からなる膜を、LB法により形成し
た。積層した膜厚は250層であった。その後300℃
で10分間の加熱焼成処理をした。
Step-e On this, a pattern to be an electrode for filling the upper wiring and the contact hole is formed with a photoresist (RD-20).
00N-41, manufactured by Hitachi Chemical Co., Ltd.), Ti of 300 A in thickness and Au of 1.0 μm in thickness are sequentially laminated by vacuum deposition, and then the photoresist pattern is dissolved in an organic solvent, and unnecessary portions are lifted off. Was removed to form an upper wiring having a desired shape and a buried electrode for a contact hole. Step-f A film made of a mixture of a palladium acetate alkylamine complex and docosanoic acid was formed on the surface of the substrate by the LB method. The laminated film thickness was 250 layers. Then 300 ° C
For 10 minutes.

【0021】さらに電子放出部形成用薄膜となるべきパ
ターンを、フォトレジスト(OMR8320cp、東京
応化社製)で形成し、ドライエッチングを行った。ドラ
イエッチングは、Arによりおこなった。この後、フォ
トレジストは、UV/O3アッシャーにて、150℃で
30分処理することにより除去した。
Further, a pattern to be a thin film for forming an electron emitting portion was formed with a photoresist (OMR8320cp, manufactured by Tokyo Ohka Co., Ltd.) and dry etching was performed. Dry etching was performed with Ar. After that, the photoresist was removed by treating with a UV / O3 asher at 150 ° C. for 30 minutes.

【0022】以上の工程により、絶縁性基板上に、下配
線、層間絶縁膜、上配線、素子電極、電子放出部形成用
薄膜を形成した。
Through the above steps, the lower wiring, the interlayer insulating film, the upper wiring, the device electrode, and the electron emitting portion forming thin film were formed on the insulating substrate.

【0023】次に、素子電極間に電圧を印加し、電子放
出部形成用薄膜に通電フォーミングすることにより、電
子放出部を作成した。
Next, a voltage was applied between the device electrodes to energize the thin film for forming the electron emitting portion to form an electron emitting portion.

【0024】この様にして作成した電子源基板は、本発
明を用いない従来の電子源基板に比べ、LB法を用いて
電子放出用薄膜を形成する際に、従来の構造に比べて下
配線方向の素子についての上配線による段差がなくなる
ため膜厚分布が向上し、素子としての特性のばらつきが
減少する。
The electron source substrate thus prepared has a lower wiring than that of the conventional structure when the electron emission thin film is formed by the LB method, as compared with the conventional electron source substrate not using the present invention. Since the step due to the upper wiring in the element in the direction is eliminated, the film thickness distribution is improved and the variation in the characteristics of the element is reduced.

【0025】実施例2 本実施例では、コンタクトホールを下配線と交差する方
向の素子に連続させた表面伝導型電子放出素子を行列状
に配列した電子源基板を用いた画像形成装置およびその
作成方法を示す。
Embodiment 2 In this embodiment, an image forming apparatus using an electron source substrate in which surface conduction electron-emitting devices in which contact holes are connected to devices in a direction intersecting with a lower wiring are arranged in a matrix, and the image forming apparatus is produced. Show the method.

【0026】[工程a]を、実施例1と同様に行った。[Step a] was performed in the same manner as in Example 1.

【0027】[工程b]においては、絶縁膜としてPS
G(phosphosilicate glass)膜
を1μm成膜した。
In [step b], PS is used as an insulating film.
A G (phosphosilicate glass) film was formed to a thickness of 1 μm.

【0028】[工程c]から[工程e]までを実施例1
と同様におこなった。
Example 1 from [step c] to [step e]
Same as above.

【0029】[工程f]酢酸パラジウム塩アルキルアミ
ン錯体とドコサン酸の混合物からなる膜を、LB法によ
り形成した。積層した膜厚は300層であった。
[Step f] A film made of a mixture of palladium acetate alkylamine complex and docosanoic acid was formed by the LB method. The laminated film thickness was 300 layers.

【0030】その後、O3 雰囲気下で、紫外線照射を8
時間行い、200℃で40分熱処理を施して酸化パラジ
ウムを形成した。
After that, UV irradiation is performed for 8 hours in an O 3 atmosphere.
Then, heat treatment was performed at 200 ° C. for 40 minutes to form palladium oxide.

【0031】次に、フォトレジスト(AZ1370−S
F、ヘキスト社製)により所望の電子放出部形成用薄膜
のパターンを形成し、ドライエッチングにより、不要な
部分の酸化パラジウムを除去し、その後、レジストを除
去した。
Next, a photoresist (AZ1370-S) is used.
F, manufactured by Hoechst Co., Ltd.) to form a desired pattern of the thin film for forming an electron emitting portion, and the palladium oxide in an unnecessary portion was removed by dry etching, and then the resist was removed.

【0032】以上の工程により、絶縁性基板上に、下配
線72、層間絶縁層111、上配線73、素子電極5
2,53、電子放出素子部形成用薄膜を形成した。
Through the above steps, the lower wiring 72, the interlayer insulating layer 111, the upper wiring 73, and the device electrode 5 are formed on the insulating substrate.
2, 53, a thin film for forming an electron-emitting device portion was formed.

【0033】この様にして、作成した電子源基板を用い
て表示装置を構成した例を図1を用いて説明する。作成
した電子源基板をリアプレート上に固定した後、基板の
5mm上方に、フェースプレート86(ガラス基板83
の内面に蛍光膜84とメタルバック85が形成されて構
成される。)を支持枠82、リアプレート81の接合部
にフリットガラスを塗布し、大気中あるいは窒素雰囲気
中で400℃ないし500℃で30分以上焼成する事に
より封着した。また、リアプレート81への基板の固定
もフリットガラスで行った。図1において、74は電子
放出素子、72,73はそれぞれ、X方向、Y方向の下
配線および上配線である。蛍光膜84は、モノクローム
の場合は蛍光体のみからなるが、本実施例では、蛍光体
はストライプ形状を採用し、先にブラックストライプの
みを形成し、その間隙部に各色蛍光体を塗布し、蛍光膜
を作成した。ブラックストライプの材料としては、通常
良く用いられている黒鉛を主成分とする材料を用いたガ
ラス基板83を用い、蛍光体を塗布する方法としてはス
ラリー法を用いた。また、蛍光膜84の内面側には通常
メタルバック85が設けられる。メタルバックは、蛍光
膜作製後、蛍光膜の内面側表面の平滑化処理(通常、フ
ィルミングと呼ばれる)を行い、その後、Alを真空蒸
着することにより作製した。フェースプレート86に
は、更に蛍光膜84の導電性を高めるため、蛍光膜の外
面側に透明電極(不図示)が設けられる場合もあるが、
本実施例では、メタルバックのみで十分な導電性が得ら
れたので省略した。前述の封着を行う際、カラーの場合
は各色蛍光体と電子放出素子とを対応させなくてはいけ
ないため、十分な位置合わせを行った。以上のようにし
て完成したガラス容器内の雰囲気を排気管(図示せず)
を通じ真空ポンプにて排気し、十分な真空度に達した
後、容器外端子Dox1ないしDoxmとDoy1ない
しDoynを通じ電子放出素子74の電極間5,6に電
圧を印加し、電子放出部3を、電子放出部形成用薄膜4
を通電処理(フォーミング処理)することにより作製し
た。
An example in which a display device is constructed using the electron source substrate thus created will be described with reference to FIG. After fixing the created electron source substrate on the rear plate, the face plate 86 (glass substrate 83
A fluorescent film 84 and a metal back 85 are formed on the inner surface of the. Frit glass was applied to the joint between the support frame 82 and the rear plate 81, and was sealed by firing at 400 ° C. to 500 ° C. for 30 minutes or more in the air or a nitrogen atmosphere. Further, the frit glass was also used to fix the substrate to the rear plate 81. In FIG. 1, 74 is an electron-emitting device, and 72 and 73 are lower and upper wirings in the X and Y directions, respectively. In the case of monochrome, the fluorescent film 84 is composed of only the phosphor, but in the present embodiment, the phosphor adopts a stripe shape, only the black stripe is formed first, and the phosphor of each color is applied to the gap portion, A fluorescent film was created. As a material for the black stripe, a glass substrate 83 made of a commonly used material containing graphite as a main component was used, and a slurry method was used as a method for applying the phosphor. A metal back 85 is usually provided on the inner surface side of the fluorescent film 84. The metal back was produced by performing a smoothing treatment (usually called filming) on the inner surface of the fluorescent film after producing the fluorescent film, and then vacuum-depositing Al. The face plate 86 may be provided with a transparent electrode (not shown) on the outer surface side of the fluorescent film in order to further increase the conductivity of the fluorescent film 84.
In this example, since sufficient conductivity was obtained only with the metal back, it was omitted. At the time of performing the above-mentioned sealing, in the case of color, since the phosphors of each color must correspond to the electron-emitting devices, sufficient alignment was performed. An exhaust pipe (not shown) is provided for the atmosphere in the glass container completed as described above.
Through a vacuum pump to reach a sufficient degree of vacuum, and then a voltage is applied between the electrodes 5 and 6 of the electron-emitting device 74 through the terminals outside the container Dox1 to Doxm and Doy1 to Doyn, and the electron-emitting portion 3 is Thin film 4 for forming electron emission portion
Was manufactured by conducting an energization process (forming process).

【0034】このように作製された電子放出部は、パラ
ジウム元素を主成分とする微粒子が分散配置された状態
となり、その微粒子の平均粒径は30Åであった。
In the electron-emitting portion thus produced, fine particles containing palladium as a main component were dispersed and arranged, and the average particle diameter of the fine particles was 30Å.

【0035】次に10-6Torr程度の真空度で、不図
示の排気管をガスバーナーで熱することで溶着し外囲器
の封止を行った。最後に封止後の真空度を維持するため
に、ゲッター処理を行った。これは、封止を行う直前
に、高周波加熱等の加熱法により、画像形成装置内の所
定の位置(不図示)に配置されたゲッターを加熱し、蒸
着膜を形成処理した。ゲッターはBa等を主成分とし
た。
Next, at a vacuum degree of about 10 -6 Torr, an exhaust pipe (not shown) was heated by a gas burner to be welded to seal the envelope. Finally, a getter process was performed to maintain the degree of vacuum after sealing. Immediately before sealing, a getter placed at a predetermined position (not shown) in the image forming apparatus was heated by a heating method such as high-frequency heating to form a vapor deposition film. The getter was mainly composed of Ba or the like.

【0036】以上のように完成した画像形成装置におい
て、各電子放出素子には、容器外端子Dox1ないしD
oxm、Doy1ないしDoynを通じ、走査信号およ
び変調信号を不図示の信号発生手段によりそれぞれ印加
することにより、電子放出させ、高圧端子Hvを通じ、
メタルバック85に数kV以上の高圧を印加し、電子ビ
ームを加速し、蛍光膜に衝突させ、励起・発光させるこ
とにより画像を表示した。この様にして作成した画像形
成装置は従来のものに比べ、LB法を用いて電子放出薄
膜を形成する際に、従来の構造に比べて下配線方向の素
子についての上配線による段差がなくなるため膜厚分布
が向上し、素子としての特性のばらつきが減少する。
In the image forming apparatus completed as described above, each of the electron-emitting devices has terminals outside the container Dox1 to Dx.
Electrons are emitted by applying a scanning signal and a modulation signal through signal generators (not shown) through oxm, Doy1 to Doyn, and through the high voltage terminal Hv.
An image was displayed by applying a high voltage of several kV or more to the metal back 85, accelerating the electron beam, causing the electron beam to collide with the fluorescent film, and exciting and emitting light. Compared with the conventional structure, the image forming apparatus manufactured in this manner has no step in the element in the lower wiring direction due to the upper wiring when the electron emission thin film is formed by using the LB method, as compared with the conventional structure. The film thickness distribution is improved, and variations in characteristics of the device are reduced.

【0037】なお、以上に述べた構成は、表示等に用い
られる好適な画像形成装置を作製する上で必要な概略構
成であり、例えば各部材の材料等、詳細な部分は上述内
容に限られるものではなく、画像装置の用途に適するよ
う適宜選択することができる。
The above-described structure is a schematic structure necessary for producing a suitable image forming apparatus used for display or the like, and the detailed parts such as the material of each member are limited to the above contents. However, it can be appropriately selected depending on the purpose of the image device.

【0038】[0038]

【発明の効果】本発明の電子源基板は、上配線とコンタ
クトホールとを離れた位置に形成し、コンタクトホール
を下配線と交差する方向の素子に連続させているので、
行列状に配列した表面伝導型電子放出素子は、電子放出
部形成用薄膜の膜厚分布が減少したことにより、通電フ
ォーミングをおこなった後のそれぞれの素子の特性のば
らつきを従来に比べ減少することができる。
In the electron source substrate of the present invention, the upper wiring and the contact hole are formed at positions separated from each other, and the contact hole is continuous with the element in the direction intersecting with the lower wiring.
In the surface conduction electron-emitting devices arranged in a matrix, the variation in the characteristics of each device after energization forming has been reduced compared to the conventional one due to the reduction in the film thickness distribution of the thin film for forming the electron-emitting region. You can

【0039】また、本発明の思想によれば、表示に用い
られる好適な画像形成装置に限るものではなく、感光性
ドラムと発光ダイオード等で構成された光プリンターの
発光ダイオード等の代替の発光源として、上述の画像形
成装置を用いることもできる。またこの際、上述のm本
の行方向配線とn本の列方向配線を、適宜選択すること
で、ライン状発光源だけでなく、2次元状の発光源とし
ても応用できる。
Further, according to the idea of the present invention, it is not limited to a suitable image forming apparatus used for display, but an alternative light emitting source such as a light emitting diode of an optical printer including a photosensitive drum and a light emitting diode. As the above, the above-mentioned image forming apparatus can be used. In this case, by appropriately selecting the above-mentioned m row-directional wirings and n column-directional wirings, the present invention can be applied not only to a linear light emitting source but also to a two-dimensional light emitting source.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例2の画像形成装置図である。FIG. 1 is a diagram of an image forming apparatus according to a second exemplary embodiment.

【図2】実施態様例であり、本発明の電子放出素子の構
造を示す斜視図である。
FIG. 2 is a perspective view showing an example of an embodiment and a structure of an electron-emitting device of the present invention.

【図3】実施態様例であり、本発明の電子放出用薄膜を
形成するための工程図の1例である。
FIG. 3 is an example of an embodiment and is an example of a process chart for forming an electron emission thin film of the present invention.

【図4】従来の表面伝導型電子放出素子の平面図であ
る。
FIG. 4 is a plan view of a conventional surface conduction electron-emitting device.

【図5】従来の表面伝導型電子放出素子を行列状に配列
した内の1素子を示した図である。
FIG. 5 is a diagram showing one of conventional surface conduction electron-emitting devices arranged in a matrix.

【符号の説明】[Explanation of symbols]

1 絶縁性基板 3 電子放出部 4 電子放出部を含む薄膜 5、6 素子電極 11 絶縁性基板 50 絶縁層 51 絶縁性基板 52、53 素子電極 54 電子放出部 59 素子配線電極 72 X方向配線(下配線) 73 Y方向配線(上配線) 74 表面伝導型電子放出素子 75 結線 76、77 素子電極 81 電子源1を固定したリアプレート 82 支持枠 83 ガラス基板 84 蛍光膜 85 メタルバック 86 フェースプレート 88 外囲器 111 層間絶縁層 112 コンタクトホール 113 上配線方向の素子について連続したコンタクト
ホール 114 コンタクトホール部を埋める接続部
1 Insulating Substrate 3 Electron Emitting Part 4 Thin Film Including Electron Emitting Part 5, 6 Element Electrode 11 Insulating Substrate 50 Insulating Layer 51 Insulating Substrate 52, 53 Element Electrode 54 Electron Emitting Section 59 Element Wiring Electrode 72 X Direction Wiring (Bottom Wiring) 73 Y direction wiring (upper wiring) 74 Surface conduction electron-emitting device 75 Connections 76, 77 Device electrode 81 Rear plate with the electron source 1 fixed 82 Support frame 83 Glass substrate 84 Fluorescent film 85 Metal back 86 Face plate 88 Outside Envelope 111 Interlayer insulating layer 112 Contact hole 113 Contact hole that is continuous for elements in the upper wiring direction 114 Connection portion that fills the contact hole portion

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上に多数個の表面伝導型電子
放出素子を行列状に配列した電子源基板において、 上配線とコンタクトホールとを離れた位置に形成し、該
コンタクトホールを下配線と交差する方向の素子に連続
させることを特徴とする電子源基板。
1. An electron source substrate having a large number of surface conduction electron-emitting devices arranged in a matrix on an insulating substrate, wherein an upper wiring and a contact hole are formed apart from each other, and the contact hole is formed as a lower wiring. An electron source substrate, characterized in that it is connected to an element in a direction intersecting with.
【請求項2】 ラングミュア・ブロジェット法により形
成された電子放出部を含む薄膜を有する請求項1に記載
の電子源基板。
2. The electron source substrate according to claim 1, wherein the electron source substrate has a thin film including an electron emitting portion formed by the Langmuir-Blodgett method.
【請求項3】 a.絶縁性基板を洗浄したのち、該基板
上に真空プロセス、フォトリソプロセスまたは印刷プロ
セスにより導電性材料で下配線を形成し、 b.真空蒸着法、印刷法またはスパッタ法により層間絶
縁層として絶縁膜を形成し、 c.a.において形成した下配線と交差する方向に各素
子部が連続になるようにコンタクトホールを形成するた
めのフォトレジストパターンを形成し、これをマスクと
して層間絶縁層をエッチングし、 d.層間絶縁層上に素子電極を形成し、 e.コンタクトホールを埋め込む接続部を形成し、a.
と同様にして上配線を形成し、 f.導電性薄膜をラングミュア・ブロジェット法によ
り、有機金属錯体、もしくは有機金属錯体と両親媒性材
料との混合物を堆積し、 焼成して電子放出用薄膜を形成することを特徴とする電
子源基板の製造方法。
3. A method according to claim 1, wherein: a. After cleaning the insulating substrate, a lower wiring is formed of a conductive material on the substrate by a vacuum process, a photolithography process, or a printing process, b. Forming an insulating film as an interlayer insulating layer by a vacuum vapor deposition method, a printing method or a sputtering method, c. a. A photoresist pattern for forming a contact hole is formed so that each element portion is continuous in a direction intersecting with the lower wiring formed in 1., the interlayer insulating layer is etched using this as a mask, and d. Forming an element electrode on the interlayer insulating layer, e. Forming a connection portion for filling the contact hole, and a.
Forming the upper wiring in the same manner as in f. A conductive thin film is deposited by the Langmuir-Blodgett method to deposit an organometallic complex or a mixture of an organometallic complex and an amphipathic material, and baked to form an electron emitting thin film. Production method.
【請求項4】 請求項1または2に記載の電子源基板に
より作成された画像形成装置。
4. An image forming apparatus formed by the electron source substrate according to claim 1.
JP16217095A 1995-06-28 1995-06-28 Electron source substrate and its manufacture and image forming device Pending JPH0917358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16217095A JPH0917358A (en) 1995-06-28 1995-06-28 Electron source substrate and its manufacture and image forming device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16217095A JPH0917358A (en) 1995-06-28 1995-06-28 Electron source substrate and its manufacture and image forming device

Publications (1)

Publication Number Publication Date
JPH0917358A true JPH0917358A (en) 1997-01-17

Family

ID=15749357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16217095A Pending JPH0917358A (en) 1995-06-28 1995-06-28 Electron source substrate and its manufacture and image forming device

Country Status (1)

Country Link
JP (1) JPH0917358A (en)

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