JPH09172544A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To identify a type of an object image with high accuracy depending on a processing condition or a read condition of the object image by providing a processing means processing image data according to the identification result and revising an identification operation of an identification means when the processing means executes magnification processing. SOLUTION: A digital color image reader (color reader) 1 is provided to an upper part of the processor and a digital color image printer (color printer) 2 is provided at the lower part. The color reader 1 uses a color separate means and a photoelectric conversion element to read color image information of an original by colors and converts the information into a digital electric image signal. Then the processor is provided with an input means entering image data, an identification means identifying a type of the image represented by the image data based on the image data, and a processing means processing the image data according to the identification result by the identification means and revises the identification operation of the identification means when the processing means executes magnification processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having a function of identifying the type of input image.

[0002]

2. Description of the Related Art Conventionally, there have been techniques for identifying the type of an input image, binarizing a character image by a single threshold value, and binarizing a halftone image by dither. Are known.

[0003]

However, since the identifying operation by the identifying means has been uniquely determined in the past, when the input image is subjected to a scaling process with a large enlargement ratio, the character edge becomes good. Could not be detected,
The input image could not be identified accurately.

Further, when the reading condition of the reading means for generating the image data is changed, it is not possible to perform the identifying operation in consideration of the change in the characteristic of the image data.

Therefore, an object of the present invention is to provide an image processing apparatus capable of accurately identifying the type of a target image according to the processing condition of the target image or the reading condition of the target image.

[0006]

In order to solve the above problems, an image processing apparatus of the present application identifies an input means for inputting image data and a type of an image represented by the image data based on the image data. An identifying means, a processing means for processing the image data according to an identification result by the identifying means, and a changing operation of the identifying means when the scaling processing is executed by the processing means. .

Further, another image processing apparatus reads an original and generates an image data corresponding to the original, and an image reading unit for identifying the type of the image represented by the image data based on the image data. The identification operation of the identification means is changed according to the reading means and the reading conditions of the reading means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the drawing, the present system has a digital color image reading device (hereinafter, referred to as a color reader) 1 at an upper part and a digital color image printing device (hereinafter, a color printer) 2 at a lower part. The color reader 1 reads color image information of a document for each color by a color separation means described later and a photoelectric conversion element such as a CCD, and converts the color image information into an electric digital image signal. The color printer 2 is an electrophotographic laser beam color printer that reproduces a color image for each color according to the digital image signal and transfers the color image to a recording paper a plurality of times in a digital dot form for recording.

First, an outline of the color reader 1 will be described.

Reference numeral 3 denotes an original, reference numeral 4 denotes a platen glass on which the original is placed, and reference numeral 5 denotes a condenser for condensing a reflected light image from the original exposed and scanned by a halogen exposure lamp 10 and inputting the image to a 1: 1 full-color sensor 6. Rod array lens,
5, 6, 7, and 10 are integrated as a document scanning unit 11 to perform exposure scanning in the direction of arrow A1. The color-separated image signal read line by line during exposure scanning is amplified to a predetermined voltage by the sensor output signal amplifier circuit 7, and then input to a video processing unit described later by a signal line 501 and subjected to signal processing. Details will be described later. Reference numeral 501 denotes a coaxial cable for ensuring faithful transmission of a signal.
A signal 502 is a signal line for supplying a drive pulse of the full-size full-color sensor 6, and all necessary drive pulses are generated in the video processing unit 12. Reference numerals 8 and 9 denote a white plate and a black plate for correcting a white level and a black level of an image signal, which will be described later, and by irradiating with a halogen exposure lamp 10, a signal level of a predetermined density can be obtained respectively. Used for signal white level correction and black level correction. Reference numeral 13 is a control unit having a microcomputer, which controls the display on the operation panel 1000 by the bus 508, key input control and control of the video processing unit 12, and the position sensors S1 and S2 to change the position of the document scanning unit 11 to the signal line 509. 51
0, and further, stepping motor drive circuit control for pulse driving the stepping motor 14 for moving the scanning body 11 by the signal line 503, signal line 50
ON / OFF control of the halogen exposure lamp 10 by the exposure lamp driver, light amount control, signal line 505
All controls of the color reader unit 1 such as control of the digitizer 16 and internal keys and display unit are performed via.
The color image signal read by the above-described exposure scanning unit 11 at the time of document exposure scanning is input to the video processing unit 12 via the amplifier circuit 7 and the signal line 501, and is subjected to various processing in the unit 12 which will be described later. , To the printer unit 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be described. A scanner 711 is a laser output unit that converts an image signal from the color reader 1 into an optical signal, a polygon mirror 712 having a polyhedron (for example, octahedron), a motor (not shown) that rotates the mirror 712, and an f / θ lens. It has (imaging lens) 713 and the like. 714 is a reflection mirror for changing the optical path of the laser beam, and 715 is a photosensitive drum. The laser light emitted from the laser output unit is reflected by the polygon mirror 712, and is reflected by the lens 713 and the mirror 714.
Scans the surface of the photosensitive drum 715 linearly (raster scan) to form a latent image corresponding to the document image.

Further, 711 is a primary charger, 718 is a full-surface exposure lamp, 723 is a cleaner part for collecting the untransferred residual toner, 724 is a pre-transfer charger, and these members are provided around the photosensitive drum 715. It is arranged.

Reference numeral 726 denotes a developing device unit for developing the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y, 731M, 731C, 731.
Bk is a developing sleeve that is in direct contact with the photosensitive drum 715 for direct development, 730Y, 730M, 730C and 730Bk are toner hoppers that hold preliminary toner, and 732 is a screw that transfers developer, and these sleeves 731Y ~ 731Bk, toner hopper 730Y ~ 7
The developing unit 726 is constituted by 30Bk and the screw 732, and these members are disposed around the rotation axis P of the developing unit. For example, when a yellow toner image is formed, yellow toner development is performed at the position shown in this figure. Body 7
The developing sleeve 7 in the magenta developing device
31M is installed. The development of cyan and black operates similarly.

Reference numeral 716 denotes a transfer drum for transferring the toner image formed on the photosensitive drum 715 onto paper.
Reference numeral 19 denotes an actuator plate for detecting the movement position of the transfer drum 716, and 720 denotes the actuator plate 719
A position sensor for detecting that the transfer drum 716 has moved to the home position position due to the proximity of
25 is a transfer drum cleaner, 727 is a paper press roller,
728 is a static eliminator and 729 is a transfer charger, and these members 719, 720, 725, 727, 729 are arranged around the transfer roller 716.

On the other hand, 735 and 736 are sheet feeding cassettes for storing sheets (paper sheets), and 737 and 738 are cassettes 73.
Paper feed rollers for feeding paper from 5,736, 739, 7
Reference numerals 40 and 741 denote timing rollers for timing of feeding and conveying, and the sheet fed and conveyed through these is guided to a paper guide 749 and wrapped around the transfer drum 716 while the leading end is carried by a gripper described later. , Shift to the image formation process.

Reference numeral 550 is a drum rotation motor,
The photosensitive drum 715 and the transfer drum 716 are synchronously rotated,
750 is a transfer drum 716 for transferring the paper after the image forming process is completed.
A peeling claw for removing the sheet, a conveying belt 742 for conveying the removed sheet, an image fixing unit 743 for fixing the sheet conveyed by the conveying belt 742, and the image fixing unit 743 includes a pair of thermal pressure rollers 744 and 745.

The image processing circuit according to the present invention will be described in detail with reference to FIG. This circuit exposes a full-color original document with an illumination source such as a halogen lamp or a fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and converts the obtained analog image signal into an A / D converter. A color image copying device that obtains a color image by digitizing it with a digital camera, processing and processing the digitized full-color image signal, and outputting it to a thermal transfer type color printer, inkjet color printer, laser beam color printer, etc., or digitalization in advance. Applied to a color image output device, etc., which inputs the generated color image signal from a computer, another color image reading device, a color image transmitting device, etc., performs processing such as composition, and outputs to the color printer described above. Is.

In FIG. 2, A is an image reading unit, which includes a staggered CCD line sensor 500a and a shift register 501.
a, sample hold circuit 502a, A / D converter 50
3a, shift correction circuit 504a, black correction / white correction circuit 50
6a, a CCD driver 533a, a panel generator 534a, and an oscillator 558a.

B is a color conversion circuit, C is a LOG conversion circuit, and D
Is a color correction circuit, O is a line memory, E is a character image correction circuit, F is a character composition circuit, P is a color balance circuit, G is an image processing / editing circuit, H is an edge enhancement circuit, I is a character image area separation circuit, J is a region signal generation circuit, K is 400 dp
i binary memory, L 100 dpi binary memory, M external device interface, N signal switching circuit, 532.
Is a binarization circuit, R is a driver for driving the printer such as a laser driver of a laser beam printer and a BJ head driver of a bubble jet printer, and S is a printer unit including the driver R.

Reference numeral 58 is a digitizer, 1000 is an operation unit, 1000 ″ is an operation interface, 18 and 19 are RAMs, 20 is a CPU, 21 is a ROM, 22 is a CPU bus, and 500 and 501 are I / O ports.

The original is first illuminated by an exposure lamp (not shown), and the reflected light is separated into individual images by the color reading sensor 500a and read, and the amplification circuit 501 is read.
A is amplified to a predetermined level. A CCD 533a supplies a pulse signal for driving the color reading sensor.
A driver and the necessary pulse source is generated by the system control pulse generator 534a.

FIG. 3 shows a color reading sensor and driving pulses. FIG. 3A shows a color reading sensor used in this example, in which 63.5 μm is set as one pixel (400 dot / inc) in order to read the image in five divisions in the main scanning direction.
h (hereinafter referred to as dpi), 1024 pixels, that is, one pixel is divided into three in the main scanning direction by G, B, and R, so that the total number of effective pixels is 1024 × 3 = 3072. On the other hand, the chips 58 to 62 are formed on the same ceramic substrate, and the first, third and fifth sensors (58a, 58a,
60a and 62a) are on the same line LA, and the second and fourth lines are LA and 4 lines (63.5 μm × 4 = 254 μm).
They are arranged on a line LB spaced apart from each other, and when scanning a document, scanning is performed in the direction of arrow AL.

Of the five CCDs, the first, third, and fifth CCDs are the drive pulse group ODRV118a, and the second and fourth CCDs are the EDRVs.
Driven independently and synchronously by 119a. O01A, O02A included in ODRV118a,
E01A and E02 included in ORS and EDRV119a
A and ERS are a charge transfer clock and a charge reset pulse in each sensor, which are 1, 3, 5 and 2, respectively.
Due to mutual interference with the fourth and noise limitation, they are generated in perfect synchronization so as not to be in jitter with each other. Therefore, these pulses are generated by one reference oscillation source OSC558a (Fig. 2).
Is generated from.

FIG. 4A shows ODRV 118a and EDRV.
A circuit block for generating 119a, FIG. 4B is a timing chart, and is included in the system control pulse generator 534a of FIG. Single OSC55
A clock K0135a obtained by dividing the original clock CLK0 generated by 8a is a clock that generates reference signals SYNC2 and SYNC3 that determine the generation timing of ODRV and EDRV, and SYNC2 and SYNC3 are set by a signal line 22 connected to the CPU bus. The output timing is determined according to the set values of the presettable counters 64a and 65a, and the SYNC2 and SYNC3 are divided by the frequency divider 66.
a, 67a and drive pulse generators 68a, 69a are initialized. That is, the HSYN input to this block
Based on C118, all one oscillation source OSC558a
ODRV1 because it is generated by CLK0 output by
The respective pulse groups of 18a and EDRV 119a are obtained as synchronized signals without any jitter, and signal disturbance due to interference between sensors can be prevented.

Here, the sensor drive pulse ODRV118a obtained in synchronization with each other is applied to the first, third and fifth sensors 58a, 60a and 62a, and the EDRV119a is applied to 2,4.
The second sensor 59a, 61a is supplied to each sensor 58.
Video signals V1 to V5 are independently output from a, 59a, 60a, 61a, and 62a in synchronization with the drive pulse, and an independent amplifier circuit 501-shown for each channel shown in FIG.
1 to 501-5 are amplified to a predetermined voltage value, V1, V3 and V5 are sent out at the timing of 00S129a in FIG. 3B through the coaxial cable 101a, and V2 and V4 signals are sent out at the timing of EOS134a. Entered in.

The document input to the video image processing circuit is
The color image signal obtained by reading by dividing the image is divided into three colors of G (green), B (blue), and R (red) by the sample hold circuit S / H 502a. Therefore, after S / H, 3 × 5 = 15 system signal processing is performed.

By the S / H circuit 502a, each color R, G,
The analog color image signal sampled and held for each B is digitized by the next stage A / D conversion circuit 503a for each 1 to 5 channels, and is output to the next stage in parallel independently for each 1 to 5 channels.

In the present embodiment, as described above, there are five staggered sensors which have an interval of four lines (63.5 μm × 4 = 254 μm) in the sub-scanning direction and are divided into five areas in the main scanning direction. Since the document is being read, the reading position is shifted between the channels 2 and 4 which are being scanned in advance and the remaining channels 1 and 3 and 5. Therefore, in order to correctly connect this, the shift correction circuit 504 including memories for a plurality of lines
The deviation is corrected by a.

Next, the black correction operation in the black correction / white correction circuit 506a will be described with reference to FIG. FIG.
As shown in (b), the black level outputs of channels 1 to 5 have large variations between chips and between pixels when the amount of light input to the sensor is very small. If this is output as it is to output an image, streaks and unevenness occur in the data portion of the image. Therefore, it is necessary to correct the output variation of this black portion.
The correction is performed by the circuit as shown in (a). Prior to the document reading operation, the document scanning unit is moved to the position of the black plate having a uniform density arranged in the non-image area at the front end of the document table, the halogen is turned on, and the black level image signal is input to this circuit.
With respect to the blue signal B _IN , the selector 82 should store one line of this image data in the black level RAM 78a.
Select A with a (d), close gate 80a (a), 81
Open a. That is, the data line is 151a → 152a →
153a, on the other hand, the address input 155a of the RAM 78a is initialized with HSYNC, the output 154a of the address counter 84a for counting VCLK is input so that C for the selector 83a is output, and the black level signal for one line is output. It is stored in the RAM 78a (hereinafter referred to as a black reference value acquisition mode).

At the time of image reading, the RAM 78a is in the data reading mode and the data line 153a → 157a.
In the path of (1), each line is read out and input pixel by pixel to the B input of the subtractor 79a. That is, at this time, the gate 8
1a is closed (b) and 80a is open (a). Further, the selector 86a has an A output. Therefore, the black correction circuit output 15
6a is obtained as B _IN (i) −DK (i) = B _OUT (i) in the case of a blue signal with respect to the black level data DK (i) (called a black correction mode). Similarly, green G _IN and red R _IN are similarly controlled by 77aG and 77aR. The control lines a, b, c, d, and e of each selector gate for this control are controlled by the latch 85a assigned as the I / O of the CPU 22 (FIG. 2).
It is performed by control. The selectors 82a, 83a, 86
By selecting a for B, the CPU 22 causes the RAM 78
a becomes accessible.

Next, referring to FIG. 6, a black correction / white correction circuit 506a.
The white level correction (shading correction) in FIG. The white level correction corrects the sensitivity variations of the illumination system, the optical system, and the sensor based on the white data obtained when the original scanning unit is moved to a uniform white plate position and irradiated. The basic circuit configuration is shown in FIG. Although the basic circuit configuration is the same as that of FIG. 5A, the subtractor 79a is used for black correction, whereas the divider 79 'is used for white correction.
Since only the point of using a is different, description of the same parts will be omitted.

CCD for reading the original at the time of color correction
When (500a) is at the reading position (home position) of the uniform white plate, that is, before the copying operation or the reading operation, the exposure lamp (not shown) is turned on, and the uniform white level image data for one line of the correction RAM 78 '.
Stored in a. For example, if it has a width in the longitudinal direction of A4 in the main scanning direction, it is 16 × 297 mm at 16 pel / mm.
= 4752 pixels, that is, at least the RAM capacity is 4
The RAM is 752 bytes, and the white plate data Wi of the i-th pixel (i = 1 to 4752) as shown in FIG.
As shown in FIG. 6C, 78'a stores data for the white plate for each pixel.

On the other hand, for Wi, the corrected data D ₀ = Di × for the read value Di of the normal image of the i-th pixel
Should be FF _H / Wi. Therefore, the CPU 22 opens the gates 80'a and 81'a to the latches 85'aa ', b', c ', d'and further the selector 82'.
It outputs so that B is selected at a, 83'a and 86'a, and makes the RAM 78'a accessible to the CPU. Next, in the procedure shown in FIG. 7, the CPU 22 sequentially calculates FF _H / W _{0 for} the _first pixel W ₀ , FF / W ₁ for W _1, and replaces the data. When the blue component of the color component image is finished (Step B in FIG. 7), the green component (Step
G) and the red component (StepR) are sequentially performed, and thereafter, for the input original image data Di, D ₀ = Di × FF _H /
The gate 80'a is opened (a ') so that Wi is output,
81'a is closed (b '), A is selected by the selectors 83'a and 86'a, and the coefficient data FF _H / Wi read from the RAM 78'a passes through the signal line 153a → 157a,
The original image data 151a input from one side is multiplied and output.

As described above, the black level and the white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between the sensors, the light intensity variation of the optical system and the white level sensitivity. Then, image data B _OUT 101, G _OUT 102, and b _B 103 that are uniformly corrected for each color of white and black are obtained over the main scanning direction. The obtained color-separated image data of which the white and black levels have been corrected are obtained by detecting pixels on an image having a specific color density or a specific color ratio according to an instruction from an operation unit (not shown), and performing the same operation. The data is sent to a color conversion circuit B for performing data conversion to another color density or a color ratio specified by the unit.

<Color Conversion> FIG. 8 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit of FIG. 8 is C for 8-bit color separation signals R _IN , G _IN , and B _IN (1b to 3b).
A color detection unit 5b that determines an arbitrary color set in the register 6b by the PU 20, an area signal Ar4b for performing color detection and color conversion for a plurality of locations, and a "specific color" output by the color detection unit. Line memories 10b to 10b for performing processing for expanding a signal (hereinafter, referred to as a hit signal) in the main scanning direction and the sub-scanning direction (only the sub-scanning direction in the example of FIG. 8).
1b, OR gate 12b, expanded hit signal 34b
And a color conversion enable signal 33b generated by the AND gate 32b from the non-rectangular signal (including rectangular) BHi27b,
The enable signal 33b and the input color separation data (R _IN ,
G _IN , B _IN 1b-3b), line memories 13b-16b for synchronizing the area signal Ar4, delay circuits 17b-20b, enable signal 33b, synchronized color separation data (R _IN ′, G _IN ′). , B _IN '21b ~ 2
3b), the area signal Ar'24b and the CPU 20 perform color conversion based on the color data after color conversion set in the register 26b, a color conversion unit 25b, and color separation data (b _B , G _OUT) subjected to color conversion processing. , B _OUT 28b-30
b), b _B , G _OUT , and B _OUT , the hit signal H _OUT 31 b is output in synchronization with the output.

Next, an outline of an algorithm for gradation color determination and gradation color conversion will be described. Here, the gradation color determination and the gradation color conversion are the same hue color determination and the same hue color for performing the color conversion while preserving the density value for the color having the same hue in performing the color determination and the color conversion. To do the conversion.

It is known that the same color (or hue) has the same ratio of the red signal R ₁ , the green signal G ₁ and the blue signal B ₁ , for example.

Then, one of the colors to be color-converted (herein the maximum value color, hereinafter referred to as the main color), data M ₁ is selected, and the ratio of it to the data of the other two colors is obtained. For example, the main color is R
Then, M ₁ = R ₁ ,

[0040]

[Outside 1] Ask for.

Then, for the input data Ri, Gi, Bi,

[0042]

[Outside 2] M ₁ × γ ₁ ≦ Ri ≦ M ₁ × γ ₂ (3) However, it is determined that a pixel for which color conversion is performed is one in which α ₂ , β ₁ , γ ₁ ≦ 1 α ₁ , β ₂ , γ ₂ ≧ 1. To do.

Further, the data after color conversion (R ₂ , G ₂ ,
B ₂ ) is also the main color (here, the maximum value color) in the data
Then, the ratio of the data M ₂ of 2 to the data of the other two colors is obtained.

For example, when G ₂ is the main color, M ₂ = G ₂ ,

[0045]

[Outside 3] Ask for.

Then, for the main color M ₁ of the input data,

[0047]

[Outside 4] Ask for.

If the data is a color conversion pixel,

[0049]

[Outside 5] Is output, and if it is not a color conversion pixel, (Ri, Gi, Bi)
Is output.

As a result, it becomes possible to detect all the portions of the same hue having gradation and output the color conversion data corresponding to the gradation.

FIG. 9 is a block diagram showing an example of the color judgment circuit. This part is a part for detecting a pixel to be color-converted.

In this figure, 50b is R _IN b1, G
A smoothing unit for smoothing the input data of _IN b2, B _IN b3, 51b is a selector 52b _R , 52b _G , 52b for selecting one of the outputs (main color) of the smoothing unit.
_B is a selector that selects one of the output of the selector 51b and fixed values R ₀ , G ₀ , and B ₀ , and 54b _R , 54b _G , and 54b _B are O.
R gates, 63b, 64b _R , 64b _G , 64b _B are selectors for setting select signals to selectors 51b, 52b _R , 52b _G , 52b _B based on area signals Ar10, Ar20, 56b _R , 56b _{G, respectively.} , 56
b _B and 57 b _R , 57 b _G , 57 b _B are multipliers for calculating the upper and lower limits of each.

Further, the respective upper limit ratio registers 58b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B set by the CPU 20 respectively detect colors for a plurality of areas based on the area signal Ar30. You can set the data to do this.

Here, Ar10, Ar20, Ar30
Is a signal generated based on FIG. 7Ar4b, and includes a required number of stages of DF / F. Further, 61b is an AND gate, 62b is an OR gate, and 67b is a register.

Next, the actual movement will be described. R _IN b
One of the data R ′, G ′, B ′ obtained by smoothing 1, G _IN b2, B _IN b3 respectively is selected by the selector 51b by the select signal S ₁ set by the CPU 20, and main color data is selected. Be done. Here, CPU2
For 0, different data A and B are set in the registers 65b and 66b, respectively, and the selector 63b selects either A or B according to the Ar10 signal and inputs it to the selector 51b as the S ₁ signal.

As described above, two registers 65b and 66b are prepared, different data are input to A and B of the selector 63b, and the area signal Ar10 selects either one of them, so that a plurality of areas are selected. Separate color detection can be performed. The area signal Ar10 may be a signal for a non-rectangular area as well as a rectangular area.

Next selectors 52b _R , 52b _G , 52b _B
Then, any one of R ₀ , G ₀ , B ₀ set by the CPU 20 or the main color data selected by the selector 51b is output from the decoder 53b by the outputs 53ba to 53bc and the fixed color mode signal S.
Selected by the select signal generated by ₂ and. The selectors 64b _R , 64b _G , and 64b _B can detect different colors for a plurality of areas by selecting either A or B according to the area signal Ar20, as in the case of the selector 63b. I am trying. Here, R ₀ , G ₀ , and B ₀ are selected when the main color in the conventional color conversion (fixed color mode) and gradation color determination is selected, and the main color data is a color other than the main color in the gradation color conversion. To be selected.

The operator can freely set the fixed color judgment and the gradation color judgment from the operation unit. Alternatively, for example, it is also possible to change by software according to color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52b _R , 52b _G , 52
From the output of b _B , the upper limit ratio registers 58b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B set by the CPU 20, R ′,
The upper and lower limits of G'and B'are the multipliers 56b _R , 5
6b _G , 56b _B and 57b _R , 57b _G , 57b _B to calculate the window comparators 60b _R , 60b.
b _G and 60 b _B are set as upper and lower limit values.

Window comparators 60b _R , 60
The AND gate 61b determines whether or not the main color data is within the range of b _G and 60 b _B and the two colors outside the main color are within the range. The register 67b can set "1" by the enable signal 68b of the determination unit regardless of the determination signal. In that case, "1"
There is a color to be converted in the part marked with.

With the above configuration, fixed color judgment or gradation color judgment can be performed for a plurality of areas.

FIG. 10 is a block diagram of an example of the color conversion circuit. This circuit selects the color-converted signal or the original signal based on the output 7b of the color determination unit 5b.

In FIG. 10, the color conversion unit 25b is a selector 111b, and main color data of the converted color (here, the maximum value).
Register 112b _R 1,1 for setting each ratio to
12b _R 2,112b _G 1,112b _G 2,112b _B 1,
112b _B 2, multipliers 113b _R , 113b _G , 113
b _B, the selector _{114b R, 114b G, 114b B} , the selector _{115b R, 115b G, 115b B} , AND gate 32 b, AR50 is generated based on the area signal Ar'24 in FIG 8, Ar60, Ar70 by the set from CPU20 The selected data to the selector 111b and the multiplier 11
3b _R , 113b _G , 113b _B , selector 114b _R , 1
Selectors 117b and 1 set to 14b _G and 114b _B
12b _R , 112b _G , 112b _B , 116b _R , 116b
_G , 116b _B , and a delay circuit 118b.

Next, the actual movement will be described.

The selector 111b receives the input signal R _IN '21.
One of b, G _IN '22b, B _IN ' 23b (main color)
Is selected according to the select signal S5. Signal S5 here
Occurs when the area signal Ar40 selects the selector 117b to either A or B for the two data set by the CPU 20. In this way, color conversion processing for a plurality of areas becomes possible.

The signal selected by the selector 111b is sent to the multipliers 113b _R , 113b _G and 113b _B as CP.
The multiplication with the register value set by U20 is performed. Again, the area signal Ar50 has two register values of 1
12b _R 1 · 112b _R 2,112b _G 1 · 112b _G 2,
112b _B 1 and 112b _B 2 are respectively selectors 112b
Different color conversion processing can be performed on a plurality of areas by selecting _R , 112b _G , and 112b _B.

Next, the selectors 114b _R , 114b _G , 11
The result of the multiplication at 4b _B and two fixed values Ro ′ · Ro ″, Go ′ · Go ″, Bo ′ · Bo ″ set by the CPU 20.
Selector 116b _R , 1 according to the inner area signal Ar70 of
One of the fixed values selected in 16b _G and 116b _B is selected by the mode signal S6. Also in this case, the mode signal S6 selected by the area signal Ar60 is used in the same manner as S5.

Finally, the selectors 115b _R , 115b _G , 1
15b _B using the select signal S _B ′, R _IN ″, G
_IN ″, B _IN ″ ′ R _IN ′, G _IN ′, B _IN ′ are delayed and timing is adjusted) and selectors 114b _R , 114
Either the output of b _G or 114b _B is selected,
It is output as R _OUT , G _OUT , and B _OUT . The hit signal H _{OUT is} also output in synchronization with b _B , G _OUT , and B _OUT .

Here, the selector signal S _B ′ is obtained by delaying the AND of the color determination result 34b and the color conversion enable signal BHi 34b. If a non-rectangular enable signal such as the dotted line in FIG. 11 is input as this BHi signal, color conversion processing can be performed on the non-rectangular region. In this case, as the area signal, a region such as the one-dot chain line, that is, the leftmost position obtained from the dotted line (see FIG.
a), top right (FIG. 11b), bottom left (FIG. 11c),
It is generated by the coordinates of the bottom rightmost position (Fig. 11d). Also,
The non-rectangular area signal BHi is an area signal input from an input device such as a digitizer and expanded in the binary memory L of 100 dpi. When color conversion is performed using this non-rectangular enable signal, the enable area can be specified along the boundary where conversion is desired, so the color detection threshold can be expanded compared to conventional color conversion using a rectangle. be able to. Therefore, it is possible to obtain an output image in which the detection capability is improved and the gradation color is converted with high accuracy.

From the above, color conversion having a lightness corresponding to the main color of the color determination section 5b (for example, when red is converted to gradation color in red, light red is converted into light blue, dark red is converted into dark blue) or fixed Any of the color values can be freely converted for a plurality of areas.

As will be described later, mosaic processing, texture processing, trimming processing, masking processing, etc. can be performed only on the area of a specific color (non-rectangular or rectangular) based on the hit signal H _OUT .

The area signals Ar10 and Ar2 are used.
0 and Ar30 are area signals Ar4 based on Ar4b.
0, Ar50, Ar60, Ar70 are signals generated based on Ar'24b and based on the area signal 134 from the area signal generation circuit J (FIG. 2), but as described above, only the rectangular area signal is generated. Instead, it may be a non-rectangular region signal. That is, the non-rectangular area signal BH based on the non-rectangular area information stored in the 100 dpi binary memory
i may be used.

The generation of the BHi signal will be described later.
In this BHi signal, both rectangular and non-rectangular area signals can be mixed.

As described above, according to this embodiment, the color conversion area can be set based on not only the rectangular but also the non-rectangular area signal, so that the color conversion processing with higher accuracy can be performed.

As shown in FIG. 2, the outputs 103, 104 and 105 of the color conversion circuit B are the logarithmic conversion circuit C for converting the image data proportional to the reflectance to the density data, the character area on the original and the half. It is sent to a character image area separation circuit I for discriminating a tone area and a halftone area, and an external device interface M for communicating data with an external device via this system and cables 135, 136 and 137.

Next, the color image data proportional to the input light amount is input to the logarithmic conversion circuit C (FIG. 2) which performs processing for matching with the human eye's spectral luminous efficiency characteristics.

Here, an image source that is converted to have white = 00 _H and black = FF _H and is further input to the image reading sensor, for example, a normal reflection original, a transparent original such as a film projector, or the same transparent original. Since the negative film, positive film or film has different sensitivity and gamma characteristics input in the exposure state,
As shown in (a) and (b), the LUT for logarithmic conversion
It has multiple (look-up tables) and uses them properly according to the purpose. Switching is performed by the signal lines lg0, lg1, lg2
The I / O port of the CPU 22 is input by an instruction input from the operation unit or the like (FIG. 2). Here, each B, G. The data output to R corresponds to the density value of the output image, and includes B (blue), G (green),
Since each R (red) signal corresponds to a toner amount of Y (yellow), M (magenta), and C (cyan), image data thereafter is associated with yellow, magenta, and cyan.

Next, the color correction circuit D performs color correction on each color component image data from the original image obtained by logarithmic conversion, that is, the yellow component, the magenta component, and the cyan component, as described below. The spectral characteristics of the color separation filter arranged on the color reading sensor for each pixel are
As shown in FIG. 15A, there is an unnecessary transmission area such as a shaded area, while the color toners (Y, M, C) transferred onto the transfer paper are also as shown in FIG. 15B. It is well known to have unwanted absorbent components. Therefore, for each color component image data Yi, Mi, Ci,

[0079]

[Outside 6] Masking correction for calculating a linear expression of each color and performing color correction is well known. Furthermore, by Yi, Mi, Ci, M
In (Yi, Mi, Ci) (minimum value of Yi, Mi, Ci) is calculated, and this is used as a smear (black), and black toner is added later (smearing) and the added black component is used. An undercolor removal (UCR) operation for reducing the amount of each color material added is often performed. 13, masking, smearing, UCR
6 shows a circuit configuration of a color correction circuit D that performs The characteristic of this configuration is that it has two systems of masking matrix and can switch at high speed by "1/0" of one signal line. With / without UCR, one signal line is "1/0". It is possible to switch at high speed with "," and to have two circuits for determining the amount of smear, and to switch at high speed with "1/0".

First, prior to image reading, the desired first matrix coefficient M ₁ and second desired matrix coefficient M ₂ are set in the CPU.
Set from the bus connected to 22. In this example

[0081]

[Outside 7] , M ₁ is set in the registers 87d to 95d, and M ₂ is set in the registers 96d to 104d.

Further, 111d to 122d, 135d, 1
Reference numerals 31d and 136d respectively denote selectors for selecting A when the S terminal = “1” and selecting B when the S terminal = “0”. Therefore, when the matrix M ₁ is selected, the switching signal MAR
When EA364 = “1” and matrix M ₂ is selected, it is set to “0”.

Reference numeral 123d is a secreter, and outputs a, b, c are obtained based on the truth table of FIG. 14 by the selection signals C ₀ , C ₁ (366d), 367d). Selection signal C
₀ , C ₁ and C ₂ correspond to the color signals to be output,
For example, in the order of Y, M, C, Bk (C ₂ , C ₁ , C ₀ ) =
(0,0,0), (0,0,1), (0,1,0),
(1,0,0), and (0,1,) as a monochrome signal.
By setting 1), a desired color-corrected color signal is obtained. Now (C ₀ , C ₁ , C ₂ ) = (0, 0, 0), and M
When AREA = "1", the registers 87d, 88d, 89d are provided at the outputs (a, b, c) of the selector 123d.
, And therefore (a _Y1 , -b _Y1 , -C _C1 ) is output. On the other hand, from the input signals Yi, Mi, Ci, Min (Y
i, Mi, Ci) = k calculated as black component signal 37
4d is subjected to a linear transformation of Y = ax-b (a and b are constants) at 137d, and subtractors 124d, 125d, 126d.
Is input to the B input. In each of the subtractors 124d to 126d, Y = Yi− (ak−b) and M = Mi are used as undercolor removal.
-(Ak-b), C = Ci- (ak-b) is calculated,
Multipliers 127d, 128d, 129d for masking calculation are provided via signal lines 377d, 378d, 379d.
Is input to

The multipliers 127d, 128d and 129d have (a _Y1 , -b _Y1 , -C _C1 ) and B input to the A input, respectively.
For input, the above-mentioned [Yi- (ak-b), Mi-8ak
-B), Ci- (ak-b)] = [Yi, Mi, Ci]
As is clear from the figure, the output D
_OUT is Y _OUT = Y under the condition of C ₂ = 0 (YorMorC)
i × (a _Y1 ) + Mi × (−b _Y1 ) + Ci × (−C _C1 ) is obtained, and yellow image data subjected to masking color correction and undercolor removal processing is obtained. _{Similarly, M OUT = Yi × (-a} Y2) + Mi × (-b M2) + Ci × (-C C2) C OUT = Yi × (-a Y3) + Mi × (-b M3) + Ci × (-C _C3 ) is output to D _OUT . The color selection is controlled by the CPU 22 according to the order of output to the color printer to be output (C ₀ , C ₁ , C ₂ ) according to the table of FIG. Register 105d~107d, 108d~110d are registers for monochrome image formation, by the principle similar to the masking color correction described _{above, MONO = k 1 Yi + l} 1 Mi +
Each color is obtained by weighted addition by m ₁ Ci.

At the time of Bk output, C ₂ (368) input as a switching signal of the selector 131d causes C ₂ =
1, therefore the primary converter 133d receives the primary conversion of Y = cx-d and outputs it from the selector 131d.
Further, BkMJ110 is a black component signal output to the outline portion of a black character based on the output of the character image area separation circuit I described later. Color switching signals C ₀ ′, C ₁ ′, C ₂ ′ 366-
368 is an output port 51 connected to the CPU bus 22.
It is set from 0, and MAREA 364 is output from the area signal generation circuit 364. Gate circuits 150d to 153d
Is a binary memory circuit (bitmap memory) L described later.
Non-rectangular area signal DHi122 read from 537
When DHi = "1", the signal _{C 0 ', C 1',} C 2 '
It is a circuit for controlling so that the data for the mono image is automatically output when “= 1,1,0”.

<Character Image Area Separation Circuit> Next, the character image area separation circuit I uses the read image data and determines whether the image data is a character, an image, a chromatic color or an achromatic color. Is a circuit for determining whether or not The flow of the process will be described with reference to FIGS. 16 and 17.

Red (R) 103, green (G) 104 input to the character image area separation circuit I from the color conversion B,
Blue (B) 105 is a minimum vegetation detection circuit M _IN (R, G,
B) 101I and maximum value detection circuit Max (R, G,
B) Input to 102I. In each block,
The maximum value and the minimum value are selected from the three types of R, G, and B luminance signals to be input. The subtraction circuit 104I calculates the difference between the selected signals. The difference is large,
That is, if the input R, G, and B are not uniform, it means that the signal is not a signal close to an achromatic color indicating black and white, but is a chromatic color in some color. Of course, if this value is small,
It can be seen that the R, G, and B signals are at substantially the same level, and that the signals are achromatic signals that are not colors of any color. This difference signal is the gray signal GR125.
Is output to the delay circuit Q. In addition, this difference is C
The threshold value arbitrarily set in the register 111I by the PU 20 is compared with the comparator 112I, and the comparison result is output to the delay circuit Q as a gray determination signal GRBi126. The signals of these GR125 and GRBi126 are
After the delay circuit Q matches the phase with other signals, it is input to a character image correction circuit E described later and used as a processing determination signal.

On the other hand, the minimum value signal obtained by M _IN (R, G, B) 101I is also input to the edge emphasis circuit 103I. The edge emphasizing circuit 103I performs edge emphasizing by performing the following calculation using the preceding and succeeding pixel data in the main scanning direction.

[0089]

[Outside 8] D _OUT : image data after edge enhancement Di: i-th pixel data

The edge enhancement is not limited to the above method, and other known techniques may be used. That is, a line memory for delaying two lines or five lines in the sub-scanning direction may be provided, and data of pixel blocks of 3 × 3 or 5 × 5 may be used to apply a normal edge enhancement filter. In this case, the edge emphasis is applied not only in the main scanning direction but also in the sub scanning direction, so that the edge emphasis effect is enhanced. By performing such edge enhancement, an excellent effect of improving the accuracy of black character detection described below is produced.

The edge-enhanced image signal in the main scanning direction is next subjected to the average value calculation in the window of 5 × 5 pixels and 3 × 3 pixels by the 5 × 5 averaging circuit 109I and the 3 × 3 averaging circuit 110I. Done. Line memory 105I-10
8I is a delay memory in the sub-scanning direction for performing the average value processing. 5 × 5 5 × 5 calculated by the averaging circuit 109I
The average value of 5 pixels in total of 25 pixels is then added by the adder 115I, 120I, 125I with the offset value independently set in the offset unit connected to the CPUBUS 22. The added 5 × 5 average value is input to the limiter 1 (113I), the limiter 2 (118I), and the limiter 3 (123I). Each limiter is connected by a CPUBUS 22, and the limiter values can be set independently of each other. When the 5 × 5 average value is larger than the set limiter value, the output is clipped by the limiter value. The output signal from each limiter is the comparator 1 116I,
Comparator 2 121I, Comparator 3 126I
Is input to First, in the comparator I 116I,
Limiter 1 113I output signal and 3 × 3 average 110I
Compared with the output from. Compared comparator 1
The output of 116I is the halftone dot area discrimination circuit 122 described later.
Delay circuit 11 to match the phase with the output signal from I
7I is input. The binarized signal is binarized by the average value of the 5 × 5 and 3 × 3 pixel blocks in order to prevent the collapse and the skip due to the MTF above a predetermined density, and the halftone dot is also used. A 3 × 3 low-pass filter is used to cut high-frequency components of the halftone dot image so that halftone dots of the image are not detected during binarization.

Next, the output signal of the comparator 2 (121I) is binarized with the through image data in order to detect the high frequency component of the image so that the halftone dot area discrimination circuit 122I in the subsequent stage can discriminate the halftone dot area. Has been done. In the halftone dot area discriminating circuit 122I, since the halftone dot image is composed of a collection of dots, it is detected by confirming that the dots are from the edge direction and counting the number of dots around it. Specifically, it is determined as follows.

<Dot determination> The dot area determination circuit 122I will be described with reference to FIG. The signal 101J binarized by the comparator 2 (121I) of the character image area separation circuit (FIG. 16) is the one-line delay (fif) shown in FIG.
o memory) 102J, 103J delays one line each, and the binarized signal 101J and the value delayed by the fifo memories 102J, 103j enter the edge detection circuit 104J. Edge detection circuit 10
In 4J, the edge direction is independently detected for the target pixel in a total of 4 directions including up, down, left and right, and two licking directions. Edge detection circuit sets the edge direction to 4 bits
After being quantized into, the dot detection circuit 109J and the 1-line delay (fifo memory) 105J are entered. 1 line delay (fifo memory) 105J, 106J, 107J,
The 4-bit edge signal delayed by 1 line at 108J enters the dot detection circuit 109J. The dot detection circuit 109J determines whether or not the pixel of interest is a dot by looking at the peripheral edge signals. For example, as shown by the hatched portion of the dot detection circuit 109J in FIG. 17, a total of 7 pixels in the previous 2 lines including the pixel of interest.

[0094]

[Outside 9] To pixels

[0095]

[Outside 10] There is at least one pixel in the direction (there is a density gradient in the direction of the target pixel), and there are a total of 7 pixels in the rear 2 lines including the target pixel.

[0096]

[Outside 11] To

[0097]

[Outside 12] There is at least 1 pixel edge in the direction (there is a density gradient in the direction of the pixel of interest), and in the same way,

[0098]

[Outside 13] If there is an edge in the direction, it is determined as a dot.

[0099]

[Outside 14] In the case of, the dot is naturally determined in the same manner. Next, the dot determination result is similarly delayed by the 1-line delays 110J and 111J, and then thickened by the thickening circuit 112J. Fattening circuit 11
In 2J, when there is at least one pixel determined to be a dot out of a total of 12 pixels of 3 line × 4 pixels, the attention pixel is determined to be a dot determination regardless of the determination result of the attention pixel. . The thickened dot determination result is delayed by 1 line by 1 line delays 113J and 114J, respectively. Output from thickening circuit 112J and 1 line delay 11
The signals delayed by a total of 2 lines by 3J and 114J are then input to the majority decision circuit 115J. In the majority decision circuit 115J, 4 lines are set for the lines before and after the line where the pixel of interest exists.
One pixel is sampled for every other pixel. With respect to the target pixel, the width of 60 pixels on the left and the right, that is, 30 pixels on each of the left and right in 2 lines of 15 pixels are sampled, and the number of pixels determined to be dots is calculated. If this value is larger than the preset value, it is determined that the pixel of interest is a halftone dot.

Here, in the copying apparatus of this embodiment,
As a scaling method, in the sub-scanning direction (paper feed direction), the moving speed of the image reading unit in the reader unit is changed according to the magnification. In this case, in order to perform accurate halftone dot determination, the above-mentioned 1-line delay 10 is applied up to a predetermined magnification when enlarging.
2J, 103J, 105J, 106J, 107J, 10
8J, 110J, 111J, 113J, 114J fi
The fo memory control is an operation of writing one line of two lines and not writing one line.

As described above, by controlling the writing in the fifo memory, it is possible to determine the halftone dots in the same-magnification image even when the magnification is changed. As a result, the determination accuracy during zooming is improved. The types of filters for edge detection, the size of the matrix of the dot detection circuit, the thickening circuit, and the majority decision circuit are not limited to the above examples, and sub-scanning at the time of scaling is also possible. The direction can be thinned out in various ways such as once every 3 lines.

Next, sampling at the time of this enlargement will be described with reference to FIG. Shows the original image. Usually, when reading an image at the same size, the original image is read within the dotted line shown in the figure. This image is continuously written line by line in the fifo memory described above. That is, as shown in the drawing, all writing is performed without omitting writing to the fifo memory. Next, at the time of enlargement, here, for the sake of simple explanation, an explanation will be given on the case of enlargement of 200%. As described above, the moving speed of the reading unit is slowed during enlargement. Therefore, at the time of 200% enlargement, the moving speed is halved, and an image of one line is read with a half width of one line shown in the figure. The image shown in the figure is shown to correspond to the original.

The image data read as shown in the figure is written in the above-mentioned fifo memory as in the case of the same size. At this time, while thinning out every line,
Writing to the fifo memory is performed, and the state is shown in the figure.

In the present embodiment, the case of 200% enlargement has been described. Therefore, writing is performed once for two lines, but this writing method can be changed according to the magnification of magnification change.

In this way, the halftone dot area discrimination circuit 122I
The OR gate 129I is logically ORed using the result of the determination made in step 1 and the signal from the delay circuit 117. After the erroneous determination is removed by the erroneous determination removing circuit 130I, AN
Output to the D gate 132I. The OR gate 129I outputs a determination signal determined to be a halftone area or a halftone area. In the erroneous determination removing circuit 130I, the image area of an image such as a photograph is narrowed and the isolated image area is first narrowed for a binarized signal by utilizing the characteristic that an image such as a photograph has a large area. Remove. Specifically, the central pixel xij
On the other hand, when there is even one pixel other than an image such as a photograph in the peripheral 1 mm square area, the central pixel is determined to be the outside area of the image. That is, the binary image in the area is ANDed and only when all are 1 (in the case of the image area), the central image xij =
Let it be 1. After removing the image area of the isolated point in this way, a thickening process is performed to restore the narrow image area.
That is, when an image area of at least one pixel such as a photograph exists in the peripheral area of 2 mm square, the central pixel xij is determined to be the image area. In this thickening processing, the binary signal after the thinning processing is ORed in the area, and at least one pixel becomes 1
In the case of (in the case of the image area), the central pixel xij = 1.

From the erroneous decision removing circuit 130I,
An inverted signal of the binary signal after the thickening process is output.
This inverted signal is a mask signal for halftone and halftone dots.

Similarly, the output of the halftone dot discriminating circuit 122I is directly input to the erroneous discrimination removing circuit 131I and subjected to thinning processing and thickening processing.

Here, the mask size of the thinning process is the same as the mask size of the thickening process, or the thickening process is made larger so that the determination result when thickening crosses. It has become. Specifically, after performing thinning with the mask of 17 × 17 pixels for both the false determination removal circuits 130I and 131I, further thinning with the mask of 5 × 5, and then thickening with the mask of 34 × 34 pixels. Has been done. The output signal SCRN signal 127 from the erroneous determination removal circuit 131I is a determination signal for preventing moire of the read image by performing smoothing processing only on the halftone dot determination section in the character image correction circuit E described later.

Next, the output signal from the comparator 3 126I extracts the contour of the input image signal in order to process the character sharply in the subsequent stage. As an extraction method, the output of the binarized comparator 3 126I is subjected to a thinning process in a 5 × 5 block, and a thickening process is performed, and a difference region between the thickened signal and the thinned signal is contoured. And The contour signal extracted by such a method is used as the erroneous decision removing circuit 130I.
After passing through a delay circuit 128I to match the phase with the mask signal output from the AND gate 132I, the contour signal masks the contour signal at the portion determined to be an image by the mask signal, and the contour signal in the original character part Output only. The output from the AND gate 132I is then output to the contour regenerating unit 133I.

The average values in the 5 × 5 and 3 × 3 windows as described above are used to detect halftones. However, the matrix size and the window method are the same as in the above case. The average value of the two types of areas including the pixel of interest is not limited to this.

Further, the erroneous decision removing circuits 130I and 131I.
Similarly, the matrix size for the thinning processing and the thickening processing can be arbitrarily set.

As described above, according to the contour signal extraction algorithm of the present embodiment, not only the walk signal is extracted, but also the AN with the mask signal based on the halftone and dot signals is used.
Since D is taken, the character / image area can be accurately separated.

The average value of 5 × 5 pixel blocks used for detecting the halftone area, the halftone area, and the character area is
The CPU 20 sets an appropriate offset according to each area.
Since it can be set by, it becomes possible to accurately detect each area.

Further, according to this embodiment, the output of the halftone dot discriminating circuit and the binary signal indicating the halftone dot or the halftone area are subjected to the thinning processing and the thickening processing so as to eliminate the false judgment. The erroneous determination portion can be removed from the area signal, and the image area can be separated with high accuracy.

Since the signal used for character image area separation is the Min (R, G, B) signal, the three color information of R, G, B should be used effectively as compared with the case of using the luminance signal Y, for example. In particular, it is possible to accurately separate characters and images in an image with a yellowish color.

Also, for the Min (R, G, B) signals,
Since the character / image area is separated after the edge emphasis is performed, the character portion can be easily detected and erroneous determination can be easily prevented.

<Contour Regenerating Unit> The contour regenerating unit 133I performs a process of setting a pixel which has not been determined to be a character contour portion as a character contour portion based on information of peripheral pixels, and as a result M
The jAr 124 is sent to the character image correction circuit E to perform the processing described later.

Specifically, as shown in FIG. 19, for a bold character ((a) in the same figure), the dotted line portion in (b) in the figure is determined to be a character and the processing described later is performed as a character determination section. As for the character ((c) in the figure), the character part becomes as shown by the dotted line part in (d) in the figure, and a gap such as a diagonal line is generated in the character part. is there. In order to prevent this, a contour re-generation process for a character portion is performed based on surrounding information regarding a portion which is not determined as a character. Specifically, by changing the shaded portion to the character portion, the character portion becomes as shown by the dotted line portion (e) in the figure, and erroneous determination is reduced even for characters or fine characters that are difficult to detect and are difficult to detect. This can improve image quality.

FIGS. 20A to 20H are diagrams showing how to use the surrounding information to regenerate the pixel of interest in the character portion. (A) to (d) are 3 × 3 pixel blocks, and when both the vertical, horizontal, and diagonal character parts (S ₁ and S ₂ are both “1”) centering on the target pixel, the target pixel is focused regardless of the information of the target pixel. The pixel is used as a character portion. On the other hand, (e) to (h) are 5 ×
In a 5-pixel block, one pixel is centered on the pixel of interest, and the vertical, horizontal, and diagonal parts are both character parts (S ₁ and S ₂ are “1”). The target pixel is the character part regardless of the information of the target pixel. is there.
In this way, by having a structure with two stages (a plurality of types of blocks), it is possible to cope with a wide range of errors.
Various modifications can be made to the size and number of this pixel block and the type of filter, such as a 7 × 7 pixel block.

23 and 24 are circuits for realizing the processing of FIGS. 20 (a) to 20 (h). The circuits of FIGS. 23 and 24 are line memories 164i to 167i, DF / Fs 104i to 126i for obtaining information around the target pixel, and FIG.
AND gate 146 for realizing 0 (a) to (h)
i to 153i and OR gate 154i.

Information of S ₁ and S ₂ of FIGS. 20A to 20H is taken out from four line memories and 23 DF / Fs. Further, 146i to 153i are registers 155i to 162i corresponding to the respective processes of (a) to (h).
Can independently control enable and disable. The signal of the register is controlled by the CPU 20.

AND circuits 146i to 153i and FIG.
The correspondence relationship between (a) to (h) is as follows.

[0123]

[Outside 15]

FIG. 25 shows line memories 164i to 167.
7 is a timing chart of WE (EN1) and RE (EN2) of i. This is when EN1 and EN2 are at the same timing at the same magnification, or when enlarged (for example, 200% to 300%).
Writes WE once in the thinned two lines. Here, the thinning amount can be arbitrarily determined. As a result, the sizes shown in FIGS. 20A to 20H are expanded. This is because the information that comes in here at the time of enlargement comes in an image enlarged only in the sub-scanning direction. Therefore, by expanding the sizes of (a) to (h), the processing is performed with the same size image even when enlarged. Is going.

This is specifically explained in FIG. 21 (a).
~ Fig. 22 (b). FIG. 21A shows 3 × 3 at the same size.
In the figure showing the shape of a filter for contour contour regeneration of a pixel block, when A = B = lorC = D = lorE = F = 1, the pixel of interest is forcibly set to 1, that is, a character contour.

On the other hand, FIG. 13B shows the shape of the filter for regenerating the contour of 200%, which corresponds to a 3 × 3 pixel block at the same magnification. The method of generating this block is as described above. A to F correspond to A'to F ', respectively.
That is, by taking A'-F 'every other line in the sub-scanning direction, it is possible to separate the character image areas under the same conditions as in the case of equal magnification even during magnification change.

The actual application of this is shown in FIG.
In FIG. 22B, when FIG. 22A is the same size, FIG.
It is assumed that the input is for the contour reproducing section at%. 2A to FIG.
When 1 (a) is used, 1 is obtained from E = F = 1.
A contour like 1 (c) is obtained. On the other hand, by using FIG. 21B in FIG. 22B, E ′ = F ′ = 1, and
″ Becomes 1, and the contour as shown in FIG. 21A is obtained.
As described above, the contour regeneration block is formed by using the thinned-out data at the time of enlargement, and the regeneration processing is performed, so that the contour regeneration having the same detection power as that at the same magnification can be performed at the time of 200% enlargement. .

In this example, the 200% enlargement was described, but the same processing can be performed when the scaling ratio is changed.

<Character Image Correction Circuit> Character image correction circuit E
Performs the following processing on each of the black character, the color character, the halftone image, and the halftone image based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing relating to black characters [1-1] Signal Bk obtained by smear extraction as video
Using Mj112 [1-2] Y, M and C data are multi-valued achromatic color signals GR
Subtraction is performed according to 125 or a set value. On the other hand, Bk
The data is added according to the multi-valued achromatic color signal GR125 or the set value. [1-3] Edge emphasis is performed [1-4] Black characters are high resolution 400 lines (400 dp
Print out in i) [1-5] A residual color removal process described below is performed.

[Processing 2] Processing relating to color characters [2-1] Performing edge enhancement [2-2] Color characters are high resolution 400 lines (400 dp).
Print out at i).

[Process 3] Process on Halftone Image [3-1] Smoothing (two pixels in the main scanning direction in this embodiment) is performed as a measure against moire.

[Process 4] Process for Halftone Image [4-1] Smoothing (two pixels in the main scanning direction) or through can be selected.

Next, a circuit for performing the above processing will be described.

FIG. 26 is a block diagram of the character image correction section E.

The circuit of FIG. 26 includes a selector 6e for selecting the video input signal 111 or the BkMj 112, an AND gate 6e 'for generating a signal for controlling the selector, a block 16e for performing a residual color removal process described later, and enabling of the same process. AND gate 16e ', GR for generating a signal
A multiplier 11e 'for multiplying the signal 125 by the set value 10e of the I / O port, a selector 11e that selects the multiplication result 10e or the set value 7e of the I / O port according to the output 12e of the I / O port 3, 6e outputs 13e and 11e
15e for multiplying the output 14e of
e and the output 9e of the I / O port 4, the XOR gate 20e, the AND gate 22e, and the adder / subtractor 2
4e, line memory 26 for delaying 1-line data
e, 28e, edge enhancement block 30e, smoothing block 31e, selector 33e for selecting through data or smoothing data, control signal S of the selector
Delay circuit 32 for synchronizing the CRN 127
e, a selector 42e for selecting a result of edge enhancement or a result of smoothing, a control signal MjAr1 of the selector 42e
A delay circuit 36e for synchronizing 24, an OR gate 39e and an AND gate 41 which take the logical sum of the output 37e of the delay circuit 36e and the output of the I / O port 8.
e, an inverter circuit 44e for outputting a high-resolution 400-line (dpi) signal (“L” output) to the character determination unit,
AND circuit 46e, OR circuit 48e and video output 1
13 and a delay circuit 43e for synchronizing the LCHG 49e. In addition, the character image correction unit E
It is connected to the CPU bus 22 via the O port 1e.

[1] Color residual removal processing for removing the color signal remaining around the edge of the black character portion and subtraction at a certain ratio with respect to the Y, M and C data of the black character portion determination portion, and with respect to the Bk data. Is a portion where addition is performed at a certain ratio, [2] edge enhancement for a character portion, smoothing for a halftone dot determination portion, a portion for selecting through data for other gradation images, and [3] an LCHG signal for a character portion. To "L" (high resolution 4
(Printing at 00 dpi) will be described below.

[1] Color Remaining Removal Processing and Addition / Subtraction Processing Here, both the signal GRBi 126 which is an achromatic color and the signal MjAR124 which is a character portion are active, that is, processing for the edge portion of a black character and its peripheral portion. Therefore, the Y, M, and C components protruding from the edge portion of the black character are removed and the edge portion is smeared.

Next, a concrete operation will be described.

This processing receives the character part determination (MjAR1
24 = “1”), which is a black character (GRBi126 =
"1") and the print mode is the color mode (DH
i122 = “0”) only. Therefore,
It is not performed in the ND (black and white) mode (DHi = "1") or in the color character (GRBi = "0").

When an original is scanned for any of the recording colors Y, M, and C, the video input 1 is selected by the selector 6e in FIG.
11 is selected (I / O-6 (5e) is set to "0"). At 15e, 20e, 22e and 17e, data to be subtracted from the video data 8e is generated.

For example, if "0" is set in the I / O-3 12e, the output data 1 of the selector 6e
3e and the value set in the I / O-17e and selected by the selector 11e are multiplied by the multiplier 15e. Here, 0 to 1 times the data 18e is generated with respect to 13e. By setting 1 in the registers 9e and 25e, the 2's complement data of 18e is generated by 17e, 20e and 22e. Finally, since the addition 23e of 8e and 23e is the two's complement by the adder / subtractor 24e, the subtraction of 17e-8e is actually performed and output from 25'e.

When "1" is set by the I / O-3 12e, the B data is selected by the selector 11e.

At this time, the value set by the I / O-2 10e in the multi-valued achromatic signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit I is set to 9e. Is multiplied by 13e and used as a multiplier of 13e. When this mode is used, the coefficient can be changed independently for each color of Y, M, and C, and the subtraction amount can be changed according to the achromaticity.

During the recording color Bk scan, BkMj 112 is selected by the selector 6e ("1" is set in I / O-65e). At 15e, 20e, 22e, and 17e, data to be added to the video 17e is generated. Above Y,
The difference from M and C is that by setting "0" in I / O-4, 9e, this results in 23e = 8e, Ci = 0, and 17e + 8e is output from 25e. Coefficient 14e
Is generated in the same manner as in Y, M and C. Also, I /
In the mode where "1" is set in O-3 12e,
The coefficient changes according to the achromaticity. Specifically, when the achromaticity is large, the addition amount is large, and when the achromaticity is small, the addition amount is small.

This processing is illustrated in FIG. 27 in which the hatched portion of the black character N is enlarged (a) and (c).
Where the character signal portion is "1" for Y, M, or C video data, subtraction from the video is performed ((b) in the figure), and for the Bk video data, the character signal portion is Is added to the video data, the addition is performed ((d) in the figure). In this figure, 13e = 18e, that is, Y, M, C data of the character portion is 0, and Bk data is twice the video data.

By this processing, the outline portion of a black character is printed with almost a single black color, but the Y, M, C data outside the outline signal shows the portion marked with * in FIG. It remains unsightly because it remains around.

The process of removing the remaining color is the color separation removal processing. This processing is performed in a range in which the character portion area is widened, and the pixel where the video data 13e is smaller than the comparator value set by the CPU 20, that is, there is a possibility that there is residual color outside the character portion. About before and after 3
This is a process for taking the minimum value of pixels or 5 pixels.

Next, a supplementary explanation will be given using a circuit.

FIG. 28 shows a character area expansion circuit which functions to expand the character area. DF / F 65e to 68e.
AND gates 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e.

I / O ports 70e, 72e, 74e, 7
When all "1" are set in 6e, MjAr124 is "1".
In contrast to the above, the signals expanded by two pixels in the front-back direction in the main scanning direction are I / O ports 70e, 75e "0", 71e, 73.
e When “1”, the signal that is expanded by 1 pixel in the front and rear direction in the main scanning direction
It is output from ig2 18e. This switching signal is shown in FIG.
Is input to the AND gate 16'e.

Next, the color residue removal processing circuit 16e will be described.

FIG. 29 is a circuit diagram of the color residue removal processing.

In FIG. 29, 57e is the input signal 13e.
On the other hand, a 3-pixel min select circuit that selects the minimum value of the target pixel and one pixel before and after that, a total of three pixels, and 58e selects the maximum value of the target pixel and two pixels before and after that, a total of five pixels, for the input signal 13e. To do. 5 pixel min select circuit, 55
e is a comparator that compares the magnitude of the input signal 13e with the magnitude of the I / O-18 (54e), and if 54e is larger, 1
Is output. 61e, 62e are selectors, 53e, 5
3'e is an OR gate and 63e is a NAND gate.

In the above configuration, the selector 60e is the CP
Based on the value of I / O-19 from the U bus 22, either 3 pixel min or 5 pixel min is selected. The effect of removing the residual color is greater for the 5 pixels min. This can be selected by manual setting by the operator or automatic setting by the CPU. It should be noted that the number of pixels min to be taken can be set arbitrarily.

The selector 62e is a NAND gate 63e.
Output is "0", that is, the video data 13e is judged to be smaller than the register value 54e by the comparator 55e, and the signal of the character portion is expanded to the range 1
If 7'e is 1, the A side is selected; otherwise, the B side is selected. (However, at this time, the registers 52e, 64
e is "1", register 52'e is "0")

When the B side is selected, the through data is output as 8e.

The EXCON 50e outputs, for example, a luminance signal of 2
When a digitized signal is input, it can be used instead of the comparator 55e.

By performing the color residue removal processing as described above, it is possible to remove dust in the color around the characters and obtain a clearer image.

FIG. 25 shows the place where the above two processes are performed. 30 (a) is a black character N, and FIG.
(B) is an area determined to be a character in the Y, M, and C data that is the density data in the shaded area, that is, the character determination unit (*
2, * 3, * 6, * 7) are reduced to 0 by subtraction processing, * 1,
* 4 becomes * 1 ← * 0, * 4 ← * 5 due to the color residue removal processing, and as a result, becomes 0, and FIG. 30C is obtained.

On the other hand, for B and data as shown in FIG. 31 (a), the character determination section (* 8, * 9, * 10, * 11)
Is subjected to only the addition processing, and an output with a black contour is prepared as shown in FIG.

The color characters are not changed as shown in FIG. 31 (c).

[2] Edge Enhancement or Smoothing Processing Here, the edge determination is performed for the character determination unit, the smoothing is performed for the halftone dot portion, and the process of outputting through is performed for the others.

Since the character part → MjAR124 is "1", the output of the 3 × 3 edge enhancement 30e generated from the signals of the three lines 25e, 27e, and 29e is the selector 42.
It is selected by e and output from 43e. Here, the edge emphasis is obtained from the matrix and the calculation formula as shown in FIG.

Halftone dot area → SCRN35e is "1", MjA
Since R21e is "0", smoothing 31e is applied to 27e, but selectors 33e and 42e
Is output. Note that the smoothing here is shown in FIG.
As shown in (b), when the pixel of interest is V _N (V _N +
A process in which V _{N + 1} ) / 2 is used as V _N data, that is, main scanning 2
Pixel smoothing. This prevents moire that may occur in the halftone dots.

Other → The other part is a process for a part which is neither a character part (character outline) nor a halftone part, specifically, a halftone part. At this time, MjAR124 and S
Since both CRNs 35e are "0", the data of 27e is output from the video output 43e as it is.

When the character is a color character, the above two processes are not performed even in the character determining section.

In the embodiment, the example in which the color residue is removed only in the main scanning direction is shown, but the color residue removal processing may be applied to both the main scanning and the sub scanning.

The types of edge enhancement filters are not limited to those described above.

Further, smoothing may be performed over both main scanning and sub scanning.

[3] Character part high resolution 400 lines (dpi)
Output processing Synchronize with video output 113 from 48e to LCHG140
Is output. Specifically, the inverted signal of MjAR124 is output in synchronization with 43e. LCHG for letters
(200/400 switching signal) = 0, other parts are LC
HG = “1”.

As a result, the character portion determination portion, specifically, the contour portion of the character is printed with a high resolution 400 lines (dpi) and the other is printed with a high gradation 200 lines by a laser beam printer.

FIG. 32 shows a soft key screen of the liquid crystal touch panel 1109 in the operation unit 1000 for changing the condition of the character image separation process of this embodiment.

In this embodiment, five kinds of conditions can be selected by soft keys. The softkey positions are configured from the left as weak, -2, -1, standard, and strong. Each of these will be described below.

The [weak] weak position is for avoiding an erroneous determination that always occurs when copying an indistinguishable original such as a line drawing. In order not to generate the contour signal, the position of 123I in FIG. Set the limiter value to an appropriate value.

As shown in FIG. 33 (a), in the standard, the limiter level is in the bright portion of the document (limiter value = 158 in this embodiment). Values above this limiter value are
As shown in FIG. 33B, the limiter value is clipped. When the position of this limiter level is [weak], it is clipped to 0 by setting it to 0 as shown in FIG. 33 (c), as shown in FIG. 33 (d). Therefore, all the binarized outputs of the comparator 3 (126I) in FIG. 16 become 1 (or 0), the contour is not extracted, and the black character processing as described above is not performed on the read image signal. In this way, the generation of the contour signal is prevented at the [weak] position, so that the processing is not performed in the separated part of the image area.

At positions [-2] [-1] -2 and -1, erroneous determinations in a document in which characters and images are mixed are made inconspicuous. The gradation resolution switching signal LCHG is controlled so that the black character of the character part separated at the time of standard document copying has a black outline in the character part and that part is imaged with high resolution. Therefore, in the case of "-2, -1", all the control of the gradation resolution signal is made the same as that of the image part, and the ratio of Y, M, C is "-1", "-" without making the black character a black color. As the number decreases to 2 ", it increases. As a result, control is performed so that the image difference of the processed image due to the determination result is not known.

Description will be made with reference to FIGS. 34 (a) to 34 (e).
The figure (a) is the read image data, which becomes darker as the value increases and becomes lighter as the value decreases. In the image area separation in the present embodiment, the processing is performed for the two pixels of the contour portion as shown in FIG. 7A, and when the soft lever displayed on the touch panel α is [standard] and [strong], Y, As for M and C, as shown in the figure (b), regarding black characters and lines, toner of Y, M, and C is not printed on the two pixels of the contour portion, and when Bk, the black line or characters are better. Sharpness (c) As shown in the figure, the ratio of the contour portion is increased. In the modes [-1] and [-2], as shown in FIG. (D), the toner is slightly deposited on the contours for Y, M, and C, and for Bk as shown in (e). To Bk
The ratio of is reduced.

[Standard] With respect to "standard", the above-described processing is performed.

[Strong] With "Strong", parameters are set so that an erroneous determination is not made regarding characters, and that thin characters, light characters, etc. are black only. Specifically, by increasing the value of the limiter 3 (123I in FIG. 16) of the contour signal, the contour signal in the highlight portion can be extracted.

As described above, by changing the image area separation condition and the processing based on the separation according to the image to be read, erroneous determination can be avoided or obscured.

Further, since the limiter value can be easily changed by the CPU 20, the circuit structure is not complicated.

The strength of the black character processing is not limited to that set in five steps. In particular, by setting it in another stage, it becomes possible to select a process that matches the original image.

<Relationship with Mode Selection> Next, processing according to the output color mode selection, such as the four-color mode, the three-color mode, and the single-color mode, will be described.

The digital color copying machine has a function of copying in a color different from the original color, for example, a function of copying a full-color original in monocolor. Further, generally, in the part where the image areas are separated, a process of changing the color balance is performed in order to clearly show the characters. Therefore, when the above-described processing is performed on the input image after separating the image area, the output image is significantly deteriorated.

Therefore, in the present embodiment, in order to provide an image processing apparatus which does not cause image deterioration due to a difference in output color mode, the conditions of the image area determination means or the processing means involved in the determination are set according to the output color mode. Changing.

That is, when the monochrome signal described in the masking section is selected, or when the three-color mode in which an image is formed only with Y, M, and C toners is selected, the input image processing by this image area separation processing is performed. Do not do

Specifically, the following processing is performed.

As shown in FIG. 33 (a), Y,
In the four-color mode in which four colors of M, C, and Bk are recorded, the limiter level is in the bright portion of the document (limiter value = 158 in this embodiment). A value equal to or larger than the limiter value is clipped to the limiter value as shown in FIG. 33 (c). This limiter level is Y, M,
In the case of the three-color mode in which the three colors of C are recorded, the output signals are all clipped to 0 by setting to 0 as shown in FIG. Therefore, the comparator 3 (126
All the binarized outputs in I) become 1 (or 0), the contour is not extracted, and the read image signal is not processed. In this way, in the three-color mode, the generation of the contour signal is prevented so that the processing is not performed in the separated part of the image area.

Also, in the case of the single color mode, the processing for extracting the character signal is not performed due to the same configuration as in the case of the above-mentioned three color mode.

As described above, in this embodiment, the discrimination means for discriminating whether the input image information is the image information or the character information based on the input image information, and the input information is processed according to the discrimination result. The color copying apparatus having the processing means has a color mode other than the normal copying, and in the color modes other than the normal copying, the processing according to the determination result is different from the normal processing. This makes it possible to simplify the processing and prevent erroneous determination.

<Relationship with Control of Lamp Light Amount> The same processing as that used in the conventional analog copying machine is required for the digital color copying machine as well.
A method is considered in which the background color of newspapers is skipped by changing the light intensity of the lamp.

However, when the light amount of the light source is changed, the level of the reflected light of the original document is also different, and accordingly, in the case of the separation method in which the character and the image are discriminated by the difference in brightness and darkness of the read image signal or the color, an erroneous determination is made. It tends to occur.

Therefore, in this embodiment, the character image discrimination condition is changed in accordance with the original reading light amount, so that the erroneous determination due to the character image discrimination due to the change in the light amount is eliminated.

First, the lamp light amount adjustment will be described. FIG. 35 shows a flow of adjusting the light quantity of the lamp. At the time of pre-scanning for detecting the position size and the like of the document, a total of 1500 points of data of 50 points in the main scanning direction and 30 lines in the sub-scanning direction at equal intervals are read, and the number of data of the document is counted (S1). Next, the maximum value in the data is detected (S
2) Count the number of data points within 85% to 100% of the maximum value (S3). At this time, this maximum value is 60
The light amount is adjusted (S7) only when the value is H or more (S4) and the point of 1/4 or more of the whole is 85% to 100% of the maximum value (S5). As the set light quantity, the maximum value is FF _H ,

[0196]

[Outside 16]

The value obtained by the above equation is set as the lamp light amount set value (S6).

On the other hand, when the maximum value of the data is less than 60H, or less than 1/4 of the total points are 85% of the maximum value.
When it is -100%, the lamp light amount is not adjusted.

Here, when the light amount adjustment is performed, the offset 2 (1190) and the offset 3 (1 in FIG. 16 are used.
24I) is set to a value larger than usual. This is because the dynamic range of the density of the read document is narrowed by increasing the light amount of the lamp, so that the noise component of the document is detected, resulting in erroneous determination in halftone detection and erroneous detection in contour extraction. Therefore, in order to prevent erroneous detection due to this noise component, the offset value is set to a large value only when the light amount is adjusted.

As described above, in the present embodiment, the original reading means for reading an image by optical scanning, the light quantity adjusting means for changing the light quantity of the reading light source according to the density of the read original, and whether the read image information is halftone information or not. In a copying machine having a discriminating means for discriminating whether it is character information and a processing means for processing input information based on the discrimination result, the discrimination condition is changed in accordance with the light amount adjustment.

In this embodiment, the lamp light quantity control is performed under a fixed condition, but the lamp light quantity control may be performed in all cases.

The sampling data during the prescan can be increased or decreased. Further, the threshold value for whether or not to adjust the light amount can be changed.

Further, the condition for distinguishing between the character and the image area may be selected from a plurality of stages according to the light amount adjustment.

<Character Image Synthesizing Circuit> Next, the character image synthesizing circuit F will be described. FIG. 37 is a block diagram of a processing / modification circuit for a binary signal of an image in this apparatus. Color image data 1 input from the image data input section
38 is input to the V input of the 3to1 selector 45f. The other two inputs A and B of the 3to1 selector 45f are
Of the lower part (A _n , B _n ) 555f of the data read from the memory 43f, A _n is input to A and B _n is input to B by being latched by the VCLK 117 in the latch 44f. Therefore, the output Y of the selector 45f is V, based on the select inputs X ₀ , X ₁ , J1, J2.
Either A or B is output (114). Data X _n
In the present embodiment, is the upper 2 bits of the data in the memory and is a mode signal that determines processing and modification. 13
Reference numeral 9 is a code signal output from the area signal generation circuit, and is controlled to switch in synchronization with VCLK117 by the control of the CPU 20 of FIG. 2 and is input as an address of the memory 43f. That is, for example, the memory 43f
At the address 10 of (X ₁₀ , A ₁₀ , B ₁₀ ) = (01,
A ₁₀ and B ₁₀ ) are written in advance, and as shown in FIG. 40B, in synchronization with the scanning of the line 1 in the main scanning direction, “10” is added from the P point to the Q point in the code signal 139 and from the Q point to the R point. If "0" is given up to, data _Xn = between P and Q
(0, 1) is read, and at the same time, (A _n , B _n ) has (A
_10, B _{1 0)} data that is latched output. 3t
The truth table of the o1 selector 45f is as shown in FIG.
(X ₁ , X ₀ ) = (0, 1) is the case of (B), and J
If 1 is "1", the A input is Y, therefore Y is a constant A _10, and if J1 is "0", V input is Y, and accordingly the input color image data is output as is 114. Means output to. Thus, for example, FIG.
A so-called plucked character composition of a character portion having a value of (A ₁₀ ) is realized for a color image of an apple like this.
Similarly, when (X ₁ , X ₀ ) = (1, 0) is set and a signal such as J1 in FIG. 40C is input to the binary input, FI
FO 47f to 49f, and circuit 46f (detailed view 38)
As a result, a signal as shown in J2 in the same figure is generated, and according to the truth table in FIG. 39, the characters are output with a frame in the apple image as shown in the figure (contour or bag character). . Similarly, in FIG. 40D, the rectangular area in the apple is output with a density of (B _n ), and the characters inside the apple are output with a density of (A _n ). In the figure (A), (X ₁ , X ₀ ) = (0,
In the case of 0), that is, with respect to any change of J1 and J2, there is a control that does nothing depending on the binary signal.

The signal with the expanded width input to J2 is expanded by 3 × 3 pixels according to FIG. 38, but it can be easily increased by adding a hardware circuit.

Here, the FH input to the FiFo 47f
The i signal 121 is a non-rectangular area stored in the 100 dpi binary memory L of FIG.
By using, it is possible to carry out various kinds of processing as described above.

The C0 and C1 (366, 367) output from the I / O port 501 of FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are the addresses of the memory 43f. Is input to the lower 2 bits of
Therefore, in correspondence with the outputs of Y, M, C and Bk, "0,
Since it changes from 0 "," 0,1 "," 1,0 "," 1,1 ", for example, when yellow (Y) is output, 0, 4, 8, 1
2, 16 ... Address, magenta (M) is 1, 5, 9, 13,
17 ... Address, cyan (C) is 2, 6, 10, 14, 18
... Address, 3, 7, 11, 15, 19 ... Address is selected for black (Bk). Therefore, for example, X1 to X4 = “1,1” (A1, A2, A3) are assigned to the addresses corresponding to the area code signal 139 that determines the area and the corresponding memory address in the area by an operation instruction on the operation panel described later. A
4) = (α1, α2, α3, α4), (B1, B2, B
3, B4) = (β1, β2, β3, β4) is written and, for example, when the J1 signal changes as shown in FIG. 40D, the section where J1 is “Lo” is (Y, M, C, Bk) =
The color is determined by (α1, α2, α3, α4), and when J1 is “Hi”, (Y, M, C, Bk) = (β
1, β2, β3, β4) is the color determined by the combination. That is, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described later, Y, M, C, and Bk are adjusted or set by (%) percent, respectively. That is, since each gradation has 8 bits, the numerical value is from 0 to 25.
Since it is 5, a variation of 1% is a digital value of 2.55. The setting value is (Y, M, C, Bk) = (y%, m%,
c%, k%), the set numerical values (that is, the numerical values written in the memory) are (2.55y, 2.
55m, 2.55c, 2.55k), which is actually a rounded integer written in a predetermined memory. Further, if the adjustment mechanism adjusts in%, the value obtained by adding (darkening) or subtracting (thinning) only 2.55Δ for the fluctuation of Δ% may be written in the memory.

As described above, according to this embodiment, Y, M,
The output colors of C and Bk can be designated for each color in units of 1%, and the operability of color designation is improved.

In the truth table of FIG. 39, the column of i is the input / output table of the character, the gradation of the image, and the resolution switching signal LCHG149, which is A or B depending on X ₁ , X ₀ , J1 and J2.
Is output to the output Y, the input is output as it is when V is output to the Y. LCHG 149 is, for example, a signal for switching the print density at the time of printing at the time of output, and when LCHG = “0”, for example, high resolution 400
When dpi and LCHG = “1”, printing is performed with high gradation of 200 dpi. Therefore, when A or B is selected, LCHG
= 0 means that the inside area of the character synthesized character is 40
Areas other than 0 dpi and characters are printed at 200 dpi. Characters are controlled to maintain high resolution and sharpness, and halftone portions maintain high gradation and smooth output. This is also the reason why the LCHG 140 outputs from the character / image correction circuit E based on the output of the character / image separation circuit I, MJAR, as described above.

<Image Processing / Editing Circuit> Next, the image signal 115 and the gradation resolution switching signal LCHG141 after receiving the color balance adjustment at P in FIG. 2 are input to the image processing / editing circuit G. A rough schematic diagram of the image editing / processing circuit G is shown in FIG.

The input image signal 115 and gradation resolution switching signal LCHG141 are first processed by the texture processing unit 1.
Input to 01g. The texture processing unit is roughly divided into a memory unit 103g for storing a texture pattern.
And the memories RD and WR for controlling the same, the address control unit 104g, and the arithmetic circuit 105 for performing the modulation processing on the input image data by the stored pattern.
g. The image data processed by the texture processing unit 101g is then input to the scaling, mosaic and taper processing unit 102g. The scaling, mosaic, and taper processing unit 102g includes a double buffer memory 105.
g, 106g, and a processing / control unit 107g, various processings are independently controlled and output by the CPU 20. Here, the texture processing unit 101g and scaling,
The mosaic / taper processing unit 102g uses the GHi1 (11) which is an enable signal for each process sent from the switching circuit N.
9) and GHi2 (149) are configured so that texture processing and mosaic processing can be performed on independent areas.

Further, the gradation resolution switching signal LCHG signal 141 inputted together with the image data 115 is processed in various editing processes while matching the phase with the image signal. Hereinafter, the image processing / editing circuit G will be described in detail.

<Texture Processing Unit> The texture processing is processing for cyclically reading out the pattern written in the memory and modulating the video.
For example, an image as shown in FIG. 42 (a) is modulated with a pattern as shown in FIG. 42 (b) to generate an output image as shown in FIG. 42 (c).

FIG. 43 is a diagram for explaining the texture processing circuit. Hereinafter, the writing portion of the modulation data 218g to the texture memory 113g, the data 216g from the texture memory 113g and the image data 215g.
The calculation unit (texture processing) will be described separately.

[Data Writing Unit to Texture Memory 113g] When writing data, the color correction circuit D that performs masking, undercolor removal, stain extraction, etc.

[0216]

[Outside 17] Is output, and data is input from 201g. This data is selected by the selector 202g. On the other hand, the data 220 is selected by the selector 208g and input to the WE of the memory 113g and the enable signal of the driver 203g. The selector 210g is generated by the vertical counter 212g that counts up in synchronization with the memory address horizontal synchronization signal HSYNC and the horizontal counter 211g that counts up in synchronization with the image clock and VCK.
B is selected at and is input to the address of the memory 113g. In this way, the density pattern of the input image is written in the memory 113g. In this pattern, a position on the original is designated by an input device, for example, a digitizer 58, and image data obtained by reading that portion is stored in the memory 113g.
Is written to.

[Write of Data by CPU] The CPU data is selected by the selector 202g. On the other hand, A is selected by the selector 208g and W of the memory 113g is selected.
E and the enable signal of the driver 203g. A is selected as the memory address by the selector 210g,
Input to the address of the memory 113g. Thus, an arbitrary density pattern is written in the memory.

[Texture memory 113g data 2
Calculation unit of 16 g and image data 215 g] This calculation is realized by the calculator 215 g. This arithmetic unit is composed of an arithmetic unit here. Only when the enable signal 128g is active, the data 216g and 201g are calculated, and when the enable signal 128g is disabled, 201 is in the through state.

In addition, 300 g and 301 g are XO respectively.
When "0" is set in the register 304g "1" 305g, which is a portion for generating an enable signal using the MJ signal 308g by the R and OR gates, that is, the character composite signal, the composite character signal is included in the texture processing. It will be applied to other parts. On the other hand, the register 304g "0" 30
When "0" is set in the register at 5g, only the portion where the synthetic character signal is included in the portion to which the texture processing is applied is applied.

Reference numeral 302g is a portion for generating an enable signal using the GHi1 signal 307g, that is, a non-rectangular signal. When the register 306g is "0", the texture processing is performed only where the GHi1 signal is enabled. At this time, if the enable 128 is kept active all the time, it is not influenced by the non-rectangle, that is, the non-rectangular texture processing synchronized with the HSNC is performed, and if the enable signal GHi1 and the enable 128 are the same, the non-rectangular signal is synchronized. It becomes texture processing. If a 31b bit signal is used for GHi1, it is possible to perform texture processing only on a certain color.

The LCHG _IN signal 141g is a gradation resolution switching signal, which is delayed by the calculator 215g and output from the LCHG _OUT 350g. Thus, in the texture processing unit, the gradation resolution switching signal LC
The HG 141 is also subjected to a predetermined delay process to correspond to the image after the texture process.

<Mosaic, Scaling, and Taper Processing Unit> Next, the outline operation of the mosaic, scaling, and taper processing unit 102g of the image processing / editing circuit G will be described with reference to FIG.

Mosaic, scaling, taper processing unit 102g
Image data 126g and LCHG signal 3 input to
50 g is first input to the mosaic processing unit 401 g.
The mosaic processing section 401g outputs the Mj signal 145 output from the character synthesizing circuit F and the area signal G from the switching circuit N.
Hi2 (149), the mosaic clock MCLK from the mosaic processing control unit 402g, the presence / absence of mosaic processing, the size of the mosaic in the main scanning direction, and the combination of characters are performed, and then input to the 1to2 selector 403g. The area signal GHi2 is based on the non-rectangular area information stored in the binary memory L of FIG. 2, and this signal enables mosaic processing on the non-rectangular area. Here, the size of the mosaic processing in the main scanning direction is the clock M for mosaic.
It is variable by controlling CLK. The control of the mosaic clock MCLK will be described in detail later.

With the 1to2 selector 403g, the HSY
A line memory select signal LMSEL obtained by dividing the NC 118 by the D flip-flop 406G outputs the input image signal and LCHG signal to either Y1 or Y2.

The output from Y1 of the 1to2 selector 403g is connected to the line memory A 404g and A of the 2to1 selector 407g. The output from Y2 is connected to the line memory B405g and B of the 2to1 selector 407g. When an image is sent to the line memory A from the selector 403g,
The line memory A 404g is in the writing mode, and the line memory B 405g is in the reading mode. Similarly, when an image is sent from the selector 403g to the line memory B 405g, the line memory B is in the writing mode and the line memory A 404g.
Becomes the read mode. In this way, the image data alternately read from the line memory A 404g and the line memory B 405g is output as continuous image data while being switched by the 2to1 selector 407g by the inversion signal of the output LMSEL signal of the D flip-flop 406g. The output image signal from the 2to1 selector 407g is output after being subjected to predetermined enlargement processing by the enlargement processing unit 414g.

Next, writing / reading control of these memories will be described. First, when writing and reading,
Line memory A404g, line memory B405g
The address given to the up / down counter 409 is synchronized with HSYNC which is a reference for one scan and is incremented / decremented in synchronization with the image CLK.
g, 410 g. The counter enable signal output from the line memory address control unit 413g, the control signal WENB for controlling the write address generated from the scaling control unit 415g, and the control signal RENB for controlling the read address.
Thus, the operation of the address counters (409g, 410g) is controlled. These controlled address signals are input to the 2to1 selectors 407g and 408g, respectively. 2to1 selector 407g, 408g
In response to the line memory select signal LMSEL, the line memory A 404g gives a read address to the line memory A 404g and a write address to the line memory B 405g in the read mode. What is this when the line memory A404g is in write mode?
The reverse operation is performed. Next, the memory write pulses WEA and WEB to the line memory A and line memory B are output from the scaling control unit 415g. The memory write pulses WEA and WEB are controlled when the input image is reduced and when the mosaic processing is performed by the mosaic length control signal MOZWE in the sub scanning direction output from the mosaic processing control unit 402g. Next, a detailed description of these operations will be given below.

<Mosaic Processing> The mosaic processing is basically realized by repeatedly outputting one image data. This mosaic processing operation will be described with reference to FIG.

First, the mosaic processing control unit 402g independently performs mosaic processing control for main scanning and sub scanning.
First, set the variable corresponding to the desired mosaic size to CPUB.
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub scanning) connected to US. First, for the mosaic processing in the main scanning direction, by writing the same data continuously to multiple addresses in the line memory, and for the mosaic processing in the sub scanning direction,
In the mosaic processing area, writing to the line memory is performed by thinning out every predetermined line.

(Mosaic processing in main scanning direction) A variable corresponding to the mosaic width in the main scanning direction is latched by the CPU 501g.
Is set to The latch 501g is connected to the main scanning mosaic width control counter 504g, and is connected to the HSYNC.
The set value is configured to be loaded by the ripple carry of the signal and the counter 504g. HSYNC
The value set in the latch 501g for each counter 504
g is loaded, a predetermined value is counted, and then ripple carry is carried out, and NOR gate 502g and AND gate 509g.
Output to The mosaic clock MCLK from the AND gate 509g is a signal obtained by spreading the image clock CLK by the lip carry from the counter 504g, and MCLK is output only when the ripple carry occurs. The MCLK output from the AND gate 509g is then input to the mosaic processing unit 401g.

The mosaic processing section 401g outputs the two D flip-flops 510g and the flip-flop 510g regardless of the Mj signal. Mosaic clock MCL when the GHi2 signal 149 is 1 and the Mj signal is 0
A signal from the flip-flop 511g controlled by K is output. When the Mj signal is 1, the output is the signal from the flip-flop 510g. With this control,
It is possible to output a part of the image in the mosaic-processed image in the main scanning direction without performing the mosaic processing. That is, with respect to the character synthesized in the image by the character synthesizing circuit F in the preceding stage as shown in FIG. 2, the mosaic processing of only the image can be performed without performing the mosaic processing. The output from the selector 512g is the 2to1 selector 403g shown in FIG.
Is input to As described above, the mosaic processing in the main scanning direction is performed.

(Subscanning direction mosaic processing) The latch 502 connected to the CPUBUS in the subscanning direction is also the same as the main scanning.
g, and counter 505g, NOR gate 503g
Is controlled by Sub-scanning mosaic width control counters are ITOP signals 144, 511g, selector 512.
g, an AND gate 514g, and an inverter 513g. A gradation resolution switching signal LCHG is connected to the flip-flops 510g and 511g in addition to an image signal. The flip-flop 510g is an image clock CLK, and the flip-flop 511g is an image data input by a mosaic processing clock MCLK. ,
And holds the LCHG signal. That is, the grayscale resolution switching signal LCHG corresponding to one pixel is supplied to the flip-flops 510g and 511g in a state of being in phase with each other by CLK and M.
It is held during each cycle of CLK. Each held image signal and LCHG signal is 2 to 1
It is input to the selector 512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. The selector 512g is

[0232]

[Table 1] The operation shown in the truth table of the above figure is performed by the AND gate 514g,
The inverter 513g is used. That is, the ripple carry pulse is generated by synchronizing with the case where the mosaic area signal GHi2 signal 149 is 0 and counting the HSYNC 118. The ripple carry pulse is applied to the OR gate 508g by the mosaic area signal GHi.
The inverted signal GHi2 of 2149 and the character signal Mj are input.

[0233]

[Table 2] The sub-scanning mosaic control signal MOZWE signal is controlled as shown in the truth table of the above figure. The MOZWE signal output in such a combination is used by the scaling controller 415.
The NAND gate 515g controls the write pulse generated by the line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit having a variable output clock rate such as a rate multiplier which is generally used for scaling control. This embodiment is different from the gist of the invention, and therefore, detailed description is omitted. As for the WR pulse controlled by the MOZWE signal, the WR pulse is alternately output from the 1to2 selector to the WEA and the WEB by the switching signal LMSEL signal in which the switching pulse is changed for each HSYNC 118. By the above control, even when the mosaic area signal GHi2 signal 149 is "1", when the Mj signal becomes "1", since writing to the memory is performed, a part of the mosaic-processed image in the sub-scanning direction is written. It is possible to output without mosaic processing. FIG. 46 is a diagram showing a distribution of density values for each pixel for a recording color when the mosaic processing is actually performed. In the mosaic processing of FIG. 46, 3 × 3
Each pixel in the pixel block is set to a representative pixel value. At the time of this processing, the mosaic processing is not performed on the character A, that is, the pixels in the shaded area based on the character signal Mj. That is, when the composite character and the mosaic processing area overlap, the character can be prioritized. Therefore, even when the mosaic processing is performed, an image can be formed so that only characters can be read. The mosaic area is not limited to a rectangle, and a mosaic process can be performed on a non-rectangular area.

(Italic processing, taper processing) Next, the italic processing will be described with reference to FIGS. 44 and 51.

The line memory address control unit 41 of FIG.
The inside of 3 g is shown in FIG. The line memory address control unit 413g uses the write / read counter 40
The enable signals of 9g and 410g are controlled, and which part in one line of main scanning is written in the line memory,
By controlling the address counter to read or write, it is possible to move or italicize. First, the enable control signal generation circuit will be described with reference to FIG.

The counter 701g has a counter output of 0 at HSYNC, and then counts the image clock 117 which is the clock of the counter 701g. The output Q of the counter 701g is the equal surface comparator 706g,
It is input to 708g, 709g, and 710g. The A input side of each comparator other than the comparator 709g is
Each of them is connected to an independent latch (not shown) connected to the CPUBUS 22, and a pulse is output when an arbitrary set value matches the output of the counter 701g. The output of the iso-surface comparator 706g is output to J of the JK flip-flop 708g, and the comparator 707
g is connected to the K input, and the JK flip-flop 708g is configured to output 1 until the comparator 706g outputs a pulse and the comparator 707g outputs a pulse. This output is used as a write address counter control signal, and the write address counter is in an operation state only in a period where it is 1, and an address is generated for the line memory. Similarly for the read address counter control signal,
Controls the read address counter. A selector 703g is connected to the input signal to the comparator 709g for differentiating the input value to the comparator depending on whether the italic processing is performed or not. If the italic processing is not performed, the CPUBUS (not shown)
The value set in the latch connected to 22 is input to the A input of the selector 703g, and similarly, the A input is output from the selector 703g by the select signal output from the latch not shown. Subsequent operations are the same as those of the comparators 706g and 707g described above. When italicized next, the value input to A of the selector 703g is also input to the selector 702g as a preset value. When the select signals of the selectors 702g and 703g select the B input, the selector 702g
Is output by an adder 704g, which is also added to a value set in a latch (not shown). Here, this value represents the amount of change for each line depending on the italic angle, and is calculated by tan θ where θ is the desired angle. The result of addition is flip-flop 7 when HSYNC 118 is clocked.
It is input to 08g and the value is held for one main scan. The output of the flip-flop 705g is the selector 702g.
And the B input of the selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scanning, so that the start of the read address counter can be changed at a constant rate from HSYNC. This allows the line memory A4
The reading from 04g and B405g is shifted with respect to HSYNC, and the italic processing becomes possible. Further, the above-mentioned change amount may be positive or negative, and when it is positive, it shifts in the direction in which the reading is separated from HSYNC, and when it is negative, it shifts in the direction in which it approaches HSYNC. Further, by changing the select signals of the selectors 702g and 703g in synchronization with HSYNC, italicization can be partially achieved.

Regarding the enlargement processing method, generally, 0th order, 1st order
Next, there is a method such as SINC interpolation, but since it is different from the gist of the present invention, description thereof is omitted. While performing italic processing,
The taper process can be performed by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line.

Further, as in the case of the mosaic processing and the texture processing, the above processing can also be performed on the non-rectangular area according to the non-rectangular area signal GHi.

Further, in these processes, the input gradation resolution switching signal is processed while being in phase with the image signal. That is, the switching signal LCHG 142 undergoes the same processing according to the processing of the image signal in each processing such as scaling, italicization, and taper. Then, the output image data 114 and the output gradation resolution switching signal LCHG 142 are output to the edge emphasis circuit.

47 and 48 are conceptual diagrams of the italic processing and the taper processing described above.

<Contour Processing Unit> FIGS. 49 (a) and 50 show
It is a figure explaining outline processing. In this embodiment, FIG.
As shown in (a), a signal inside a character or an image (inside broken line in (I) diagram, (II) FIG. 103Q) and an outside signal (outside broken line in (I) diagram, (II) FIG. 102Q) are displayed. The contour is extracted by generating the logical product of both signals.
In the timing diagram (FIGS. 49 (a) (II)), 10
1Q is a signal obtained by binarizing a multi-valued original signal with a predetermined threshold value, and indicates a boundary portion with the background of the original image (hatched portion) in FIG. On the other hand, 102Q is a signal obtained by expanding the “Hi” portion of 101Q to thicken the character portion (a signal after thickening processing), and 103Q degenerates the “Hi” portion of 101Q to generate the character portion. Is a signal obtained by further inverting the signal obtained by thinning (the signal after the thinning processing). 104Q is the result of the logical product of 102Q and 103Q, and is the extracted contour signal. The shaded portion of 104Q indicates that a wider contour is extracted. This means that a wider width can be selected in 102Q and a larger degeneracy width can be selected in 103Q. To be extracted. That is, the width of the contour can be changed. Figure 50
FIG. 38 is an example of a circuit diagram for realizing the contour processing described with reference to FIG. This circuit is provided in the image processing / editing circuit G in FIG. Input multi-valued image data 13
Reference numeral 8 denotes a comparator 2q, which compares the magnitude with a predetermined threshold value 116q to generate a binary signal 101q. Threshold 11
6q is an output of the data selector 3q, which is a color to be printed by a CPU (not shown), yellow, magenta, cyan,
The value set in the register group 4q for each black, r1,
From the outputs 110q to 113q from r2, r3, and r4,
This is a signal selected and output by the selector 3q corresponding to the same color. That is, it is possible to output 2 for each color by the signals 114q and 115q that are switched for each color from the CPU (not shown)
The threshold for binarization is made variable so that the effect of color contour can be made variable. The data selector 3q is, for example, (114q,
115q) = (0,0), (0,1), (1,0),
In (1, 1), A, B, C and D are selected respectively, and each corresponds to the threshold values of yellow, magenta, cyan and black. The binary signal 101q is stored in the line buffers 5q to 8q for 5 lines and is output to the thickening circuit 150q and the thinning circuit 151q in the next stage. 150q is a circuit for generating the signal 102q, which is 5 × 5.
If at least one of the 25 (or 9) pixels in the (or 3 × 3) small pixel block has “1”, the value of the central pixel is determined to be “1”. That is, FIG. 49 (a)
2 pixels (or 1) with respect to the original image (hatched portion) of (I)
The outer signal 0 for pixels) is formed. Similarly, 151q is a circuit for generating the signal 103q, which is 5 × 5 (or 3 ×).
1) out of 25 (or 9) pixels in the small pixel block of 3)
If there is at least "0", it operates so as to determine the value of the central pixel to "0". This forms the signal I inside two pixels (or one pixel) in FIG. 49 (a) (I). Therefore, as described in FIGS. 49 (a) and (II), 102q and 10
The logical product of 3q is taken by the AND gate 41q to generate the contour signal 104q. As can be seen from the circuit operation, the signals 110q and 111q correspond to the above-mentioned small pixel block 3 × 3.
Or 3 × 3 is selected, (110q, 111q) = (0,1)
The contour width at this time is two pixels because the thick one pixel and the thin one pixel. When 5 × 5 is selected, (110q, 111q) = (1, 1), and similarly the contour width is 4 pixels wide. This is a CPU (not shown) so that the operator can switch it according to the intended use or desired effect.
Controlled by the I / O port connected to the.

In FIG. 50, a selector 45q is a selector for switching whether to output the original signal 138 as it is or to output the extracted contour, and either A or B is selected based on the output of the selector 45'q. It The selector 45'q outputs an inverted signal of the contour signal 104q and an I / O port connected to a CPU (not shown). E
One of the DSL signals is output as the select signal of the selector 45q. At that time, the CPU selects the selector 45 '.
The select signal SEL is input to q.

The selector 44q is a selector for selecting fixed values r5 and r6 set in the registers 42q and 43q by the CPU in accordance with the contour signal 104q. All of the selectors 44q, 45q, 45'q select A when the switching terminal S = 0 and B when S = 1.

Now, "1" is set to the switching terminal of the selector 45'q.
Is input, the B side terminal is selected and the selector 4
5q is switched by a signal ESDL output from an I / O port connected to a CPU (not shown). And E
When SDL = "0", the A side of the selector 45q is selected to be the normal copy mode, and when ESDL = "1", the B side is selected to be the contour output mode. q42 and q43 are registers in which fixed values r5 and r6 are set by a CPU (not shown). When the contour output mode is selected, the contour output 104q is "0", the value of r5, and 104q is "1". The value of r6 is output. That is, for example, r5 = 00 _H ,
Assuming that r6 = FF _H is set, FIG. 49 (b)
The contour part is FF _{H, that} is, black, and the other part is 00 _H ,
That is, it becomes white and a contour image is formed. Since the values of r5 and r6 are programmable, different effects can be obtained by changing them for each color. That is, it is not always necessary to set FF _H and 00 _H, and two different levels such as FF _H and 88 _H may be set.

On the other hand, when "0" is set to the switching terminal S of the selector 45'q, the A side is selected, and the switching signal S of the selector 45q receives the inverted signal of the contour signal 104q. Then, in the selector 45q, the original data on the A side is output to the contour portion, and to the portions other than the contour portion, 00 _H selected by the selector 44q among the fixed values on the B side, that is, white, is output. In this way, it is possible to perform processing on the contour portion using multivalued original data instead of fixed values for each of Y, M, C, and K.

As described above, according to this embodiment, Y, M,
The operator can arbitrarily select a mode for outputting a binary contour image for each of C and K (multi-color contour processing mode) and a mode for outputting a multivalued contour image (full color contour processing mode).

The threshold for contour extraction is also set in the register 4
By setting r1, r2, r3, r4 to q,
Different values can be set for each of Y, M, C and K. The value can be appropriately rewritten by the CPU.

By selecting the matrix size, the width of the contour can be changed, and the contour image of different images can be obtained.

The contour extraction matrix is the above 5 ×.
The number is not limited to 5 and 3 × 3, and can be freely changed by increasing or decreasing the number of line memories and gates.

The contour processing circuit Q shown in FIG. 50 is provided in the image processing / editing circuit G shown in FIG. The image processing / editing circuit G also includes a texture processing unit 101g,
A scaling, mosaic, and taper processing unit 102g are provided, but since these are connected in series, any processing can be freely combined by operating the operation unit 1000 described below. Further, the order of various processes can be freely set by arranging the processing units in parallel and combining the selectors.

In this embodiment, each color component input to the contour processing circuit Q is binarized to obtain a contour signal for each color component, and a contour image is output in a color corresponding to the color component. However, it is not limited to such a method, for example,
Read signal R (red), G (green), B (blue)
It is also possible to generate an ND image signal from the above, extract a contour based on the ND image signal, and apply original multi-valued data or predetermined binary data for each recording color to the contour portion to form a contour image. At that time, the ND image signal can be generated based on any of the R, G, and B signals. Especially, the G signal is a neutral density signal (ND image signal).
Since the characteristics are closest to, it is effective to use this directly as the ND signal from the viewpoint of the circuit configuration and the like.

Also, an NTSC Y signal (luminance signal) may be used.

<Non-Rectangular Area Storage Unit> Next, a means for storing the non-rectangular area designated in the present invention will be described.

Conventionally, in the designated area editing process, the designated area is a rectangle or a non-rectangular figure 56 (a) in which the number of input points is limited, and the mixed figure 56 of the rectangle and the non-rectangle.
Only (b) was possible. Therefore, there are the following drawbacks.

That is, as shown in FIG. 57, the red color "F
Since it is not possible to perform the process of converting the character "uji" into a free color and converting it to green, or making only the red cloud part into blue paint, the editing process is extremely limited.

Therefore, in this embodiment, by providing a memory for storing the non-rectangular area, it is possible to cope with such advanced editing processing.

FIG. 52 is a block diagram showing details of the mask bitmap memory 573L for controlling the area of an arbitrary shape and its control. This memory is shown in Figure 2.
Corresponds to 100 dpi memory L in the whole circuit of
For example, in the shape as shown in FIG. 55, various image processing and editing operations such as the above-described color conversion, image cutting (non-rectangular trimming), and image filling (non-rectangular paint) are turned on.
It is used as a means for generating (processing) and OFF (not processing) switching signals. That is, in FIG. 2, the color conversion circuit B, the color correction circuit D, the character synthesizing circuit F, the image processing / editing circuit G, the color balance circuit P, and the external device image synthesizing circuit 502 are used as switching signals for ON and OFF, respectively. BHi123, DHi122, FHi1
21, GHi119, PHi145, and AHi148 signal lines.

The “non-rectangular” described here does not mean that a rectangle is excluded, and a rectangular area is also included in the non-rectangular area.

Since the mask has 4 × 4 pixels as one block as shown in FIG. 64 and one bit of the bit map memory corresponds to one block, for example, an image having a pixel density of 16 pel / mm is provided. Then, 297m
For m x 420 mm (A3 size), (297 x
420 × 16 × 16) ÷ 16≈2 Mbit, that is,
For example, 1 Mbit dynamic RAM, 2 chips
Can be composed of

The signal 132 input to the FIFO 559L in FIG. 52 is the non-rectangular area data input line for mask generation as described above. As the signal 132, for example, the output signal 421 of the binarizing circuit 532 in FIG. 2 is input through the switching circuit N.

A signal from the reader unit A or the external device interface M is input to the binarization circuit.
When the signal 132 is input, it is first input to the buffers 559L, 560L, 561L and 562L for 1 bit × 4 lines in order to count the number of “1” in the 4 × 4 block. The FIFOs 559L to 562L are connected such that the output of 559L is connected to the input of 560L and the output of 560L is connected to the input of 561L as shown in the figure. The output of each FIFO is connected to latches 563L to 565L in 4 bits in parallel and V
It is latched by CLK (see the timing chart in FIG. 54). FIFO output 615L and latch 563
L, 564L, 565L outputs 616L, 617L,
618L is added in addition periods 566L, 567L, 568L (signal 602L), and the magnitude is compared with a value (for example, "12") set by the CPU 22 in the comparator 569L via the I / O port 25L. . That is, here, it is determined whether or not the number of 1's in the 4 × 4 block is larger than a predetermined number.

In FIG. 54, the number of "1" s in the block N is "14", and the number of 1s in the block (N + 1) is
Since it is "4", the output 603L of the comparator 569L of FIG. 52 is "12" when the signal 602L is "14".
When it is "1" and "4", it is "0" because it is smaller than "12". Therefore, the latch pulse 6 of FIG.
05L causes the latch 570L to latch once in one block of 4 × 4, and the Q output of the latch 570 is stored in the memory 573.
It becomes the D _IN input of L, that is, the mask creation data. 5
Reference numeral 80L is an H address counter for generating an address in the main scanning direction of the mask memory. Since one address is assigned in a 4 × 4 block, the pixel clock VCLK6
08 is counted up by a frequency divider 577L by 4 to count up. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, the divider 574L counts up by a clock obtained by dividing the synchronizing signal HSYNC of each line by 4 to obtain an H address, The operation of the V address is controlled so as to be synchronized with the counting (addition) operation of "1" in the 4 × 4 block.

Further, the lower 2 bits of the output of the V address counter, 610L and 611L, are NOR gates 572L.
A signal 606L that gates the clock 607L divided by 4 is generated, and the AND gate 571L is used to latch only once in the 4 × 4 block as shown in the timing chart of FIG. 53 (b). Signal 6
05L is made. 616L is the CPU bus 22
This is a data bus included in (FIG. 2), and non-rectangular area data can be set in the bitmap memory 573L according to an instruction from the CPU 20. For example, as shown in FIG. 55, a circle or an ellipse is calculated by the CPU 20 (the procedure will be described later), and the calculated data is stored in the memory 57.
By writing to 3L, a fixed non-rectangular mask can be generated. At this time, for example, the radius and center position of the circle can be designated by the numeric keypad of the operation unit 1000 (FIG. 2) or input by the digitizer 58. 61
Similarly, 3L is an address bus, and signal 615L is C
It is a write pulse WR from the PU 22. During the WR (write) operation from the CPU 22 to the memory 573L, the write pulse becomes “Lo”, and the gates 578L, 576L,
581L is opened and the address bus 613 from the CPU 22 is opened.
L, the data bus 616L is connected to the memory 573L,
When predetermined non-rectangular area data is written at random, and when WR (write) and RD read are performed sequentially by the H address counter and V address counter, the gate 576 'connected to the I / O port 25L
L and 582L control lines enable gates 576'L and 582
L opens and sequential address is memory 573L
Is supplied to.

For example, if a mask as shown in FIG. 65 is formed by the output 421 of the binarized output 532 or the CPU 22, the image can be cut out, combined or the like based on the area in the thick line frame.

Further, the bit map memory 573 shown in FIG.
L is thinned out in both the H and V directions at the time of reading,
Alternatively, it is possible to reduce or enlarge and read by interpolation. That is, as shown in detail in FIG. 66 for the H or V address counter (580L, 575L) in FIG. 52, for example, the MULSEL 636L is set to "0" so that the B input of the selector 634L is selected during reduction. The selection signal 636L is sent through the CPU 22.
Reference numeral 635L is a thinning circuit (rate multiplier) for the input clock 614L, and as shown in FIG. 67 (timing diagram), it is thinned out so that CLK is output once every three times (setting is I / O port 641L). by)
(637L). On the other hand, for example, "2" is set in 630L, and only when the thinned output 637L is output, the values (for example, "2") set in the outputs 638L and 639L of the address counter 632L are added, and the result is Loaded on the counter. Therefore, as shown in FIG.
1 → 2 → 3 → 5 → 6 → 7 → 9 ... and “+” every 3 clocks
By 2 ", it will be reduced by 80%. On the other hand, when expanding, MUL
Since SEL = “1” and the A input 614L is selected, the address count proceeds in the order of 1 → 2 → 3 → 3 → 4 → 5 → 6 → 6 → ... As shown in the timing chart of FIG.

FIG. 66 shows the H address counter 58 of FIG.
Details of the 0L and V address counter 575L and the hardware circuit are the same, so the description will be limited to FIG.

By controlling this address counter, FIG.
Enlarged 2 to the non-rectangular area 1 that was immediately input, such as 8
Since the reduction 1 is generated, once the non-rectangular area is input, it is possible to change the magnification according to various magnifications with one mask plane without performing new input work.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be described. In FIG. 69, a binarization circuit 532 is a circuit that compares the video signal 113 output from the character image correction circuit E with a threshold value 141k to obtain a binarized signal. The threshold value is linked to the operation unit by the CPU bus 22. Is set. That is, the threshold value is the amplitude value of the input data = 256, and the memory of the operation unit in FIG. 7 is set to M (middle point).
When it is specified to, it is "128", and as the scale moves in the + direction, it changes by "-30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "weak → -2
→ -1 → M → + 1 → + 2 → strong ”corresponding to the threshold of“ 2
It is controlled so as to change in the order of 18 → 188 → 158 → 128 → 98 → 68 → 38 ”.

Further, as shown in FIG. 69, CPUB
From US22, two kinds of thresholds are set, and the selector 35k switches the thresholds by the switching signal 151 and sets the thresholds in the comparator 32k. The switching signal 151 from the area generation circuit J is such that another threshold value is set only within the specific area set by the digitizer 58. For example, the threshold value is relatively low in the single color area of the document, and the mixed color area is set. Can be set relatively high so that a uniform binary signal can always be obtained regardless of the color of the original.

The memory circuit K outputs the binarized signal 421.
Is a memory for storing the signal output to 130 for one page of an image, and this apparatus has a size of A3, 400 (dp
Since the image is handled at the density of i), about 32 Mbi
have t. Details of the memory circuit K will be described with reference to FIG. The input data D _IN 130 is gated by the enable signal HE 528 from the area generation circuit J at the time of memory writing, and further, W / R 1 from the CPU 20 at the time of writing.
When the signal 549 is "Hi", it is input to the memory unit 37k. At the same time, the synchronization signal HSYNC118 in the main scanning (horizontal scanning) direction is supplied from the synchronization signal ITOP144 in the vertical direction of the image.
To generate a vertical address. The V-address counter 35k and the HSYNC 118 count the image transfer clock VCLK117 to count horizontal addresses. An address corresponding to the storage of the image data is generated by the H address counter. At this time, a clock having the same phase as the clock VCLK117 is input as a strobe to the memory WP input (write timing signal) 551k, and the input data Di is input.
Are sequentially stored in the memory unit 37k (timing diagram,
72). When reading data from the memory 37k,
By setting the control signal W / R 1 to “Lo”, the output data D _OUT is read out in exactly the same procedure. However,
Data writing, reading, since both carried out in HE528, for example, the HE528 as in FIG. 72 D ₂
When it is raised to "Hi" at the input timing of Dm and lowered to "Lo" at the input timing of Dm, only the images from D ₂ to Dm are input to the memory 37k, and D ₀ ,
Data is not written after D ₁ and D _{m + 1} , and data “0” is written instead. The same applies to reading, and data "0" is read except in the section where HE is "Hi". HE is a region signal generation circuit 1 described later.
7 is output. That is, for example, FIG.
If a character document such as A is placed and HE is generated as shown in the drawing when writing the binarized signal, the binary image can be captured in the memory only by the character portion as in A '. Similarly, unnecessary characters and the like can be erased and written to the memory.

Further, since the address counters 35k and 36k for reading the data of the main memory 37k have the same configuration as that of FIG. 66 and operate at the same timing as that of FIG. 67,
As described above, the binary data read from 37k can be scaled. Therefore, when synthesizing a binary character image as shown in FIG. 74B, which is stored in advance in this memory as shown in FIG. 74, into an image of FIG. It is possible to perform composition or composition such as enlarging only the character part to be composed without changing the size of the sketch (the part (A)) as in (D).

FIG. 75 is a binary bit map memory L for non-rectangular mask stored at the above-mentioned 100 dpi equivalent.
(Figure 2) and 400dpi binary memory K for characters and line images
Each image processing block A, B, of data from (FIG. 2)
A switching circuit for distributing to D, F, P, and G, switching between distributing binarized video images to memories L and K, and performing real-time selectable output of rectangular and non-rectangular area signals. . The rectangular / non-rectangular area real-time switching will be described later. The mask data for limiting the non-rectangular area stored in the memory L is sent to, for example, the above-mentioned color conversion circuit B (BHi123), for example, as shown in FIG.
Color conversion is applied only to the inside of the shape as shown in FIG. In FIG. 75, 1n is an I / O connected to the CPU bus 22.
The ports, 8n to 13n, are 2to1 selectors, and are configured to output the A input when the switching input S = “9” and the B input to the Y when S = “0”. So, for example,
As described above, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B, the selector 9n selects A, that is, 28n = “1”, and the AND gate 3n.
In, the 21n input may be set to "1". Similarly,
Other signals can be arbitrarily controlled by 16n to 31n.
Outputs of the I / O port n1, 30n and 31n are control signals for storing the output of the binarization circuit 532 (FIG. 2) in the binary memories L and K. When 30n = “1”, 2 Value input 421 to 100 dpi memory L, 31n = “1”
At that time, the data is input to the 400 dpi memory K. By the way, when AHi148 = “1”, the image data sent from the external device is combined, and when BHi123 = “1”, the color conversion is performed as described above, and DHi122 =
When "1", monochrome image data is calculated and output from the color correction circuit. Hereinafter, FHi 121, PHi 14
5, GHi1 119, and GHi2 149 are used for character composition, color balance change, texture processing, and mosaic processing, respectively.

As described above, the 100 dpi memory L and the 40
By having two binary memories of 0 dpi memory K, character information is input to high density 400 dpi memory K, and area information (including rectangular and non-rectangular) is input to 100 dpi memory L. Character composition can also be performed on a rectangular area.

Further, by having a plurality of bit map memories, color map processing as shown in FIG. 92 becomes possible.

FIG. 77 is a diagram for explaining the area signal generating circuit J. In FIG. The area refers to, for example, a hatched portion in FIG. 79 (a), which is a signal such as the timing chart AREA in FIG. 79 (a) for each line in the section in the sub-scanning direction A → B. Is distinguished from other areas. Each area is designated by the digitizer 58 in FIG. 77 (a)-
(C), FIG. 78 shows the generation position, section length,
The number of sections is programmable by the CPU 20 and a large number of sections are obtained. In this configuration, 1
The area signal of the book is generated by 1 bit of the RAM accessible by the CPU, and for example, the area signals AREA0 to A of the n areas are generated.
In order to obtain REAn, it has two n-bit RAMs (60j and 61j in FIG. 78). Now, FIG. 77
Assuming that area signals AREA0 and AREAn as shown in (b) are obtained, bit 0 of RAM addresses x ₁ and x ₃
Is set to "1" and bit 0 of the remaining address is set to "0". On the other hand, RAM addresses 1, x ₁ , x
₂ and x ₄ are set to “1” to set all the bits n of other addresses to “0”. When the RAM data is sequentially read out in synchronization with the constant clock 117 with the HSYNC 118 as a reference, for example, as shown in FIG. 77 (c), the data "1" is read out at the points of the addresses x ₁ and x _3. . This read data is shown in FIG.
Since it is in both J and K terminals of the JK flip-flops of -0 to 62j-n, the output is a toggle operation, that is, R
When “1” is read from AM and CLK is input, the output changes from “0” → “1”, “1” → “0”, and ARE
An interval signal such as A0, and thus a region signal, is generated.
Also, if data = "0" across all addresses,
No region section is generated and no region is set. FIG. 78 shows this circuit configuration, and 60j and 61j are the above-mentioned RAMs. This is because in order to switch the area section at high speed, for example, while the data is being read from the RAMA 60j line by line, the CPU
As shown in FIG. 2, the memory writing operation for setting different areas is performed, and the interval generation and the memory writing from the CPU are alternately switched. Therefore, FIG. 49 (f)
When the hatched area is designated, RAMA and RAMB are switched as in A → B → A → B → A.
In (b), (C ₃ , C ₄ , C ₅ ) = (0, 1,
0), the counter output counted by VCLK117 is used as an address and RA is output through the selector 63j.
It is given to the MA 60j (Aa), and the gate 66j is opened and the gate 68j is closed to be read from the RAMA 60j.
0 to 62j-n, and AR depending on the set value
A section signal of EA0-AREAn is generated. C to B
During the writing from the PU, the address bus A-Bu is supplied during this period.
s, data bus D-Bus, and access signal R / W
By. On the contrary, when a section signal is generated based on the data set in the RAMB 61j (C ₃ , C ₄ , C ₅
) = (1,0,1)
Data can be written from the CPU to the RAMA 60j.

Reference numeral 58 is a digitizer for designating an area, and the coordinates of the designated position are input from the CPU 20 through the I / O port. For example, in FIG. 80, two points A and B
Is specified, the coordinates of A (X ₁ , Y ₂ ) and B (X ₂ , Y ₁ ) are input.

In FIG. 58, when images of a rectangular area and a non-rectangular area are mixed in one original,
It is a figure explaining the method of performing a process and an edit process. sgl
1 to sgln and ArCnt are rectangular area signals, and outputs AREA0 to AREAn of the rectangular area generation circuit shown in FIG.
Is a signal like.

On the other hand, Hi is a non-rectangular area signal, and the output 1 of the bit map memory L and its control circuit shown in FIG.
It is a signal like 33.

Sgl1 to sgln (h _{21 to} h _2n ) are enable signals for the respective edit processing, and the rectangular areas are enabled wherever the edit processing is desired. On the other hand, for the non-rectangular area, only the rectangular area inscribed in the non-rectangular area is enabled. Specifically, FIG.
As shown in FIG. 3, the rectangular area indicated by the dotted line is enabled with respect to the non-rectangular area indicated by the solid lines A and B.

ArCnt (h ₃ ) is enabled for the rectangular area in synchronization with sgl1 to sgln. On the other hand, the non-rectangular area is disabled.

Hi (h ₂ ) is enabled in the non-rectangular area for the non-rectangular area. It is disabled for rectangular areas.

The Hi signal h ₂ and the ArCnt signal h ₃ are ORed together.
The logical sum is calculated in the circuit h ₁ , and the logical product of the logical sum is calculated in the AND circuits h _{31 to} h _3n and sgl 1 to sgln (h _{21 to} h _2n ).

Thus, the outputs out1 to outn (h ₄₁ to
From h _4n ), a desired rectangular area signal and non-rectangular signal can be mixed.

58 to 62 are views for explaining what each input signal looks like when the rectangular area signal (B) and the non-rectangular area signal (A) are mixed.

As described above, sgl1 to sgln (FIG. 60) are enabled for a rectangular area which inscribes the entire area for a rectangle and the non-rectangular area for a non-rectangle.

As described above, Hi (FIG. 61) is disenabled for a rectangle and is disabled for a non-rectangle.

ArCnt In FIG. 62, the entire area is enabled for the rectangle and the entire area is disabled for the non-rectangle as described above.

Finally, the correspondence between FIG. 58 and FIG. 75 will be described.

The OR gate h ₁ in FIG. 58 corresponds to 38 in FIG.
AND gate h _{31 of} FIG.
-H _3n are in 4n to 7n and 32n in FIG. 75, the area signals in FIG. 58, sgl1 to sgln (h _{21 to} h _2n ) are in 33n to 37n in FIG. 75, and the outputs out1 to outn in FIG.
(H _{41 to} h _4n ) are DHi, FHi, PHi, GHi1,
It corresponds to GHi2.

As described above, it is possible to edit and process a plurality of areas in which a rectangular area and a non-rectangular area are mixed in one original.

As described above, according to this embodiment, means for designating a rectangular area (area signals sgl1 to sgln)
Means for specifying a non-rectangular area (hit signal Hih ₂ ), real-time selecting means for the rectangular area and non-rectangular area (AN
By providing the D gate h ₃₁ ~h _3n), it is possible to perform the editing processing rectangular area specified and non-rectangular area designation are mixed in one document.

In particular, according to this embodiment, the signals sgl1 to sgl1.about.
Since n is a rectangular area in which the non-rectangular area is inscribed, it is possible to select rectangular / non-rectangular according to the non-rectangular area signal Hi and the rectangular area signal ArCnt.

Area designation according to the nature of the area to be designated, for example, a rectangle can be designated when rough designation is required, and a non-rectangle area can be designated when high precision is required. Can be done efficiently.

The number of regions, that is, the number of AND gates can be set freely. Also, the type of processing performed in each area is I based on the input from the operation unit 1000.
It can be freely determined by setting the / O port 1n.

FIG. 81 shows an interface circuit M for bidirectional communication of image data with an external device connected to the image processing system. 1m is CPU bus 22
I / O port connected to each of the data buses A0 to A0
Signals 5m to 9m for controlling the directions of C0, A1 to C1 and D
Is output. 2m and 3m are bus buffers having an output dry state control signal E, and 3m can change its direction by D input. E input for 2m and 3m =
When it is "1", a signal is output, and when it is "0", it is in an output high impedance state. 10 m is a 3 tol selector that selects one from the parallel inputs A, B and C of three systems by selecting signals 6 m and 7 m. In this circuit, basically 1. (A0, B0, C0) → (A1, B1, C
1), 2. There is a bus flow of (A1, B1, C1) → D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, as shown in FIG. 53, an image input from an external device through A1, A2 and A3 can be either rectangular as shown in FIG. 83A or non-rectangular as shown in FIG. I am taking it. FIG.
In the case of inputting a rectangular shape such as 3 (A), the control signal 14 from the I / O port 501 is set so that the switching input of the selector 503 in FIG. 2 is set to "1" so that A is selected.
7 is output. At the same time, it corresponds to the area to be combined. As described above, the rectangular area signal 129 is generated by writing the predetermined data from the CPU to the predetermined addresses of the RAMs 60j and 61j (FIG. 81) in the area signal generation circuit J. Image input 128 from an external device is selector 5
In the area selected in 07, not only the image data 128 but also the gradation and resolution switching signal 140 are switched at the same time. That is, in the area where the image from the external device is input, the gradation / resolution that is generated based on the character area signal MjAR124 (FIG. 2) detected from the color separation signal of the image read from the document table. By stopping the switching signal and forcibly setting it to "Hi", the image area from the external device to be fitted is smoothly output with high gradation. Further, as described with reference to FIG. 81, the bit map mask signal AHi148 from the binary memory L is sent to the selector 50.
3 is selected by the signal 147, image composition from an external device as shown in FIG. 83B is realized.

<Outline of Operation Unit> FIG. 84 shows an overview of the operation unit 1000 of the main body of this embodiment. The key 1100 is a copy start key. A key 1101 is a reset key, and returns all the settings on the operation unit to the values when the power was turned on. Key 1
A clear stop key 102 is used for resetting input numerical values such as the number of sheets to be specified and for canceling the copy operation. A group of keys 1103 is a ten-key pad used to input numerical values such as the number of copies and magnification. A key 1104 is a document size detection key. A key 1105 is a center movement designation key.
A key 1106 is an ACS function (black document recognition) key.
When ACS is ON, a black monochromatic original is copied in black. A key 1107 is a remote key, and is a key for giving a control right to the connected device. Key 1108 is a preheat key.

A liquid crystal screen 1109 displays various information. In addition, the surface of the screen is a transparent touch panel, and when pressed with a finger or the like, its coordinate value is captured.

In the standard state, the magnification, the selected paper size, the number of copies, and the copy density are displayed. While various copy modes are being set, the screens required for mode setting are sequentially displayed. (The copy mode is set using the keys displayed on the screen.) The self-diagnosis display screen of the guide screen is displayed.

A key 1110 is a zoom key, and is an enter key for entering a mode for designating a magnification for zooming. Key 1
Reference numeral 111 denotes a zoom program key, which is an enter key for entering a mode in which a scaling factor is calculated from a document size and a copy size. A key 1112 is an enlarged continuous shooting key, and is an enter key for the enlarged continuous shooting mode. A key 1113 is a key for setting inset combination. A key 1114 is a key set by character composition. A key 1115 is a key for setting color balance. A key 1116 is a key for setting a color mode such as monochrome / negative / positive inversion. A key 1117 is a user's color key and can set an arbitrary color mode. A key 1118 is a paint key, and a paint mode can be set. A key 1119 is a key for setting the color conversion mode. A key 1120 is a key for setting the contour mode. The key 1121 sets the mirror image mode. Keys 1124 and 1123 specify trimming and masking. An area can be designated by the key 1122, and the internal processing can be set differently from other portions. A key 1129 is an enter key for a mode for performing work such as reading a texture image. A key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

A key 1127 is an enter key for a mode for adjusting the sharpness of the edge of the output image. Key 112
Reference numeral 6 is a key for setting the image repeat mode for repeatedly outputting the designated image.

A key 1125 is a key for applying a slanted / tapered image processing or the like. A key 1135 is a key for changing the movement mode. A key 1134 is used to make settings such as page continuous shooting and arbitrary division. A key 1133 is used to make settings relating to the projector. A key 1132 is an enter key for a mode for controlling an optional connected device. The key 1131 is a recall key, and the set contents up to three times before can be called. The key 1130 is an asterisk key. Keys 1136 to 1139 are mode memory calling keys, which are used when calling the registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used when calling the registered operation program.

<Color conversion operation procedure> The color conversion operation procedure will be described with reference to FIG.

First, the color conversion key 1119 on the operation unit of the main body.
When is pressed, the display unit 1109 is displayed as P050. Place the original on the digitizer and specify the color before conversion with a pen. When the input is completed, the screen of P051 is displayed. Here, the touch key 1050 and the touch key 1051 are used to adjust the width of the color before conversion, and the touch key 10 after the setting is completed.
Press 52. The screen changes to P052, and the touch key 1053 and the touch key 1054 are used to select whether to add shade to the converted color. If the shade is selected, the converted color also has a gradation in accordance with the shade of the color before conversion. That is, the above-described gradation color conversion is performed. On the other hand, if no shading is selected, it is converted to a designated color having the same density. If you select with / without shading, P053
Will be displayed and select the type of color after conversion. If 1055 is selected in P053, the operator can specify an arbitrary color in P054. Also, if you press the color adjustment key, P055
Then, the color adjustment can be performed in 1% steps for each of Y, M, C, and Bk.

When pressing 1056 on P053, P05
Move to 6 and specify the desired color of the original on the digitizer with the point pen. Further, the shade of color can be adjusted with P057.

[0305] When pressing 1057 on P053, P05
Moving to No. 8, a predetermined registered color can be selected by a number.

<Procedure for Specifying Trimming Area> Hereinafter, with reference to FIGS. 86 and 87, trimming (the same applies to masking, and the area specifying method is similar to partial processing). An area designation procedure will be described.

Trimming key 1 on main unit operation unit 1000
When the user presses 124 and inputs two diagonal points of the rectangle using the digitizer when the display unit 1109 becomes P001, P0
The screen of 02 is displayed, and the rectangular area can be continuously input. If multiple areas are specified, P001
By pressing the previous area key 1001 and then the area key 1002, each designated area in the XY coordinates can be confirmed as in P002.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. While the screen P001 is being displayed, the touch key 1003 is pressed to move to P003. Select the shape here. Yen, oval, R
When a necessary coordinate value is input to the rectangle or the like, the CPU 20 calculates the shape in the bitmap memory. In the case of a free shape, the coordinate values are continuously input by tracing the desired shape with the point pen using the digitizer 58,
The value is processed and recorded on the bitmap.

Each of the non-rectangular area designations will be described below.

(Circular area designation) P003 key 1004
When is pressed, the display unit 1109 moves to P004 and a circular area can be designated.

Designation of a circular area will be described below with reference to the flowchart of FIG. In S101, the center point is input from the digitizer 58 in FIG. 2 (P00
4). Next, the display unit 1109 moves to P005 and S103
At, a digitizer 58 inputs one point on the circumference of a circle having a radius to be designated. FIG. 2 bit map memory L (100 dpi binary memory) of the input coordinate values in S105.
The coordinate values above are calculated by the CPU 20.

Also, in S107, the coordinate value of another point on the circumference is calculated. Next, in S109, the bank of the bitmap memory L is selected, and in S111, the calculation result is input to the bitmap memory L via the CPU bus 22. In FIG. 52, the data is written from the CPU DATA 616L through the driver 578L to the bit map memory from 604L. The address control is the same as that described above, and will be omitted. This is repeated for all points on the circumference (S113), and the circular area designation is completed.

Note that, instead of inputting while calculating in the CPU 20 as described above, the template information for the information of two points inputted in advance is stored in the ROM 11 and the calculation is performed by designating these two points with the digitizer. It is also possible to write directly to the bitmap memory L without the need.

(Oval area designation) In P003, when the key 1005 is pressed, the process moves to P007. This will be described below with reference to the flowchart of FIG. 89.

First, in S202, the two diagonal points of the largest rectangular area inscribed in the ellipse are designated by the digitizer 58. The circumferential portion is written into the bitmap memory L in the procedure of S206 to S212 in the same manner as in the case of designating the circular area.

Next, regarding the straight line portion, S214 to S220
The procedure is to write to the memory L and finish the area designation. As in the case of a circle, RO is used as template information in advance.
It can also be stored in M21.

(R rectangular area designation) This is the designation method,
Since it is similar to the case of the ellipse when writing to the memory, the description is omitted.

The case of a circle, an ellipse and an R rectangle has been described above as an example, but it is needless to say that other non-rectangular areas can be designated based on similar template information.

P006, P008, P010, P102
In, the clear key (1009-10
By pressing 12), partial erasure on the bitmap memory can be performed.

Therefore, even if a mistake is made in designation, only two points can be cleared immediately and only two points can be designated again.

Further, it is also possible to successively designate a plurality of areas. In the case of specifying a plurality of areas, the processing of the area specified later is prioritized in performing each processing on the overlapping area. However, for this, the priority may be given to the one specified earlier.

FIG. 87 shows an output example in which trimming is performed on the oval with the above settings.

<Operating Procedure for Character Synthesis> FIG. 9 below
0, FIG. 91, and FIG. 92, the operation setting procedure regarding character synthesis will be described. Character synthesis key 11 on the operation panel
When 14 is pressed, the liquid crystal display unit 1109 is displayed as P020. Character original 120 to be combined on the above-mentioned original table
When 1 is placed and the touch key 120 is pressed, the text original is read, binarization processing is performed, and the image information is stored in the above-mentioned bitmap memory FIG. Since the specific means of the processing has been described above, duplication is avoided. To specify the range of the image to be stored at this time, press the touch key 1021 in P020 to go to the screen of P021, place the text original 1201 on the digitizer 58 described above, and use the point pen of the digitizer to set the range with two points. specify. When the designation is completed, the display section becomes as shown in P022, and it is selected whether to read within the range designated by the touch keys 1023 and 1024 (trimming) or outside the designated range (masking). Further, for some character documents, it is difficult to extract a character portion in the character document during the above-described binarization process. In this case, it is possible to move to the screen of P023 with the touch key 1022 in P020 and adjust the slice level of the binarization processing with the touch keys 1025 and 1026.

Since the slice level can be manually adjusted in this way, an appropriate binarization process can be performed according to the color and thickness of the characters on the document.

Further, the touch key 1027 is pressed, and P0
P0 by specifying the area with 24 ', P025'
It is possible to partially change the slice level at 26 '.

As described above, by specifying the area and changing the slice level only for that portion, even if there is, for example, a yellow character in a part of the black character manuscript, different appropriate slices are provided for the black character and the yellow character, respectively. By setting the level, excellent binarization processing can be performed on the entire character.

Of course, at that time, such processing can be performed according to the non-rectangular area information stored in the binary memory L of FIG.

When the reading of the text original is completed, the display unit 110
9 is as shown in FIG. 91P024.

To select the color blanking process, the touch key 1027 in P024 is pressed to move to the screen of P025, and the color of the character to be combined is selected from the displayed colors. It is also possible to partially change the character color. In that case, the touch key 1029 is pressed to move to the screen of P027, the area is designated, and then the character color is selected on the screen of P030. It is also possible to add color border trimming processing to the borders of the combined characters. In that case, P03
Touch key 031 in 0 to move to the screen of P032,
Select the border color. At this time, the color can be adjusted
This is similar to the case of the above color conversion. Touch key 103
3 is pressed, and the border width is adjusted on the screen of P041.

Next, the case where the coloring process is added to the rectangular area containing the character to be combined (hereinafter referred to as the mud process) will be described. Press the touch key 1028 in P024 and press P034.
Move to the screen of and specify the area. Mado processing is performed in the range specified here. When area designation is completed, P
The character color is selected with 037, the touch key 1032 is pressed, and the screen for P039 is displayed to select the color of the mud.

In the above-mentioned color selection, for example, in the screen of P025, by pressing the color adjustment key of the touch key 1030, it is possible to move to the screen of P026 and change the color tone of the selected color.

Character synthesis is performed by the procedure described above.
FIG. 92 shows an output example when the settings are actually made.

In addition to the rectangular area designation, the area designation
It is also possible to specify the non-rectangular area as described above.

<Texture Processing Setting Procedure> Next, FIG.
The texture processing will be described using.

When the texture key 1129 on the main body operation unit 1000 is pressed, the display unit 1109 displays as P060. When applying the texture processing, the touch key 1060 is pressed to highlight this key. When the image pattern for texture processing is read into the texture image memory (113g in FIG. 43), the touch key 1061 is pressed. At this time, if the pattern is already in the image memory, the display is P061, as shown in P062. By placing the original of the image to be read on the original table and pressing the touch key 1062, the image data is stored in the texture image memory. At this time, in order to read an arbitrary portion of the document, the touch key 1063 is pressed, and designation is made by the digitizer 58 on the P063 screen. Designation is reading range, 1
It can be performed by pen-inputting the center of 6 mm × 16 mm with one point.

The reading of the texture pattern by designating one point as described above can be performed as follows.

Without reading the pattern, the touch key 1060 is pressed to set the texture processing, and the copy start key 1100 and other mode keys (1110-11
43), or when attempting to get out of the P064 screen with the touch key 1064 or the like, the display section gives a warning as shown in P065.

The reading range can be set so that the operator can specify the vertical and horizontal lengths using the ten keys of the operation unit 1000.

FIG. 94 shows a flowchart of the CPU 20 at the time of reading the texture pattern.

First, when in the texture mode, the coordinates of the center point of the portion used as a texture pattern on the original (a square is taken as an example in this embodiment, but another figure such as a rectangle) may be input from the digitizer 58. It is determined whether there is any (s1). At that time, the coordinate input is S
It is grasped by the (x, y) coordinates of the input point as shown in 1 '. If there is no coordinate input, wait for input, if there is input, horizontal direction, memory write start,
The address of the memory write end is calculated (s2 ') and set in the vertical counter (s2). At this time, a rectangular pattern can be obtained by making the side lengths a different in the horizontal direction and the vertical direction. Next, the scanner unit A scans, reads the image data, and writes the image data at the predetermined position in the texture memory 113g (FIG. 43). The storage operation of the texture pattern is completed as described above, and the normal copying operation is performed by the above-described method (s4) to synthesize the texture pattern.

According to this embodiment, the texture pattern can be read by designating one point on the digitizer, and the operability is greatly improved.

<Mosaic Processing Setting Procedure> FIG. 95 is a view for explaining the mosaic processing setting procedure.

When the mosaic key 1128 on the operation section of the main body is pressed, the display section is displayed as P100. To apply mosaic processing to the manuscript, press the touch key 1400,
Highlight this key.

To change the mosaic size when performing the mosaic processing, the touch key 1401 is pressed and the P101 screen is displayed. The change of the mosaic size can be set independently in both the vertical (Y) direction and the horizontal (X) direction.

FIG. 96 is a diagram showing a flow of the above-mentioned mosaic size setting. When the mosaic mode is set, the CPU 20 determines whether the mosaic size (X, Y) is input from the liquid crystal touch panel 1109 (s1). If it is not entered, it will wait for input,
When it is input, (X, Y) is entered in the mosaic processing register (in 402g of FIG. 45) in the digital processor.
Set the parameters of. Based on this, the mosaic processing is performed with the size of X mm in width and Y mm in length by the method described above.

As described above, in the present embodiment, since the mosaic size can be independently identified vertically and horizontally, it is possible to meet various needs for image editing processing. Especially, it is considered to be widely used in the field of design.

<Regarding Mode Operating Procedure> FIG. 97 shows *
It is a figure explaining a mode operation procedure.

When the * key 1130 on the main body operation unit 1000 is pressed, the * mode is entered, and the display unit 1109 is displayed as shown in P110. The touch key 1500 enters a color registration mode for registering color information used for paint user's color, color conversion, color characters, and the like. Touch key 1501
ON / OF the function to correct the image missing by the printer
F The touch key 1502 is a key for entering the mode memory registration mode. The touch key 1503 enters a mode for designating a manual feed size. The touch key 1504 enters the program memory registration mode. Touch key 15
Reference numeral 05 is a key for entering a mode for setting a color balance default value.

(Regarding color registration mode) When the touch key 1500 is pressed at the time of displaying P110, the color registration mode is entered. The display section looks like P111, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and adjust the value of each component of yellow, magenta, cyan, and black in 1% steps on the screen of P117. can do.

To register an arbitrary color on the original, press the touch key 1507, select the registration destination number on the screen of P118, specify it using the digitizer 58, and select P120.
When the screen is displayed, place the original on the platen and touch the key 15
Press 10 to register.

(Regarding manual feed size designation) As shown in P112, the manual feed size can be designated as either regular or non-standard.

As for the non-standard size, both the horizontal (X) direction and the vertical (Y) direction can be designated in units of 1 mm.

(Regarding Mode Memory Registration) The mode set as shown in P113 can be registered in the mode memory.

(Regarding program memory registration) P11
As shown in FIG. 4, it is possible to register a series of programs for performing area designation and predetermined processing.

(Regarding color balance registration) P115
As shown in, the color balance can be registered for each of Y, M, C, and Bk.

(Regarding program memory operation procedure)
The registration operation to the program memory and the use procedure thereof will be described below with reference to FIGS. 98 and 99.

The program memory is a memory function for storing the procedure of operation related to setting and reproducing it. It is possible to connect necessary modes and skip unnecessary screens. As an example, let's use a program memory to perform the procedure of image repeat by scaling a certain area in the document.

Press the * mode key 1130 on the main body operation unit to display the P080 screen on the liquid crystal display unit and touch key 1
Press the 200 program memory key. In this embodiment,
Four programs can be registered. Select the number to register on the screen of P081. Thereafter, the mode shifts to the program registration mode. In the program registration mode, for example, in the normal mode, the screen 1300 in FIG.
01. The skip key of the touch keys 1302 is designated when skipping the current screen. The clear key of the touch keys 1303 is used when the registration so far is canceled during the registration of the program memory and the registration is restarted from the beginning. The end key of the touch key 1304 goes out of the registration mode of the program memory and registers in the memory of the number determined first.

First, the trimming key 11 in the main body operation section
Press 24 and specify the area with the digitizer. The display section displays P084, but if the area is not set any further, press the touch key 1202,
It is designated to skip this screen (the screen becomes P085).

Next, when the zoom key 1110 on the operation section of the main body is pressed, the display section becomes P086. When the magnification is set here and the touch key 1203 is pressed, the display portion changes to P087. Finally, the image repeat key 1 on the operation panel of the main unit
After pressing 126 and setting for image repeat on the screen of P088, the touch key 1204 is used to register the number 1 in the program memory.

To call the program registered in the above procedure, the program memory 1 call key 1140 on the main body operation unit is pressed. The display unit displays P091 and waits for the area input. When the area is entered using the digitizer, P092 is displayed on the display and the next P0
Move to 93. After setting the magnification here, touch key 1
When 210 is pressed, the display becomes P094 and the image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (called a trace mode) is exited. In addition, until the program memory is called and it is finished, each key (1110-11
43) is invalidated, and the operation can be performed according to the registered program.

FIG. 101 shows a program memory registration algorithm. The screen turning in S301 means rewriting the display on the display unit with a key or a touch key. When the touch key 1302 is pressed to specify that the currently displayed screen be skipped (S303), that information is set on the recording table when the next screen is turned (S303).
305). Then, in S307, a new screen number is set in the recording table. When the clear key is pressed, all the recording tables are cleared (S309, S311), and in other cases, the process returns to S301 and moves to the next new screen. FIG. 103 shows the format of the recording table.
FIG. 102 shows an algorithm showing the operation after calling the program memory.

If the screen is turned over in S401, it is determined whether or not the new screen is the standard screen (S403). If it is the standard screen, the process proceeds to S411, the next screen number is set from the recording table, and if it is not the standard image, the new screen number and the planned screen number in the recording table are compared (S405). Moves to S409, and if there is a skip flag, skips S411 and returns to S401. If they are not equal, recovery processing is performed (S40
7) Turn the screen.

Next, the means for outputting the image by switching the printing resolution according to the present invention will be described. This means is configured to switch the printing resolution based on the resolution switching signal 140 generated according to the character portion and the halftone portion separated by the character image separating circuit I described above. This corresponds to the driver in FIG. In this embodiment, the character part has a high resolution of 400d.
The pi halftone part is printed at 200 dpi. The details will be described below. PW which is a part of the driver in FIG.
The M circuit 778 is included in the printer controller 700 of the printer 2 of FIG. 1, receives the video data 138 which is the final output of the entire circuit diagram of FIG. To do.

Below is a portion of the driver of FIG.
PWM that supplies the signal to output the laser beam
Details of the circuit 778 will be described.

FIG. 104A shows a block diagram of the PWM circuit, and FIG. 104B shows a timing diagram.

The input VIDEO DATA 138 is latched by the latch circuit 900 at the rising edge of VCLK117 and is synchronized with the clock (FIG. 104).
(B) 800,801). V output from the latch
The gradation of the IDE DATA 138 is corrected by a LUT (look-up table) 901 composed of ROM or RAM, and the D / A (digital / analog) converter 902 performs D
A / A conversion is performed to generate one analog video signal,
The generated analog signal is output to the next-stage comparator 910,
It is input to 911 and compared with a triangular wave described later. The signals 808 and 809 input to the other comparator are V
These are triangular waves (808 and 809 in FIG. 104 (B)) that are individually generated by being synchronized with CLK. That is, VC
Synchronous clock 2VCLK1 having twice the frequency of LK801
17 ', one of which is, for example, a JK flip-flop 906.
The triangular wave WV1 generated by the triangular wave generation circuit 908 according to the reference signal 806 for generating the triangular wave divided by 2, and the other is the triangular wave WV2 generated by the triangular wave generation circuit 909 according to 2VCLK. 2VCLK117 'is V
It is generated by a multiplication circuit (not shown) based on CLK117.
Each triangular wave 808,809 and VIDEO DATA138
Are all generated in synchronization with VCLK as shown in FIG. Furthermore, HS generated in synchronization with VCLK
HSYNC inverted to synchronize with YNC118
Resets the circuit 906 at the timing of HSYNC. By the above operation, CMP1 910, CMP2 9
11 outputs 810 and 811 have input VIDEO D
According to the value of ATA138, a signal having a pulse width as shown in FIG. That is, in this system, when the output of the AND gate 913 in FIG. (A) is "1", the laser is turned on, a dot is printed on the printing paper, and when the output is "0", the laser is turned off, and nothing is printed on the printing paper. Not done. Therefore, turning off can be controlled by the control signal LON (805) from the CPU 20. In the figure (C), "black" → "white" from left to right.
→→ It shows the situation when the level of the image signal Di changes. The input to the PWM circuit is "white" is "FF",
Since “black” is input as “00”, the output of the D / A converter 902 changes like Di in FIG. On the other hand, the triangular wave is WV1 in (i) and WV in (ii)
The pulse width becomes narrower as the outputs of CMP1 and CNP2 shift from "black" to "white" like PW1 and PW2, respectively. Further, as is apparent from the figure, when PW1 is selected, dots on the print paper are formed at intervals of P ₁ → P ₂ , and the pulse width variation has a dynamic range of W1. On the other hand, if you select PW2 dots formed at intervals of _{P 3 → P 4 → P 5} → P 6, the dynamic range of the pulse width is W2 becomes PW1
Compared to each half. By the way, for example, the print density (resolution) is about 200 lines / inch at PW1.
When PW2, it is set to about 400 lines / inch. Further, as is clear from this, when PW1 is selected, the gradation is improved about twice as much as when it is PW2, while when PW2 is selected, the resolution is significantly improved. Therefore, for example, PW2 should be selected when high resolution is required and PW1 should be selected when high gradation is required.
HG143 is provided. That is, 91 in FIG.
Reference numeral 2 denotes a selector, which selects the A input when the LCHG 143 is "0", that is, when the PW1 is "1", the PW2 is the output terminal O.
The laser is turned on for the pulse width finally output, and the dots are printed.

The LUT 901 is a table conversion ROM for gradation correction, and has addresses 812 ', 812, 813.
C ₂ , C ₁ , C ₀ , 814 table switching signal, 81
VID with 5 video signals input and corrected from output
EO DATA is obtained. For example, when the LCHG 143 is set to "0" to select PW1, all the outputs of the binary counter 903 become "0" and the correction table for PW1 in 901 is selected. Further, C ₀ , C ₁ and C ₂ are switched according to the color signal to be output. For example, C ₀ , C ₁ and C 2
₂ = Yellow output when "0, 0, 0", "0, 1,
When it is "0", it outputs magenta, when it is "1,0,0", it outputs cyan, and when it is "1,1,0", it outputs black.This is the same as the case of the masking described above. switch the gradation complementarity characteristics for each color image. Thus, to compensate the difference in gradation characteristic caused by a difference in image reproduction characteristic due to the color laser beam printer. the C ₂
It is possible to perform a more extensive gradation complementarity The combination of C _0, C ₁ and. For example, the gradation conversion characteristics of each color can be switched according to the type of the input image. Next, when the LCHG 143 is set to "1" to select the PW1, the binary counter 903 counts the line synchronization signal, and "1" → "2" → "1" → "2" → ... Is LUT.
To the address 814. As a result, the gradation complementarity table is switched for each line to further improve the gradation.

This will be described in detail with reference to FIG. A curve A in FIG. 9A is a characteristic curve of input data versus print density when PW2 is selected and the input data is changed from "FF", that is, "white" to "0", that is, "black". . As a standard, it is desirable that the characteristic is K. Therefore, B, which is the inverse characteristic of A, is set in the gradation complementarity table. FIG. 6B shows the gradation complementary characteristics A and B for each line when PW1 is selected, and the pulse width in the main scanning direction (laser scanning direction) is changed by the above-mentioned triangular wave and at the same time the sub scanning direction is set. As shown in the figure, (gradation direction of image) is provided with two gradation levels to further improve the gradation characteristics. That is, the characteristic A is predominant in the portion where the density change is abrupt, and the sharp reproducibility is reproduced, and the smooth gradation is reproduced by the characteristic B. Therefore, even when PW2 is selected as described above, a certain level of gradation is ensured with high resolution, and when PW1 is selected, extremely excellent gradation is guaranteed.

The video signal converted into the pulse width as described above is supplied to the laser driver 711 via the line 224.
L modulates the laser light LB.

Note that the signals C ₀ , C ₁ , and
C ₂ and LON are output from a control circuit (not shown) in the printer controller 700 shown in FIG.

Now, consider a case where a color original including a character area is processed. Returning to the overall circuit diagram of FIG. 2, the processing procedure will be described. That is, the input character and halftone mixed image data passes through the input circuit (A block), and one of them is LOG for obtaining a proper image.
The conversion (C) and color complementarity (D) circuits are input, and the other is input to a detection circuit (I) for separating a character and a halftone area, and detection is performed according to the character area and the halftone area. Signals MjAR (124) to SCRN (127)
Is output. Of this detection signal, MjAR (12
4) is a signal indicating a character portion, and based on this, the resolution switching signal LCHG in the character image complementary circuit E
(140 in FIG. 2, 140 in FIG. 21) is already generated. As shown in FIG. 2, the LCHG 140 is a multi-valued video signal 113, 114, 115, 116, 13
In addition to the above, the switching signal is sent in parallel to the printer unit, and the character portion becomes a high resolution output (400 dpi) and the halftone portion becomes a high gradation output (200 dpi) switching signal as described above.

The subsequent processing is performed as described above.

[Image Forming Operation] Now, the image output data 81
The laser beam LB modulated corresponding to 6 is horizontally scanned at a high speed by a polygon mirror 712 rotating at a high speed within a width of an arrow AB, and the f / θ lens 713 and the mirror 71 are scanned.
An image is formed on the surface of the photosensitive drum 715 through the image forming unit 4 and dot exposure corresponding to the image data is performed. One horizontal scan of the laser beam corresponds to one horizontal scan of the document image, and in this embodiment, corresponds to a width of 1/16 mm in the feed direction (sub-scan direction).

On the other hand, since the photosensitive drum 715 is rotating at a constant speed in the direction of arrow L in the figure, the laser beam is scanned in the main scanning direction of the drum, and the photosensitive drum 715 is exposed in the sub scanning direction of the drum. Since the drum 715 is rotated at a constant speed,
As a result, the planar image is sequentially exposed to form a latent image. From the uniform charging by the charger 717 prior to the exposure, the above-described exposure → the toner development by the developing sleeve 731 forms toner development. For example, by developing with the yellow toner of the developing sleeve 731Y in response to the first original exposure scanning in the color reader,
A toner image corresponding to the yellow component of the original 3 is formed on the photosensitive drum 715.

Then, a yellow toner image is formed on the paper sheet 754 whose tip is supported by the gripper 751 and wound around the transfer drum 716 by the transfer charger 729 provided at the contact point between the photosensitive drum 715 and the transfer drum 716. Is transferred and formed. The same processing steps are repeated for M (magenta), C (cyan), and BK (black) images, and the toner images are superimposed on the paper sheet 754 to form a full-color image with four-color toner. It

Then, the transfer paper 791 is separated from the transfer drum 716 by the movable separation claw 750 shown in FIG. 1, guided to the image fixing section 743 by the conveyor belt 742, and transferred to the fixing section 743 by the heat and pressure rollers 744 and 745. Paper 79
1 is fused and fixed.

In the present embodiment, the driver for printing drives the color laser beam printer. However, even in a color image copying apparatus for obtaining a color image such as a thermal transfer type color printer or an ink jet color image The present invention can be applied as long as it has a function of switching the resolution accordingly.

In the present embodiment, a means for performing high resolution processing on a character image to be combined, a means for performing high gradation processing on a color image to be combined, and a color image portion to be combined are combined. By providing a means for giving priority to high resolution processing to the area where the character portions overlap, it is possible to obtain an optimum combined image that matches the characteristics of the combined image.

Here, in this embodiment, as the high resolution processing,
Although 400 dpi printing and 200 dpi printing were performed as high gradation processing, this processing means is not limited to this. That is, the resolution can be set freely. Further, not only two-step switching but also multi-step switching such as three-step switching may be performed.

As described above, according to this embodiment, the high resolution processing is performed when the composite image is a character, and the high gradation processing is performed when the color image is a high resolution at a portion where two kinds of composite images overlap. Since the processing is performed, it is possible to obtain a high-quality and high-definition composite image that is not affected by the reflective original.

[0382]

As described above, according to the invention of the present application, according to the processing condition of the target image or the reading condition of the target image,
It is possible to accurately identify the type of the target image.

[Brief description of the drawings]

FIG. 1 is an overall view of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 3 is a diagram showing a color reading sensor and a driving pulse.

FIG. 4 is a circuit diagram for generating ODRV118a and EDRV119a.

FIG. 5 is a diagram illustrating a black correction operation.

FIG. 6 is a circuit diagram of shading correction.

FIG. 7 is a diagram showing a procedure of white correction.

FIG. 8 is a color conversion block diagram.

FIG. 9 is a block diagram of a color detection unit.

FIG. 10 is a block diagram of a color conversion circuit.

FIG. 11 is a diagram showing a specific example of color conversion.

FIG. 12 is a diagram illustrating logarithmic conversion.

FIG. 13 is a circuit diagram of a color correction circuit.

FIG. 14 is a diagram showing color correction coefficients.

FIG. 15 is a diagram showing unnecessary transmission regions and unnecessary absorption components of the filter.

FIG. 16 is a circuit diagram of a character image area separation circuit.

FIG. 17 is a circuit diagram of a dot area control circuit.

FIG. 18 is a diagram showing a determination sample line during zooming.

FIG. 19 is a conceptual diagram of contour regeneration.

FIG. 20 is a diagram illustrating the concept of contour regeneration.

FIG. 21 is a diagram illustrating the concept of contour regeneration.

FIG. 22 is a diagram illustrating the concept of contour regeneration.

FIG. 23 is a contour regenerating circuit diagram.

FIG. 24 is a contour regenerating circuit diagram.

FIG. 25 is a timing chart of EN1 and EN2.

FIG. 26 is a block diagram of a character image correction unit.

FIG. 27 is an explanatory diagram of addition / subtraction processing.

FIG. 28 is a switching signal generation circuit diagram.

FIG. 29 is a color residual removal processing circuit diagram.

FIG. 30 is a diagram illustrating remaining color removal processing, addition / subtraction processing, and the like.

FIG. 31 is a diagram illustrating remaining color removal processing, addition / subtraction processing, and the like.

FIG. 32 is a diagram for explaining color residue removal processing, addition / subtraction processing, and the like.

FIG. 33 is a diagram for explaining color residue removal processing, addition / subtraction processing and the like.

FIG. 34 is a diagram for explaining color residue removal processing, addition / subtraction processing and the like.

FIG. 35 is a diagram illustrating residual color removal processing, addition / subtraction processing, and the like.

FIG. 36 is a diagram showing edge enhancement and smoothing.

FIG. 37 is a diagram for explaining processing and modification processing using a binary signal.

FIG. 38 is a diagram for explaining processing and modification processing using a binary signal.

FIG. 39 is a diagram for explaining processing and modification processing using a binary signal.

FIG. 40 is a diagram showing character and image combination.

FIG. 41 is a block diagram of an image editing / processing circuit.

FIG. 42 is a diagram showing texture processing.

FIG. 43 is a circuit diagram of texture processing.

FIG. 44 is a circuit diagram of mosaic, scaling, and taper processing.

FIG. 45 is a circuit diagram of mosaic processing.

FIG. 46 is a diagram illustrating mosaic processing.

FIG. 47 is a diagram illustrating italic processing.

FIG. 48 is a diagram illustrating taper processing.

FIG. 49 is a diagram illustrating contour processing.

FIG. 50 is a block diagram of contour processing.

FIG. 51 is a circuit diagram of a line memory address control unit.

FIG. 52 is an explanatory diagram of a mask bit memory and the like.

FIG. 53 is an explanatory diagram of a mask bit memory and the like.

FIG. 54 is an explanatory diagram of a mask bit memory and the like.

FIG. 55 is an explanatory diagram of a mask bit memory and the like.

FIG. 56 is an explanatory diagram of a mask bit memory and the like.

FIG. 57 is an explanatory diagram of a mask bit memory and the like.

FIG. 58 is an explanatory diagram of a mask bit memory and the like.

FIG. 59 is an explanatory diagram of a mask bit memory and the like.

FIG. 60 is an explanatory diagram of a mask bit memory and the like.

FIG. 61 is an explanatory diagram of a mask bit memory and the like.

FIG. 62 is an explanatory diagram of a mask bit memory and the like.

FIG. 63 is an explanatory diagram of a mask bit memory and the like.

FIG. 64 is a diagram showing addresses.

FIG. 65 is a diagram showing a specific example of a mask.

FIG. 66 is a circuit diagram of an address counter.

FIG. 67 is a timing chart of enlargement and reduction.

FIG. 68 is a diagram showing a specific example of enlargement and reduction.

69 is an explanatory diagram of a binarization circuit. FIG.

FIG. 70 is a block diagram showing the periphery of a memory.

FIG. 71 is a diagram for explaining binarization level adjustment.

FIG. 72 is a timing chart of the address counter.

FIG. 73 is a diagram showing a specific example of bitmap memory writing.

FIG. 74 is a diagram showing a specific example of character / image combination.

FIG. 75 is a circuit diagram of distribution switching.

FIG. 76 is a diagram showing a specific example of a non-linear mask.

FIG. 77 is a circuit diagram of a region signal generation circuit.

FIG. 78 is a circuit diagram of a region signal generation circuit.

FIG. 79 is a diagram for explaining area generation.

FIG. 80 is a diagram showing area designation by a digitizer.

FIG. 81 is an interface circuit diagram with an external device.

FIG. 82 is a truth table of a selector.

FIG. 83 is a diagram showing an example of a rectangular area and a non-rectangular area.

FIG. 84 is an external view of the operation unit.

FIG. 85 is a diagram illustrating a procedure of a color conversion operation.

FIG. 86 is a diagram illustrating a procedure for designating a trimming area.

FIG. 87 is a diagram illustrating a procedure for designating a trimming area.

FIG. 88 is a diagram showing an algorithm for designating a circular area.

FIG. 89 is a diagram showing an algorithm for designating an area of an ellipse and an R rectangle.

FIG. 90 is an explanatory diagram of a character synthesizing operation procedure.

FIG. 91 is an explanatory diagram of a character synthesizing operation procedure.

FIG. 92 is an explanatory diagram of a character synthesizing operation procedure.

FIG. 93 is a diagram illustrating a procedure of texture processing.

FIG. 94 is a view for explaining the procedure of texture processing.

FIG. 95 is a view for explaining the mosaic processing procedure.

FIG. 96 is a view for explaining the procedure of mosaic processing.

FIG. 97 is a diagram illustrating a procedure of * mode operation.

FIG. 98 is a view for explaining the procedure of program memory operation.

FIG. 99 is a view for explaining the procedure of program memory operation.

FIG. 100 is a view for explaining the procedure of program memory operation.

101 is a diagram showing an algorithm of program memory registration. FIG.

FIG. 102 is a diagram showing an algorithm of an operation after calling a program memory.

FIG. 103 is a diagram showing a format of a recording table.

FIG. 104 is a diagram showing part of a driver of a color laser beam printer and a timing chart.

FIG. 105 is a diagram showing a triangular wave.

FIG. 106 is a diagram showing the contents of a gradation correction table.

FIG. 107 is a perspective view showing the outer appearance of a laser beam printer.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location B41J 29/38 B41J 3/00 A G03G 15/01 B H04N 1/04 101 3/12 G

Claims (3)

[Claims] 1. An input unit for inputting image data, an identifying unit for identifying a type of an image represented by the image data based on the image data, and processing the image data according to an identification result by the identifying unit. An image processing apparatus, comprising: a processing unit for performing the scaling process; and a changing operation of the identification unit when the scaling process is performed by the processing unit. 2. An image reading means for reading an original and generating image data corresponding to the original, an identifying means for identifying a type of an image represented by the image data based on the image data, and the reading means. An image processing apparatus, characterized in that an identification operation of the identification means is changed according to a reading condition. 3. The image processing apparatus according to claim 2, wherein the reading condition is a light amount of a light source that illuminates the document.