JPH09172261A - Manufacture of multilayered printed wiring board - Google Patents

Manufacture of multilayered printed wiring board

Info

Publication number
JPH09172261A
JPH09172261A JP34853395A JP34853395A JPH09172261A JP H09172261 A JPH09172261 A JP H09172261A JP 34853395 A JP34853395 A JP 34853395A JP 34853395 A JP34853395 A JP 34853395A JP H09172261 A JPH09172261 A JP H09172261A
Authority
JP
Japan
Prior art keywords
hole
lands
land
layers
small
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34853395A
Other languages
Japanese (ja)
Inventor
Masaru Hanamori
優 花森
Kenji Komatsu
健治 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP34853395A priority Critical patent/JPH09172261A/en
Publication of JPH09172261A publication Critical patent/JPH09172261A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce the working manhour of a via-hole, by almost coaxially forming small holes having smaller diameters in order from the surface side of a laminate, in lands except lands of the lowermost layer, and forming via- holes with laser which penetrate the small holes of a plurality of lands from the surface of the laminate and reach the lands of the lowermost layer. SOLUTION: In a copper foil 52 of a laminate wherein a board 50 is laminated, a small hole 56 is formed by eliminating a position for forming a via-hole by photo etching or the like. In the position where the via-hole is formed, lands 12B, 16B of circuit patterns 12A, 16A formed on boards 10, 14 are superimposed in the thickness direction of the laminate. Excepting the land 12B of the circuit pattern 12A which turns to the bottom of the via-hole, in the land 16B above the land 12B and in the outermost copper foil 52, a small hole 58 and the small 56 are so formed that the diameter becomes larger toward the surface side. Thereby via-holes 60, 62 are formed at the same time when the small hole 56 is irradiated perpendicularly to the laminate surface with laser.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明が属する技術分野】本発明は、ビヤホールにより
異なる層間の接続を行う多層プリント配線板の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board in which different layers are connected by via holes.

【0002】[0002]

【従来の技術】多層プリント配線板においては、異なる
層間の電気接続を行うためにビアホール(via hole、バ
イアホールともいう)を設けている。このビアホールを
形成するのにレーザを用いることが従来より知られてい
る。
2. Description of the Related Art In a multilayer printed wiring board, a via hole (also referred to as a via hole) is provided for making electrical connection between different layers. It is conventionally known to use a laser to form this via hole.

【0003】図4、5は従来のレーザを用いたビアホー
ルの加工工程の一例を示す図である。この方法は3層以
上の隣接する内層回路を接続するものである。これらの
図で(A)〜(H)は加工工程を順に示す。まず絶縁性
基板10を準備する(図4の工程(A))。この基板1
0はガラス繊維などレーザにより加工が不可能または困
難な基材を含んでいてもよい。この基板10の両面には
銅箔12、12が接着されている。
4 and 5 are views showing an example of a conventional via hole processing process using a laser. This method connects adjacent inner layer circuits of three or more layers. In these figures, (A) to (H) show processing steps in order. First, the insulating substrate 10 is prepared (step (A) in FIG. 4). This substrate 1
0 may include a base material such as glass fiber which is impossible or difficult to process by laser. Copper foils 12, 12 are adhered to both surfaces of the substrate 10.

【0004】この基板10の両面に回路パターン12
A、12Aを公知の方法、例えばフォトエッチング法に
より形成する(同図の工程(B))。この基板10の両
面に他の基板14、14あるいは銅箔を接着剤シート等
により接着し積層する(図4の工程(C))。ここに用
いる接着剤シートはガラス繊維を含まないものとする。
この基板14、14は前記基板10と同様にガラス繊維
を含まない樹脂板とするのが望ましい。また両基板1
4、14の外側の面には銅箔16、16がそれぞれ接着
されている。
Circuit patterns 12 are formed on both sides of the substrate 10.
A and 12A are formed by a known method, for example, a photoetching method (step (B) in the figure). Other substrates 14 and 14 or copper foils are adhered and laminated with an adhesive sheet or the like on both surfaces of the substrate 10 (step (C) in FIG. 4). The adhesive sheet used here does not contain glass fibers.
Like the substrate 10, the substrates 14 and 14 are preferably resin plates containing no glass fiber. Both boards 1
Copper foils 16 and 16 are adhered to the outer surfaces of 4 and 14, respectively.

【0005】この積層体18の銅箔16、16はビアホ
ールを形成する位置を例えばフォトエッチングによって
除去して小孔を形成しておく。なおこのビアホールは、
前記基板10の銅箔12、12に形成した回路パターン
のランドに重なる位置にある。そしてこの積層体18に
レーザを用いて穴あけ加工を行う(図4の工程
(D))。
The copper foils 16 and 16 of the laminated body 18 have small holes formed by removing the positions where via holes are to be formed, for example, by photoetching. This via hole is
It is located at a position overlapping the land of the circuit pattern formed on the copper foils 12, 12 of the substrate 10. Then, a drilling process is performed on the laminated body 18 using a laser (step (D) in FIG. 4).

【0006】ここに用いるレーザはビアホール用に積層
体18の銅箔16、16を除去した小孔の部分に照射さ
れる。このレーザの照射により銅箔16の小孔の下方で
基板14、14の樹脂が消失し、ビアホール孔20が形
成される。レーザは基板10の回路パターン12Aに形
成したランドに到達すると、このランドが銅箔であるた
めにランドに孔をあけることができない。このためビア
ホール孔20はこのランドまでの深さとなり、それより
下の基板10には変化を及ぼさない。なお実際のビアホ
ール孔20は下層に向って次第に小径となる円錐状とな
るが、この図4、5では簡略にするため円柱状に表示し
ている。
The laser used here is applied to the portion of the small hole for removing the copper foils 16, 16 of the laminated body 18 for the via hole. The irradiation of the laser causes the resin of the substrates 14 and 14 to disappear under the small holes of the copper foil 16, and the via hole 20 is formed. When the laser reaches the land formed on the circuit pattern 12A of the substrate 10, the land cannot be perforated because the land is a copper foil. Therefore, the via hole 20 has a depth up to this land and does not affect the substrate 10 below it. The actual via-hole 20 has a conical shape whose diameter gradually decreases toward the lower layer, but in FIGS. 4 and 5, it is shown as a column for simplicity.

【0007】このようにビアホール孔20を形成した
後、無電解めっき処理によりビアホール孔20の内面に
導電性を付与し、さらに電解銅めっきを行う。そして積
層体18の外面に回路パターン16Aを形成する(図4
の工程(E))。この銅めっき処理によって基板10の
回路パターン12Aと、基板14の回路パターン16A
との異なる層間が電気的に接続される。すなわちビアホ
ール20Aが形成される。
After the via hole 20 is formed in this manner, electroconductivity is applied to the inner surface of the via hole 20 to provide conductivity, and then electrolytic copper plating is performed. Then, the circuit pattern 16A is formed on the outer surface of the laminate 18 (see FIG. 4).
Step (E)). The circuit pattern 12A of the substrate 10 and the circuit pattern 16A of the substrate 14 by this copper plating process
And different layers are electrically connected. That is, the via hole 20A is formed.

【0008】このようにビアホール20Aを形成した積
層体18には、さらに他の基板22、22あるいは銅箔
が積層されて積層体18Aが形成される。この時に用い
る接着剤シートはガラス繊維を含まない。この接着剤シ
ートに含まれる接着剤がビアホール20A内に流入して
このビアホール20Aを埋める(図5の工程(F))。
なおこの基板22、22も前記基板14と同様に片面に
銅箔24、24を張ったものであり、この銅箔24を外
側にして積層する。
The laminated body 18 in which the via holes 20A are formed in this manner is further laminated with another substrate 22, 22 or a copper foil to form a laminated body 18A. The adhesive sheet used at this time does not contain glass fiber. The adhesive contained in the adhesive sheet flows into the via hole 20A to fill the via hole 20A (step (F) in FIG. 5).
The substrates 22 and 22 are also provided with copper foils 24 and 24 on one side like the substrate 14, and the copper foils 24 are laminated outside.

【0009】この銅箔24には、この基板22に形成す
るビアホールの位置に対応する部分を例えばフォトエッ
チングにより除去することにより小孔が形成される。そ
してレーザを用いてこの基板22にビアホール孔26を
穴あけ加工する(図5の工程(G))。このビアホール
孔26の底は、基板14の回路パターン16Aのランド
となっている。そしてこの積層体18Aのスルーホール
孔26に無電解めっきにより導電性を付与した後、電解
めっきを施し、最外層の回路パターン24Aを形成する
(図5の工程(H))。この結果回路パターン24Aと
内層回路パターン16Aとを接続するビアホール26A
が形成される。
Small holes are formed in the copper foil 24 by removing the portions corresponding to the positions of the via holes formed in the substrate 22 by, for example, photoetching. Then, a laser is used to form a via hole 26 in the substrate 22 (step (G) in FIG. 5). The bottom of the via hole hole 26 is a land of the circuit pattern 16A of the substrate 14. Then, after electroconductivity is applied to the through-holes 26 of the laminate 18A by electroless plating, electroplating is performed to form the outermost circuit pattern 24A (step (H) in FIG. 5). As a result, the via hole 26A connecting the circuit pattern 24A and the inner layer circuit pattern 16A
Is formed.

【0010】図7は隣接しない2つの層間を接続する従
来のビアホールの加工方法を示す図である。この図にお
いて100はコアとなる絶縁性基板、102、104、
106はこの基板100に積層された基板である。これ
ら基板100、102、104にはそれぞれ内層回路パ
ターン108、110、112が形成され、最上層の基
板106には外層回路パターン114が形成されてい
る。
FIG. 7 is a diagram showing a conventional method of processing a via hole for connecting two layers which are not adjacent to each other. In this figure, 100 is an insulating substrate serving as a core, 102, 104,
Reference numeral 106 denotes a substrate laminated on the substrate 100. Inner layer circuit patterns 108, 110 and 112 are formed on these substrates 100, 102 and 104, respectively, and outer layer circuit pattern 114 is formed on the uppermost substrate 106.

【0011】ここに内層回路パターン108と110と
はビアホール116により接続され、内層回路パターン
110と112とはビアホール118により接続され
る。また内層回路パターン112と114とはビアホー
ル120により接続される。ビアホール116は基板1
00に基板102を積層した状態でレーザを用いて基板
102の回路パターン110側から小孔を穿設し、銅め
っき処理することにより形成される。
Here, the inner layer circuit patterns 108 and 110 are connected by via holes 116, and the inner layer circuit patterns 110 and 112 are connected by via holes 118. The inner layer circuit patterns 112 and 114 are connected by the via hole 120. Via hole 116 is substrate 1
It is formed by forming a small hole from the side of the circuit pattern 110 of the substrate 102 using a laser in a state where the substrate 102 is laminated on the substrate 00, and performing copper plating treatment.

【0012】同様にビアホール118は基板104を積
層した状態で加工され、ビアホール120は基板106
を積層した状態で加工される。このように従来は、隣接
しない2つの層間の接続を行うために、その間の各層ご
とに順番に接続していたから、各基板102、104、
106を積層する度にビアホール116、118、12
0を加工する必要があった。
Similarly, the via hole 118 is processed in a state in which the substrates 104 are laminated, and the via hole 120 is formed in the substrate 106.
Are processed in a laminated state. As described above, conventionally, in order to make a connection between two layers that are not adjacent to each other, the layers are connected in order between layers, so that the substrates 102, 104,
The via holes 116, 118, 12 are formed every time 106 is laminated.
It was necessary to process 0.

【0013】[0013]

【従来技術の問題点】このように従来の方法は、基板を
積層する度にこの新たに積層した基板にレーザによりビ
ヤホール孔20、26、66、68、70を形成するも
のであった。またビヤホール孔20、26、66、6
8、70を形成する度にその内面に銅めっきを施して隣
接する層間の電気的接続を得る必要があった。このため
基板の積層枚数の増加に対応して製造工程数が著しく増
えるという問題があった。
As described above, in the conventional method, each time a substrate is laminated, the via holes 20, 26, 66, 68, 70 are formed on the newly laminated substrate by laser. Also, the via hole holes 20, 26, 66, 6
It was necessary to copper-plat the inner surface of each of the layers 8 and 70 to form an electrical connection between adjacent layers. Therefore, there has been a problem that the number of manufacturing steps significantly increases in response to the increase in the number of laminated substrates.

【0014】[0014]

【発明の目的】本発明はこのような事情に鑑みなされた
ものであり、ビヤホールの加工工数を減らし、特に基板
の積層枚数が多い場合の製造工程数を著しく減らして生
産性を高めることができる多層プリント配線板の製造方
法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to improve the productivity by reducing the number of man-hours for processing a via hole and remarkably reducing the number of manufacturing steps particularly when the number of laminated substrates is large. An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board.

【0015】[0015]

【発明の構成】本発明によればこの目的は、回路パター
ンを形成した複数の絶縁性基板を絶縁層を介して積層圧
着する一方、異なる3層以上の層間の回路パターンをビ
アホールで接続する多層プリント配線板の製造方法にお
いて、複数の内層回路パターンは積層体の厚さ方向に重
なるランドをそれぞれ持ち、これらランドのうち最下層
のランド以外のランドには積層体の表面側から順に小径
となる小孔が略同軸上に形成され、前記積層体の表面か
ら複数のランドの小孔を貫通して前記最下層のランドに
到達するビアホール孔をレーザを用いて形成し、前記ビ
アホール孔に銅めっきを施して異なる層間の回路パター
ンを接続することを特徴とする多層プリント配線板の製
造方法、により達成される。
According to the present invention, an object of the present invention is to provide a multilayer structure in which a plurality of insulating substrates having circuit patterns are laminated and pressure-bonded via insulating layers, while circuit patterns between three or more different layers are connected by via holes. In the method for manufacturing a printed wiring board, each of the plurality of inner layer circuit patterns has a land that overlaps in the thickness direction of the laminated body, and the lands other than the land of the lowermost layer among these lands have smaller diameters in order from the surface side of the laminated body. A small hole is formed substantially coaxially, a via hole hole that penetrates the small holes of a plurality of lands from the surface of the laminated body and reaches the land of the lowermost layer is formed by using a laser, and the via hole hole is copper-plated. And a circuit pattern between different layers are connected to each other to achieve a multilayer printed wiring board manufacturing method.

【0016】また同一の目的は、回路パターンを形成し
た複数の絶縁性基板を絶縁層を介して3層以上に積層圧
着する一方、隣接しない異なる層間の回路パターンをビ
アホールで接続する多層プリント配線板の製造方法にお
いて、隣接しない2つの層の内層回路パターンはこれら
2つの層の間の内層回路パターンに重ならないで積層体
の厚さ方向に重なるランドをそれぞれ持ち、これらラン
ドのうち外層のランドに小孔を形成し、前記積層体の表
面から上層のランドの小孔を貫通して前記下層のランド
に到達するビアホール孔をレーザを用いて形成し、前記
ビアホール孔に銅めっきを施して異なる層間の回路パタ
ーンを接続することを特徴とする多層プリント配線板の
製造方法、により達成される。
Further, the same purpose is to laminate a plurality of insulating substrates on which circuit patterns are formed by laminating and pressing into three or more layers through insulating layers, while connecting circuit patterns between different layers which are not adjacent to each other by via holes. In the manufacturing method of 1., the inner layer circuit patterns of the two layers that are not adjacent to each other have lands that overlap in the thickness direction of the laminated body without overlapping the inner layer circuit patterns between these two layers. A small hole is formed, a via hole hole that penetrates the small hole of the land of the upper layer and reaches the land of the lower layer from the surface of the laminated body is formed by using a laser, and copper plating is applied to the via hole hole to form different layers. And a method for manufacturing a multilayer printed wiring board, which is characterized in that the circuit patterns are connected.

【0017】[0017]

【発明の実施の態様】図1および図2は本発明の一実施
態様の加工工程を示す図、図3は図1の工程Fの一部で
あるII矢視部分の拡大図である。この実施例は3層以上
の回路パターンを接続するビアホールを形成するもので
ある。図1において工程(A)〜(C)は前記図4に示
したものと同じであるから、同一部分に同一符号を付し
てその説明は繰り返えさない。
1 and 2 are views showing a processing step according to an embodiment of the present invention, and FIG. 3 is an enlarged view of a portion viewed from an arrow II which is a part of step F in FIG. In this embodiment, via holes for connecting circuit patterns of three or more layers are formed. Since steps (A) to (C) in FIG. 1 are the same as those shown in FIG. 4, the same reference numerals are given to the same portions and the description thereof will not be repeated.

【0018】この実施態様では、基板10の両面に片面
に銅箔を張った基板14、14を積層した後(図1の工
程(C))、回路パターン16A、16Aを形成する
(図1の工程(D))。すなわちビアホール孔を加工せ
ずにまず回路パターン16Aを形成するものである。そ
してこの積層体18の両面にさらに他の基板50、50
あるいは銅箔を接着剤シートなどを介して積層する(工
程(E))。この基板50、50も片面に銅箔52、5
2を張ったものである。
In this embodiment, the circuit patterns 16A and 16A are formed (in FIG. 1) after the substrates 14 and 14 each having copper foil on one side are laminated on both sides of the substrate 10 (step (C) in FIG. 1). Step (D)). That is, the circuit pattern 16A is first formed without processing the via hole. Further, the other substrates 50, 50 are provided on both surfaces of the laminated body 18.
Alternatively, copper foils are laminated via an adhesive sheet or the like (step (E)). This board 50, 50 also has copper foils 52, 5 on one side.
It is a stretch of 2.

【0019】このように基板50、50を積層した積層
体54の銅箔52、52には、ビアホールを形成する位
置をフォトエッチングなどによって除去して小孔56
(図3参照)を形成しておく。またこのビアホールを形
成する位置には前記基板10、14に形成した回路パタ
ーン12A、16Aのランド12B、16B(図3)が
積層体54の厚さ方向に重なる。そしてビアホールの底
となる回路パターン12Aのランド12Bを除き、その
上方のランド16Bおよび最外層の銅箔52には、表面
側に向って順に大径となるように小孔58、56が形成
されている(図3)。
In the copper foils 52, 52 of the laminated body 54 in which the substrates 50, 50 are laminated in this way, the positions where the via holes are formed are removed by photoetching or the like to form the small holes 56.
(See FIG. 3). The lands 12B and 16B (FIG. 3) of the circuit patterns 12A and 16A formed on the substrates 10 and 14 are overlapped in the thickness direction of the laminated body 54 at the positions where the via holes are formed. Except for the land 12B of the circuit pattern 12A which is the bottom of the via hole, small holes 58 and 56 are formed in the land 16B above and the copper foil 52 of the outermost layer so that the diameter becomes larger toward the surface side. (Fig. 3).

【0020】従ってレーザを積層体54の表面に対して
垂直に小孔56に向って照射すれば、基板50に対して
は小孔56と略同径のビアホール孔60が、また基板1
4に対しては小孔58と略同径のビアホール孔62が一
度に同軸上に連続して形成される。(図2の工程
(F))。
Therefore, when the laser is irradiated perpendicularly to the surface of the laminated body 54 toward the small hole 56, the substrate 50 is provided with the via hole hole 60 having substantially the same diameter as that of the small hole 56, and the substrate 1 also.
For 4, the via holes 62 having substantially the same diameter as the small holes 58 are formed coaxially and continuously at one time. (Step (F) in FIG. 2).

【0021】このようにしてビアホール孔60、62を
加工した後、銅めっきを行ってビアホール孔60、62
の内面に導電性を与え、さらに最外層に回路パターン5
2Aを形成する(図2の工程(G))。この結果内層回
路パターン12A、16Aと外層回路パターン52Aと
を接続するビアホール64が形成される。勿論この時最
外層の基板50だけを貫通するビアホール64Aを同時
に形成してもよい。
After processing the via hole holes 60 and 62 in this way, copper plating is performed to form the via hole holes 60 and 62.
Conductivity is given to the inner surface of and the circuit pattern 5 is applied to the outermost layer.
2A is formed (step (G) in FIG. 2). As a result, a via hole 64 connecting the inner layer circuit patterns 12A and 16A and the outer layer circuit pattern 52A is formed. Of course, at this time, the via hole 64A penetrating only the outermost substrate 50 may be simultaneously formed.

【0022】この実施態様では3層の回路パターン12
A、16A、52Aを接続するビアホール64を形成す
るが、4層以上の回路パターンを接続するビアホールも
勿論可能である。なお最外層の回路パターン52Aや内
層のランド16Bに形成する小孔56、58は、表面側
から順に小径としたが、積層時の各層の位置決め精度が
高ければこれら小孔の径の差は小さくできる。
In this embodiment, the three-layer circuit pattern 12 is used.
The via hole 64 connecting A, 16A, and 52A is formed, but a via hole connecting circuit patterns of four layers or more can of course be formed. The small holes 56 and 58 formed in the outermost layer circuit pattern 52A and the inner layer land 16B have a small diameter in order from the front surface side. However, if the positioning accuracy of each layer at the time of stacking is high, the difference in diameter between these small holes is small. it can.

【0023】図6は他の実施態様を示す図であり、前記
図7に示した隣接しない2つの層間を接続するものであ
る。すなわち最下層と最上層の回路パターン108Aと
114Aの接続を行う場合に、両層間に挟まれる回路パ
ターン110A、112Aは回路パターン108Aと1
14Aのランド間に挟まれないように形成しておくもの
である。
FIG. 6 is a view showing another embodiment, in which two non-adjacent layers shown in FIG. 7 are connected. That is, when the circuit patterns 108A and 114A on the lowermost layer and the uppermost layer are connected, the circuit patterns 110A and 112A sandwiched between the two layers are the circuit patterns 108A and 1A, respectively.
It is formed so as not to be sandwiched between the lands of 14A.

【0024】そして最上層の回路パターン114Aに設
けた小孔から最下層の回路パターン108Aに到達する
ビアホール孔をレーザーにより加工し、めっき処理を施
すものである。このようにして形成されたビアホール1
22は、1度の加工処理により形成することができる。
The via hole that reaches the circuit pattern 108A in the lowermost layer from the small hole provided in the circuit pattern 114A in the uppermost layer is processed by laser and plated. Via hole 1 formed in this way
22 can be formed by one-time processing.

【0025】また本発明における穴あけ加工で用いるレ
ーザは、XeClやKrFなどのエキシマレーザが好適
である。使用するレーザはエキシマレーザに限定され
ず、CO2レーザ、YAGレーザなどであってもよい。
The excimer laser such as XeCl or KrF is suitable for the laser used in the drilling process of the present invention. The laser used is not limited to the excimer laser, but may be a CO 2 laser, a YAG laser, or the like.

【0026】[0026]

【発明の効果】請求項1の発明は以上のように、3層以
上のの層間の回路パターンを接続するビヤホールを、一
度のレーザによる穴あけ加工と、一度の銅めっき処理と
を用いて形成することができるから、従来の方法のよう
に基板を1枚積層する度に穴あけ加工と銅めっき処理と
を施す必要がなくなり、加工工数を著しく減らすことが
可能になる。このため多層プリント配線板の生産性が向
上する。
As described above, according to the first aspect of the present invention, a via hole for connecting a circuit pattern between three or more layers is formed by using one laser drilling process and one copper plating process. Therefore, unlike the conventional method, it is not necessary to perform the drilling process and the copper plating process every time one substrate is laminated, and the processing man-hour can be remarkably reduced. Therefore, the productivity of the multilayer printed wiring board is improved.

【0027】また請求項2の発明によれば、隣接しない
層間を接続するビアホールにこれら両層の間の回路パタ
ーンが接触しないように回路パターンを形成しておき、
積層後に一度のレーザによる穴あけ加工とめっき処理で
ビアホールを形成するものであるから、加工工数を著し
く減らすことができる。
According to the second aspect of the present invention, the circuit pattern is formed in advance so that the circuit pattern between the two layers does not come into contact with the via hole that connects the non-adjacent layers.
Since the via hole is formed by one-time laser drilling and plating after stacking, the number of processing steps can be significantly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施態様の加工工程(前半)を示す
FIG. 1 is a diagram showing a processing step (first half) of an embodiment of the present invention.

【図2】本発明の一実施態様の加工工数(後半)を示す
FIG. 2 is a diagram showing a processing man-hour (second half) according to an embodiment of the present invention.

【図3】図1における工程Fの一部拡大図FIG. 3 is a partially enlarged view of step F in FIG.

【図4】従来の加工工程(前半)を示す図FIG. 4 is a diagram showing a conventional processing step (first half).

【図5】従来加工工程(後半)を示す図FIG. 5 is a diagram showing a conventional processing step (second half).

【図6】本発明の他の実施態様の加工方法を示す図FIG. 6 is a diagram showing a processing method according to another embodiment of the present invention.

【図7】従来の加工方法を示す図FIG. 7 is a diagram showing a conventional processing method.

【符号の説明】[Explanation of symbols]

10、14、22、50、100、102、104、1
06 基板 12、16、24、52 銅箔 12A、16A、24A、52A、108A、110
A、112A、114A回路パターン 20、26、60、62 ビヤホール孔 20A、26A、64、64A、122 ビヤホール
10, 14, 22, 50, 100, 102, 104, 1
06 substrate 12, 16, 24, 52 copper foil 12A, 16A, 24A, 52A, 108A, 110
A, 112A, 114A Circuit pattern 20, 26, 60, 62 Beer hole hole 20A, 26A, 64, 64A, 122 Beer hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 回路パターンを形成した複数の絶縁性基
板を絶縁層を介して積層圧着する一方、異なる3層以上
の層間の回路パターンをビアホールで接続する多層プリ
ント配線板の製造方法において、複数の内層回路パター
ンは積層体の厚さ方向に重なるランドをそれぞれ持ち、
これらランドのうち最下層のランド以外のランドには積
層体の表面側から順に小径となる小孔が略同軸上に形成
され、前記積層体の表面から複数のランドの小孔を貫通
して前記最下層のランドに到達するビアホール孔をレー
ザを用いて形成し、前記ビアホール孔に銅めっきを施し
て異なる層間の回路パターンを接続することを特徴とす
る多層プリント配線板の製造方法。
1. A method for manufacturing a multi-layer printed wiring board, wherein a plurality of insulating substrates having circuit patterns are laminated and pressure-bonded via insulating layers, while circuit patterns between three or more different layers are connected by via holes. The inner layer circuit pattern of each has lands overlapping in the thickness direction of the laminated body,
Small lands having a smaller diameter are formed on the lands other than the land of the lowermost layer of these lands in order from the surface side of the laminated body substantially coaxially, and through the small holes of a plurality of lands from the surface of the laminated body, A method of manufacturing a multilayer printed wiring board, comprising forming a via hole hole reaching a land of the lowermost layer by using a laser, and performing copper plating on the via hole hole to connect circuit patterns between different layers.
【請求項2】 回路パターンを形成した複数の絶縁性基
板を絶縁層を介して3層以上に積層圧着する一方、隣接
しない異なる層間の回路パターンをビアホールで接続す
る多層プリント配線板の製造方法において、隣接しない
2つの層の内層回路パターンはこれら2つの層の間の内
層回路パターンに重ならないで積層体の厚さ方向に重な
るランドをそれぞれ持ち、これらランドのうち外層のラ
ンドに小孔を形成し、前記積層体の表面から上層のラン
ドの小孔を貫通して前記下層のランドに到達するビアホ
ール孔をレーザを用いて形成し、前記ビアホール孔に銅
めっきを施して異なる層間の回路パターンを接続するこ
とを特徴とする多層プリント配線板の製造方法。
2. A method for manufacturing a multilayer printed wiring board, wherein a plurality of insulating substrates having a circuit pattern formed thereon are laminated and pressure-bonded in three or more layers with an insulating layer interposed therebetween, and circuit patterns between different layers which are not adjacent to each other are connected by via holes. , The inner layer circuit patterns of two layers which are not adjacent to each other have lands that overlap in the thickness direction of the laminated body without overlapping the inner layer circuit pattern between these two layers, and small holes are formed in the lands of the outer layer of these lands. Then, a via hole hole is formed from the surface of the laminated body through the small hole of the land of the upper layer to reach the land of the lower layer using a laser, and copper plating is applied to the via hole hole to form a circuit pattern between different layers. A method for manufacturing a multi-layer printed wiring board, which comprises connecting.
JP34853395A 1995-12-20 1995-12-20 Manufacture of multilayered printed wiring board Pending JPH09172261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34853395A JPH09172261A (en) 1995-12-20 1995-12-20 Manufacture of multilayered printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34853395A JPH09172261A (en) 1995-12-20 1995-12-20 Manufacture of multilayered printed wiring board

Publications (1)

Publication Number Publication Date
JPH09172261A true JPH09172261A (en) 1997-06-30

Family

ID=18397656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34853395A Pending JPH09172261A (en) 1995-12-20 1995-12-20 Manufacture of multilayered printed wiring board

Country Status (1)

Country Link
JP (1) JPH09172261A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971570A1 (en) * 1997-02-03 2000-01-12 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
EP1117283A1 (en) * 1998-09-14 2001-07-18 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
JP2002319762A (en) * 2001-04-20 2002-10-31 Toppan Printing Co Ltd Multilayer wiring board
JP2005183952A (en) * 2003-12-18 2005-07-07 Endicott Interconnect Technologies Inc Manufacturing method of printed circuit board having conductive holes and board thereof
JP2007128970A (en) * 2005-11-01 2007-05-24 Nippon Mektron Ltd Manufacturing method of multilayer wiring board having cable section
JP2008108880A (en) * 2006-10-25 2008-05-08 Matsushita Electric Ind Co Ltd Multilayer printed circuit board and its manufacturing method
JP2010183102A (en) * 2010-04-14 2010-08-19 Nippon Mektron Ltd Method of manufacturing multilayered wiring board having cable part
US8507807B2 (en) 2010-03-17 2013-08-13 Nec Corporation Wiring board
WO2024045411A1 (en) * 2022-08-30 2024-03-07 德中(天津)技术发展股份有限公司 Method for manufacturing multi-layer circuit board by laser-guided electrical patterns and electrical interconnection of different surfaces

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971570A4 (en) * 1997-02-03 2006-01-04 Ibiden Co Ltd Printed wiring board and its manufacturing method
EP0971570A1 (en) * 1997-02-03 2000-01-12 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
US7552531B2 (en) 1997-02-03 2009-06-30 Ibiden Co., Ltd. Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit
US7691189B2 (en) 1998-09-14 2010-04-06 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
EP1117283A1 (en) * 1998-09-14 2001-07-18 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
US7827680B2 (en) 1998-09-14 2010-11-09 Ibiden Co., Ltd. Electroplating process of electroplating an elecrically conductive sustrate
EP1667507A1 (en) * 1998-09-14 2006-06-07 Ibiden Co., Ltd. A multilayer printed circuit board and a process for manufacturing the same
US8065794B2 (en) 1998-09-14 2011-11-29 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
US7230188B1 (en) 1998-09-14 2007-06-12 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
JP2002319762A (en) * 2001-04-20 2002-10-31 Toppan Printing Co Ltd Multilayer wiring board
JP2005183952A (en) * 2003-12-18 2005-07-07 Endicott Interconnect Technologies Inc Manufacturing method of printed circuit board having conductive holes and board thereof
JP4527045B2 (en) * 2005-11-01 2010-08-18 日本メクトロン株式会社 Method for manufacturing multilayer wiring board having cable portion
JP2007128970A (en) * 2005-11-01 2007-05-24 Nippon Mektron Ltd Manufacturing method of multilayer wiring board having cable section
JP2008108880A (en) * 2006-10-25 2008-05-08 Matsushita Electric Ind Co Ltd Multilayer printed circuit board and its manufacturing method
US8507807B2 (en) 2010-03-17 2013-08-13 Nec Corporation Wiring board
JP2010183102A (en) * 2010-04-14 2010-08-19 Nippon Mektron Ltd Method of manufacturing multilayered wiring board having cable part
WO2024045411A1 (en) * 2022-08-30 2024-03-07 德中(天津)技术发展股份有限公司 Method for manufacturing multi-layer circuit board by laser-guided electrical patterns and electrical interconnection of different surfaces

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