JPH09171963A - Manufacture of minute semiconductor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the position of a self-formed quantum box accurately by forming an opening part and a dent in the main surface of the first semiconductor substrate, growing the second semiconductor having the larger lattice constant than the first semiconductor on the substrate and forming the minute semiconductor structure comprising the semiconductor grown in the indentation. SOLUTION: A dent 4, whose position is controlled, is formed in the first semiconductor substrate by the means such as lithography and etching. The depth of the dent 4 is made shallower than the height of a quantum box 3 to be manufactured. The size of the opening part of the dent at the substrate surface is made smaller than the bottom surface of the quantum box 3 to be manufactured. Then, by growing the second semiconductor having the larger lattice constant than the first semiconductor on the substrate, the quantum box 3 having the uniform size is manufactured accurately at the position of the dent. Furthermore, this dent 4 or the groove is constituted of the plane, wherein at least one of integers (l), (m) and (n) expressing the high-order exponents (l, m and n) is larger than 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor fine structure for manufacturing quantum boxes and quantum wires, which are important for improving the performance of electric devices or optical devices utilizing the quantum effect.

[0002]

2. Description of the Related Art A method of manufacturing a quantum box related to the present invention is as follows.
Conventionally, it is called a naturally formed quantum box manufacturing method, and is as shown in FIG. 8 below. First, the same semiconductor 2 as the first semiconductor is grown as a buffer layer on the first semiconductor substrate 1 by a molecular beam epitaxy method, a metal organic chemical vapor deposition method, or the like as shown in (b). Then, a second semiconductor layer having a larger lattice constant than that of the first semiconductor is grown by the same method. The second semiconductor layer grows uniformly on the substrate at the beginning of growth, but when several atomic layers (usually 1 to 3 atomic layers) grow, atoms are rearranged to form island-shaped atomic groups 3, and the growth continues as it is. . This is an excess energy determined by the shape of the growth layer, that is, (energy of the interface between the first semiconductor and the second semiconductor).
+ (Energy of the surface of the first and second semiconductors) +
This is because atoms move and rearrange bonds so that (energy of strain inside the growth layer) becomes small. That is,
Since the temperature is high during the growth, the atoms forming the growth layer can move within a certain range. At this time, when the atoms of the second semiconductor agglomerate, the sum of the area of the interface and the area of the surface increases, which acts as a factor for increasing the sum of the energy of the interface and the surface. Since strain due to lattice mismatch is relaxed inside the semiconductor, it works as a factor for reducing the strain energy inside the growth layer. The ratio of the atoms existing inside the island to the atoms existing on the surface or the interface becomes larger as the size of the island becomes larger, so that the larger the island becomes, the more the effect of relaxing strain inside the crystal becomes dominant. That is, as the growth progresses and the number of atoms of the second semiconductor increases, the excess energy becomes smaller when the second semiconductor aggregates in an island shape. Therefore, when the growth of the second semiconductor progresses, the crystal growth mode changes from the layered state to the islanded state from a certain point. Since this process is defined by the binding energy of atoms, the islands have the same size.

For example, InAs which grows 1 to 3 atomic layers of InAs on GaAs aggregates in an island shape, and the size thereof becomes 10 to 100 nm suitable for a quantum box. Various methods have been reported for applying this principle to self-assemble quantum boxes.

[0004]

In the self-assembled quantum box structure produced by the conventional method, the individual quantum boxes have the same size, but it is controlled where they are formed on the first semiconductor. It was impossible. Therefore, the following method was proposed. The first is Proceedings of the 42nd Joint Lecture on Applied Physics No. 3, 1212, 28a-SZK-17 (Fig. 9). First, the vicinal GaAs substrate is heat-treated to form the atomic layer step 21. After that, when a few atomic layers of InAs are grown in the same manner as described above, the quantum boxes 3 are selectively formed at the step ends. However, this method cannot control the position of the quantum box at each step end. The second is Proceedings of the 56th Academic Meeting of the Japan Society of Applied Physics No. 3,105
This is the method described in 7,29p-ZM-4 (Fig. 10). This is what growing InAs was patterned beforehand with SiO ₂ 31 to the GaAs substrate. Although this method can form one or two quantum boxes 3 in a pattern, it is not possible to control which position in each pattern is formed. Also, if the pattern is made as small as a quantum box by this method, the number of atoms that agglomerate due to rearrangement will be limited, so the energy reduced by aggregation will decrease, and the quantum box will be formed self-formingly. Becomes difficult. The third is Proceedings of the 56th JSAP Academic Lecture No. No. 3,1058,27p-ZM-7, in which a V-groove (FIG. 11) and a pyramid-shaped recess (FIG. 12) are formed in advance on a GaAs substrate to fabricate a self-assembled quantum box. Is the way. In this method, it is difficult to control the position of the quantum box on each slope in the V-groove type. Further, the pyramid type has the same problem as that of the V groove, and at the same time, the second semiconductor 5 formed on the top of the pyramid shown in the enlarged view (b).
Since 3 is not layered but has a triangular pyramid shape with a small surface or interface area from the beginning, the self-formation mechanism of the quantum box does not work.
Therefore, it is difficult to control the size of each quantum box.

An object of the present invention is to accurately control the position of a self-assembled quantum box and obtain a semiconductor quantum box having a uniform size and spatial position.

[0006]

The above object is to provide an opening on the main surface of a substrate made of a first semiconductor, the opening having a size to be covered by the bottom surface of the semiconductor fine structure to be manufactured, and the height of the semiconductor fine structure. A step of forming a recess having a shallower depth, a second semiconductor having a lattice constant larger than that of the first semiconductor grown on the substrate, and a semiconductor microstructure made of a semiconductor grown in the recess of the semiconductor microstructure. And forming the structure.

Further, on the main surface of the substrate made of the first semiconductor, a groove having a width narrower than the width of the fine line-shaped semiconductor fine structure to be manufactured and a depth shallower than the height of the fine line-shaped semiconductor fine structure. And forming a second semiconductor having a lattice constant larger than that of the first semiconductor on the substrate to form a semiconductor fine structure having the fine line-shaped semiconductor fine structure and the semiconductor grown in the groove. Obtained from the process.

When the lattice constant of the second semiconductor grown on the first semiconductor is smaller than that of the first semiconductor, the respective objects are achieved.

Further, an integer l representing the surface index (lmn),
When at least one of m and n is provided with a surface having a surface larger than 1, each of the objects is achieved by using the above-mentioned recess or groove as the recess or groove.

That is, according to the present invention, as shown in FIG. 1A, the position-controlled recess 4 is formed in advance on the first semiconductor substrate by means such as lithography and etching, and the recess 4 is formed.
The depth is smaller than the height of the quantum box 3 to be manufactured, and the size of the opening of the recess on the substrate surface is smaller than the bottom surface of the quantum box to be manufactured. The substrate has a second semiconductor having a lattice constant different from that of the first semiconductor.
By growing the semiconductor of (1), it is possible to manufacture a quantum box (FIG. 1 (b)) having a uniform size at the exact position of the depression. It is also possible to self-form a quantum wire whose position is controlled by forming the depression as a groove. Further, by forming the depression or groove with a surface having at least one of the integers l, m, and n representing a higher-order index surface (surface index (lmn)) larger than 1,
It facilitates the formation of the quantum box or quantum wire.

[0011]

FIG. 2 shows a process of forming a quantum box according to the present invention. Here, the case where the second semiconductor is larger than the lattice constant of the first semiconductor forming the substrate is shown. When the recess 71 is formed on the semiconductor substrate 72 and the second semiconductor 73 having a lattice constant different from that of the substrate is grown, the layer initially grows, but when several atomic layers grow, the strain energy inside the growth layer increases. When the depression is composed of low-order index planes that do not have atomic steps (FIG. 2D), atomic steps are present at the intersections between the low-index planes. When the second semiconductor is grown in the groove having such an atomic step, the number of bonds with a different atom per atom becomes the highest in the atomic step. Therefore, the strain energy due to the lattice mismatch (interface energy and internal strain energy) is most concentrated in this atomic step, so that the rearrangement of the atoms of the second semiconductor starts from this atomic step. That is, the rearrangement of atoms proceeds with the group of atoms rearranged at the atomic step inside the groove as a nucleus. This rearrangement is second
This causes deformation of the semiconductor layer, which relaxes the strain (FIG. 2E), and finally the quantum box 3 is formed and ends. In the subsequent growth, the supplied atoms are absorbed in this quantum box and the quantum box grows (FIG. 2 (f)). Although FIG. 2 shows the case where the second semiconductor has a large lattice constant, the quantum box is similarly formed even if the lattice constant is small. At this time, the strain applied to the growth film becomes tensile strain. Also,
When the depression is composed of a higher-order exponential plane as shown in FIG. 2 (g), atomic steps exist from the beginning in this exponential plane, so that a nucleus is easily formed and rearrangement easily proceeds.

Further, if the above-mentioned depression is made into a groove, it is possible to form a fine line-shaped fine structure, that is, a quantum fine line, as can be easily understood from the above description.

[0013]

【Example】

First Embodiment A first embodiment of the present invention is shown in FIG. First, GaAs (10
0) Using a molecular beam epitaxy apparatus on a substrate 1, a GaAs single film is grown to a thickness of about 0.1 μm under normal conditions as shown in FIG. The substrate thus formed is taken out from the molecular beam epitaxy apparatus, ZEP resist (ZEP520) 5 is applied, and EB is applied.
Patterning is performed by lithography. Next, it is developed with a developing solution (ZED-N50), and the size is 10 nm × 10 n.
A patterned substrate of FIG. 3C with m, depth of 2 μm and pitch of 30 nm is prepared. Next, sulfuric acid: hydrogen peroxide water: water =
Etch for 2 seconds at 4: 1: 4. In this etching, the facet surface of GaAs is not formed, and it becomes a shallow depression in which minute atomic layer steps are gathered as shown in FIG. This substrate is then dipped in a ZEP solvent (normal methylpyrrolidine) to remove the ZEP resist.
A substrate having fine patterns arranged as shown in (e) is prepared. When this substrate is put into the molecular beam epitaxy apparatus again, and the substrate temperature is 530 ° C., and about 2 atomic layers of InAs are grown,
An InAs quantum box as shown in FIG. 2 (f) is formed as shown in FIG. 3 (f). Next, when GaAs is continuously grown, this InAs quantum box 3 can be embedded with GaAs 88 as shown in FIG. The dimensions of the completed quantum box were about 20 nm in width and about 6 nm in height.

Second Embodiment A second embodiment of the present invention is shown in FIG. In this example STM
Using a (scanning tunneling microscope), the first semiconductor substrate 9
The recesses 93 are formed on the surface 2 at equal intervals. The tunnel current of the STM is made larger than that during normal image observation in order to form the depression 93.

Third Embodiment A third embodiment of the present invention is shown in FIG. In this example, in order to increase the energy difference between the quantum box which is the active layer and the barrier layer, the GaAs (100) substrate 1 is followed by the GaAs 101,
Further, AlGaAs 102 is grown, and after the same lithography and etching steps as those in the first embodiment, InAs3 is used.
Is grown to a thickness of 2 atomic layers, and AlGaAs 102 is grown again. As a result, a uniform quantum box 3 surrounded by AlGaAs is formed.

Fourth Embodiment A fourth embodiment of the present invention is shown in FIG. In this embodiment, the GaAs layer of the barrier layer is doped with Si to form the n-type modulation doping structure 111. Moreover, a p-type modulation doping structure can be produced by doping Be.

Fifth Embodiment FIG. 7 shows a fifth embodiment of the present invention. In this embodiment, n-type G
Using the aAs substrate 1, first an n-type GaAs 121 is grown, then an undoped GaAs 122 is grown, and then an InAs 3 is grown to form a self-assembled quantum box. Then, undoped GaAs122 and p-type GaAs123 are grown to form a pin junction. As a result, a pin diode having a quantum box with uniform spatial position and size in the active layer can be formed. Also, when forming the depression, B
When the r-methanol solution was used, a depression having a low index plane {111} A plane was formed, and a quantum box could be formed also in this case.

In the above example, the lattice constant of the second semiconductor is the first.
It is larger than the lattice constant of the semiconductor, but G as the second semiconductor.
When aAs is selected and InP is selected as the first semiconductor, the magnitude relation of the lattice constants is reversed. Also in this case, the quantum box could be formed. When a groove having a width of 10 nm, a length of 100 nm and a depth of 2 nm was formed on the substrate instead of the depression, a quantum wire having a width of 20 nm, a length of 110 nm and a depth of 2 nm could be formed.

[0019]

As described above, the method of manufacturing a semiconductor fine structure according to the present invention comprises:
A step of forming an opening having a size to be covered by the bottom surface of the semiconductor fine structure to be manufactured, and forming a recess having a depth shallower than the height of the semiconductor fine structure;
The second semiconductor having a lattice constant larger than that of the semiconductor is grown, and a semiconductor fine structure made of the grown semiconductor is formed in the depression of the semiconductor fine structure. By forming the depression or groove, it is possible to control the position of the self-forming quantum box formed when the second semiconductor is grown,
Quantum boxes or quantum wires having the same size and spatial position as each other can be manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor fine structure according to the present invention, in which (a) is a position-controlled recess and (b) is a quantum box formed at the position of the recess.

FIG. 2 is a diagram for explaining the basic operation of the present invention, in which (a)-
(G) is a figure explaining each step.

FIG. 3 is a diagram for explaining the first embodiment of the present invention, in which (a)-
(G) is a figure explaining each process.

4A and 4B are diagrams illustrating a second embodiment of the present invention, in which FIG. 4A is a diagram in which a depression is formed by a scanning tunneling microscope, and FIG.
[Fig. 6] is a view showing a formed depression.

FIG. 5 is a diagram illustrating a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 7 is a diagram illustrating a fifth embodiment of the present invention.

FIG. 8 is a diagram illustrating a conventional technique, and FIGS. 8A to 8C are diagrams showing a process of forming a semiconductor fine structure.

FIG. 9 is a diagram illustrating an example of a conventional technique, and (a) and (b) are diagrams showing respective steps.

FIG. 10 is a diagram illustrating an example of a conventional technique, and (a) and (b) are diagrams showing respective steps.

FIG. 11 is a diagram illustrating an example of a conventional technique, and (a) and (b) are diagrams showing respective steps.

12A and 12B are diagrams illustrating an example of a conventional technique, FIG. 12A is a perspective view thereof, and FIG. 12B is an enlarged view of an inverted pyramid-shaped depression.

[Explanation of symbols]

 1 ... Substrate 3 ... Semiconductor microstructure 4, 93 ... Dimple

Claims (5)

[Claims] 1. An opening on the main surface of a substrate made of a first semiconductor, the opening having a size to be covered by a bottom surface of a semiconductor fine structure to be manufactured, and a recess having a depth shallower than the height of the semiconductor fine structure. And a step of growing a second semiconductor having a lattice constant larger than that of the first semiconductor on the substrate and forming a semiconductor fine structure made of the semiconductor grown in the depression of the semiconductor fine structure. Method for manufacturing a semiconductor fine structure. 2. A width narrower than a width of a fine line-shaped semiconductor fine structure to be manufactured, on a main surface of a substrate made of a first semiconductor,
Forming a groove having a depth shallower than the height of the fine line-shaped semiconductor fine structure, and growing a second semiconductor having a lattice constant larger than that of the first semiconductor on the substrate to form the fine line-shaped semiconductor fine structure. A method of manufacturing a fine line-shaped semiconductor fine structure, which comprises a step of forming a semiconductor fine structure made of a semiconductor grown in the groove. 3. An opening having a size large enough to cover the bottom surface of the semiconductor microstructure to be manufactured and a recess having a depth shallower than the height of the semiconductor microstructure, on the main surface of the substrate made of the first semiconductor. And a step of growing a second semiconductor having a lattice constant smaller than that of the first semiconductor on the substrate to form a semiconductor fine structure composed of the semiconductor fine structure and the semiconductor grown in the recess. A method for manufacturing a semiconductor fine structure comprising. 4. A width narrower than a width of a fine line-shaped semiconductor fine structure to be manufactured on a main surface of a substrate made of a first semiconductor,
Forming a groove having a depth shallower than the height of the fine line-shaped semiconductor fine structure, and growing a second semiconductor having a lattice constant smaller than that of the first semiconductor on the substrate to form the fine line-shaped semiconductor fine structure. A method of manufacturing a semiconductor fine structure, comprising the step of forming a semiconductor fine structure made of a semiconductor grown in the depression. 5. A depression or groove provided with at least one of the integers l, m, and n representing the surface index (lmn) having a surface greater than 1, as the depression or groove. 4. The method for manufacturing a semiconductor fine structure according to any one of 4 above.