JP2624450B2 - Manufacturing method of quantum wire structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing quantum wires in a compound semiconductor device structure such as a semiconductor laser used in the fields of optical communication, optical information processing and optical measurement.

[0002]

2. Description of the Related Art In optical devices, electronic devices, and optoelectronic integrated circuits used in optical information processing, optical communication, optical measurement, and the like, the activity of a semiconductor laser, which is a light emitting element, is required for miniaturization and high functionality of the element. The element characteristics can be improved by introducing a structure in which ultrafine processing such as a quantum wire structure or a quantum box structure is applied to the layer. In a method of forming a quantum wire by wet etching a quantum well structure using an ultrafine pattern mask, a method using an insulating film such as a resist, an oxide film, or a nitride film as a mask at the time of etching is generally used. The thinning is performed to such an extent that the quantum confinement effect in the horizontal direction is exhibited. On the other hand, in the method using dry etching, similarly, a quantum well structure is etched by using an insulating film such as a resist, an oxide film, and a nitride film as a mask, and using an ultrafine pattern mask to form a quantum wire.

FIG. 6 is a schematic diagram showing a process of a conventional method of forming a GaAs quantum wire by wet etching, and a quantum wire is formed in the following steps (a) to (d).

A GaAs buffer layer 602, an Al0.3 Ga0.7 As barrier layer 603, a GaAs quantum well layer 604, and an Al0.3 Ga0.7 As barrier layer 605 are sequentially crystal-grown on a GaAs substrate 601 to form a mask on a wafer. A silicon oxide film 606 serving as a layer is deposited, and a resist pattern 607 is formed into a stripe pattern by electron beam lithography or the like (a).

A silicon oxide film 6 is formed by using a hydrofluoric acid-based etchant.
06 is etched to transfer a resist pattern 607 (b).

A sulfuric acid-based etchant (H 2 SO 4: H 2 O)
(2: H2O = 1: 1: 20) is sequentially etched on the Al0.3Ga0.7As barrier layer and the GaAs quantum well layer. At this time, the etching in the horizontal direction (over-etching) proceeds simultaneously with the etching in the vertical direction to form a GaAs thin line (c).

Further etching is performed, and GaAs quantum wires 608 are formed. Finally, the silicon oxide film serving as an etching mask is removed with a hydrofluoric acid based etchant (d).

[0008]

However, in the process configuration in the above-described method of forming a GaAs quantum wire by wet etching, the fine line density is determined by the pitch of the first mask pattern, and the pitch of the fine pattern is not less than the pitch of the patterning. However, there is a problem that it is impossible to increase the density of the fine wire.

Another problem is that only a cross-sectional shape having a certain aspect ratio determined by the vertical and horizontal etching rates can be formed, and it is difficult to obtain a sufficient vertical etching depth. Had.

[0010]

In order to achieve the above object, a method of manufacturing a quantum wire structure according to the present invention comprises the following means. (1) A step of forming a fine line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask, the compound semiconductor structure has directionality. A first etching step of etching in a fine line shape with the particle beam;
By over etching by wet etching,
A second etching step of narrowing the line width of the thin compound semiconductor structure formed by the first etching.
A method of manufacturing a quantum wire structure, comprising: a barrier layer, a single or multiple quantum well layer, and a second barrier layer, and removing the single or multiple quantum well layer by etching in a first etching step. (2) The method for manufacturing a quantum wire structure according to (1), wherein the line width of the single or multiple quantum well layer is reduced while removing the first barrier layer by the second etching step. (3) forming a thin line-shaped first etching mask on the compound semiconductor structure having a single or multiple quantum well layer; and using the first etching mask as a mask, the compound semiconductor structure has directionality. A first etching step of etching in a fine line shape with the particle beam;
By over etching by wet etching,
A second etching step of narrowing the line width of the thin compound semiconductor structure formed by the first etching, wherein a compound semiconductor layer continuously grown on the compound semiconductor structure is formed on the compound semiconductor structure. 1. A method for manufacturing a quantum wire structure using an etching mask. (4) a step of growing a compound semiconductor layer on the compound semiconductor structure having a single or multiple quantum well layer continuously with the compound semiconductor structure; and selectively etching the compound semiconductor layer to form a first mask. Forming a second mask on a side wall of the first mask; removing the first mask; and etching the compound semiconductor structure using the second mask as a mask. And a method for manufacturing a quantum wire structure comprising: (5) A step of growing a compound semiconductor layer continuously on the compound semiconductor structure having a single or multiple quantum well layer and a step of forming a first mask on the compound semiconductor layer Etching a part of the compound semiconductor layer using the first mask as a mask, reducing the width of the compound semiconductor layer by wet etching, and embedding the compound semiconductor layer with a predetermined material A step of etching and removing the predetermined material using the first mask as a mask; a step of removing the first mask and the compound semiconductor layer; and a step of removing the compound semiconductor using the predetermined material as a mask Forming a quantum wire by etching the structure;
The manufacturing method of the quantum wire structure provided with. (6) a step of growing a compound semiconductor layer continuously on the compound semiconductor structure having a single or multiple quantum well layer and a step of forming a first mask on the compound semiconductor layer A step of etching part of the compound semiconductor layer using the first mask as a mask, a step of reducing the width of the compound semiconductor by wet etching, and a step of etching the compound using the first mask as a mask. Forming a second mask on the semiconductor structure; and etching the compound semiconductor structure to form a quantum wire using the compound semiconductor layer and the second mask as a mask. The method of manufacturing the structure. (7) In the above (6), a method for manufacturing a quantum wire structure in which quantum wires having different widths are formed by making the intervals of the first masks substantially the same. (8) A step of forming a thin-line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask, the compound semiconductor structure has directionality. A first etching step of etching in a fine line shape with the particle beam;
By over etching by wet etching,
A second etching step of reducing the line width of the thin compound semiconductor structure formed by the first etching, wherein a material composition and a thickness of a crystal layer formed on the compound semiconductor structure are changed. A method of manufacturing a quantum wire structure in which the angle of the etching side wall of the single or multiple quantum well layer of the compound semiconductor structure after the first etching step is arbitrarily changed. (9) A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask, the compound semiconductor structure has directionality. A first etching step of etching in a fine line shape with the particle beam;
By over etching by wet etching,
A second etching step of narrowing the line width of the thin compound semiconductor structure formed by the first etching, wherein the angle of the cross section of the compound semiconductor structure formed in the first etching step is a normal mesa. A method of manufacturing a quantum wire structure in which a compound semiconductor structure of a forward mesa is etched in a second etching step capable of forming a cross section in a reverse mesa direction. (10) A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask, the compound semiconductor structure has directionality. A first etching step of etching in a fine line shape with the particle beam;
By over etching by wet etching,
A second etching step of narrowing the line width of the thin line-shaped compound semiconductor structure formed by the first etching, wherein the angle of the cross section of the compound semiconductor structure formed in the first etching step is reversed. A method of manufacturing a quantum wire structure in which a compound semiconductor structure having an inverted mesa is etched in the second etching step in which a cross section in a mesa direction and a forward mesa direction can be formed.

[0011]

In order to achieve the above object, a method for manufacturing a quantum wire structure according to the present invention comprises the following steps: (1) forming a first thin wire on a compound semiconductor structure having a single or multiple quantum well layer; Forming an etching mask, and using the first etching mask as a mask, a first etching step of etching the compound semiconductor structure in a fine line shape with a directional particle beam;
By over etching by wet etching,
A second etching step of reducing a line width of the compound semiconductor structure having a thin line shape formed by the first etching. (2) The method according to (1), wherein reactive ion beam etching is used in the first etching step. (3) a compound semiconductor structure comprising a first barrier layer from the substrate side;
The method according to (1), further comprising a single or multiple quantum well layer and a second barrier layer, wherein the single or multiple quantum well layer is etched away in the first etching step. This is a method for manufacturing a quantum wire structure. (4) The method for manufacturing a quantum wire structure according to claim 3, wherein the line width of the single or multiple quantum well layer is reduced while removing the first barrier layer by the second etching step. And (5) The method for manufacturing a quantum wire structure according to (1), wherein a compound semiconductor layer formed by continuously growing crystals on the compound semiconductor structure is used as a first etching mask. (6) a step of growing a compound semiconductor layer continuously on the compound semiconductor structure having a single or multiple quantum well layer, and selectively etching the compound semiconductor layer to form a first mask Forming a second mask on a side wall of the first mask; removing the first mask; and etching the compound semiconductor structure using the second mask as a mask. And characterized in that: (7) a step of growing a compound semiconductor layer continuously on the compound semiconductor structure having a single or multiple quantum well layer and a step of forming a first mask on the compound semiconductor layer Etching a part of the compound semiconductor layer using the first mask as a mask, reducing the width of the compound semiconductor layer by wet etching, and embedding the compound semiconductor layer with a predetermined material A step of etching and removing the predetermined material using the first mask as a mask; a step of removing the first mask and the compound semiconductor layer; and a step of removing the compound semiconductor using the predetermined material as a mask Forming a quantum wire by etching the structure. (8) A step of growing a compound semiconductor layer continuously on the compound semiconductor structure having a single or multiple quantum well layer and a step of forming a first mask on the compound semiconductor layer A step of etching part of the compound semiconductor layer using the first mask as a mask, a step of reducing the width of the compound semiconductor by wet etching, and a step of etching the compound using the first mask as a mask. Forming a second mask on the semiconductor structure; and forming a quantum wire by etching the compound semiconductor structure using the compound semiconductor layer and the second mask as masks. And (9) The method of manufacturing a quantum wire structure according to (8), wherein the intervals between the first masks are made substantially the same to form quantum wires having different widths. (10) The method of manufacturing a quantum wire structure according to (1), wherein the first etching step removes up to the lowermost end of the compound semiconductor structure by etching. (11) The method for manufacturing a quantum wire structure according to (1), wherein the side wall of the compound semiconductor structure is made substantially vertical by the first etching step. (12) In the first etching step of the compound semiconductor structure having the multiple quantum well layer, the line width of the uppermost layer and the lowermost layer of the multiple quantum well layer is made substantially equal. This is a method for manufacturing a fine wire structure. (13) By changing the material composition and thickness of the crystal layer formed on the compound semiconductor structure, the angle of the etching side wall of the single or multiple quantum well layer of the compound semiconductor structure after the first etching step is changed. The method of manufacturing a quantum wire structure according to (1), wherein the method is arbitrarily changed. (14) The cross-sectional angle of the compound semiconductor structure formed in the first etching step is in the forward mesa direction, and the compound semiconductor structure in the forward mesa is etched in the second etching step in which a cross section in the reverse mesa direction can be formed. A method for manufacturing a quantum wire structure according to (1), wherein (15) The angle of the cross section of the compound semiconductor structure formed in the first etching step is the reverse mesa direction, and the compound semiconductor structure of the reverse mesa is etched in the second etching step in which a cross section in the forward mesa direction can be formed. A method of manufacturing a quantum wire structure according to claim 1.

[0012]

According to the present invention, as a means for forming an ultrafine structure such as a quantum wire by etching using the above-described structure, a first etching step of etching with a directional particle beam having a specific incident angle, This is a method for manufacturing a compound semiconductor quantum wire structure in which a quantum wire is formed by a two-stage etching process including a second etching process for reducing the line width by side etching using wet etching. According to this method, a quantum wire can be formed with low damage and good controllability. In addition, etching at a desired depth becomes possible, and the degree of freedom in manufacturing a quantum wire is increased. Further, by forming the pattern in a lattice shape in advance, it is possible to form not only quantum wires but also a fine pattern such as a quantum box.

Another aspect of the present invention is a method of forming a thin film layer on a surface including at least an etching groove side wall, following a first etching step, ie, etching with a directional particle beam, The step of removing the thin film layer using anisotropic etching can form an etching mask pattern having a density twice as long as the initial pattern period. With this method, quantum wires can be formed with good controllability and high density.

Further, another invention is a step of covering at least a surface including an etching groove side wall with a substance serving as an etching mask, following the wet etching which is a second etching step, and the step of covering the surface other than the lower part of the first etching mask. This is a method for manufacturing a quantum wire structure by a process of removing a substance using anisotropic etching. An etching mask pattern having a density twice the initial pattern period can be formed. With this method, quantum wires can be formed with good controllability and high density.

Another aspect of the present invention resides in a step of forming a second etching mask by a vapor deposition method using a directional particle beam subsequent to wet etching as a second etching step, and a step of forming a second etching mask at an upper end portion of the fine wire. A method for manufacturing a quantum wire structure includes a step of removing the first etching mask together with the second etching mask and a third etching step of etching with a directional particle beam.
An etching mask pattern having a density twice the initial pattern period can be formed. With this method, quantum wires can be formed with good controllability and high density.

Another aspect of the present invention is a semiconductor laser having an active layer having a quantum wire structure manufactured in a step in which a thin line width formed after the second etching step and a second etching mask width are different. In this structure,
Two types of quantum wires having different line widths are formed, and a semiconductor laser having an oscillation wavelength determined by the line widths can be formed. An active layer having a quantum wire structure having two different wire widths can be formed with high controllability and high density.

[0017]

(Embodiment 1) FIG. 1 shows a process chart of a method of manufacturing a quantum wire structure of a compound semiconductor according to a first embodiment of the present invention. Here, a process of manufacturing a quantum wire in a single quantum well structure will be described.

In FIG. 1, 101 is a GaAs substrate, 1
02 is a GaAs buffer layer, 103 is Al0.3Ga0.7A
s barrier layer, 104 is a GaAs quantum well layer, 105 is Al
A 0.3Ga0.7As barrier layer, 106 is a silicon oxide film serving as an etching mask, and 107 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon oxide film.

In the steps of the method for forming a fine structure according to this embodiment configured as described above, the forming method will be described below with reference to process diagrams (a) to (e).

(A): GaAs on GaAs substrate 101
Buffer layer 102, Al0.3Ga0.7As barrier layer 103,
The GaAs quantum well layer 104 and the Al0.3Ga0.7As barrier layer 105 are continuously crystal-grown. The thickness of the GaAs buffer layer 102 is 1 μm, and the Al 0.3 Ga 0.7 As barrier layer 10
3 has a thickness of 100 nm, the GaAs quantum well layer 104 has a thickness of 10 nm, and the Al0.3Ga0.7As barrier layer 105 has a thickness of about 30 nm. Next, a silicon oxide film 106 is deposited to a thickness of about 10 nm, and a resist pattern 107 is formed by electron beam lithography. The direction of the stripe pattern may be any direction with respect to the crystal orientation. Each line and space of the pattern is 100 nm.

(B): etching the silicon oxide film 106 with a hydrofluoric acid-based etchant to form a resist pattern 107
Is transferred to form an etching mask. The resist is removed.

(C): A reactive ion beam etching is used for etching with a directional particle beam.
10.3 Ga0.7 As barrier layer 105, GaAs quantum well layer 1
04 is etched. An etching depth of about 150 nm is obtained, but the etching proceeds almost vertically, and the etching in the lateral direction hardly progresses.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. Al0.3Ga0.7As barrier layer 103 in the depth direction
And the etching proceeds in the lateral direction (undercut), and the line width of the Al0.3Ga0.7As barrier layer 105 and the GaAs quantum well layer 104 thinned in the first etching step is further reduced. The etching rate in the horizontal direction changes depending on the adhesion between the silicon oxide film 106 serving as an etching mask and the Al0.3Ga0.7As barrier layer 105, but the etching rate in the vertical direction and the horizontal direction is about 2: 1. A GaAs quantum wire 108 is formed.

(E): The silicon oxide film is etched with a hydrofluoric acid-based etchant, and the whole is crystal-grown in the Al0.3Ga0.7As buried layer 109 by using a molecular beam epitaxy method. At this time, the thickness to be grown is 200 nm. A GaAs quantum wire 108 having an embedded structure is formed.

As in this process, after the quantum well layer is patterned by substantially vertical etching (step C), the width of the quantum well layer is reduced by lateral etching (step d). Problem that "only a cross-sectional shape with a certain aspect ratio determined by the vertical and horizontal etching rates can be formed, and it is difficult to achieve sufficient vertical etching depth" Can be overcome. In particular, when the overall thickness is greater than that of a single quantum well, such as a multiple quantum well, and an etching depth is required, a quantum wire having excellent controllability of the cross-sectional shape can be formed by this two-stage etching method. Can be formed.

In the embodiment, the quantum well layer has one
Although a single quantum well structure having only layers is used, a multiple quantum well structure having multiple quantum well layers may be used. In addition, by forming the mask pattern in a lattice shape, it goes without saying that not only quantum wires but also fine patterns such as quantum boxes can be formed.

(Embodiment 2) FIG. 2 shows a process chart of a method for manufacturing a quantum wire structure of a compound semiconductor according to a second embodiment of the present invention. Here, a process of manufacturing a quantum wire in a single quantum well structure will be described. In FIG. 2, 201 is G
aAs substrate, 202 is a GaAs buffer layer, 203 is A
10.3Ga0.7As barrier layer, 204 is a GaAs quantum well layer, 205 is an Al0.3Ga0.7As barrier layer, 206 is Ga
0.5In0.5P etching stop layer, 207 is GaAs
A spacer layer, 208 is a silicon oxide film serving as an etching mask, and 209 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon oxide film.

In the steps of the method for forming a fine structure according to this embodiment configured as described above, the formation method will be described below with reference to process diagrams (a) to (g).

(A): GaAs on GaAs substrate 201
Buffer layer 202, Al0.3Ga0.7As barrier layer 203,
GaAs quantum well layer 204, Al0.3 Ga0.7 As barrier layer 205, GaInP etching stop layer 206, Ga
The As spacer layer 207 is continuously grown. Ga
The thickness of the As buffer layer 202 is 1 μm, and Al 0.3 Ga 0.7
The thickness of the As barrier layer 203 is 100 nm, the thickness of the GaAs quantum well layer 204 is 10 nm, the thickness of the Al0.3 Ga0.7 As barrier layer 205 is 30 nm, the thickness of the Ga0.5 In0.5 P etching stop layer 206 is 5 nm, The thickness of the GaAs spacer layer 207 is about 100 nm. Next, a silicon oxide film 208 is deposited to a thickness of about 10 nm, and a resist pattern 209 is formed by electron beam lithography. The direction of the stripe pattern may be any direction with respect to the crystal orientation. Each line and space of the pattern is 100 nm.

(B): The silicon oxide film 208 is etched with a hydrofluoric acid-based etchant to form a resist pattern 209.
Is transferred to form an etching mask. The resist is removed.

(C): As the etching by the directional particle beam, reactive ion beam etching is used to obtain G
The aAs spacer layer 207 is etched. About 10
Although an etching depth of 0 nm is obtained, the etching proceeds almost vertically and the etching in the lateral direction hardly progresses.

(D): The silicon oxide film 208 is removed with a hydrofluoric acid-based etchant. (E): A thin film layer of silicon nitride 210 having a thickness of 20 nm is formed on the entire exposed surface including the etching groove side wall.

(F): The silicon nitride film mask 211 is formed by removing the thin film layer other than the groove side wall, that is, the bottom and upper ends of the groove by using anisotropic etching.

(G): The GaAs spacer layer 207 is removed with a sulfuric acid-based etchant to form an etching mask pattern 211 made of silicon nitride having a period twice as long as the initially formed resist pattern. Subsequently, etching is performed to process the lower quantum well layer to form a quantum wire.

In this method of forming a quantum wire, reactive ion beam etching is used as etching with a directional particle beam. By this etching, the quantum well layer is etched into quantum wires. This etching proceeds substantially in the vertical direction, and the etching in the horizontal direction hardly progresses, so that a quantum fine wire almost as a mask can be formed.

In the structure of this process, the fine line density determined by the pitch of the initial mask pattern, which is shown in the conventional example, overcomes the problem that it is impossible to increase the fine line density beyond the patterning pitch. can do.

In the embodiment, the quantum well layer is formed by
Although a single quantum well structure having only layers is used, a multiple quantum well structure having multiple quantum well layers may be used. In addition, by forming the mask pattern in a lattice shape, it goes without saying that not only quantum wires but also fine patterns such as quantum boxes can be formed.

(Embodiment 3) FIG. 3 shows a process chart of a method for manufacturing a quantum wire structure of a compound semiconductor according to a third embodiment of the present invention. Here, a process of manufacturing a quantum wire in a single quantum well structure will be described. In FIG. 3, 301 is G
aAs substrate, 302 is a GaAs buffer layer, 303 is A
10.3Ga0.7As barrier layer, 304 is a GaAs quantum well layer, 305 is an Al0.3Ga0.7As barrier layer, 306 is Ga
0.5In0.5P etching stop layer, 307 is GaAs
A spacer layer, 308 is a silicon oxide film serving as an etching mask, and 309 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon oxide film.

In the steps of the method for forming a fine structure according to the present embodiment having the above-described structure, the method for forming the fine structure will be described below with reference to process diagrams (a) to (g).

(A): GaAs on GaAs substrate 301
Buffer layer 302, Al0.3Ga0.7As barrier layer 303,
GaAs quantum well layer 304, Al0.3 Ga0.7 As barrier layer 305, GaInP etching stop layer 306, Ga
The As spacer layer 307 is continuously grown. Ga
The thickness of the As buffer layer 302 is 1 μm, Al 0.3 Ga 0.7
The thickness of the As barrier layer 303 is 100 nm, the thickness of the GaAs quantum well layer 304 is 10 nm, the thickness of the Al0.3Ga0.7As barrier layer 305 is 30 nm, the thickness of the Ga0.5In0.5P etching stop layer 306 is 5 nm, The thickness of the GaAs spacer layer 307 is about 150 nm. Next, a silicon oxide film 308 is deposited to a thickness of about 10 nm, and a resist pattern 309 is formed by electron beam lithography. The direction of the stripe pattern may be any direction with respect to the crystal orientation. Each line and space of the pattern is 100 nm.

(B): The silicon oxide film 308 is etched with a hydrofluoric acid-based etchant to form a resist pattern 309.
Is transferred to form an etching mask. The resist is removed.

(C): As the etching by the directional particle beam, reactive ion beam etching is used to obtain G
The aAs spacer layer 307 is etched by about 50 nm. The etching proceeds substantially in the vertical direction, and the etching in the horizontal direction hardly proceeds.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. While etching the GaAs spacer layer 307 in the depth direction, the etching also proceeds in the horizontal direction (undercut), and the etching rate in the horizontal direction is reduced by the adhesion between the silicon oxide film 308 serving as an etching mask and the GaAs spacer layer 307. Although varying, the vertical and horizontal etch rates are approximately 2: 1. In this etchant, the etching in the depth direction was Ga0.5I.
Stop at the n0.5P etching stop layer 306.

(E): The entire exposed crystal surface including the etching groove side wall is buried with polyimide 310. At this time, the thickness of the first GaAs spacer layer is 150 n.
m.

(F): As the etching with the directional particle beam, the polyimide 310 is etched by about 50 nm using reactive ion beam etching. The etching proceeds substantially in the vertical direction, and the etching in the horizontal direction hardly proceeds.

(G): After removing the silicon oxide film 308 with a hydrofluoric acid-based etchant, the GaAs spacer layer is removed with a sulfuric acid-based etchant. An etching mask made of polyimide is formed. This mask has twice the period of the resist pattern formed first. Subsequently, etching is performed to process the lower quantum well layer to form a quantum wire.

In this method of forming a quantum wire, reactive ion beam etching is used as etching with a directional particle beam. By this etching, the quantum well layer is etched into quantum wires. This etching proceeds substantially in the vertical direction, and the etching in the horizontal direction hardly progresses, so that a quantum fine wire almost as a mask can be formed.

In this process configuration, an etching mask pattern having a density twice as high as the initial mask pattern can be produced. The fine line density determined by the pitch of the initial mask pattern, which is shown in the conventional example, can overcome the problem that it is impossible to increase the density of the fine lines beyond the patterning pitch.

In the embodiment, the quantum well layer has one
Although a single quantum well structure having only layers is used, a multiple quantum well structure having multiple quantum well layers may be used. In addition, by forming the mask pattern in a lattice shape, it goes without saying that not only quantum wires but also fine patterns such as quantum boxes can be formed.

(Embodiment 4) FIG. 4 shows a process chart of a method for manufacturing a compound semiconductor quantum wire structure according to a fourth embodiment of the present invention. Here, a process of manufacturing a quantum wire in a single quantum well structure will be described. In FIG. 4, 401 is G
aAs substrate, 402 is a GaAs buffer layer, 403 is A
10.3Ga0.7As barrier layer, 404 is a GaAs quantum well layer, 405 is an Al0.3Ga0.7As barrier layer, 406 is Ga
An As spacer layer, 407 is a silicon nitride film serving as an etching mask, and 408 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon nitride film.

In the steps of the method for forming a fine structure according to the present embodiment having the above-described structure, the method for forming the fine structure will be described below with reference to process diagrams (a) to (h).

(A): GaAs on GaAs substrate 401
Buffer layer 402, Al0.3Ga0.7As barrier layer 403,
The GaAs quantum well layer 404, the Al0.3Ga0.7As barrier layer 405, and the GaAs spacer layer 406 are continuously grown. The thickness of the GaAs buffer layer 402 is 1 μm,
The thickness of the l0.3Ga0.7As barrier layer 403 is 100 nm,
The thickness of the aAs quantum well layer 404 is 10 nm,
The thickness of the a0.7As barrier layer 405 is 30 nm, and the thickness of the GaAs spacer layer 406 is about 150 nm. Next, a silicon nitride film 407 is deposited to a thickness of about 10 nm, and a resist pattern 408 is formed by electron beam lithography. The direction of the stripe pattern may be any direction with respect to the crystal orientation. The line width of the pattern is 100 nm and the space is 30 nm.

(B): etching the silicon nitride film 407 with a phosphoric acid-based etchant to form a resist pattern 40
8 is transferred and used as an etching mask. The resist is removed.

(C): As the etching by the directional particle beam, reactive ion beam etching is used to obtain G
The aAs spacer layer 406 is etched. Although an etching depth of 50 nm is obtained, the etching proceeds almost vertically and the etching in the lateral direction hardly progresses.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. While etching the GaAs spacer layer 406 in the depth direction, the etching also proceeds in the lateral direction (undercut), and the lateral etching rate is reduced by the adhesion between the silicon nitride film 407 as an etching mask and the GaAs spacer layer 406. Although varying, the vertical and horizontal etch rates are approximately 2: 1. The etching time is controlled so that the fine line width becomes 30 nm.

(E): A silicon oxide film is deposited by a directional method such as an electron beam evaporation method or a sputtering method. The silicon oxide film 409 is a silicon nitride film 4
07 and an Al0.3Ga0.7As barrier layer 405 which is not covered by the eaves of the silicon nitride film 407.

(F): When the silicon nitride film 407 is etched with a phosphoric acid-based etchant,
7 is removed, and the silicon oxide film 409 on the
Only the upper part of the Ga0.7As barrier layer 405 remains as an etching mask. The width of this etching mask is the space of the resist pattern formed first. (G): As etching by directional particle beam,
GaAs top using reactive ion beam etching
Etching is performed until all the spacer layers 406 are etched. Al0.3Ga0.7As barrier layer 405, GaAs quantum well layer 404, and Al0.3Ga which are not covered with silicon oxide film 409 and GaAs spacer layer 406.
The 0.7 As barrier layer 403 is etched to approximately 150
Although an etching depth of nm is obtained, the etching proceeds almost vertically, and the etching in the lateral direction hardly progresses. A GaAs quantum wire 410 is formed.

(H): The silicon oxide film 409 is etched with a hydrofluoric acid-based etchant, and the whole is etched using a molecular beam epitaxy method to form an Al0.3Ga0.7As buried layer 411.
The crystal grows. At this time, the thickness to be grown is 200 nm.
It is. A GaAs quantum wire 410 having an embedded structure is formed.

In the structure of this process, an etching mask pattern having a density twice as high as that of the first mask pattern can be produced. The fine line density determined by the pitch of the initial mask pattern, which is shown in the conventional example, can overcome the problem that it is impossible to increase the density of the fine lines beyond the patterning pitch.

In the embodiment, one quantum well layer is used.
Although a single quantum well structure having only layers is used, a multiple quantum well structure having multiple quantum well layers may be used. In addition, by forming the mask pattern in a lattice shape, it goes without saying that not only quantum wires but also fine patterns such as quantum boxes can be formed.

(Embodiment 5) FIG. 5 shows a process chart of a method of manufacturing a quantum wire structure of a compound semiconductor according to a fifth embodiment of the present invention. A process for producing a quantum wire having two types of line widths to be introduced into an active layer of a semiconductor laser will be described. In FIG. 5, 501 is a GaAs substrate, 502 is GaAs
A buffer layer 503 is an Al0.3Ga0.7As barrier layer;
4 is a GaAs quantum well layer, 505 is Al0.3Ga0.7As
A barrier layer, 506 is a GaAs spacer layer, 507 is a silicon nitride film serving as an etching mask, and 508 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon nitride film.

In the steps of the method for forming a fine structure according to this embodiment having the above-described structure, the method for forming the fine structure will be described below with reference to process diagrams (a) to (h).

(A): GaAs on GaAs substrate 501
Buffer layer 502, Al0.3Ga0.7As barrier layer 503,
The GaAs quantum well layer 504, the Al0.3Ga0.7As barrier layer 505, and the GaAs spacer layer 506 are continuously grown. The thickness of the GaAs buffer layer 502 is 1 μm,
The thickness of the l0.3Ga0.7As barrier layer 503 is 100 nm,
The thickness of the aAs quantum well layer 504 is 10 nm,
The thickness of the a0.7As barrier layer 505 is 30 nm, and the thickness of the GaAs spacer layer 506 is about 150 nm. Next, a silicon nitride film 507 is deposited to a thickness of about 10 nm, and a resist pattern 508 is formed by electron beam lithography. The direction of the stripe pattern may be any direction with respect to the crystal orientation. Each line and space of the pattern is 100 nm.

(B): etching the silicon nitride film 507 with a phosphoric acid-based etchant to form a resist pattern 50
8 is transferred and used as an etching mask. The resist is removed.

(C): As the etching by the directional particle beam, reactive ion beam etching is used to obtain G
The aAs spacer layer 506 is etched. Although an etching depth of 50 nm is obtained, the etching proceeds almost vertically and the etching in the lateral direction hardly progresses.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. While etching the GaAs spacer layer 506 in the depth direction, the etching also proceeds in the horizontal direction (undercut), and the etching rate in the horizontal direction is reduced due to the adhesion between the silicon nitride film 507 as an etching mask and the GaAs spacer layer 506. Although varying, the vertical and horizontal etch rates are approximately 2: 1. The etching time is controlled so that the fine line width becomes 10 nm.

(E): A silicon oxide film is deposited by a directional method such as an electron beam evaporation method or a sputtering method. The silicon oxide film 509 is a silicon nitride film 5
07 and an Al0.3Ga0.7As barrier layer 505 which is not covered by the eaves of the silicon nitride film 507.

(F): When the silicon nitride film 507 is etched with a phosphoric acid-based etchant,
7 is removed, and the silicon oxide film 509 on the
Only the upper part of the Ga0.7As barrier layer 505 remains as an etching mask. The width of this etching mask is 100 nm, which is the space of the resist pattern formed first.

(G): As the etching with the directional particle beam, the etching is performed by using the reactive ion beam etching until the upper GaAs spacer layer 506 is entirely etched. Silicon oxide film 509 and Ga
Al0.3 not covered by As spacer layer 506
Ga0.7As barrier layer 505, GaAs quantum well layer 50
4. The Al0.3Ga0.7As barrier layer 503 is etched to obtain an etching depth of about 150 nm,
The etching proceeds substantially in the vertical direction, and the etching in the horizontal direction hardly proceeds. The line width is 30 nm each,
100 nm different GaAs quantum wires 510 and 511 are formed.

(H): The silicon oxide film 509 is etched with a hydrofluoric acid-based etchant, and the whole is etched using molecular beam epitaxy to form an Al0.3Ga0.7As buried layer 512.
The crystal grows. At this time, the thickness to be grown is 200 nm.
It is. Embedded-structure GaAs quantum wires 510;
511 are formed.

According to the structure of this process, a semiconductor laser having a quantum wire structure having a different thin line width in the active layer can be manufactured, and an oscillation wavelength determined by the thin line width, that is, a semiconductor laser having two different oscillation wavelengths can be formed. it can. In addition, each fine line density can be manufactured with the initial mask pattern density.

(Embodiment 6) FIG. 7 shows a process chart of a method of manufacturing a quantum wire structure of a compound semiconductor according to a sixth embodiment of the present invention. Here, a process of manufacturing a multiple quantum wire from a multiple quantum well structure will be described.

Hereinafter, the forming method will be described with reference to process diagrams (a) to (e).
It will be described according to. (A): GaAs buffer layer 7 on GaAs substrate 701
02, Al_0.3Ga_0.7As barrier layer 703, Al_0.3Ga
_0.7As / GaAs multiple quantum well layer 704, Al _0.3Ga
_0.7The As barrier layer 705 is continuously grown. Ga
The thickness of the As buffer layer 702 is 1 μm,_0.3Ga_0.7
The thickness of the As barrier layer 703 is 100 nm,_0.3Ga_0.7
The thickness of the As / GaAs multiple quantum well layer 704 is 75 n.
m, Al_0.3Ga_0.7The thickness of the As barrier layer 705 is 30 nm.
It is about. Next, a silicon oxide film 706 is formed to a thickness of 10 nm.
Deposited to a degree and resist patterning by electron beam lithography.
707 is formed. The direction of the stripe pattern is
The crystal orientation may be any direction. Pattern lines
And space is 100 nm each.

(B): The silicon oxide film 706 is etched with a hydrofluoric acid-based etchant to form a resist pattern 707.
Is transferred to form an etching mask. The resist is removed.

(C): A reactive ion beam etching is used for etching with a directional particle beam.
l _0.3 Ga _0.7 As barrier layer 705, Al _0.3 Ga _0.7 As /
The GaAs multiple quantum well layer 704 and the Al _0.3 Ga _0.7 As barrier layer 703 are continuously etched. About 200n
Although an etching depth of m is obtained, the etching is performed under such a condition that the etching proceeds almost vertically, and the etching in the horizontal direction hardly proceeds.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. Al _0.3 Ga _0.7 As barrier layer 70 in the depth direction
3. While etching the GaAs buffer layer, the etching also progresses in the lateral direction (undercut), and the Al _0.3 Ga _0.7 As barrier layer 705 and the Al _0.3 Ga _0.7 As / GaAs multiplex thinned in the first etching step. The line width of the quantum well layer 704 is further reduced. Although the etching rate in the horizontal direction changes due to the adhesion between the silicon oxide film 706 serving as an etching mask and the Al _0.3 Ga _0.7 As barrier layer 705, the etching rates in the vertical and horizontal directions are about 2:
It will be about 1. A GaAs multiple quantum wire 708 is formed.

(E): The silicon oxide film is etched with a hydrofluoric acid-based etchant, and the whole is crystal-grown on the Al _0.3 Ga _0.7 As buried layer 709 by molecular beam epitaxy. At this time, the thickness to be grown is about 300 nm. GaAs multiple quantum wire 708 with embedded structure
Is formed.

As described above, since the multiple quantum well layer and the barrier layer are simultaneously etched to have the same width by the substantially vertical etching, and the thin line structure is obtained by the horizontal etching, the same can be achieved.

Although the multiple quantum wire layer is substantially perpendicular to the substrate here, even if the cross section is oblique (the cross section is a parallelogram), the widths of the uppermost layer and the lowermost layer are the same. May be a multiple quantum wire structure.

As a result, as shown in the conventional example, "only a cross-sectional shape having a certain aspect ratio determined by the etching rate in the vertical direction and the horizontal direction can be formed, and the etching depth in the vertical direction can be sufficiently obtained. Is difficult. " In particular, when the overall thickness is greater than that of a single quantum well, such as a multiple quantum well, and an etching depth is required, the two-step etching method can provide a uniform cross-sectional shape, in particular, a uniform vertical line width. It is possible to form a quantum wire having excellent properties.

In the embodiment, quantum wires are manufactured. However, by forming a mask pattern in a lattice pattern, it is possible to form not only quantum wires but also a fine pattern such as a quantum box. Needless to say.

(Embodiment 7) FIG. 8 is a flow chart showing a method of manufacturing a compound semiconductor quantum wire structure according to a seventh embodiment of the present invention. Here, a process of manufacturing a multiple quantum wire from a multiple quantum well structure will be described.

Hereinafter, the formation method will be described with reference to the process diagram (a).
A description will be given according to (e). (A): GaAs buffer layer 8 on GaAs substrate 801
02, Al_0.3Ga_0.7As barrier layer 803, Al_0.3Ga
_0.7As / GaAs multiple quantum well layer 804, Al _0.3Ga
_0.7The As barrier layer 805 is continuously grown. Ga
The thickness of the As buffer layer 802 is 1 μm,_0.3Ga_0.7
The thickness of the As barrier layer 803 is 100 nm,_0.3Ga_0.7
The thickness of the As / GaAs multiple quantum well layer 804 is 75 n
m, Al_0.3Ga_0.7The thickness of the As barrier layer 805 is 30 nm.
It is about. Next, a silicon oxide film 806 is formed to a thickness of 10 nm.
Deposited to a degree and resist patterning by electron beam lithography.
807 is formed. The direction of the stripe pattern is
The crystal orientation may be any direction. Pattern lines
And space is 100 nm each.

(B): The silicon oxide film 806 is etched with a hydrofluoric acid-based etchant to form a resist pattern 807
Is transferred to form an etching mask. The resist is removed.

(C): A reactive ion beam etching is used as the etching with the directional particle beam.
l _0.3 Ga _0.7 As barrier layer 805, Al _0.3 Ga _0.7 As /
The GaAs multiple quantum well layer 804 is continuously etched. Here, the etching is stopped until Al _0.3 Ga _{0 .7} As / GaAs multiple quantum well layer 804. The etching depth can be controlled by controlling the etching time.
Although an etching depth of 5 nm is obtained, the etching is performed under such a condition that the etching proceeds almost vertically, and the etching in the horizontal direction hardly proceeds. Where Al _0.3
The etching is stopped up to the Ga _0.7 As / GaAs multiple quantum well layer 804 in order to make the line width after the etching uniform and to minimize the damage to the underlying Al _0.3 Ga _0.7 As barrier layer 803. It is.

(D): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 1: 1: 20 as an etchant. Al _0.3 Ga _0.7 As barrier layer 803 in the depth direction
And the etching progresses in the lateral direction (undercut), and the Al _0.3 Ga _0.7 As barrier layer 805 and the Al _0.3 G thinned in the first etching step.
The line width of the a _0.7 As / GaAs multiple quantum well layer 804 is further reduced. Silicon oxide film 8 serving as an etching mask
The etching rate in the lateral direction by 06 and adhesion between the Al _0.3 Ga _0.7 As barrier layer 805 changes, the etch rate in the longitudinal direction and the lateral direction is about 2: is about 1. GaAs
An s multiple quantum wire 808 is formed.

(E): The silicon oxide film 806 is etched with a hydrofluoric acid-based etchant, and the whole is etched by molecular beam epitaxy to form an Al _0.3 Ga _0.7 As buried layer 809.
The crystal grows. The thickness grown at this time is 300 nm
It is about. A GaAs multiple quantum wire 808 having an embedded structure is formed.

In the embodiment, quantum wires are manufactured. However, by forming a mask pattern in a lattice pattern, it is possible to form not only quantum wires but also a fine pattern such as a quantum box. Needless to say.

(Embodiment 8) FIG. 9 shows a process chart of a method for manufacturing a compound semiconductor quantum wire structure according to an eighth embodiment of the present invention. Here, a process of manufacturing a multiple quantum wire from a multiple quantum well structure will be described.

Hereinafter, the formation method will be described with reference to the process diagram (a).
A description will be given according to (f). (A): GaAs buffer layer 9 on GaAs substrate 901
02, Al_0.3Ga_0.7As barrier layer 903, Al_0.3Ga
_0.7As / GaAs multiple quantum well layer 904, Al _0.3Ga
_0.7The As barrier layer 905 is continuously grown. Ga
The thickness of the As buffer layer 902 is 1 μm,_0.3Ga_0.7
The thickness of the As barrier layer 903 is 100 nm,_0.3Ga_0.7
The thickness of the As / GaAs multiple quantum well layer 904 is 75 n.
m, Al_0.3Ga_0.7The thickness of the As barrier layer 905 is 30 nm.
It is about. Next, a silicon oxide film 906 is formed to a thickness of 10 nm.
Deposited to a degree and resist patterning by electron beam lithography.
907 is formed. The direction of the stripe pattern is
The crystal orientation may be any direction. Pattern lines
And space is 100 nm each.

(B): The pattern is formed in a direction satisfying the crystal orientation shown in the figure. That is, a mask pattern is formed in a direction that satisfies the condition for forming an inverted mesa cross section during wet etching. That is, the substrate is (10
The (0) plane and the side surface are the (0-11) plane, and the cross section (the cross section perpendicular to the resist pattern) is the (0-1-1-1) plane.

(C): The silicon oxide film 906 is etched with a hydrofluoric acid-based etchant to form a resist pattern 907.
Is transferred to form an etching mask. The resist is removed.

(D): Reactive ion beam etching is used for etching with directional particle beams.
l _0.3 Ga _0.7 As barrier layer 905, Al _0.3 Ga _0.7 As /
The GaAs multiple quantum well layer 904 is continuously etched. Here, the etching is stopped until Al _0.3 Ga _{0 .7} As / GaAs multiple quantum well layer 804. The etching depth can be controlled by controlling the etching time.
Although an etching depth of 5 nm can be obtained, the etching is performed under such conditions that a forward mesa orientation is obtained.

(E): Wet etching is performed using sulfuric acid: hydrogen peroxide: water = 3: 1: 1 as an etchant. In addition to etching the Al _0.3 Ga _0.7 As barrier layer 903 in the depth direction, the etching also proceeds in the lateral direction (undercut), and the Al _0.3 Ga _0.7 As barrier layer 905, which has been thinned in the first etching step, _0.3 Ga
The line width of the _0.7 As / GaAs multiple quantum well layer 904 is further reduced. At this time, since the pattern is formed in the direction in which the reverse mesa orientation is formed, the normal mesa shape formed by the first stage etching changes to the reverse mesa shape as the etching progresses. The wet etching is stopped when the sectional angle becomes vertical. In wet etching, a silicon oxide film 9 serving as an etching mask
The etching rate in the lateral direction by 06 and adhesion between the Al _0.3 Ga _0.7 As barrier layer 905 changes, the etch rate in the longitudinal direction and the lateral direction is about 2: is about 1. A GaAs multiple quantum wire 908 having a vertical cross section, that is, the upper and lower line widths of the multiple quantum wire portion are formed.

(F): The silicon oxide film 906 is etched with a hydrofluoric acid-based etchant, and the whole is etched using an Al _0.3 Ga _0.7 As buried layer 909 by molecular beam epitaxy.
The crystal grows. The thickness grown at this time is 300 nm
It is about. A GaAs multiple quantum wire 908 having an embedded structure is formed.

In the embodiment, the etching is performed in the second etching step in which the cross section formed in the first etching step has a forward mesa direction and a cross section in the reverse mesa direction is formed. Of course, it is needless to say that the etching can be performed in the second etching step in which the cross section formed in the first etching step has a reverse mesa direction and the cross section in the forward mesa direction is formed.

The silicon oxide film 906 formed on the barrier layer 905 has another material composition or its thickness is changed so that the silicon oxide film 906 below the oxide film 906 can be formed.
It has been experimentally confirmed that the angles of the etching side walls of the barrier layers 903 and 905 and the quantum well layer 905 can be arbitrarily changed.

Although the quantum wires are manufactured, it goes without saying that not only the quantum wires but also a fine pattern such as a quantum box can be formed by forming the mask pattern in a lattice shape.

[0099]

As described above, according to the present invention,
A method for forming a quantum wire structure of a compound semiconductor with low damage, good controllability, and high density can be provided, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a quantum wire structure according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a quantum wire structure according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a quantum wire structure according to a third embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing a quantum wire structure according to a fourth embodiment of the present invention.

FIG. 5 is a process sectional view of a method for manufacturing a quantum wire structure according to a fifth embodiment of the present invention.

FIG. 6 is a process sectional view of a conventional method for manufacturing a quantum wire structure on a GaAs-based compound semiconductor substrate.

FIG. 7 is a process sectional view of a method for manufacturing a quantum wire structure according to a sixth embodiment of the present invention.

FIG. 8 is a process sectional view of a method for manufacturing a quantum wire structure according to a seventh embodiment of the present invention.

FIG. 9 is a process sectional view of a method for manufacturing a quantum wire structure according to an eighth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 101 GaAs substrate 102 GaAs buffer layer 103 Al0.3 Ga0.7 As barrier layer 104 GaAs quantum well layer 105 Al0.3 Ga0.7 As barrier layer 106 Silicon oxide film serving as etching mask 107 Resist pattern 108 GaAs quantum wire 109 embedded with Al0.3 Ga0.7 As Layer 201 GaAs substrate 202 GaAs buffer layer 203 Al0.3 Ga0.7 As barrier layer 204 GaAs quantum well layer 205 Al0.3 Ga0.7 As barrier layer 206 Ga0.5 In0.5 P etching stop layer 207 GaAs spacer layer 208 Silicon oxide film serving as an etching mask 209 Resist pattern 210 Silicon nitride film 211 Silicon nitride film mask 301 GaAs substrate 302 GaAs buffer layer 303 Al0.3 Ga0.7 As barrier layer 304 GaAs quantum well layer 30 Al0.3Ga0.7As barrier layer 306 Ga0.5In0.5P etching stop layer 307 GaAs spacer layer 308 Silicon oxide film serving as an etching mask 309 Resist pattern 310 Polyimide 311 Polyimide mask 401 GaAs substrate 402 GaAs buffer layer 403 Al0.3Ga0.7As barrier Layer 404 GaAs quantum well layer 405 Al0.3 Ga0.7 As barrier layer 406 GaAs spacer layer 407 Silicon nitride film 408 as an etching mask 408 Resist pattern 409 Silicon oxide film 410 GaAs quantum wires 411 Al0.3 Ga0.7 As buried layer 501 GaAs substrate 502 GaAs Buffer layer 503 Al0.3 Ga0.7 As barrier layer 504 GaAs quantum well layer 505 Al0.3 Ga0.7 As barrier layer 506 GaAs spacer layer 507 Etchin Silicon nitride film 508 as a mask Resist pattern 509 Silicon oxide film 510 GaAs quantum wire 511 GaAs quantum wire 512 Al0.3Ga0.7As buried layer 601 GaAs substrate 602 GaAs buffer layer 603 Al0.3Ga0.7As barrier layer 604 GaAs quantum well layer 605 Al0.3Ga0.7As barrier layer 606 a silicon oxide film 607 resist pattern 608 GaAs quantum wire 701 GaAs substrate 702 GaAs buffer layer 703 Al _0.3 Ga _0.7 As barrier layer 704 Al _0.3 Ga _0.7 As / GaAs multiple quantum well layer 705 Al _0.3 Ga _0.7 silicon oxide film serving as as barrier layer 706 an etch mask 707 resist pattern 708 GaA multi s quantum wires 709 Al _0.3 Ga _0.7 as buried layer 801 GaAs substrate 802 G As buffer layer 803 Al _0.3 Ga _0.7 As barrier layer 804 Al _0.3 Ga _0.7 As / GaAs multiple quantum well layer 805 Al _0.3 Ga _0.7 As barrier layer 806 a silicon oxide film 807 resist pattern 808 GaAs multiple quantum wire 809 Al _0.3 as an etching mask Ga _0.7 As buried layer 901 GaAs substrate 902 GaAs buffer layer 903 Al _0.3 Ga _0.7 As barrier layer 904 Al _0.3 Ga _0.7 As / GaAs multiple quantum well layer 905 Al _0.3 Ga _0.7 As barrier layer 906 Silicon oxide film used as etching mask 907 Resist pattern 908 GaAs multiple quantum wire 909 Al _0.3 Ga _0.7 As buried layer

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-124938 (JP, A) IEICE Technical Report, CPM 92-121 to 131 (Hei 4-11-19) 31-36 APPL. PHYS. LETT. 63 (7), (16 AUG. 1993) p. 905-907 JPN. J. APPL. PHYS. P HYS. PART2, VOL. 31, NO. 7B (15JULY.1992) P. (L990-L991)

Claims (10)

(57) [Claims] 1. A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask to direct the compound semiconductor structure. A first etching step of etching in a fine line shape with a particle beam having, and an over-etching by wet etching,
A second etching step of reducing the line width of the thin compound semiconductor structure formed by the first etching, wherein the compound semiconductor structure is a first barrier layer, a single barrier layer or a multiple barrier layer from the substrate side. A method for manufacturing a quantum wire structure, comprising a quantum well layer and a second barrier layer, wherein up to the single or multiple quantum well layer is removed by etching in a first etching step. 2. The quantum wire structure according to claim 1, wherein the line width of the single or multiple quantum well layer is reduced by removing the first barrier layer by the second etching step. Production method. 3. A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask to direct the compound semiconductor structure. A first etching step of etching in a fine line shape with a particle beam having, and an over-etching by wet etching,
A second etching step of narrowing the line width of the thin line-shaped compound semiconductor structure formed by the first etching; and forming a compound semiconductor layer on which crystal is continuously grown on the compound semiconductor structure. A method for manufacturing a quantum wire structure, wherein the method is used as an etching mask of (1). 4. A step of growing a compound semiconductor layer on the compound semiconductor structure having a single or multiple quantum well layer continuously with the compound semiconductor structure, and selectively etching the compound semiconductor layer to form a first layer. Forming a second mask on a side wall of the first mask; removing the first mask; and etching the compound semiconductor structure using the second mask as a mask. A method for manufacturing a quantum wire structure, comprising: 5. A step of growing a compound semiconductor layer continuously with the compound semiconductor structure on a compound semiconductor structure having a single or multiple quantum well layer; and forming a first mask on the compound semiconductor layer. Performing a step of etching a part of the compound semiconductor layer using the first mask as a mask; reducing the width of the compound semiconductor layer by wet etching; and forming the compound semiconductor layer into a predetermined material. Embedding, removing the predetermined material by etching using the first mask as a mask, removing the first mask and the compound semiconductor layer, and using the predetermined material as a mask, Forming a quantum wire by etching the compound semiconductor structure. A method for manufacturing a quantum wire structure, comprising: 6. A step of growing a compound semiconductor layer continuously with the compound semiconductor structure on a compound semiconductor structure having a single or multiple quantum well layer, and forming a first mask on the compound semiconductor layer. Performing a step of: etching a part of the compound semiconductor layer using the first mask as a mask; reducing the width of the compound semiconductor by wet etching; and using the first mask as a mask. Forming a second mask on the compound semiconductor structure; and forming a quantum wire by etching the compound semiconductor structure using the compound semiconductor layer and the second mask as masks. A method for manufacturing a quantum wire structure, characterized in that: 7. The distance between the first masks is substantially the same,
7. The method according to claim 6, wherein quantum wires having different widths are formed. 8. A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask to direct the compound semiconductor structure. A first etching step of etching in a fine line shape with a particle beam having, and an over-etching by wet etching,
A second etching step of reducing a line width of the thin compound semiconductor structure formed by the first etching, wherein a material composition and a thickness of a crystal layer formed on the compound semiconductor structure are changed. A method of manufacturing a quantum wire structure, wherein the angle of the etching side wall of the single or multiple quantum well layer of the compound semiconductor structure after the first etching step is arbitrarily changed. 9. A step of forming a thin line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask to direct the compound semiconductor structure. A first etching step of etching in a fine line shape with a particle beam having, and an over-etching by wet etching,
A second etching step for reducing the line width of the thin compound semiconductor structure formed by the first etching, wherein the angle of the cross-section of the compound semiconductor structure formed in the first etching step is a regular mesa. A method of manufacturing a quantum wire structure, wherein the compound semiconductor structure of the normal mesa is etched in a second etching step capable of forming a cross section in the direction opposite to the mesa. 10. A step of forming a thin-line-shaped first etching mask on a compound semiconductor structure having a single or multiple quantum well layer, and using the first etching mask as a mask to direct the compound semiconductor structure. A first etching step of etching in a fine line shape with a particle beam having, and an over-etching by wet etching,
A second etching step of reducing the line width of the thin compound semiconductor structure formed by the first etching, wherein the angle of the cross section of the compound semiconductor structure formed in the first etching step is reversed. A method for manufacturing a quantum wire structure, characterized in that the compound semiconductor structure of the inverse mesa is etched in the second etching step in which a cross section in a mesa direction and a forward mesa direction can be formed.