JPH05291237A - Formation method of microstructure in compound semiconductor - Google Patents

Abstract

PURPOSE:To provide the formation method of an AlxGa1-xAs/GaAs-based microstructure with excellent controllability, uniformity, resistance to damage and workability. CONSTITUTION:The following are crystal-grown continuously on a GaAs substrate 11: a GaAs buffer layer 12; an Al0.3Ga0.7As barrier layer 13; a GaAs quantum well layer 14; an Al0.3Ga0.7As barrier layer 15; and a Ga0.5In0.5P spacer layer 16. Then, a silicon oxide film 17 is deposited; a resist pattern 18 is formed; the silicon oxide film 17 is etched. The Ga0.5In0.5P spacer layer 16 is etched; a pattern by the silicon oxide film is transferred. At this time, the Al0.3Ga0.7As barrier layer 15 is not etched by a hydrochloric acid-based etchant. While the silicon oxide film and the Ga0.5In0.5P spacer layer are used as an etching mask, the Al0.3Ga0.7As barrier layer, the GaAs well layer and the Al0.3Ga0.7As barrier layer are etched sequentially by a dry etching operation. At this time, the silicon oxide film acts sufficiently as a mask because its etch rate at the dry etching operation is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine structure of a compound semiconductor in a compound semiconductor device such as a semiconductor laser used in the fields of optical communication, optical information processing and optical measurement.

[0002]

2. Description of the Related Art In optical devices, electronic devices, and optoelectronic integrated circuits used in optical information processing, optical communication, optical measurement, etc., the activity of a semiconductor laser, which is a light emitting element, is required in order to miniaturize and enhance the functionality of the element. It is possible to improve device characteristics by introducing a structure in which ultrafine processing such as a quantum wire or a quantum box structure is introduced into the layer. Among the methods for forming a quantum wire by etching a quantum well structure using an ultrafine pattern mask, in etching a compound semiconductor having a quantum well structure of GaAs or Al _x Ga _{1 -x} As system, a wet etching is performed. An insulating film such as a resist, an oxide film, or a nitride film is used as an etching mask of.

FIG. 4 is a schematic view showing a process of a conventional method for forming a GaAs quantum wire using etching, and the quantum wire is formed by the following steps.

GaAs buffer layer 4 on GaAs substrate 41
2. A silicon oxide film 46 serving as a mask layer is deposited on a wafer having a quantum well structure in which an Al _0.3 Ga _0.7 As barrier layer 43, a GaAs quantum well layer 44, and an Al _0.3 Ga _0.7 As barrier layer 45 are sequentially grown. A resist pattern 47 is formed by electron beam lithography or the like so that the stripe pattern has a crystal orientation (110) direction (a).

Silicon oxide film 4 with a hydrofluoric acid type etchant
6 is etched, and the resist pattern 47 is transferred (b).

Sulfuric acid type etchant (H ₂ SO ₄ : H
₂ O ₂ : H ₂ O = 1: 1: 20) is sequentially etched into the Al _0.3 Ga _0.7 As barrier layer and the GaAs quantum well layer.
At that time, the etching in the horizontal direction (overetching) simultaneously with the etching in the vertical direction progresses to form quantum wires (c).

The silicon oxide film as an etching mask is removed with a hydrofluoric acid type etchant (d).

If etching is selective,
It is preferable to use a continuously grown crystal layer as an etching mask, but GaAs and Al _x Ga _1-x As are used.
However, since there is no etchant capable of obtaining sufficient etching selectivity, an insulating film such as a resist, a silicon oxide film, or a silicon nitride film is used.

[0009]

However, in the process configuration of the forming method using wet etching of GaAs quantum wires as described above, there is a problem that lateral etching (overetching) immediately below the etching mask proceeds. I had. With such a method, it is difficult to obtain a desired etching depth even if a high-density and ultra-fine mask pattern is used, and it becomes difficult to manufacture a high-density quantum wire, which is disadvantageous especially when manufacturing a device. Become. In order to obtain high-density and highly uniform etching, there is a method of using dry etching having a large aspect ratio, but it has a problem that a damaged layer is generated during etching. In addition, Al _x Ga _1-x As and GaA
In s, the etching selectivity by the etchant is small,
An etching method that selectively etches one is difficult.

In view of the above points, the present invention is directed to Al _x Ga _{1 -x} A
An object of the present invention is to provide a method for forming a fine structure of a compound semiconductor such as an s / GaAs-based quantum wire with low damage, good controllability, and high density.

[0011]

The present invention relates to Al _x Ga _1-x.
Ga _x In _1-x P (0 ≤ x ≤ 1) is added to a compound semiconductor having an As (0 ≤ x ≤ 1) or GaAs quantum well structure.
Crystal growth of a spacer layer made of a material, a step of etching the Ga _x In _1-x P (0 ≦ x ≦ 1) spacer layer using a hydrochloric acid-based etchant through an etching mask, and a dry etching Using Al _x G
a _1-x As (0 ≦ x ≦ 1) or a step of etching a compound semiconductor having a GaAs-based quantum well structure,
Subsequently, a Ga-based etchant containing hydrochloric acid is used.
_x In _1-x P (0 ≦ x ≦ 1) spacer layer is completely removed, which is a method for forming a fine structure of a compound semiconductor.

A spacer layer made of Ga _x In _{1 -x} P (0 ≦ x ≦ 1) is continuously grown directly on the quantum well layer made of GaAs. This is a fine structure forming method.

After dry etching, Al _x Ga _{1 -x} As (0≤x≤1) is obtained by using a sulfuric acid type etchant.
Alternatively, the method for forming a fine structure of a compound semiconductor according to claim 1, further comprising a step of etching a compound semiconductor having a GaAs-based quantum well structure.

[0014]

The present invention has the above-mentioned structure and is made of Al_xGa_1-xA
s / GaAs system fine structure using dry etching
As a means for forming, Al_xGa_1-xAs / GaAs type
Ga in the quantum well structure_xIn_1-xConsists of P (0 ≦ x ≦ 1)
The spacer layer is continuously crystallized and pre-formed
The fine pattern is made into Ga by using a hydrochloric acid-based etchant._x
In_1-xA to be transferred to the P spacer layer and etched
l_xGa_1-xExposing As / GaAs and dry etching
Method using Al_xGa_1-xAs (0 ≦ x ≦ 1) or
Etching compound semiconductor with GaAs quantum well structure
This is a microfabrication method. Ga_xIn_1-xP spacer
Layer is etching mask and Al_xGa_1-xAs / GaAs amount
It is inserted between the sub-well structures and during dry etching
Al _xGa_1-xReduces damage to As / GaAs
And after the etching is completed, Ga_xIn_1-xP space
Selectively remove only the sa layer using hydrochloric acid type etchant
To do. Low damage, good controllability, and high density
A fine structure can be formed. In addition, the first
Fine mask pattern formed by sub-beam lithography
By forming the lattice in a lattice shape, it is possible to use only quantum wires.
In addition, it becomes possible to form a fine pattern such as a quantum box.

Another invention is Al _x Ga _{1 -x} As / G.
As a means for forming an aAs-based fine structure, Al _x G is formed by using a sulfuric acid-based etchant subsequent to dry etching.
This is a microfabrication method for etching a compound semiconductor having a _1-x As (0 ≦ x ≦ 1) or GaAs quantum well structure. Al _x Ga _1-x As during dry etching
The damage layer to / GaAs is removed to reduce the damage and overetching is used to reduce the processing size. A fine structure such as a quantum wire can be formed with low damage, good controllability, and high density.

[0016]

FIG. 1 is a process chart of a method for forming a quantum wire which is one of the fine structures of compound semiconductors in the first embodiment of the present invention.

In FIG. 1, 11 is a GaAs substrate on which a quantum wire structure is formed, 12 is a GaAs buffer layer, 13
Is an Al _0.3 Ga _0.7 As barrier layer, 14 is a GaAs quantum well layer, 15 is an Al _0.3 Ga _0.7 As barrier layer, and 16 is Ga _0.5
In _0.5 P spacer layer, 17 is a silicon oxide film serving as an etching mask formed on the crystal structure, 18 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon oxide film, and 19 is formed GaAs It is a quantum wire.

In the steps of the fine structure forming method of this embodiment having the above-described structure, the forming method will be described below with reference to process drawings.

On the GaAs substrate 11, a GaAs buffer layer 12, an Al _0.3 Ga _0.7 As barrier layer 13, a GaAs quantum well layer 14, an Al _0.3 Ga _0.7 As barrier layer 15, and a Ga _0.5 I layer.
Crystal growth of the n _0.5 P spacer layer 16 is continuously performed. G
The thickness of the a _0.5 In _0.5 P layer 16 needs to be several tens of nm. Next, a silicon oxide film 17 is deposited and a resist pattern 18 is formed by electron beam lithography. The stripe pattern is drawn so that the crystal orientation is the (110) direction (a).

Silicon oxide film 1 with a hydrofluoric acid type etchant
7 is etched, and the resist pattern 18 is transferred (b).

Hydrochloric acid type etchant (HCl: H₂O =
2: 1) Ga_0.5In_0.5Etching the P spacer layer 16
And transfer the pattern of the silicon oxide film. At this time,
Al _0.3Ga_0.7As barrier layer 15 is a hydrochloric acid-based etchant
Is not etched (c).

Using a silicon oxide film and a Ga _0.5 In _0.5 P spacer layer as an etching mask by dry etching, Al _0.3 Ga _0.7 As barrier layer, GaAs well layer, Al
_{The 0.3} Ga _0.7 As barrier layer is sequentially etched. At this time,
The silicon oxide film has a low etching rate during dry etching and sufficiently acts as a mask. The forming method using wet etching has a problem that it is difficult to form a fine line shape having a large aspect ratio because lateral etching (over etching) immediately below the etching mask progresses, but dry etching is used. For example, a GaAs quantum wire 19 that faithfully reflects the mask pattern can be formed. Al _0. during dry etching ₃ Ga _0.7 As / G
Damage to aAs can be reduced by the presence of the Ga _0.5 In _0.5 P spacer layer (d).

The Ga _0.5 In _0.5 P spacer layer inserted between the silicon oxide film as the etching mask and the Al _0.3 Ga _0.7 As / GaAs quantum well structure is selectively removed using a hydrochloric acid-based etchant (e ).

In this structure, the Ga _0.5 In _0.5 P spacer layer is used to form Al _0.3 Ga _0.7 during dry etching.
The damage to As / GaAs can be reduced, and after the etching is completed, only the Ga _0.5 In _0.5 P spacer layer can be selectively removed by using a hydrochloric acid-based etchant. By using dry etching, since the progress of lateral etching (overetching) is smaller than that when using wet etching shown in the conventional example, low damage, good controllability, and high density of quantum wires etc. A fine structure can be formed.

In the embodiment, the mask pattern formed by electron beam lithography is set to the crystal orientation (110).
Although the lines are drawn so that they are oriented in the same direction, it is possible to achieve thin lines by drawing in different directions. In addition, the spacer layer Ga
_{The x of x} In _1-x P is set to 0.5, which is lattice-matched with GaAs. However, by introducing a strained superlattice, x can take any value between 0 and 1 to grow crystals. .. Further, it goes without saying that by forming the mask pattern in a lattice pattern, not only quantum wires but also fine patterns such as quantum boxes can be formed.

FIG. 2 is a process chart of a method for forming a quantum wire which is one of the fine structures of compound semiconductors in the second embodiment of the present invention. In FIG. 2, 21 is a GaAs substrate on which a quantum wire structure is formed, 22 is a GaAs buffer layer, 23 is an Al _0.3 Ga _0.7 As barrier layer, and 24 is G.
a As quantum well layer, 25 is Ga _0.5 I which becomes a spacer layer
n _0.5 P layer, 26 is a silicon oxide film formed on the above crystal structure, 27 is a resist pattern formed by electron beam lithography to transfer the pattern to the silicon oxide film, and 28 is a regrowth on the formed quantum wire. Done Al
_0.3 Ga _0.7 As barrier layer, 29 is an embedded GaAs quantum wire.

In the steps of the fine structure forming method of this embodiment having the above-described structure, the forming method will be described below with reference to process drawings.

A GaAs buffer layer 22, an Al _0.3 Ga _0.7 As barrier layer 23, a GaAs quantum well layer 24, and a Ga _0.5 In _0.5 P spacer layer 25 are continuously grown on the GaAs substrate 21 by crystal growth. The Ga _0.5 In _0.5 P spacer layer 25 needs to have a thickness of several tens of nm. Next, a silicon oxide film 26 is deposited and a resist pattern 27 is formed by electron beam lithography (a).

Silicon oxide film 2 with a hydrofluoric acid-based etchant
6 is etched to transfer the resist pattern 27 (b).

Hydrochloric acid type etchant (HCl: H ₂ O =
In 2: 1), the Ga _0.5 In _0.5 P spacer layer 25 is etched to transfer the pattern of the silicon oxide film. At this time G
The aAs quantum well layer 24 is not etched by a hydrochloric acid-based etchant (c).

By dry etching, a silicon oxide film and
And Ga_0.5In_0.5Using the P spacer layer as an etching mask
Then, the GaAs well layer is etched. At this time, Silico
Oxide film has a low etching rate during dry etching
It works well as a mask. For wet etching
In the forming method used in the above method, the lateral etchant directly below the etching mask is used.
Aspect ratio
The problem is that it is difficult to form a thin line shape with large
However, if dry etching is used, the mask pattern
It is possible to form a quantum wire that faithfully reflects the image. Dry Et
Al during ching _0.3Ga_0.7Damage to As / GaAs
Ga_0.5In_0.5Reduced by having P spacer layer
It can be done (d).

After the Ga _0.5 In _0.5 P spacer layer inserted between the silicon oxide film as the etching mask and the Al _0.3 Ga _0.7 As / GaAs quantum well structure is selectively removed using a hydrochloric acid-based etchant, Ga _0.5 In _0.5 P with hydrochloric acid type etchant (HCl: H ₂ O = 2: 1)
The spacer layer is removed (e).

The Al _0.3 Ga _0.7 As barrier layer 28 is regrown on the thin wire to complete the shape in which the GaAs quantum wire 29 is embedded (f).

In this structure, the Ga _0.5 In _0.5 P layer which is the spacer layer is provided immediately above the GaAs quantum well layer,
Since the Al _0.3 Ga _0.7 As barrier layer is not inserted, the controllability of the line width at the time of forming the quantum thin line by dry etching can be improved. That is, it is possible to form the high density quantum wires with good uniformity.

In the embodiment, the mask pattern formed by electron beam lithography is set to the crystal orientation (110).
Although the lines are drawn so that they are oriented in the same direction, it is possible to achieve thin lines by drawing in different directions. Also, although only the GaAs well layer is etched by dry etching,
It is also possible to sequentially etch the GaAs well layer and the Al _0.3 Ga _0.7 As barrier layer. In addition, the spacer layer G
The _{x of} a _x In _{1 -x} P is set to 0.5, which is lattice-matched with GaAs, but depending on the introduction of the strained superlattice, x is 0 to 1
It is also possible to grow the crystal by taking any value between. Further, it goes without saying that by forming the mask pattern in a lattice pattern, not only quantum wires but also fine patterns such as quantum boxes can be formed.

FIG. 3 is a process diagram of a method for forming a quantum wire which is one of the fine structures of compound semiconductors in the third embodiment of the present invention. In FIG. 3, 31 is a GaAs substrate on which a quantum wire structure is formed, 32 is a GaAs buffer layer, 33 is an Al _0.3 Ga _0.7 As barrier layer, and 34 is G.
aAs quantum well layer, 35 is an Al _0.3 Ga _0.7 As barrier layer,
36 is a Ga _0.5 In _0.5 P layer to be a spacer layer, 37 is a silicon oxide film serving as an etching mask formed on the crystal structure, 38 is a resist pattern formed by electron beam lithography to transfer a pattern to the silicon oxide film. , 19 are formed GaAs quantum wires.

In the steps of the fine structure forming method of this embodiment having the above-described structure, the forming method will be described below with reference to process drawings.

On the GaAs substrate 31, a GaAs buffer layer 32, an Al _0.3 Ga _0.7 As barrier layer 33, a GaAs quantum well layer 34, an Al _0.3 Ga _0.7 As barrier layer 35, and a Ga _0.5 I layer.
Crystal growth of the n _0.5 P spacer layer 36 is continuously performed. G
The thickness of the a _0.5 In _0.5 P layer 36 needs to be several tens of nm. Next, a silicon oxide film 37 is deposited and a resist pattern 38 is formed by electron beam lithography. The stripe pattern is drawn so that the crystal orientation is the (110) direction (a).

Silicon oxide film 3 with a hydrofluoric acid-based etchant
7 is etched, and the resist pattern 38 is transferred (b).

Hydrochloric acid type etchant (HCl: H ₂ O =
At 2: 1), the Ga _0.5 In _0.5 P spacer layer 36 is etched to transfer the pattern of the silicon oxide film. At this time, A
l _{0. 3} Ga _0.7 As barrier layer 35 is not etched for etchant hydrochloric acid (c).

By dry etching using the silicon oxide film and the Ga _0.5 In _0.5 P spacer layer as an etching mask, Al _0.3 Ga _0.7 As barrier layer, GaAs well layer, Al
_{The 0.3} Ga _0.7 As barrier layer is sequentially etched. At this time,
The silicon oxide film has a small etching rate during dry etching and sufficiently acts as a mask (d).

Al _0.3 Ga using a sulfuric acid-based etchant
_{The 0.7} As / GaAs thin line is further etched. At the same time as the etching in the depth direction, the etching in the lateral direction (overetching) is advanced to further reduce the thickness. At this time, since the Ga _0.5 In _0.5 P layer is not etched with respect to the sulfuric acid-based etchant, it sufficiently acts as a mask (e).

The Ga _0.5 In _0.5 P spacer layer inserted between the silicon oxide film as the etching mask and the Al _0.3 Ga _0.7 As / GaAs quantum well structure is selectively removed by using a hydrochloric acid-based etchant (f). ..

In this structure, due to the Ga _0.5 In _0.5 P spacer layer, Al _0.3 Ga _0.7 during dry etching is used.
It is possible to reduce the occurrence of a damaged layer on As / GaAs.
Furthermore, after the dry etching is completed, the etching in the depth direction and the etching in the lateral direction (overetching) are performed simultaneously.
The quantum thin line can be formed by advancing the process, removing the damaged layer, and simultaneously further reducing the line width of the well layer. Since the Ga _0.5 In _0.5 P spacer layer, which serves as an etching mask at the time of overetching, is continuously crystallized in advance, there is no contamination at the interface and the adhesion is not deteriorated due to the formation of a natural oxide film. In this case, the controllability of line width can be improved. That is, a fine structure such as a quantum wire can be formed with low damage, good controllability, and high density.

In the embodiment, the mask pattern formed by electron beam lithography is set to the crystal orientation (110).
Although the lines are drawn so that they are oriented in the same direction, it is possible to achieve thin lines by drawing in different directions. In addition, the spacer layer Ga
_x In _1-x P composition ratio x is lattice-matched with GaAs 0.5
However, depending on the introduction of the strained superlattice, x can be set to an arbitrary value between 0 and 1 to grow crystals. Further, it goes without saying that by forming the mask pattern in a lattice pattern, not only quantum wires but also fine patterns such as quantum boxes can be formed.

[0046]

As described above, according to the present invention,
It is possible to provide a method for forming a GaAs-based compound semiconductor fine structure with low damage, good controllability, and high density,
Its practical effect is great.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for forming a fine structure of a compound semiconductor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for forming a fine structure of a compound semiconductor according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a method for forming a fine structure of a compound semiconductor in a third embodiment of the present invention.

FIG. 4 is a process cross-sectional view of a process of a conventional fine structure forming method on a GaAs compound semiconductor substrate.

[Explanation of symbols]

11 GaAs Substrate 12 GaAs Buffer Layer 13 Al _0.3 Ga _0.7 As Barrier Layer 14 GaAs Quantum Well Layer 15 Al _0.3 Ga _0.7 As Barrier Layer 16 Ga _0.5 In _0.5 P Spacer Layer 17 Silicon Oxide Film 18 Resist Pattern 19 GaAs Quantum Wire 21 GaAs Substrate 22 GaAs buffer layer 23 Al _0.3 Ga _0.7 As barrier layer 24 GaAs quantum well layer 25 Ga _0.5 In _0.5 P spacer layer 26 silicon oxide film 27 resist pattern 28 Al _0.3 Ga _0.7 As barrier layer 29 GaAs quantum wire 31 GaAs substrate 32 GaAs buffer Layer 33 Al _0.3 Ga _0.7 As barrier layer 34 GaAs quantum well layer 35 Al _0.3 Ga _0.7 As barrier layer 36 Ga _0.5 In _0.5 P spacer layer 37 Silicon oxide film 38 Resist pattern 39 GaAs quantum wire 41 GaAs Substrate 42 GaAs buffer layer 43 Al _0.3 Ga _0.7 As barrier layer 44 GaAs quantum well layer 45 Al _0.3 Ga _0.7 As barrier layer 46 Silicon oxide film 47 Resist pattern 48 GaAs quantum wire

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yukio Toyoda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A compound semiconductor having a quantum well structure of Al _x Ga _{1 -x} As (0 ≦ x ≦ 1) or GaAs is Ga.
_x In _1-x P (0 ≤ x ≤ 1) is continuously crystal-grown, and the Ga _x In _{1 -x} P (0 ≤ x is obtained by using a hydrochloric acid-based etchant through an etching mask. ≤
1) a step of etching the spacer layer, a step of etching the compound semiconductor having a quantum well structure of Al _x Ga _{1 -x} As (0 ≦ x ≦ 1) or GaAs using dry etching, and subsequently hydrochloric acid And a step of completely removing the Ga _x In _{1 -x} P (0 ≦ x ≦ 1) spacer layer using a system etchant. 2. Ga directly on the quantum well layer made of GaAs.
_2. A step of continuously crystal growing a spacer layer made of _x In _{1 -x} P (0 ≦ x ≦ 1).
A method for forming a fine structure of a compound semiconductor according to claim 1. 3. A method of etching a compound semiconductor having a quantum well structure of Al _x Ga _{1 -x} As (0 ≦ x ≦ 1) or GaAs using a sulfuric acid-based etchant after the dry etching. The method for forming a fine structure of a compound semiconductor according to claim 1.