JPH09171606A - Floppy disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible reproducing a magnetic medium recorded at plural recording density with the same device by respectively applying switch signals according to magnetic density to a rotation drive device, a write-in device and a read-out device. SOLUTION: When a signal is recorded/reproduced on the magnetic medium 12a of regular density, a changeover switch 24 is switched to a regular density use. Then, a spindle motor 13 rotates at 300r.p.m, and a write-in current of a write-in circuit 15 and an erase current of an erase circuit 16 become the regular density use. Further, at a reproducing time, a cut-off frequency of an LPF 19 to 300kHz, a resonance frequency of a differential amplifier circuit 20 to 350kHz and a time constant of a time domain filter 22 to 1/2 at a high density time are switched respectively. Then, when the signal is recorded/ reproduced on the medium 12b of high density, when the switch 24 is switched to the high density side, the write-in current C and the erase current of the erase circuit 16 become double and 1.4 fold of regular time, and the cut-off frequency of the LPF 19 at the reproducing time is made 400kHz. Then, the media 12a, 12b are shifted by the switch 24, and the signal is recorded/ reproduced by one device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floppy disk drive used for an auxiliary storage device of an electronic computer.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional floppy disk drive, and FIG. 10 is a signal waveform diagram of the same floppy disk drive. The configuration of this conventional example will be described below with reference to FIGS.

In FIG. 9, reference numeral 1 denotes a magnetic medium which can be attached to and detached from a floppy disk drive. The magnetic medium 1 is rotated by a spindle motor 2 and records and reproduces signals via a magnetic head 3. .

When a signal is recorded on the magnetic medium 1, a write signal b is input to a write circuit 4, and the output (FIG. 10 (c)) is recorded from the magnetic head 3. This magnetic medium 1 is driven by the voltage shown in FIG.
It is magnetized as shown in FIG.

It should be noted that erasing heads (not shown) are provided at the left and right ends of the magnetic head 3 in the traveling direction to prevent erroneous detection during reproduction. Since this erasing head is provided at the rear of the magnetic head 3 in the traveling direction, a delay circuit 6 is provided to delay the write gate signal h and the erasing circuit 5 outputs it to the erasing head.

When reproducing the signal of the magnetic medium 1, the signal i is detected from the magnetic head 3 and the preamplifier 7 is used.
The signal is amplified by, the noise component is removed by the low pass filter 8 (FIG. 10E), and the signal is input to the differential amplifier circuit 9. The signal f differentiated by the differential amplifier circuit 9 is input to a comparator 10. In this comparator 10, when the input signal f passes the voltage 0V (zero cross), the output signal g changes (“0” → “1”, “1”).
→ "0").

The signal g is transmitted to the time domain filter 11
When the signal g changes (“0” →
"1", "1" → "0"), one pulse is output, and the signal b
The same output signal j is output to the outside.

By the way, the floppy disk devices currently on the market are classified into a normal density type and a high density type, as shown in Table 1, and have different standards.

[0009]

[Table 1]

[0010]

However, in the above-mentioned conventional example, when the magnetic medium is used for high density, the conventional floppy disk device must be changed to a device separately designed and assembled for high density. However, there were problems in operation time and cost.

The present invention eliminates the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a floppy disk device capable of reproducing a magnetic medium recorded at a plurality of recording densities with the same device.

[0012]

In order to achieve the above-mentioned object, the present invention applies a switching signal according to the recording density to each of the rotation driving means, the writing means and the reading means, whereby the rotation speed, It is configured to switch the write current value and other characteristics.

[0013]

The present invention has the above-mentioned structure and has the effect that the magnetic medium recorded with a plurality of magnetic densities can be reproduced by the same device.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a floppy disk drive according to one embodiment of the present invention, and FIG. 2 is a signal waveform diagram for normal density and high density.

In FIG. 1, reference numeral 12a is a magnetic medium of a normal density which can be attached to and detached from a floppy disk device. The magnetic medium 12a has a coercive force of 300 Oersted,
The thickness of the magnetic layer is 2.5 microns. 12b is a high-density magnetic medium that can be attached to and detached from the floppy disk drive,
The magnetic medium 12b has, for example, a coercive force of 600 Oersted and a magnetic layer thickness of 1.5 microns.

Reference numeral 13 is a spindle motor, and this spindle motor 13 sends a switching signal to the motor drive circuit 13a.
By inputting the DDM, for example, 300 per minute
It can be switched to rotation or 360 rotation. Reference numeral 14 denotes a magnetic head capable of recording and reproducing data on both high-density and normal-density magnetic media.

Reference numeral 15 is a write circuit. The write circuit 15 converts the write data signal b controlled by the write gate signal h into a write current C for high density or normal density by a switching signal -LS, Input to the magnetic head 14.

The delay circuit 17 and the erase circuit 16
Is to prevent erroneous detection at the time of reproduction as in the conventional example, but changes the delay time for high density and for normal density by the switching signal + LS or -LS.

When reproducing the signals of the magnetic media 12a and 12b, the signal i is detected from the magnetic head 14, the signal is amplified by the preamplifier 18, and the noise component is removed by the low-pass filter 19. The low-pass filter 19 switches to a cutoff frequency (300 KHz or 400 KHz) for high density or normal density in response to the switching signal + LS, and corrects a center frequency shift (peak shift) during reading on the inner peripheral side of the magnetic medium. ing.

The differential amplifier circuit 20 uses the switching signal -LS to set the resonance frequency (350 kHz) for high density or normal density.
Or 500 KHz) to stabilize the change in gain and remove unnecessary high-frequency noise to suppress jitter. This differential amplifier circuit 20 differentiates an input signal and sends it out as an output signal.

In the comparator 21, the input signal f passes the voltage 0V (zero cross) as in the conventional example ("0" →
The output signal g changes as “1”, “1” → “0”).

When the output signal g is input to the time domain filter 22, one pulse is output when the signal g changes ("0" → "1", "1" → "0"), and the signal b is output. The same signal j is output as the read pulse signal j to the outside. The time domain filter 22 switches the built-in malfunction prevention circuit by the switching signal -LS.

Reference numeral 24 is a host computer or changeover switch, and the host computer or changeover switch 2
In the case where the host computer 4 is a host computer, when a reproduction signal of the floppy disk drive is inputted, if the reproduction signal cannot be determined, it is determined that "recording density setting error", and the switching signal circuit 23 is instructed to switch. Things.

When the host computer or the changeover switch 24 is a changeover switch, the operator changes the recording density by switching the changeover switch when the reproduction signal cannot be discriminated by the operator.

Reference numeral 23 denotes a switching signal circuit. The switching signal circuit 23 has three output signals -DD when the operator switches the changeover switch 24 to the + B side or the ground side.
M, -LS and + LS are switched to "1" or "0".

For normal density, -DDM is "0",
−LS is “0” and + LS is “1”.
A signal of "1" is sent to -DDM and a signal of "0" is sent to + LS. Although -DDM transmits a signal having the same polarity as -LS, it can drive a large current for the motor drive circuit 13a.

In the present embodiment, the changeover signal circuit 23 is changed over between the high density and the normal density by operating the changeover switch 24, but instead of the changeover switch 24, a host computer (not shown) is used. It may be switched by an instruction. When the host computer receives the reproduction signal of the floppy disk device and cannot determine the reproduction signal, it may determine that "recording density setting error" and output the switching instruction to the switching signal circuit 23. It is.

FIG. 2 shows data a1 and write signal b1 for normal density, and data a2 and write signal b for high density.
FIG. 2 is a signal waveform diagram showing No. 2; As shown in FIG. 2, the write signal b1 for normal density and the write signal b2 for high density have the same output voltage but different frequencies.

Next, the operation of the above embodiment will be described.
In FIG. 1, when recording and reproducing a signal on and from a normal density magnetic medium 12a, when the changeover switch 24 is switched to the normal density, the spindle motor 13 rotates at 300 revolutions per minute. The erasing current is usually for density. For reproduction at normal density, the cut-off frequency of the low-pass filter 19 is set to 300 KHz and the resonance frequency of the differential amplifier circuit 20 is set to 3 kHz.
The time constant of the 50 KHz, time domain filter 22 is switched to ½ of that at the time of high density.

Next, when the signal is recorded / reproduced on / from the high density magnetic medium 12b, if the changeover switch 24 is switched to the high density side, the spindle motor 13 becomes 360 rpm and the write current C of the write circuit 15 and The erasing current of the erasing circuit 16 is twice and 1.4 times that of the normal density, respectively. In high-density reproduction, the cut-off frequency of the low-pass filter 19 is switched to 400 KHz, the resonance frequency of the differential amplifier circuit 20 is set to 500 KHz, and the time constant of the time-domain filter 22 is switched to twice the normal density.

As described above, in the case of recording and reproducing signals on the magnetic media 12a and 12b for normal density and high density,
It can be implemented by switching the changeover switch 24. That is, as shown in Table 1, in the magnetic medium 12a for normal density, the storage capacity is 1 Mbyte, the data transfer speed is 250 Kbit / s, the number of tracks is 80, and the thickness of the magnetic layer is 2.5 microns.

For the high density magnetic medium 12b, the changeover switch 24 is used for the magnetic mediums 12a and 12b having a storage capacity of 1.6 Mbytes, a data transfer rate of 500 Kbit / s, a track number of 70, and a magnetic layer thickness of 1.5 μm. Both can be recorded and reproduced by one device by switching.

Next, regarding the floppy disk device of this embodiment, circuits corresponding to individual blocks in the block diagram of FIG. 1 will be described.

FIG. 3 is a circuit diagram of the switching signal circuit 23. In FIG. 3, reference numeral 30 denotes a -LOW SPEED terminal, which is set to "1" or "0" when the operator switches the changeover switch 24.
Is applied, and “0” is applied at a normal density and “1” is applied at a high density.

31 is an internal drive select signal + DS
This is a terminal to which INT is applied.
Is applied, the floppy disk device becomes operable, and when "1" is added to 31, it becomes inoperative. 32
Is a power-on reset-POR terminal, and "0" is applied to this terminal when the power is turned on. Reference numeral 33 is a D flip-flop. This D flip-flop 33 has a signal of "1" at the D input, and when the T input becomes "1 → 0", the Q output changes ("0 → 1", "1"). → 0 ”).

Reference numeral 34 is a pull-up resistor that holds the D input to "1" unless the -LOW SPEED 30 is "0". Reference numeral 35 denotes a pull-up resistor for inhibiting the setting of the D flip-flop 33. A buffer amplifier 36 amplifies the current of the Q output of the D flip-flop 33. Reference numeral 37 is a pull-up resistor that holds "1" unless the buffer amplifier 36 becomes "0".

Reference numeral 38 is a capacitor for lowering the output impedance of the buffer amplifier 36. 39 is the first
-L which is "0" at normal density.
This is an S (low signal) signal. 40 converts the Q output of the D flip-flop 33 (“0” → “1”, “1” →
"0"). 41 is an inverter 40
Is a pull-up resistor that holds “1” unless “0” becomes “0”.

Reference numeral 42 is a capacitor for lowering the output impedance of the inverter 40. 43 is the second output terminal, which becomes "1" at the normal density + LS
(Low signal) signal. 44 is an NPN type switching transistor. Reference numeral 45 denotes a bias resistor in which the output terminal of the inverter 40 is connected to the base of the transistor 44.

Reference numeral 46 is a third output terminal, which is an open collector -DDM (direct drive motor) signal for starting and stopping a motor for driving a floppy disk.

Next, the operation of the switching signal circuit of FIG. 3 will be described. First, when the power switch of this device is turned on, -P
The OR terminal 32 becomes “0” and the D flip-flop 33
Reset terminal R becomes "0", and is reset, and the Q output becomes "0". When the operator selects the drive of the present floppy disk device, + DSINT31 becomes "0", and the value of the Q output of the D flip-flop 33 changes according to the signal of -LOW SPEED30.

That is, when -LOW SPEED 30 is "0" (normal density), the Q output is "0". Further, when -LOW SPEED 30 is "1" (high density), the Q output is "1". When the Q output is "0", the first output terminal 39 is "0", the second output terminal 43 is "1", and the third output terminal 46 is "0". When the Q output is “1”, the first output terminal 39
Is "1", the second output terminal 43 is "0", and the third output terminal 46 is high impedance.

FIGS. 4 and 5 show the write circuit 15 and the delay circuit 1.
6, an erasing circuit 17, a magnetic head 14, and other attached circuits. 4 and 5, the connection terminals having the same numbers are connected to each other.

The write circuit 15 of FIGS. 4 and 5 has a write current switching circuit 15a, a stabilizing power supply circuit 15b, and a write drive circuit 15c.

In the write current switching circuit 15a of FIGS. 4 and 5, 39 is the first switching signal-LS terminal.
The LS terminal 39 is connected to -LS39 in FIG.
Reference numeral 53 denotes a transistor whose terminal is connected to the base via the resistor 52.

Reference numeral 55 denotes a transistor 53 via a resistor 54.
Is a transistor whose collector and base are connected together. A resistor 56 is connected between the emitter and the base of the transistor 55, and a resistor 57 is connected between the emitter and the collector.
And 58 are connected in series, and the voltage from the stabilized power supply circuit 15b is applied to the emitter.

In the write current switching circuit 15a, the -LS terminal 39 is "0" at normal density, so that the transistors 53 and 55 are non-conductive. Therefore, the voltage of the stabilized power supply circuit 15b becomes the current I via only the resistor 57 and is output to the write drive circuit 15c.

Further, at high density, in the write current switching circuit 15a, the -LS terminal 39 becomes "1", so that
The transistors 53 and 55 are turned on. Therefore, the voltage of the stabilized power supply circuit 15b flows through the resistor 58 via the emitter and the collector of the transistor 55 in parallel with the resistor 57.
Therefore, since the current I output to the write drive circuit 15c is determined by the combined resistance value of the resistors 57 and 58, a current larger than the current value determined by the resistance value of the resistor 57 alone flows.

As described above, the current I output to the write drive circuit 15c is determined by the -LS terminal 39, and when "0", that is, the normal density, a small current flows, and when "1", that is, the high density. Large current flows.

In the stabilized power supply circuit 15b, 59 is +
The +12 V terminal 59 is connected to the base of the transistor 60 via the resistor 61 and to the collector of the transistor 60 via the resistor 62. The emitter of the transistor 60 is connected to the ground, and the collector of the transistor 60 is connected to the base of the transistor 64 and the cathode of the Zener diode 63.

The anode of the Zener diode 63 is connected to the ground. The collector of the transistor 64 is connected to the + 12V terminal 59, and the emitter of the transistor 64 is connected to the emitter of the transistor 55.

The stabilized power supply circuit 15b outputs a voltage from the emitter of the transistor 64 when the base of the transistor 60 is "0". That is, when the base of the transistor 60 is “0”, the transistor 60 is turned off, and +12 V flows to the Zener diode 63 via the resistor 62. Zener diode 6
3 is applied to the base of the transistor 64, so that the stabilized voltage
4 from the four emitters.

On the other hand, the write data (FIG. 1B) is W
A pulse waveform is input to the RITE DATA terminal 65. Reference numeral 67 denotes an inverter. The input of the inverter 67 is at +5 V, that is, "1" through the resistor 66 when there is no signal from the WRITE DATA terminal 65. Reference numeral 68 denotes a D flip-flop. The T terminal of the D flip-flop 68 is connected to the output terminal of the inverter 67, the D terminal is connected to the Q output terminal, and the R terminal is connected to the output terminal of the OR gate 71. It is connected.

One input terminal of the OR gate 71 is connected to the WRITEGATE 69 via the buffer amplifier 70, and the other input terminal is connected to the DS via the buffer amplifier 73.
It is connected to INT31.

Since the inversion information Q of the Q output becomes the D input, the D flip-flop 68 inverts the Q output when the T input changes from "1" to "0". That is, the D flip-flop 68 divides the frequency of the T input by two.

Reference numeral 76 is an inverter, and the output of the inverter 76 drives the transistor 79 via the resistor 77. In the transistor 79, a voltage (output of the transistor 64) stabilized by the resistor 78 is connected to the base, the write current I is supplied to the emitter of the transistor 79, and the collector is connected to the ground via the resistor 80. It is connected.

Reference numeral 81 is an inverter, and the output of this inverter 81 drives a transistor 84 via a resistor 82. The transistor 84 is connected to the emitter of the transistor 64 via the resistor 83. The write current I is connected to the emitter of the transistor 84, and the collector is connected to the ground via the resistor 85.

A resistor 86 is connected between the collector of the transistor 79 and the collector of the transistor 84.
The collector of the transistor 79 is connected to the read / write coil 101 of the first magnetic head 100 via the diode 87.
It is connected to the. The collector of the transistor 79 is also connected to the write / read coil 106 of the second magnetic head 105 via the diode 88.

The collector of the transistor 84 is connected to the write / read coil 102 of the first magnetic head 100 via the diode 89. Also, the transistor 8
4 is also connected to the write / read coil 107 of the second magnetic head 105 via the diode 90.

Reference numeral 75 is a power-on reset-POR terminal, and "0" is applied to this -POR terminal 75 only for a temporary period immediately after the power is turned on. Reference numeral 74 denotes a NAND gate. One input of the NAND gate 74 is -POR.
75 is input, and the other input is input to the internal drive select DSINT terminal 31 via the buffer amplifier 73. The output of NAND gate 74 is
0 is connected to the base.

Next, the delay circuit 16 and the erasing circuit 17 shown in FIGS. 4 and 5 will be described. In FIGS.
Is -ESW (eraseable signal) indicating that erasing is possible. Reference numeral 43 denotes a second switching terminal (+ LS terminal) which is set to "1" when driving for normal density. Reference numeral 113 denotes a one-shot multi IC in which the output time of the output voltage is determined by the time constant of the resistor 112 and the capacitor 118 connected to 5 V. This IC 113 is used when the -ESW 110 via the buffer 111 becomes "0". Start output.

However, at normal density, + LS43 is "1".
Therefore, the transistor 116 via the resistor 115 conducts, and the capacitor 117 is connected to the ground. In this state, since the capacitors 118 and 117 are connected in parallel, the function of extending the output time of the IC 113 is provided. The output of the IC 113 is the NAND gate 1
19 and the output to the NOR Dot 125.

The NAND gate 119 is connected to the IC 113
, And -POR75, and the output is connected to the base of the transistor 122 via the resistor 120. This transistor 122 is connected to the base via
V is applied, and the collector is connected to ground via a resistor 124.

A diode 123 whose anode is connected to the ground is connected in parallel to the resistor 124. The collector of the transistor 122 has diodes 126, 1
27 are connected to this diode 12
The cathode 6 is the erasing coil 1 of the first magnetic head 100.
03, and the cathode of the diode 127 is connected to the erasing coil 108 of the second magnetic head 105.

A capacitor 104 for removing noise is connected in parallel to the erasing coil 103, and a capacitor 109 for removing noise is similarly connected to the erasing coil 108. When the output of the AND gate 138 or 140 becomes "0", a current is supplied from the collector of the transistor 122, and the connected erase coil 103 or 108 starts an erase operation.

Next, the erasing circuit 17 will be described. 3
9 is -LS which is a signal of "0" for normal density. 1
29 is a base bias resistor of the transistor 130. The transistor 130 has an emitter connected to the ground and a collector connected to the bias resistor 131.

+ 5V is connected to the emitter of the transistor 132, connected to the base via the resistor 133, and connected to the collector via the resistors 134 and 135. In addition,
The midpoint of resistors 134 and 135 is connected to the emitter of transistor 122.

In this erase circuit 17, -LS128 is "0".
, Ie, for normal density, transistor 1
Since transistor 30 does not conduct, transistor 132 also does not conduct, and +5 V is applied to transistor 1 through resistor 134 only.
It is supplied to 22 emitters.

On the other hand, when -LS128 is "1", that is, for high density, the transistor 130 is turned on and the transistor 132 is turned on, and + 5V passes through the parallel connection of the resistors 134 and 135 and the emitter of the transistor 122 is reached. Will be supplied to.

Reference numeral 136 is "1" when the first magnetic head 100 of the floppy disk is driven, and "0" when the second magnetic head 105 is driven-SIDE SEL
ECT. 137 input is -SIDE SELECT
At T136, there is an inverter whose output is connected to AND gates 138 and 141. AND gates 139 and 1
The -SIDE SELECT 136 is directly connected to the input of 40.

The outputs of the NOR gate 125 are connected to the other inputs of the AND gates 138 to 141, respectively.

The relationship between the AND gates 138 to 141, the NOR gate 125, and the -SIDE SELECT 136 is as follows. (1) NOR gate 125 = “0”, SIDE SEL
When ECT136 = "0".

Since the output of the inverter 137 is "1", the output of the AND gates 138, 140, 141 = "1" The output of the AND gate 139 = "0" (2) NOR gate 125 = "0", -SIDE SE
LECT136 = "1".

Since the output of the inverter 137 is "0", the output of the AND gates 139, 140, 141 = "1" The output of the AND gate 138 = "0" (3) NOR gate 125 = "1", -SIDE SE
LECT136 = "0".

Since the output of the inverter 137 is "0", the output of the NAND gates 138, 139, 140 = "1" The output of the NAND gate 141 = "0" (4) NOR gate 125 = "1", -SIDE SE
LECT136 = "0".

Since the output of the inverter 137 is "1", the output of the NAND gates 138, 139, 141 is "1" and the output of the NAND gate 140 is "0".

The functions of the outputs of these NAND gates 138 to 141 are as follows. (1) When the NAND gate 138 is "0".

The first magnetic head 100 of the magnetic head 14
Since the middle point of the coils 101 to 103 becomes 0 V and the erasing coil 103 operates, writing to the first magnetic head 100 becomes possible. (2) When the NAND gate 139 is “0”.

The middle point of the coils 106 to 108 on the side 1 105 of the magnetic head 14 becomes 0 V, and the erasing coil 10
8 operates, so that writing by the second magnetic head 105 becomes possible. (3) When the NAND gate 140 is "0".

First magnetic head 100 of magnetic head 14
Of the coils 101 to 103 becomes 6 V, and the erase coil 103 does not operate. This is because the resistors 144 and 14
This is because the value of 2 is the same, the voltage at the midpoint becomes 6 V, and no current flows through the erase coil 103. At this time, reading from the first magnetic head 100 becomes possible. (4) When the NAND gate 141 is “0”.

The second magnetic head 105 of the magnetic head 14
The middle point of the coils 106 to 108 becomes 6 V, and the erase coil 108 does not operate. This is the resistance 145,
This is because the voltage of the middle point becomes 6 V and the current does not flow in the erasing coil 103 because the value of 143 is made the same. At this time, reading of the second magnetic head 105 becomes possible.

Next, the magnetic head 14 will be described.
The magnetic head 14 has a first magnetic head 100 and a second magnetic head 105. This corresponds to the front and back surfaces of the floppy disks 12a and 12b.

The first magnetic head 100 has write / read coils 101 and 102, an erase coil 103, and a capacitor 104. One end of each of the three coils is controlled by a common control line, and the other end is
1 for volt, write and read coils 101 and 102
Two volts are applied. At the time of writing, the control line becomes 0 volt (the NAND gate 138 is "0" and the 140 is "1"), and the writing and reading coils 101 and 102 and the erasing coil 103 are also driven.

Further, since the control line becomes 6 volts (NAND gate 140 is "0" and 138 is "1") at the time of reading, the erase coil 103 is not driven, and only the write and read coils 101 and 102 are driven.

Similarly, the second magnetic head 105 has write / read coils 106 and 107 and an erase coil 1.
08 and the capacitor 109. All three coils,
One end is controlled by a common control line, and the other end is
8 is 5 volts, the write and read coils 106 and 10
At 7, 12 volts is applied.

At the time of writing, the control line is set to 0 volt (NAND)
The gate 139 becomes “0”, and 141 becomes “1”), and the write / read coils 106 and 107 and the erase coil 108.
Are also driven. Further, since the control line becomes 6 volts (NAND gate 141 is “0” and 139 is “1”) at the time of reading, the erase coil 108 is not driven, and only the write and read coils 106 and 107 are driven.

Next, the operations of the write circuit 15, the delay circuit 16, the erase circuit 17 and the magnetic head 14 of FIGS.

4 and 5, the write data (FIG. 9)
(B)) is applied to the WRITE DATA terminal 65. If writing is possible, a write gate signal (FIG. 1)
(H)) is applied to the WRITE GATE 69 to release the reset of the D flip-flop 68 and divide the write data (FIG. 10B) by two.

When writing is possible, DS INT
31 and -POR75 are "1", the transistor 60 is non-conductive, and the + 12V terminal 5
The + 12V applied to 9 is stabilized by the stabilized power supply circuit 15b and applied to the write switching circuit 15a.

In the write switching circuit 15a, a signal of "0" at a normal density and a signal of "1" at a high density are input to the -LS terminal 39, and the signal of the -LS terminal 39 causes the write current I to reach the normal density. A small current flowing only through the resistor 57 and a large current flowing through both the resistors 57 and 58 at high density flow to the write drive circuit 15c.

On the other hand, the write data output from the D flip-flop 68 is controlled by the transistors 79 and 84 to control the write current I, is written through the diodes 87 to 90, and is applied to the read coils 101, 102, 106 and 107. It Writing to the floppy disks 12a and 12b is controlled by NAND gates 138 and 139, and only one of the first magnetic head 100 and the second magnetic head 105 is driven.

Next, the operations of the delay circuit 16 and the erase circuit 17 will be described. In the delay circuit 16, the erasable signal (-E
SW 110) is delayed by the one-shot multi IC 113. The delay time of the IC 113 differs between the normal density and the high density, and is switched by the + CS terminal 43. The output of the delay circuit 16 is supplied to the NA through a NOR gate 125.
Applied to ND gates 138-141.

Further, the erase current is supplied from the transistor 122 through the diodes 126 and 127 to the erase coil 103,
108 is applied. The erasing current is switched by the -LS terminal 39. At a normal density, a small current via only the resistor 134 is applied to the erasing coils 103 and 108 at a high density. is there.

The erase current is controlled by the NAND gates 138 and 138 similarly to the write current, and only either the first magnetic head 100 or the second magnetic head 105 is driven.

At the time of reading, WRITE GATE
Both the terminal 69 and the −ESW terminal 110 become “1”, the NOR gate 125 is set to “1”, the NAND gates 138 and 139 are closed, and the NAND gates 140 and 141 are turned off.
open. At this time, control lines (each coil 101 to 103,
106-108) is increased from 0 volts to 6 volts, and the erase coils 103, 108 to which 5 volts are applied are applied.
Operation is stopped.

Therefore, at the time of reading, any two of the writing and reading coils 101, 102, 106 and 107 are driven, and the READ1 151 terminal and the READ 215 terminal are read.
It is read from the 0 terminal.

Next, the read circuit group will be described with reference to FIGS. 4, 5, 6A to 6C and FIG.

4 and 5, reference numeral 146 denotes a magnetic coil 1
The diode 147 is connected to the magnetic coil 10.
2 and 148 are magnetic coils 106
And 149 are diodes connected to the magnetic coil 101. Diodes 146 and 14
The anode 7 is commonly connected from the READ2 terminal 150 to the READ2 of the preamplifier 18 in FIG.

On the other hand, the anodes of the diodes 148 and 149 are commonly connected to the preamplifier 1 shown in FIG.
8 READ1 terminal 151.

FIG. 6A is a circuit diagram showing the preamplifier 18 and the low-pass filter 19. In FIG. 6, 150 is an input terminal of READ1, and 151 is READ
2 input terminal. Reference numerals 152 and 153 denote bias resistors connected to + 12V.
2, 153 are READ1 150 and REA, respectively.
D2 151 biases the magnetic head coils 101, 102, 106 and 107 via the diodes 146 to 149.

Reference numeral 154 denotes READ1 150 and READ1.
It is a resistor that determines the input impedance between 2 151.

The low-pass filter 19 receives the outputs of the + PC ON terminal 156, + LS terminal 43 and the preamplifier 155, and outputs them from LPF + 189 and LPF-190. + PC ON terminal (Write compensation:
The pre-compensation ON 156 is connected to the middle point of the diodes 170 and 171 via the buffer amplifier 157.

The + PC ON terminal 156 is connected to a track counter (not shown) for counting the current position (the number of tracks) of the magnetic head (3) in contact with the rotating floppy disk (1), and has 0 to 43 tracks. "0",
"1" is applied in 44 to 76 tracks.
With the PCON terminal 156 and + LS43, the cutoff frequency of the low-pass filter 19 can be increased when the inner tracks (44 to 76 tracks) are arranged at high density.

The + LS terminal (normal density) 43 becomes "1" at the normal density, and the transistor 1 is connected through the resistor 160.
61 is made conductive. + 12V is the resistance 176
Through the anode of the diode 164, the diode 17
0 and to the capacitor 177. Further, + 12V is connected to the diode 1 via the resistor 181.
67, the anode of the diode 171 and the capacitor 172.

The output of READ1a 158 is connected on the one hand to the base of capacitor 172 and transistor 174 via coil 168, and on the other hand to the base of transistor 163 via resistor 162. The emitter of the transistor 163 is connected to the cathode of the diode 164, and the collector is connected to the ground. The emitter of the transistor 174 is connected to a resistor 175
, The collector is connected to ground, and the base is connected to ground via a resistor 173.

The output of the READ2a 159 is connected to the capacitor 177 and the base of the transistor 179 via the coil 169 on the one hand and to the base of the transistor 166 via the resistor 165 on the other hand.
The emitter of this transistor 166 is a diode 167
And the collector is connected to ground. The emitter of the transistor 179 is connected to the resistor 18.
0 is connected to + 12V and the collector is connected to ground,
The base is connected to ground via a resistor 178.

The emitter of the transistor 174 is the coil 1
It is connected to capacitors 184 and 187 and a resistor 185 via 82. The other end of the resistor 185 is connected to ground, and the other end of the capacitor 187 is connected to a terminal 189 of LPF +. The emitter of the transistor 179 is connected to the other of the capacitor 184, the resistor 186 and the capacitor 188 via the coil 183. The other end of the resistor 186 is connected to the ground, and the other end of the capacitor 188 is connected to the terminal 190 of the LPF-.

FIG. 6B shows a filter circuit of the low-pass filter 19 at the normal density. In FIG. 6B, inputs are READ1a158 and 2a159, which are output via coils 168 and 169. This output is
This is the base of transistors 174 and 179. A capacitor 1 is connected between the base of this output 174 and the base of 179.
A series circuit of 72 and 177 and a series circuit of resistors 173 and 178 are connected.

In FIG. 6B, since the + LS43 terminal is "1", the transistor 161 becomes conductive,
The diodes 170 and 171 are connected to the ground. FIG. 6C shows a filter circuit of the low-pass filter 19 at high density. In FIG. 6C,
Inputs READ1a158, 2a159 and coil 1
68, and 169. This output is the base of transistors 174,179. Also, the input RE
AD1a158 outputs the output 17 via a capacitor 177.
9 connected to the base. READ 2 a 159 is connected to the base of output 174 via capacitor 172. A series circuit of resistors 173 and 178 is connected between the base of this output 174 and the base of 179.

As described above, the low-pass filter 19 has the characteristics of the cut-off frequency defined by the filter as shown in FIG. 6B at normal density, and FIG.
It has a cutoff frequency characteristic determined by a filter as shown in FIG.

Next, the operations of the preamplifier 18 and the low-pass filter 19 shown in FIG. 6A will be described.

Generally, a floppy disk drive has a surface,
Since the back surfaces are not reproduced at the same time, only one read circuit is required. Therefore, as shown in FIGS. 4 and 5, the first magnetic head 100 and the second magnetic head 105
Are reproduced in a single system.

Thus, the coil 10 of the magnetic head is
The information read from 1,102,106,107 is
The signal is amplified and output to the operational amplifier 155 via the diodes 146 to 149.

On the READ1a side, the output of the operational amplifier 155 passes through the low pass filter of the coil 168 and the capacitor 172 and is input to the transistor 174. Also R
On the EAD 2a side, the signal passes through the low-pass filter of the coil 169 and the capacitor 177 and is input to the transistor 179.

READ1a of low-pass filter circuit 19
The output of the operational amplifier 155 is connected to the terminal 158 and the READ2a terminal 159, respectively. At the normal density, since the + LS terminal 43 is “1”, the transistor 161 conducts, and +12 V flows to the ground via the resistor 176, the diode 170, and the transistor 161.

Further, + 12V flows to the ground through the resistor 181, the diode 170 and the transistor 161. At this time, the diode 164 and the transistor 163, and the diode 167 and the transistor 166.
Does not operate because of reverse bias. Therefore, in the case of normal density, from READ1a 158 and READ2a 159 to the base of the transistor 174 and the transistor 179.
The circuit between the bases is equivalent to the circuit diagram shown in FIG.

Next, at high density, the + LS terminal 43 becomes "0".
And the transistor 161 becomes non-conductive.
+ PC ON terminal 156 is connected to floppy disk 12b
Since the output of the buffer amplifier 157 is also "0" because the track is 0 in tracks 0 to 43, the circuit diagram of FIG. 6B can be applied as it is.

Also, the floppy disk 12b 44-
Since + PC ON 156 is "1" in the case of 76 tracks, + 12V cannot conduct the diode 170 after passing through the resistor 176, so that the diode 164 and the transistor 163 are conducted. Similarly, + 12V
Since the diode 171 cannot be conducted after passing through the resistor 181, the diode 167 and the transistor 166 are conducted.

Therefore, in the case of high density, READ1a1
58 and READ2a159, the circuit between the base of transistor 174 and the base of transistor 179 is shown in FIG.
This is equivalent to the circuit diagram shown in FIG.

Thereafter, the frequency characteristics are corrected by the coils 182, 183 and the capacitor 184, and the LPF + terminal 18 is corrected.
9 and LPF- terminal 190.

Next, the differential amplifier circuit 20 will be described with reference to FIG. In FIG. 7, reference numeral 39 denotes -LS to which "0" is input at normal density and "1" is input at high density. 2
01, 202, and 204 are bias resistors of the transistor 203. 205 is a FET (field effect transistor)
Reference numeral 206 denotes a bias resistor. The source of the FET 206,
Capacitors 207 and 208 are connected in series between the drains.

A resistor 209 is connected in parallel to both ends of the capacitor 208, and a resistor 210 and a semi-fixed resistor 21 are connected.
3. The series circuit of the coil 211 is also connected in parallel.
The movable portion of the semi-fixed resistor 213 is connected to the ground via the resistor 212. On the other hand, the LPF + 189 is connected to the base of the transistor 191, and the LPF-190 is connected to the base of the transistor 194.

The collector of the transistor 191 is connected to + 12V via the comparator 21 and the resistor 192,
The emitter is connected to the constant current source 193. The collector of the transistor 194 has a comparator 21 and a resistor 1
It is connected to + 12V via 95, and the emitter is connected to the constant current source 196. The emitter of the transistor 191 is connected to one terminal of the semi-fixed resistor 213, and the emitter of the transistor 194 is connected to the other terminal of the semi-fixed resistor 213.

Next, the comparator 21 and the time domain filter 22 will be described with reference to FIG.

In FIG. 7, the signal of -LS39 is input to the base of the transistor 227 via the bias resistor 226.

The emitter of the transistor 227 is connected to the ground, and the collector of the transistor 227 is connected through the resistor 228.
29 connected to the base. A bias resistor 230 is connected between the base and the emitter of the transistor 229, and a series circuit of resistors 229 and 232 is connected between the collector and the emitter.

The midpoint between the resistors 229 and 232 is connected to the one-shot multi 221, and the capacitor 233 is connected between this midpoint and the other point of the one-shot multi 221. The emitter of the transistor 229 is connected to +12 V via a resistor 234 and to the ground via a zener diode 235. The emitter of the transistor 229 is connected to the one-shot multi 223 via the resistor 236. A capacitor 237 is connected between one terminal of the one-shot multi 223 and the other terminal.

The comparator 21 compares two input voltages and outputs the difference, and the pulse generator 220
And, it is connected to the D terminal of the D flip-flop 222. The pal generator 220 receives the output voltage of the comparator 21 and generates one short pulse when the polarity of the output voltage is inverted.

The one-shot multi 221 sends a signal of a length of time determined by a short pulse of the pulse generator 220, and the length of time is the time when the capacitor 233 and the resistor 232 or 231 are used. It is determined by a constant. Reference numeral 222 denotes a D flip-flop. The D flip-flop 222 has a D input as an output of the comparator 21 and a T input as a one-shot multi-two.
When the D input is "1", the Q and NOTQ outputs are inverted with the inversion of the T input.

Reference numeral 223 denotes a one-shot multi circuit. This one-shot multi circuit 223 has a D flip-flop 222.
When the Q and NOTQ outputs are inverted, a signal of a predetermined length of time is sent out. The length of this time is
It is determined by the time constants of the capacitor 237 and the resistor 236.

The output of this one-shot multi is AND
Input to the gate 224, READENABLE 225
Is "1", the AND gate 224 outputs
It is output to the terminal of TA226.

Next, the operations of the differential amplifier circuit 20, the comparator 21 and the time domain filter 22 shown in FIG. 7 will be described.

In FIG. 7, the output of the low-pass filter 19, that is, the signals of LPF + 189 and LPF-190 are input to the transistors 191 and 194, and in the case of high density, the coil 211 connected between both transistors and the capacitor. It is differentiated by the differentiation circuit by 208 (see FIG. 10 (f)).

In the case of the normal density, -LS200 is "0".
, The transistor 203 becomes non-conductive, and FE
T206 becomes conductive, and the differentiating circuit is formed by the parallel circuit of the capacitors 207 and 208 and the coil 211. The resonance frequency of the capacitors 207 and 208 and the coil 211 at the normal density is lower than the resonance frequency of the capacitor 208 and the coil 211 at the high density.

The reason is that the basic formula at the resonance frequency is as follows:

[0135]

[Equation 1]

In C, the value of C is higher in normal density than in high density. The signal thus differentiated is
The signal is input to the comparator 21, and the output is inverted when the polarities of the two input signals are inverted (FIG. 10 (f)).

The output of the comparator 21 is input to the one-shot multi 223 via the pulse generator 220, the one-shot multi 221 and the D flip-flop 222. This pulse generator 220, one shot multi 22
1, the D flip-flop 222 is a slackened portion (f1, f of the output of the differential amplifier circuit 20 shown in FIG. 10 (f).
2 and f3) prevent malfunction due to noise.

That is, the output of the comparator 21 is once input to the pulse generator 220, and then the comparator 2
When the polarity of the output of 1 changes, a short pulse is output. The one-shot multi 221 is driven by the output of the pulse generator 220. The output time of this one-shot multi is different for normal density and for high density.

For normal density, -LS39 becomes "0" and the transistor 229 is made non-conductive, so that the one-shot pulse time width is the capacitor 223 and the resistor 23.
It is determined by the time constant determined in 2. In the case of high-density use, -LS39 becomes "1".
9 is conductive, the pulse time width of one shot is determined by a time constant determined by a combined resistance of the capacitor 223 and the resistors 232 and 231.

Since the T input of the D flip-flop 222 is driven at the end of the pulse transmission of the one-shot multi 221, if the output slack of the differential amplifier circuit 20 (FIGS. 10f1 to f3) is mixed with noise. Since it is masked by the pulse transmission time of the one-shot multi 221, the malfunction of the D flip-flop 222 does not occur.

The output of the D flip-flop 222 is
When the waveform is shaped by the one-shot multi 223 and the data can be read, the READ ENABLE 225 becomes “1” and is sent to the outside as READ DATA 226.

Next, the motor drive circuit will be described with reference to FIG. The motor drive circuit in FIG. 8 includes a direct drive motor (DD motor) 13, an integrated circuit (IC) 240 for controlling the number of revolutions (μPC1043C phase and the like), and a motor drive integrated circuit (IC) 241 (TA-7245AP phase and the like). It consists of other accessory parts. Reference numeral 242 denotes a -DDM terminal which is "0" for normal density and "1" for high density. 243 is D.E. This is a MOTOR ON terminal which becomes "1" when the D motor 13 is driven. 244
Is + 12V.

Reference numeral 245 is an F.F. of a pulse wave-shaped print pattern mounted perpendicularly to the rotation axis of the motor. G. FIG. This F. G. FIG. The (frequency oscillator) detects the rotation of the magnetic flux generated by the rotation of the permanent magnet built in the motor when the motor rotates, based on the print pattern, and generates an induced electromotive voltage. 246 is the IC240
Is a preamplifier built in the
6 is F. G. FIG. The voltage of H.245 is input to the plus terminal, and the output is connected to the minus terminal via the resistor 250.

The minus terminal of the preamplifier 246 is
F. through a series circuit of a capacitor 248 and a resistor 249.
G. FIG. 245 is connected to the other end. This F. G. FIG. 24
The other end of 5 is connected to the ground via a capacitor 247.

A series circuit of a resistor 252 and a capacitor 251 is connected in parallel to the resistor 250. Preamplifier 2
The output of 46 is input to the minus terminal of the Schmitt trigger 254 built in the IC 240 via the capacitor 253. The output of the Schmitt trigger 254 is fed back to the plus terminal via the resistor 255.

The Schmitt trigger 254 is used to shape the waveform of the input signal into a pulse shape with a predetermined threshold value, and its output is input to the differentiating circuit 257 via the capacitor 256. The differentiated signal is input to the timing circuit 258. In the timing circuit 258, the fall time of the differentiated signal is determined by the time constant of the resistor 264 and the capacitor 265.

The output of the timing circuit 258 is
The signal is input to the hold circuit 259, and a sawtooth waveform is formed. This sawtooth waveform has a gradient determined by the capacitor 270 and the resistor 271 and the semi-fixed resistor 272 at normal density. At the time of high density, it has a gradient determined by a resistor 273 and a semi-fixed resistor 274 in addition to the capacitor 270, the resistor 271 and the semi-fixed resistor 272.

The switching between the normal density and the high density is performed by
Depends on the signal of DM242. That is, at the normal density, since the -DDM 242 becomes "0", the base of the transistor 275 via the resistor 276 becomes "0", the transistor 275 becomes non-conductive, and the resistor 273 and the semi-fixed resistor 274 No effect. When the density is high, the value of -DDM242 is "1".
75 is conductive and the semi-fixed resistor 274 is connected to ground.

The combined resistance of the series circuit of the resistor 271 and the semi-fixed resistor 272 and the series circuit of the resistor 273 and the semi-fixed resistor 274 forms the sawtooth waveform time constant with the capacitor 270. Reference numeral 278 denotes a noise removing capacitor of the sample-and-hold circuit 259. To the capacitor 278, a voltage which is half the power supply voltage generated by the power supply circuit 261 is applied as a reference voltage.
By 78, the noise component is removed.

Reference numeral 260 denotes a comparison and DC amplifier. The comparison and DC amplifier 260 compares the sawtooth waveform signal from the sample and hold circuit 259 with a reference voltage and sends out a current for controlling the rotation of the motor. To do. The output voltage of the comparison and DC amplifier 260 is again compared with the DC voltage of the DC amplifier 260 via a series connection of a capacitor 279 and a resistor 280 and a parallel circuit with a capacitor 281.
The signal is fed back to the amplifier 260 and performs phase correction for motor control.

Reference numeral 261 denotes a power supply circuit.
61 inputs + 12V244 via the coil 262,
A stabilized power supply voltage is supplied to the resistor 290, the capacitor 270, the resistor 269, and the resistor 264.

Reference numeral 243 denotes D.C. D. MOTOR ON for controlling the driving and stopping of the motor 13.
ON243 is D. D. When driving the motor 13, a signal of “1” comes and the transistor 268 via the resistor 266 is turned on. 267 and 269 are transistors 2
68 are the bias resistors. When the transistor 268 is turned on, the comparison and DC amplifier 260 inputs a “0” signal, and the D.C. D. This is to stop the rotation of the motor 13.

Noise is removed by the coil 262 and the capacitor 263, and the + 12V 244 is connected to the resistors 282 and 27.
7, the capacitor 292, and the power supply circuit 261. The + 12V 244 supplied to the resistor 282 is connected to the ground via the Hall elements H1 283, H2 284, H3 285 and the resistor 286.

The two detection terminals of the Hall element H1 283 are connected in parallel with the capacitor 287 and are connected to the (3) and (4) terminals of the IC 241. Hall element H2 2
The two detection terminals 84 are connected to a capacitor 288 in parallel, and are connected to terminals (13) and (14) of the IC 241. A capacitor 289 is connected in parallel to the two detection terminals of the Hall element H3 285, and (1) of IC241,
(2) Connected to terminal.

The Hall elements 283 to 285 are arranged in the vicinity of the coils 300 to 305, and the D.H. D. Motor 13
This detects the positions of the N pole and S pole of the permanent magnet built in.

The terminals (6), (7) and (8) of the IC 241 are D. D. 3 to coils 300 to 305 of motor 13
Terminal for supplying phase AC voltage. 306 is (6),
The capacitor 307 connected between the terminals (8) and 307 is the capacitor connected between the terminals (6) and (7).
Reference numeral 8 denotes a capacitor connected between terminals (7) and (8), which is used for correcting the phase of the three-phase AC voltage.
Terminal (10) is ground terminal, terminal (9) is + 12V
The terminal (9) is connected to the ground via the capacitor 292 to remove noise.

The terminal (11) of the IC 241 is
The output voltage of the power supply circuit 261 of 0 is input via a resistor 290 and used as a reference voltage. The reference voltage at the terminal (11) is connected to the terminal (5) via the Zener diode 291.

The terminal (5) is an overcurrent protection terminal. This overcurrent protection terminal (5) is a D.D. D. When the overcurrent is supplied to the motor 13, the voltage of the (5) terminal becomes high, and the transistor 295 is made conductive through the resistor 294, and has a function of setting the output voltage of the comparison and DC amplifier 260 to 0V. Is. 293 is a bias resistor connected between the ground and the (5) terminal, and 296 is a comparison and D
This is a noise removal capacitor of the C amplifier 260.

Next, the operation of the motor drive circuit will be described. D. stopped D. To drive the motor 13, when the MOTOR ON 243 is set to “1”, the transistor 268 is turned on, the comparison and the DC amplifier 260 are set to “0”, and a rotation start voltage is applied to the terminal (12) of the IC 241.

Then, (6), (7),
(8) Three-phase AC voltage from terminals 300 to 305
Is supplied to D. D. The motor 13 starts rotating by a reaction with a permanent magnet built in the motor 13. The phase and frequency of this three-phase AC voltage are determined by the Hall elements 283 to 285.
It is adjusted by the rotational position of the permanent magnet divided into six parts, N pole and S pole.

As described above, D.I. D. When the rotation of the motor 13 is started, F.F. G245 detects the rotation of the permanent magnet and generates an induced electromotive voltage. The induced electromotive force is amplified by the preamplifier 246, shaped into a pulse by the Schmitt trigger 254, and differentiated by the differentiating circuit 257. The output of the differentiating circuit 257 is corrected for the fall characteristic by a time constant determined by the resistor 264 and the capacitor 265, and is input to the sample & hold circuit 259.

The sample-and-hold circuit 259 is different in the sawtooth waveform, which is normally output depending on the high density. At the normal density, the -DDM 242 becomes "0", the transistor 275 becomes non-conductive, and the resistance 273 and the semi-fixed resistance 274 have no effect on the sample & hold circuit. Therefore, the sawtooth waveform has a time constant determined by the capacitor 270, the resistor 271 and the semi-fixed resistor 272.

When the density is high, -DDM242 becomes "1", the transistor 275 becomes conductive, and the sawtooth waveform has a time constant due to the capacitor 270, the resistor 273, the semi-fixed resistor 274 and the resistor 271, and the semi-fixed resistor 272. Is determined. The sample-and-hold circuit 259 generates a reference voltage of half the power supply voltage, compares the reference voltage with the sawtooth waveform, and sets the reference voltage to the DC amplifier 2.
Sent to 60.

The comparison and CD amplifier 260 compares the reference voltage with the sawtooth waveform to determine the D.D. D. Motor 13
And outputs an output in a direction to increase or decrease the number of rotations. This output is input to terminal (12) of motor drive IC 241 (6),
From the terminals (7) and (8), a three-phase AC voltage is applied and
D. It is supplied to the motor 13.

Note that D.S. D. The rotation speed of the motor 13 is finely adjusted by the semi-fixed resistor 274 at high density, and finely adjusted by the semi-fixed resistor 272 at normal density. D. D. When an overcurrent is supplied to the motor 13, a motor stop voltage is sent from the terminal (5) of the IC 241 to stop the comparison and the output of the DC amplifier 260. D. Motor 1
3 is stopped.

[0166]

The present invention has the above-mentioned structure. According to the present invention, the rotation speed and the write speed are changed by applying the switching signals corresponding to the magnetic densities to the rotary drive means, the write means and the read means, respectively. The current value and other characteristics are switched, and it is possible to reproduce the magnetic medium recorded at a plurality of recording densities by the same device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a floppy disk drive according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for normal density and high density

FIG. 3 is a circuit diagram of a switching signal circuit.

FIG. 4 is a circuit diagram of a write circuit, a delay circuit, and an erase circuit.

FIG. 5 is a circuit diagram of a write circuit, a delay circuit, and an erase circuit.

6A is a circuit diagram of a preamplifier and a low-pass filter. FIG. 6B is a circuit diagram of a low-pass filter at a normal density.

FIG. 7 is a circuit diagram of a differential amplifier circuit, a comparator, and a time domain filter.

FIG. 8 is a circuit diagram of a motor drive circuit.

FIG. 9 is a block diagram of a conventional floppy disk device.

FIG. 10 is a signal waveform diagram of a conventional device.

[Explanation of symbols]

 12a Normal density magnetic medium 12b High density magnetic medium 13 Spindle motor 14 Magnetic head 15 Write circuit 16 Erase circuit 17 Delay circuit 18 Preamplifier 19 Low pass filter 20 Differential amplifier circuit 21 Comparator 22 Time domain filter b Write data signal c Write current h Write gate signal i Read signal j Read pulse signal -DDM, -LS, + LS switch signal

Claims (6)

[Claims] 1. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means generates a switching signal, and the writing means operates the magnetic head by the switching signal. Write circuit for changing the write current value to the write / read head, a delay circuit for changing the delay time with respect to the write current by the switching signal, and the delay circuit for changing the erase current value for the magnetic head by the switching signal. An erasing circuit for delaying the signal to be sent to the circuit, and the reading means changes a cutoff frequency of a read signal from the magnetic head by the switching signal, and a resonance frequency by the switching signal. And a differential amplifier circuit that differentiates the output of the low-pass filter, and the differential circuit amplifier that changes the pulse time width by the switching signal. A floppy disk device having a time domain filter for converting the output of the circuit into a pulse waveform. 2. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means generates a switching signal, and the writing means operates in the magnetic head by the switching signal. Of the write / read head, and an erase circuit for changing the erase current value of the erase head in the magnetic head in response to the switching signal. A low-pass filter that changes the cut-off frequency of the read signal from the magnetic head by a signal, a differential amplifier circuit that changes the resonance frequency by the switching signal to differentiate the output of the low-pass filter, and a pulse width by the switching signal. And a time domain filter for changing the output of the differentiating circuit amplifying circuit into a pulse waveform. Click device. 3. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means selectively generates a switching signal for each circuit, and the writing means comprises: A write circuit capable of changing the write current value to the write / read head in the magnetic head by the switching signal, and an erase circuit capable of changing the erase current value to the erase head in the magnetic head by the switch signal. The read means includes a low-pass filter capable of changing the cutoff frequency of the read signal from the magnetic head by the switching signal, and a differential amplifier circuit differentiating the output of the low-pass filter so that the resonance frequency can be changed by the switching signal. , A time domain filter that changes the pulse time width by the switching signal and that makes the output of the differentiating circuit amplification circuit a pulse waveform. I have a floppy disk drive. 4. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means selectively generates a switching signal for each circuit, and the writing means comprises: A write circuit capable of changing the write current value to the write / read head in the magnetic head by the switching signal is used. The reading means can change the cutoff frequency of the read signal from the magnetic head by the switching signal. A low-pass filter, a differential amplification circuit that differentiates the output of the low-pass filter so that the resonance frequency can be changed by the switching signal, and a pulse width that can change the pulse time width by the switching signal. A floppy disk drive having a time domain filter for. 5. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means selectively generates a switching signal for each circuit, and the writing means includes: A write circuit is provided which can change the write current value to the write / read head in the magnetic head by the switching signal, and the read means can output the output from the magnetic head so that the resonance frequency can be changed by the switching signal. A floppy disk device comprising: a differential amplifier circuit for differentiating, and a time domain filter for changing the pulse time width by the switching signal so as to change the output of the differential circuit amplifier circuit into a pulse waveform. 6. A switching signal generating means, a writing means, and a reading means, wherein the switching signal generating means selectively generates a switching signal for each circuit, and the writing means comprises: A write circuit capable of changing the write current value to the write / read head in the magnetic head by the switching signal is used. The reading means can change the cutoff frequency of the read signal from the magnetic head by the switching signal. A floppy disk device comprising: a low-pass filter; and a time domain filter that changes the time width of the pulse by the switching signal so as to change the output of the differentiating circuit amplification circuit into a pulse waveform.