JP2725670B2 - Floppy disk drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auxiliary storage device for an electronic computer.
Related to the floppy disk drive used for
You. [0002] FIG. 9 shows a conventional floppy disk drive.
FIG. 10 is a block diagram showing a signal waveform diagram of the device.
You. The configuration of this conventional example will be described below with reference to FIGS.
This will be described in detail. In FIG. 9, reference numeral 1 denotes a floppy disk drive.
The magnetic medium 1 is a magnetic medium that can be attached to and detached from the
Rotated by the handle motor 2, via the magnetic head 3
Recording and reproduction of signals are performed. When recording a signal on the magnetic medium 1, a write
The write signal b is input to the embedding circuit 4 and its output (FIG.
10 (c)) is recorded from the magnetic head 3.
You. This magnetic medium 1 is driven by the voltage shown in FIG.
It is magnetized as shown in FIG. In the direction of movement of the magnetic head 3,
Erasing heads (not shown) are provided at both left and right ends for playback.
This prevents erroneous detection in the event. This erase head is magnetic
It is provided at the rear part in the traveling direction from the pad 3
Thus, a delay circuit 6 is provided to delay the write gate signal h.
Then, the data is output to the erasing head by the erasing circuit 5. Further, when reproducing the signal of the magnetic medium 1,
In this case, the signal i is detected from the magnetic head 3 and the preamplifier 7
And the noise component is removed by the low-pass filter 8.
(FIG. 10 (e)) and input to the differential amplifier circuit 9.
You. The signal f differentiated by the differential amplifier circuit 9 is
Data 10. This comparator 10 has an input
When the signal f passes the voltage 0V (zero cross), the output
The signal g changes (“0” → “1”, “1”).
→ "0"). The signal g is transmitted to the time domain filter 11
When the signal g changes (“0” →
"1", "1" → "0"), one pulse is output, and the signal b
Output the same output signal j and output to the outside
It is. [0008] By the way, currently available floppy disks
As shown in Table 1, there are two types of disk drives: normal density type and high density type.
And each has a different standard. [0009] [Table 1] [0010] SUMMARY OF THE INVENTION
In the conventional case, when the magnetic medium becomes high density,
The conventional floppy disk unit was designed and assembled separately for high density.
The equipment must be changed to a standing one, and operation time and cost
There was a problem on the strike. The present invention eliminates the above-mentioned disadvantages of the prior art.
In other words, magnetic recording at multiple recording densities with the same device
To provide a floppy disk device capable of reproducing a medium.
And for the purpose. [0012] The present invention achieves the above object.
Driving means, writing means, and reading
Apply a switching signal corresponding to the recording density to each of the means.
Speed, write current value, and other characteristics
Is switched. [0013] According to the present invention, the present invention has the above-mentioned configuration and a plurality of the same devices can be used.
The ability to reproduce magnetic media recorded at
It has fruit. [0014] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
It will be explained together with the surface. FIG. 1 is a block diagram of an embodiment of the present invention.
Block diagram of a floppy disk drive, Fig. 2 for normal density
FIG. 4 is a signal waveform diagram for a high-density circuit. In FIG. 1, reference numeral 12a denotes a floppy disk.
This is a normal-density magnetic medium that can be
The air medium 12a has, for example, a coercive force of 300 Oersted,
The thickness of the magnetic layer is 2.5 microns. 12b is a floppy
-It is a high-density magnetic medium that can be
The magnetic medium 12b has, for example, a coercive force of 600
And the thickness of the magnetic layer is 1.5 microns. Reference numeral 13 denotes a spindle motor.
The idle motor 13 sends a switching signal to the motor drive circuit 13a.
By inputting the DDM, for example, 300 per minute
It can be switched to rotation or 360 rotation. 14 is
Record and playback on both high and normal density magnetic media
It is a magnetic head. Reference numeral 15 denotes a write circuit.
15 is a write data signal controlled by the write gate signal h.
Signal b for high density or normal density by switching signal -LS
To the write current C for use in the magnetic head 14.
You. The delay circuit 17 and the erase circuit 16
Is to prevent erroneous detection during playback as in the conventional example.
However, the switching signal + LS or -LS causes
This is to change the delay time for normal density. The signals of the magnetic media 12a and 12b are
Is reproduced, the signal i is detected from the magnetic head 14.
The signal is amplified by the preamplifier 18 and the low-pass filter
At 19, the noise component is removed. This low pass filter
19 is a switching signal + LS, for high density or normal density
Cut-off frequency (300 KHz or 400 KHz)
Instead, the center frequency shift at the time of reading on the inner circumference side of the magnetic medium
(Peak shift). The differential amplifier circuit 20 operates according to the switching signal -LS.
Resonance frequency for high density or normal density (350KHz
Or 500kHz) to keep the gain change constant
And eliminate unnecessary high frequency noise to suppress jitter
Things. This differential amplifier circuit 20 differentiates an input signal.
And sends it out as an output signal. The comparator 21 receives an input signal in the same manner as in the prior art.
The signal f passes through the voltage 0 V (zero cross) (“0” →
"1", "1" → "0") and the output signal g changes
It is. The output signal g is a time domain filter
22 when this signal g changes
("0" → "1", "1" → "0") 1 pulse output
Then, the same signal j as the signal b is output, and the read pulse signal is output.
It is output to the outside as the number j. Time domain
The error filter 22 built in by the switching signal -LS
The operation prevention circuit has been switched. [0023] [0024] Reference numeral 23 denotes a switching signal circuit.
The circuit 23Controlled by host computer or operator
ControlledSet the changeover switch 24 to + B side or earth side.
The three output signals -DDM, -LS,
+ LS is switched to "1" or "0". For normal density, -DDM is "0",
−LS is “0” and + LS is “1”.
A signal of "1" is sent for -DDM and a signal of "0" is sent for + LS.
You. Also, -DDM sends out a signal of the same polarity as -LS.
However, a large current can be driven for the motor drive circuit 13a.
It has become so. [0027] FIG. 2 shows data a1 for normal density and writing.
Signal b1, data a2 for high density and write signal b
FIG. 2 is a signal waveform diagram showing No. 2; Normally as shown in FIG.
The write signal b1 for high density and the write signal b2 for high density are
The output voltages are the same and the frequencies are different. Next, the operation of the above embodiment will be described.
In FIG. 1, signals are recorded on a magnetic medium 12a having a normal density.
When recording and reproducing, the changeover switch 24 is set to the normal density.
Is switched on, the spindle motor 13 rotates 300 times per minute
The write current of the write circuit 15 and the erase circuit
The erase current of 16 is usually for density. Again
For reproduction at normal density, the cut-off frequency of the low-pass filter 19
The number is 300 KHz, and the resonance frequency of the differential amplifier 20 is 3
50 KHz, high time constant of time domain filter 22
The density is switched to 1/2 from the density. Next, a signal is recorded on the high-density magnetic medium 12b.
When recording or reproducing, set the changeover switch 24 to the high-density side.
When switched, the spindle motor 13 rotates 360 rpm
And the write current C of the write circuit 15 and the erase circuit
16 erase currents are twice and 1.4 times the normal density, respectively.
It is what becomes. Also, for playback at high density,
The cut-off frequency of the filter 19 is 400 KHz,
The resonance frequency of the circuit 20 is set to 500 KHz in the time domain.
Switching the time constant of the filter 22 to twice that of the normal density
Things. As described above, the magnets for the normal density and the high density
When recording and reproducing signals on and from the media 12a and 12b,
It can be implemented by switching the changeover switch 24.
It is. That is, as shown in Table 1, for normal density
The magnetic medium 12a has a storage capacity of 1 Mbyte and data transfer.
Speed 250Kbit / s, number of tracks 80, thickness of magnetic layer
2.5 microns. In the high-density magnetic medium 12b, the storage capacity
1.6 Mbytes, data transfer rate 500 Kbit / s,
Magnet with 70 racks and 1.5 micron layer thickness
Switching the changeover switch 24 between the media 12a and 12b
Can be recorded and played back by one device.
You. Next, the floppy disk drive of this embodiment
1 corresponds to each block in the block diagram of FIG.
The circuit will be described. FIG. 3 is a circuit diagram of the switching signal circuit 23.
You. In FIG. 3, 30 is a -LOWSPEED terminal.
This -LOW SPEED terminal 30 allows the operator to
"1" or "0" when the changeover switch 24 is switched
Is applied at normal density, and “0” at normal density
“1” is applied. 31 is an internal drive select signal + DS
This is a terminal to which INT is applied.
This floppy disk drive can operate when
The function becomes inoperative, and when "1" is added to 31, it becomes inoperative. 32
Is a power-on reset-POR terminal.
When power is turned on, "0" is applied. 33 is D
This D flip-flop 33 is a flip-flop.
There is a signal of “1” at the D input and the T input changes to “1 → 0”.
Q output changes (“0 → 1”, “1 → 0”)
Things. Reference numeral 34 denotes a -LOW SPEED 30
Keep D input at "1" unless it becomes "0"
Pull-up resistor. 35 is a D flip-flop
This is a pull-up resistor that inhibits the setting of 33. 36 is
A bar for amplifying the current of the Q output of the D flip-flop 33
It is a buffer amplifier. 37 is a buffer amplifier 36
Pull-up resistor that keeps "1" unless it becomes "0"
It is. 38 is the output impedance of the buffer amplifier 36.
This is a capacitor for lowering the dance. 39 is the first
-L which is "0" at normal density.
This is an S (low signal) signal. 40 is D flip flip
The Q output of rop 33 is converted (“0” → “1”, “1” →
"0"). 41 is an inverter 40
Pull-up resistor that holds “1” unless “0”
It is anti. 42 is an output impedance of the inverter 40
This is a capacitor to lower the impedance. 43 is the second out
+ LS which becomes "1" at normal density
(Low signal) signal. 44 is an NPN type switch.
A switching transistor. 45 is the output of the inverter 40
A via whose input terminal is connected to the base of transistor 44
Resistance. Reference numeral 46 denotes a third output terminal, which is a floppy disk.
Open to start and stop the motor that drives the disk
-DDM (Direct Drive Mode)
Data) signal. Next, the operation of the switching signal circuit of FIG.
explain. First, when the power switch of this device is turned on, -P
The OR terminal 32 becomes “0” and the D flip-flop 33
Reset terminal R becomes “0”, reset, and Q output
The force becomes “0”. When the operator mounts this floppy disk
+ DSINT31 becomes “0” when the drive of
D flip by the signal of -LOW SPEED30.
The value of the Q output of the flop 33 changes. That is, -LOW SPEED 30 is
When it is "0" (when the density is normal), the Q output becomes "0".
You. Also, when -LOW SPEED30 is "1"
(When the density is high), the Q output becomes “1”. Q output
When “0”, the first output terminal 39 is “0”, and the second output terminal 39 is “0”.
The output terminal 43 becomes "1" and the third output terminal 46 becomes "0".
You. When the Q output is “1”, the first output terminal 39
Is “1”, the second output terminal 43 is “0”, and the third output terminal
The child 46 has a high impedance. FIGS. 4 and 5 show the write circuit 15 and the delay circuit 1.
6, erase circuit 17, magnetic head 14, and other attached circuits
Is shown. Note that the connection terminals of FIGS.
Are interconnected. The write circuit 15 shown in FIGS.
Switching circuit 15a, stabilized power supply circuit 15b, write drive circuit
Road 15c. The write current switching circuit 15a shown in FIGS.
Reference numeral 39 denotes a first switching signal-LS terminal.
The LS terminal 39 is connected to -LS39 in FIG.
53 is the terminal 39 and the base connected via the resistor 52
Transistor. Reference numeral 55 denotes a transistor 53 via a resistor 54.
Transistor whose collector and base are connected.
You. A resistor is provided between the emitter and base of the transistor 55.
A resistor 56 is connected, and a resistor 57 is connected between the emitter and the collector.
And 58 are connected in series.
The voltage from the circuit 15b is applied. This write current switching circuit 15a is normally
At the same time, the −LS terminal 39 becomes “0”.
The transistors 53 and 55 become non-conductive. Therefore, a stabilized power supply
The voltage of the circuit 15b becomes the current I via only the resistor 57.
Output to the write drive circuit 15c. At a high density, the write current
Since the −LS terminal 39 becomes “1”, the replacement circuit 15 a
The transistors 53 and 55 are turned on. Therefore, stabilization
The voltage of the power supply circuit 15b is a transistor in parallel with the resistor 57.
The current flows through a resistor 58 via an emitter and a collector 55.
Therefore, the current I output to the write drive circuit 15c is
Since it is determined by the combined resistance value of the resistors 57 and 58,
Larger than the current value determined by the resistance value of the anti-57 only
A large current flows. As described above, the output to the write drive circuit 15c
The current I is determined by the -LS terminal 39,
In other words, at a normal density, a small current flows,
In other words, at a high density, a large current flows. In the stabilized power supply circuit 15b, 59 is +
The + 12V terminal 59 is connected to the resistor 61.
To the base of the transistor 60 via the resistor 62
Connected to the collector of transistor 60. Tran
The emitter of the transistor 60 is connected to ground,
The collector of transistor 60 is connected to the transistor
And the cathode of the Zener diode 63.
ing. The anode of this Zener diode 63 is
Connected to earth. Collector of transistor 64
Is connected to the + 12V terminal 59, and the
The emitter is connected to the emitter of transistor 55
You. This stabilized power supply circuit 15b has a transistor
When the base of the transistor 60 is “0”, the transistor 64
The voltage is output from the mitter. That is,
When the base of the transistor 60 is "0", the transistor
And the + 12V is connected via the resistor 62.
It flows to the zener diode 63. Zener diode 6
3 is applied to the base of the transistor 64.
As a result, the stabilized voltage
4 from the four emitters. On the other hand, the write data (FIG. 1B) is W
Input as a pulse waveform to RITE DATA terminal 65
It is. Reference numeral 67 denotes an inverter.
If there is no signal from WRITE DATA terminal 65
, The state of + 5V, that is, "1" through the resistor 66
It is something that has become. 68 is a D flip-flop
And the T terminal of the D flip-flop 68
Data terminal is connected to the output terminal of the
R terminal is the output terminal of OR gate 71
Connected to child. One input terminal of the OR gate 71 is a buffer.
Connected to WRITE GATE 69 via the amplifier 70
The other input terminal is connected to DS via a buffer amplifier 73.
It is connected to INT31. The D flip-flop 68 has a Q output
Since the inverted information Q becomes the D input, the T input changes from “1”.
When it becomes "0", the Q output is inverted. That is,
D flip-flop 68 divides the T input by 2
It is. Reference numeral 76 denotes an inverter.
Output of 76 drives transistor 79 via resistor 77
Is what you do. This transistor 79 is controlled by a resistor 78.
The stabilized voltage (output of transistor 64)
And the emitter of transistor 79 is
The write current I is supplied, and the collector is connected through a resistor 80.
And connected to earth. Reference numeral 81 denotes an inverter.
The output of 81 drives the transistor 84 via the resistor 82
Is what you do. This transistor 84 is connected via a resistor 83
And connected to the emitter of the transistor 64. G
The write current I is connected to the emitter of the transistor 84.
And the collector is connected to ground via a resistor 85.
ing. The collector of the transistor 79 and the transistor
A resistor 86 is connected between the collectors of the star 84.
The collector of the transistor 79 is connected through a diode 87
Read / write coil 101 of first magnetic head 100
It is connected to the. The collector of transistor 79 is
Writing of the second magnetic head 105 via the diode 88
The readout coil 106 is also connected. The collector of the transistor 84 is
Read / write of the first magnetic head 100 through the
It is connected to the coil 102. The transistor 8
4 is connected to the second magnetic head via a diode 90.
Connected to the write / read coil 107 of the
You. Numeral 75 is a power-on reset-POR terminal.
The -POR terminal 75 has a short period
Only "0" is applied. 74 is a NAND gate
And one input of this NAND gate 74 is -POR.
75 is input, and a buffer amplifier 73 is input to the other input.
Input via internal drive select DSINT terminal 31
Is done. The output of NAND gate 74 is
0 is connected to the base. Next, the delay circuit 16 shown in FIGS.
The circuit 17 will be described. In FIGS.
Is -ESW (eraseable signal) indicating that erasing is possible.
You. 43 becomes “1” when driving the normal density type
This is a second switching terminal (+ LS terminal). 113 to 5V
The time constant of the connected resistor 112 and capacitor 118
One-shot multi that determines the output time of the output voltage
This is an IC, and this IC 113
-Start output when ESW110 becomes "0"
Things. However, at normal density, + LS43 is "1".
Therefore, the transistor 116 via the resistor 115
It conducts, and the capacitor 117 is connected to the ground. this
In the state, the capacitors 118 and 117 are connected in parallel.
Therefore, it has the function of extending the output time of the IC 113.
is there. The output of the IC 113 is the NAND gate 1
19 and the output to the NOR Dot 125. The NAND gate 119 is connected to the IC 113
And -POR75 are input, and the output is
And is connected to the base of the transistor 122. This
Transistor 122 is connected to the base 5
V is applied and the collector is grounded via a resistor 124
Connected to The anode side of the resistor 124 is connected to the ground.
The connected diodes 123 are connected in parallel. Tiger
The collector of the transistor 122 has diodes 126, 1
27 are connected to this diode 12
6 is the erase coil 1 of the first magnetic head 100.
03, and the cathode of the diode 127 is connected to the
Connected to the erase coil 108 of the second magnetic head 105
I have. The erasing coil 103 is used for removing noise.
Capacitors 104 are connected in parallel, as well as erase coils
108 is connected to a capacitor 109 for noise removal.
ing. The output of AND gate 138 or 140 is
When it becomes “0”, the collector of the transistor 122
From the connected erase coil 103 or
108 starts the erase operation. Next, the erasing circuit 17 will be described. 3
9 is -LS which is a signal of "0" for normal density. 1
29 is a base bias resistor of the transistor 130.
You. Transistor 130 has its emitter connected to ground,
Is connected to the bias resistor 131. +5 V is applied to the emitter of the transistor 132
Connected to the base via a resistor 133,
And 135 to the collector. In addition,
The midpoint between the resistors 134 and 135
Connected to the mitter. In this erase circuit 17, -LS128 is "0".
, Ie, for normal density, transistor 1
Since transistor 30 does not conduct, transistor 132 also conducts.
+ 5V is the transistor 1 via only the resistor 134
It is supplied to 22 emitters. On the other hand, when -LS128 is "1",
In other words, for high-density use, the transistor 130 is turned on.
The transistor 132 is also turned on, and + 5V is connected to the resistor 134.
135 is connected to the transistor 122 via the parallel connection.
Is supplied to the printer. Reference numeral 136 denotes a first magnetic disk of the floppy disk.
"1" when the magnetic head 100 is driven, the second magnetic head
SEL becomes “0” when the drive 105 is driven.
ECT. 137 input is -SIDE SELECT
At T136, output connected to AND gates 138 and 141
Is an inverter. AND gates 139 and 1
-SIDE SELECT 136 is directly input to 40
It is connected. Another of the AND gates 138 to 141
Are connected to the output of the NOR gate 125, respectively.
Has been continued. AND gates 138 to 141 and NOR gate
And the relationship with -SIDE SELECT 136
It is as follows. (1) NOR gate 125 = “0”, SIDE SEL
When ECT136 = "0". Since the output of the inverter 137 is "1", Output of AND gates 138, 140, 141 = "1" Output of AND gate 139 = "0" (2) NOR gate 125 = "0", -SIDE SE
LECT136 = "1". Since the output of the inverter 137 is "0", Output of AND gates 139, 140, 141 = "1" Output of AND gate 138 = "0" (3) NOR gate 125 = "1", -SIDE SE
LECT136 = "0". Since the output of the inverter 137 is "0", Output of NAND gates 138, 139, 140 = "1" Output of NAND gate 141 = "0" (4) NOR gate 125 = “1”, −SIDE SE
LECT136 = "0". Since the output of the inverter 137 is "1", Output of NAND gates 138, 139, 141 = "1" Output of NAND gate 140 = "0" It is what becomes. The outputs of these NAND gates 138 to 141
The work of power is as follows. (1) When the NAND gate 138 is "0". The first magnetic head 100 of the magnetic head 14
Of the coils 101 to 103 become 0 V,
The first magnetic head 100
Can be included. (2) When the NAND gate 139 is “0”. Carp of side 1 105 of magnetic head 14
The middle point of the coils 106 to 108 becomes 0 V, and the erase coil 10
8 operates, the writing of the second magnetic head 105 is
It becomes possible. (3) When the NAND gate 140 is "0". First magnetic head 100 of magnetic head 14
The middle point of the coils 101 to 103 becomes 6 V,
The console 103 does not operate. This is because the resistors 144 and 14
Since the value of 2 was the same, the voltage at the middle point was 6 V,
This is because no current flows through the leaving coil 103. this
At this time, reading from the first magnetic head 100 becomes possible.
You. (4) When the NAND gate 141 is “0”. The second magnetic head 105 of the magnetic head 14
Of the coils 106 to 108 becomes 6 V,
The console 108 does not operate. This is the resistance 145,
  143, the voltage at the middle point becomes 6V.
Because the current stops flowing through the erase coil 103.
is there. At this time, the reading of the second magnetic head 105 is performed.
It becomes possible. Next, the magnetic head 14 will be described.
The magnetic head 14 includes a first magnetic head 100 and a second magnetic head.
And a head 105. This is a floppy
It corresponds to the front and back surfaces of the discs 12a and 12b.
is there. The first magnetic head 100 writes and reads data
Coils 101 and 102 and erase coil 103
And a capacitor 104. One end of each of the three coils
The other end is controlled by 5 lines in the erase coil 103.
1 for volt, write and read coils 101 and 102
Two volts are applied. Control line is 0 volt at writing
(NAND gate 138 is “0”, 140 is “1”)
Read / write coils 101 and 102 and erase
The coil 103 is also driven. When reading, the control line is set to 6 volts.
(NAND gate 140 is “0”, 138 is “1”)
Therefore, the erase coil 103 is not driven,
Only the output coils 101 and 102 are driven. Similarly, writing is performed on the second magnetic head 105.
Read coil 106, 107 and erase coil 1
08 and the capacitor 109. All three coils,
One end is controlled by a common control line, and the other end is
8 is 5 volts, the write and read coils 106 and 10
At 7, 12 volts is applied. At the time of writing, the control line is set to 0 volt (NAND)
(Gate 139 is "0", 141 is "1")
Read coil 106, 107, erase coil 108
Are also driven. When reading, the control line
Is 6 volts (NAND gate 141 is “0”, 139 is
"1"), the erase coil 108 is not driven,
Only the read coils 106 and 107 are driven. Next, the write circuit 15 and the delay circuit shown in FIGS.
16, the erase circuit 17, and the operation of the magnetic head 14.
I will tell. 4 and 5, the write data (FIG. 9)
(B)) is applied to the WRITE DATA terminal 65
You. If writing is possible, a write gate signal (FIG. 1)
(H)) is applied to WRITE GATE 69, and D
Release the reset of the flip-flop 68 and write data
(FIG. 10B) is divided by two. When writing is possible, DS INT
31 and -POR75 are set to "1".
The transistor 60 is non-conductive, and the + 12V terminal 5
+ 12V applied to 9 is stabilized by the stabilized power supply circuit 15b
And applied to the write switching circuit 15a. The write switching circuit 15a has a -LS terminal
A signal of “0” at normal density and “1” at high density is
And the write current is controlled by the signal of the -LS terminal 39.
I is a normal density, a small current flowing only through the resistor 57,
Large current flows through both the resistors 57 and 58,
It is applied to the drive circuit 15c. On the other hand, the output from D flip-flop 68
The written data is written by transistors 79 and 84.
Current I, and write through diodes 87-90.
To read coils 101, 102, 106, 107
Applied. Writing to floppy disks 12a and 12b
Is controlled by NAND gates 138 and 139.
Of the first magnetic head 100 or the second magnetic head 105
Only one of them is driven. Next, the operation of the delay circuit 16 and the erase circuit 17
Will be described. In the delay circuit 16, the erasable signal (-E
SW110) is delayed by the one-shot multi IC 113.
I'm making it. The delay time of this IC 113 is usually high density and high density.
Depends on the degree, and is switched by the + CS terminal 43. this
The output of the delay circuit 16 is output to the NA
Applied to ND gates 138-141. The erase current is supplied from transistor 122
The erasing coil 103, via the diodes 126, 127,
108 is applied. This erase current is applied to the -LS terminal 39.
More switched, at normal density only via resistor 134
A small current flows through both resistors 134 and 135 at high densities
Large current is applied to the erasing coils 103 and 108
It is. The erase current is the same as the write current.
Controlled by NAND gates 138 and 138, the first
Either the magnetic head 100 or the second magnetic head 105
Only one of them is driven. At the time of reading, WRITE GATE
Both the terminal 69 and the −ESW terminal 110 become “1”.
The NOR gate 125 is set to "1" and the NAND gate
138 and 139 are closed and NAND gates 140 and 141 are closed.
open. At this time, control lines (each coil 101 to 103,
106-108) from 0 volts to 6 volts
And the erase coils 103 and 108 applied with 5 volts.
Operation is stopped. Therefore, at the time of reading, writing and reading
Any of the two 101, 102, 106, 107
And the READ1 151 terminal and READ215
It is read from the 0 terminal. Next, the readout circuit group will be described with reference to FIGS.
6 (a) to 6 (c) and FIG. 4 and 5, reference numeral 146 denotes a magnetic coil 1
The diode 147 is connected to the magnetic coil 10.
2 and 148 are magnetic coils 106
Is connected to the magnetic coil 101.
Connected diode. Diodes 146 and 14
7 is commonly connected to the READ2 terminal 150 from FIG.
It is connected to READ2 of the preamplifier 18. On the other hand, the diodes 148 and 149
The READ1 terminal 151 is common to the preamplifier 1 of FIG.
8 READ1 terminal 151. FIG. 6A shows the preamplifier 18 and the low amplifier.
FIG. 3 is a circuit diagram showing a pass filter 19; Figure 6
150 is an input terminal of READ1, and 151 is READ
2 input terminal. 152 and 153 are connected to + 12V
This is a bias resistor connected to the
2, 153 are READ1 150 and REA, respectively.
D2 151 is magnetized via diodes 146-149.
Via the head coils 101, 102, 106, 107
It is something to do. Reference numeral 154 denotes READ1 150 and READ1.
2 151 is a resistor that determines the input impedance between
You. The low-pass filter 19 has a + PC ON terminal.
156, + LS terminal 43 and output of preamplifier 155.
Input force and output from LPF + 189 and LPF-190
It is something that is empowered. + PC ON terminal (Write compensation:
156 is a buffer amplifier
157 to the midpoint of diodes 170 and 171
It is connected. The + PC ON terminal 156 is
The magnetic head (3) in contact with the floppy disk (1)
Track counter that counts the current position (number of tracks)
(Not shown), "0" on tracks 0-43,
"1" is applied in 44 to 76 tracks.
With this PC ON terminal 156 and + LS43, high density
When the inner track (44-76 tracks)
The cutoff frequency of the filter 19 can be increased. The + LS terminal (normal density) 43 has a normal density
At this time, it becomes “1”, and the transistor 1
61 is made conductive. + 12V is the resistance 176
Through the anode of the diode 164, the diode 17
0 and the capacitor 177
You. Further, + 12V is connected to the diode 1 via the resistor 181.
67 anode, diode 171 anode and core
Capacitor 172. The output of READ1a158 on the other hand
Through a capacitor 172 and a transistor
174, and the other via a resistor 162
It is connected to the base of the transistor 163. This
The emitter of the transistor 163 is connected to the diode 164.
Connected to the sword and the collector to earth
You. The emitter of the transistor 174 is connected to a resistor 175
+ 12V is connected through the
The ground is connected to ground via a resistor 173. The output of READ2a159 is
Is connected to the capacitor 177 and the transformer via the coil 169.
Connected to the base of the transistor 179, and the other is connected to the resistor 165.
Is connected to the base of the transistor 166 via
The emitter of this transistor 166 is a diode 167
Connected to the cathode and the collector is connected to ground
I have. The emitter of the transistor 179 is connected to the resistor 18.
0 is connected to + 12V and the collector is connected to ground,
The base is connected to ground via a resistor 178. The emitter of the transistor 174 is the coil 1
82 to the capacitors 184 and 187 and the resistor 185
It is connected. The other end of this resistor 185 is connected to ground.
The other end of the capacitor 187 is connected to the terminal 189 of the LPF +.
Have been. The emitter of the transistor 179 is
The other side of the capacitor 184 and the resistor
It is connected to an anti-186 and a capacitor 188. This
The other end of the resistor 186 to ground and the other end of the capacitor 188
The other is connected to the terminal 190 of the LPF-. FIG. 6B shows a low-pass filter at normal density.
This is a filter circuit of the filter 19. FIG. 6 (b) smell
The input is READ1a158, 2a159, and
Output via the files 168 and 169. This output is
This is the base of transistors 174 and 179. This output
A capacitor 1 is connected between the bases 174 and 179.
72 and 177 in series and resistors 173 and 178
A series circuit is connected. In FIG. 6B, the + LS43 terminal is
Since this is the case of “1”, the transistor 161 conducts,
Diodes 170 and 171 are connected to ground
It is. FIG. 6C shows a low-pass filter at a high density.
This is a filter circuit of the filter 19. In FIG. 6C,
Inputs READ1a158, 2a159 and coil 1
68, and 169. This output is
This is the base of the stars 174 and 179. Also, the input RE
AD1a158 outputs the output 17 via a capacitor 177.
9 connected to the base. READ2a159
Connected to the base of the output 174 via a capacitor 172
Have been. This output 174 base and 179 base
A series circuit of resistors 173 and 178 is connected between them.
You. As described above, the low-pass filter 19
At normal density, the shielding determined by a filter as shown in FIG.
It has the characteristic of cut-off frequency.
Cutoff frequency characteristics determined by a filter as in (c)
With Next, the preamplifier 18 shown in FIG.
The operation of the low-pass filter 19 will be described. Generally, a floppy disk drive has a surface,
Since the back side is not reproduced at the same time, the read circuit
Need only be for one system. Therefore, as shown in FIGS.
The first magnetic head 100 and the second magnetic head 105
Are reproduced in a single system. Thus, the coil 10 of the magnetic head is
The information read from 1,102,106,107 is
To the operational amplifier 155 via the diodes 146 to 149
It is amplified and output. The output of the operational amplifier 155 is on the READ1a side.
Now, the low-pass filter of the coil 168 and the capacitor 172
The signal passes through the filter and is input to the transistor 174. Also R
On the EAD2a side, the coil 169 and the capacitor 177
The signal passes through a low-pass filter and is input to transistor 179.
It is. READ1a of low-pass filter circuit 19
Terminal 158 and READ2a terminal 159
The outputs of the loops 155 are respectively connected. Normal density
Indicates that the + LS terminal 43 is "1",
The star 161 conducts, + 12V is a resistor 176, a diode
Flows to ground via the transistor 170 and the transistor 161
You. +12 V is a resistor 181, a diode
170, also flows to ground via transistor 161
It is. At this time, the diode 164 and the transistor
163, and a diode 167 and a transistor 166
Does not operate because of reverse bias. Therefore, usually the density
In the case of READ1a158 and READ2a159
The base of the transistor 174 and the transistor 179
The circuit between the bases is equivalent to the circuit diagram shown in FIG.
It becomes. Next, at high density, the + LS terminal 43 becomes "0".
And the transistor 161 becomes non-conductive.
+ PC ON terminal 156 is connected to floppy disk 12b
Is 0 for tracks 0 to 43,
Since the output of the amplifier 157 also becomes “0”, the circuit shown in FIG.
The road map can be applied as it is. Further, 44 to 44 of the floppy disk 12b
For 76 tracks, + PC ON 156 indicates “1”
+ 12V passes through the resistor 176,
Diode 170 cannot be conducted.
The transistor 163 is made conductive. Similarly, + 12V
Can conduct diode 171 after passing through resistor 181
There is no diode 167 and transistor 166
Through. Therefore, in the case of high density, READ1a1
58 and READ2a159, the transistor 174
The circuit between the base and the base of transistor 179 is shown in FIG.
This is equivalent to the circuit diagram shown in FIG. Thereafter, the coils 182 and 183
The frequency characteristic is corrected by the
9 and LPF- terminal 190. Next, FIG. 7 shows the differential amplifier circuit 20.
It will be described using FIG. In FIG. 7, 39 is a normal density.
“-LS” is input with “0” and “1” at high density. 2
01, 202 and 204 are biases of the transistor 203
Resistance. 205 is a FET (field effect transistor)
Reference numeral 206 denotes a bias resistor. The source of the FET 206,
Capacitors 207 and 208 are connected in series between the drains.
It is connected. A resistor 209 is provided at both ends of the capacitor 208.
The resistor 210 and the semi-fixed resistor 21 are connected in parallel.
3. The series circuit of the coil 211 is also connected in parallel.
The movable portion of the semi-fixed resistor 213 is connected via a resistor 212
Connected to earth. On the other hand, LPF + 189
LPF-190 is a transformer on the base of transistor 191.
Each is connected to the base of the transistor 194. The collector of the transistor 191 is a comparator.
Data 21 and + 12V via a resistor 192,
The emitter is connected to the constant current source 193. Transi
The collector of the star 194 includes the comparator 21 and the resistor 1
95 is connected to + 12V, and the emitter is a constant current source
196. The transistor 191
The transmitter is connected to one terminal of the semi-fixed resistor 213
The other of the emitter of the transistor 194 and the semi-fixed resistor 213
Terminal. Next, the comparator 21 and the time domain
The filter 22 will be described with reference to FIG. In FIG. 7, the signal of -LS39 is a via signal.
Into the base of the transistor 227 via the resistor 226.
Is forced. The emitter of the transistor 227 is grounded.
And the collector is connected to the transistor 2 through the resistor 228.
29 connected to the base. Of this transistor 229
A bias resistor 230 is connected between the base and the emitter.
The resistors 229 and 232 are connected directly between the collector and the emitter.
A column circuit is connected. The middle point between resistors 229 and 232 is one shot
Connected to Multi 221
The capacitor 233 is connected between the other point of the
ing. The emitter of the transistor 229 has a resistor.
+ 12V is connected via 234, and Zener diode
It is connected to the ground via the gate 235. This tran
The emitter of the transistor 229 is connected to
It is connected to the boat multi 223. This one-shot
A capacitor is connected between one terminal of the toe 223 and the other terminal.
237 are connected. The comparator 21 compares the two input voltages with each other.
The pulse generator 220 outputs the difference.
And connected to the D terminal of the D flip-flop 222
ing. The pal generator 220 outputs the output of the comparator 21
When the voltage is input and the polarity of the output voltage is
This is to generate one pulse. The one-shot multi 221 generates a pulse.
Of the length of time determined by the short pulse
Signal, and the length of time
Depending on the time constant of the sensor 233 and the resistor 232 or 231.
It is determined. 222 is a D flip-flop
This D flip-flop 222 has a D input
The output of the parator 21 and the T input are one shot multi 2
21 when the D input is "1".
The Q and NOTQ outputs are inverted with the reversal of force.
You. Reference numeral 223 denotes a one-shot multi.
One shot multi 223 is a D flip-flop 222
Of the time determined when the Q and NOTQ outputs of
It sends out a length signal. The length of this time is
Determined by the time constant of the capacitor 237 and the resistor 236
It is what is done. The output of this one-shot multi is AND
Input to the gate 224, READENABLE 225
Is "1", the AND gate 224 outputs
It is output to the terminal of TA226. Next, the differential amplifier circuit 20 shown in FIG.
Data 21 and the operation of the time domain filter 22.
Will be described. In FIG. 7, the output of the low-pass filter 19 is
Force, ie, the signals of LPF + 189 and LPF-190
Is input to transistors 191 and 194.
In the case of high density, the coil connected between both transistors
Of the differential circuit by the
(See FIG. 10F). In the case of the normal density, -LS200 is "0".
, The transistor 203 becomes non-conductive, and FE
T206 becomes conductive, and the differentiating circuit connects with the capacitor 207.
What is formed by the parallel circuit 208 and the coil 211
It is. Capacitors 207 and 208 at normal density
The resonance frequency of the coil 211 is
Lower than the resonance frequency of the capacitor 208 and the coil 211
It becomes. The reason is that the basic formula at the resonance frequency is as follows: [0135] (Equation 1) In the above, the value of C is smaller than that of normal density.
Because they are bigger. The signal thus differentiated is
Input to the comparator 21 and the polarities of the two input signals are
When inverted, the output is inverted (FIG. 10 (f)). The output of the comparator 21 is a pulse generator
220, one-shot multi 221, D flip-flop
Input to the one-shot multi 223 via the
You. This pulse generator 220, one shot multi 22
1, the D flip-flop 222 is shown in FIG.
Of the output of the differential amplifier circuit 20 (f1, f
2, f3) to prevent malfunction due to noise.
Things. That is, the output of the comparator 21 is
It is just input to the pulse generator 220 and the comparator 2
When the polarity of the output of 1 changes, a short pulse is output
You. The output of this pulse generator 220 is
221 is driven. The output of this one-shot multi
The time is usually different for high density and high density applications. For normal density, -LS39 is "0".
Since the transistor 229 is turned off,
The pulse time width of the shot is determined by the capacitor 223 and the resistor 23.
It is determined by the time constant determined in 2. Also high density
-LS39 becomes "1", the transistor 22
9 is conducting, so the pulse time width of one shot
Is the combined resistance of the capacitor 223 and the resistors 232 and 231
Is determined by the time constant determined by This one-shot multi 221 pulse transmission
At the end of output, the T input of the D flip-flop 222 is driven.
So that if the output of the differential amplifier circuit 20
Even if noise is mixed in the slack (Fig. 10f1 to f3)
Masked during the one-shot multi 221 pulse transmission time
Therefore, no malfunction of the D flip-flop 222 occurs.
It is a thing. The output of the D flip-flop 222 is
Waveform shaped by One-Shot Multi 223 and can be read
When enabled, READ ENABLE 225 is set to "1".
And sent to the outside as READ DATA 226.
It is what is done. Next, a motor drive circuit will be described with reference to FIG.
Will be explained. The motor drive circuit of FIG.
Eve motor (DD motor) 13, integrated rotation for rotation speed control
(IC) 240 (μPC1043C phase etc.), motor drive
Operating integrated circuit (IC) 241 (TA-7245AP phase)
Etc.) and other accessory parts. 242 is
It becomes “0” for normal density and “1” for high density.
Terminal. 243 is D.E. When driving the D motor 13
Is a terminal of MOTOR ON which becomes "1". 244
Is + 12V. 245 is mounted vertically to the rotation axis of the motor.
F. of the printed pattern in the form of G. FIG. so
Yes, this F. G. FIG. (Frequency oscillator), the motor rotates
When the permanent magnet built into the motor rotates
The rotation of the generated magnetic flux is detected by the above printed pattern and
An electromotive voltage is generated. 246 is the IC240
Is a preamplifier built in the
6 is F. G. FIG. Input the voltage of H.245 to the plus terminal and output
Is connected to a negative terminal via a resistor 250. The minus terminal of the preamplifier 246 is
F. through a series circuit of a capacitor 248 and a resistor 249.
G. FIG. 245 is connected to the other end. This F. G. FIG. 24
5 is connected to the ground via a capacitor 247.
ing. The resistor 250 includes a resistor 252 and a capacitor.
251 series circuits are connected in parallel. Preamplifier 2
The output of 46 is supplied to the IC 240 via the capacitor 253.
Input to the minus terminal of the Schmidt trigger 254
You. The output of the Schmitt trigger 254 passes through the resistor 255
Is fed back to the plus terminal. Further, this Schmitt trigger 254 is
Shapes the signal into pulses at a specified threshold
Whose output is differentiated via capacitor 256
The signal is input to the circuit 257. Differentiated signal is timing
The signal is input to the circuit 258. The timing circuit 258
Differentiated by the time constant of anti-264 and capacitor 265
The fall time of the signal is set. The output of the timing circuit 258 is
Input to the hold circuit 259 to form a sawtooth waveform
Is done. This sawtooth waveform is usually used for
And the resistor 271 and the semi-fixed resistor 272
It has a fixed inclination. Also, at high density
Is the capacitor 270, the resistor 271, and the semi-fixed resistor 272.
In addition, the slope determined by the resistor 273 and the semi-fixed resistor 274
It has. The switching between the normal density and the high density is performed by
Depends on the signal of DM242. That is, at normal density
Goes through the resistor 276 because -DDM 242 becomes “0”.
The base of the transistor 275 becomes “0” and the transistor
The transistor 275 becomes non-conductive, and the resistor 273 and the semi-fixed resistor
Anti-274 has no effect on the circuit. Also, when high density
Since -DDM242 becomes "1", the transistor 2
75 is conductive and the semi-fixed resistor 274 is connected to ground.
It is. The series circuit of the resistor 271 and the semi-fixed resistor 272
And a combined resistor of a series circuit of the resistor 273 and the semi-fixed resistor 274.
With the capacitor 270, the time constant of the sawtooth waveform is
To form. 278 is a sample and hold circuit
259 is a capacitor for removing noise.
The power supply circuit 261 generates a half of the power supply voltage.
Is applied as a reference voltage.
By 78, the noise component is removed. Reference numeral 260 denotes a comparison and DC amplifier.
The comparison and DC amplifier 260 is a sample and hold circuit
259, the ratio of the sawtooth signal to the reference voltage
In comparison, it sends out the current for controlling the rotation of the motor.
You. This comparison and the output voltage of DC amplifier 260
The series connection of the capacitor 279 and the resistor 280 and the capacitor
Again through a parallel circuit with the
Feedback to amplifier 260, phase correction for motor control
Is what you are doing. Reference numeral 261 denotes a power supply circuit.
61 inputs + 12V244 via the coil 262,
Resistor 290, capacitor 270, resistor 269 and resistor
A stable power supply voltage is supplied to the resistor 264. Reference numeral 243 denotes D.C. D. Drive and stop of motor 13
MOTOR ON which controls the
ON243 is D. D. When driving the motor 13
When the signal of "1" comes, the transistor through the resistor 266
268 is turned on. 267 and 269 are transistors 2
68 are the bias resistors. Transistor 268 conducts
Then, the comparison and DC amplifier 260 inputs the signal of “0”.
Force, D. Stops the rotation of the motor 13.
You. The coil 262 and the capacitor 263 form
The + 12V 244 whose noise has been removed is connected to the resistors 282 and 27.
7, the capacitor 292, and the power supply circuit 261.
It is. + 12V244 supplied to the resistor 282 is
Element H1 283, H2 284, H3 285 and resistor
286 is connected to the ground. Two detection terminals of the Hall element H1 283
Connects a capacitor 287 in parallel and
Connected to terminals (3) and (4). Hall element H2 2
The two detection terminals 84 connect a capacitor 288 in parallel.
Connected to terminals (13) and (14) of IC 241.
It is. The two detection terminals of the Hall element H3 285
Densers 289 are connected in parallel, and IC 241 (1),
(2) Connected to terminal. The Hall elements 283 to 285 are formed of coils
300 to 305; D. Motor 13
To detect the position of N pole and S pole of the permanent magnet built in
It is. Terminals (6), (7) and (8) of IC 241
The child is D. D. 3 to coils 300 to 305 of motor 13
Terminal for supplying phase AC voltage. 306 is (6),
The capacitor connected between terminals (8) and 307 is
A capacitor connected between terminals (6) and (7), 30
8 is a capacitor connected between terminals (7) and (8)
Yes, it is used for phase correction of three-phase AC voltage.
Terminal (10) is ground terminal, terminal (9) is + 12V
The terminal (9) is connected to the capacitor 292.
It is connected to the ground through to remove noise. The terminal (11) of the IC 241 is
0 through the resistor 290.
To the reference voltage. The reference for this terminal (11)
The voltage is applied to terminal (5) via Zener diode 291
It is connected to the. Terminal (5) is an overcurrent protection terminal.
The overcurrent protection terminal (5) of D.C. D. Overload on motor 13
When the current is supplied, the voltage of the terminal (5) increases,
The transistor 295 is turned on through the anti-294 and the ratio
Function to make the output voltage of the DC amplifier 260
Have 293 is the ground and (5)
A bias resistor 296 connected between the terminals is used for comparison and D.
This is a noise removal capacitor of the C amplifier 260. Next, the operation of the motor drive circuit will be described.
I do. D. stopped D. To drive the motor 13
When MOTOR ON 243 is set to “1”,
The transistor 268 conducts and the comparison and DC amplifier 260
Set to “0” and start rotation to terminal (12) of IC 241
Voltage. Then, (6), (7),
(8) Three-phase AC voltage from terminals 300 to 305
Is supplied to D. D. Permanent magnet built into motor 13
Starts rotation due to the reaction with Of this three-phase AC voltage
The phase and frequency are determined by the Hall elements 283 to 285.
Adjusted according to the rotational position of the permanent magnet divided into six parts, N pole and S pole
Is to be adjusted. As described above, D.I. D. Turn of motor 13
When the rotation is started, F.R. G245 detects rotation of permanent magnet
To generate an induced electromotive voltage. This induction
The electromotive voltage is amplified by the preamplifier 246,
The pulse is shaped into a pulse by a gas 254, and finely divided by a differentiating circuit 257.
Divided. The output of this differentiating circuit 257 is
With the time constant determined by the capacitor 265, the fall
Characteristics corrected and input to sample & hold circuit 259
Is done. The sample and hold circuit 259
Normal density is output by high density, sawtooth waveform is different
Things. At normal density -DDM242 is
It becomes “0” and the transistor 275 becomes non-conductive,
Anti-273 and semi-fixed resistor 274 are sample & hold circuits
Is no longer affected. Therefore, the sawtooth waveform
The resistor 271 and the semi-fixed resistor 272
It becomes a waveform having a time constant determined as follows. When the density is high, -DDM242 is
"1", the transistor 275 becomes conductive, and
The narrow waveform has a capacitor 270, a resistor 273, and a half
A fixed resistor 274, a resistor 271, and a semi-fixed resistor 272
The time constant is determined. Sample and hold
The circuit 259 generates another reference voltage of half the power supply voltage.
And the DC amplifier 2
Sent to 60. [0164] The comparison and CD amplifier 260
By comparing the pressure and the sawtooth waveform, D.I. D. Motor 13
Speed is detected and the speed is increased or decreased
The output is sent in the direction of This output is
Input at terminal (12) of data driver IC 241 (6),
From the terminals (7) and (8), a three-phase AC voltage is applied and
D. It is supplied to the motor 13. Note that D.S. D. The rotation speed of the motor 13 is high
The degree is finely adjusted by the semi-fixed resistor 274.
Fine adjustment is performed by the fixed resistor 272. D. D. Mo
When an overcurrent is supplied to the
(5) Motor stop voltage is sent out from terminal No.
The output of the DC amplifier 260 is stopped. D. Motor 1
3 is stopped. [0166] The present invention has the above configuration, and
According to the description, a rotation driving means, a writing means and a reading means
Applying a switching signal according to the magnetic density to each of the
Rotation speed, write current value, and other characteristics can be switched by
In addition, magnetic media recorded with the same device at multiple recording densities
It has the effect of regenerating the body.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a floppy disk drive according to one embodiment of the present invention. FIG. 2 is a signal waveform diagram for normal density and high density. FIG. 3 is a circuit diagram of a switching signal circuit. FIG. 4 is a circuit diagram of a write circuit, a delay circuit, and an erase circuit. FIG. 5 is a circuit diagram of a write circuit, a delay circuit, and an erase circuit. FIG. 6A is a circuit diagram of a preamplifier and a low-pass filter. Filter circuit diagram of filter (c) Filter circuit diagram of low-pass filter at high density [Fig. 7] Circuit diagram of differential amplifier circuit, comparator and time domain filter [Fig. 8] Circuit diagram of motor drive circuit [Fig. 9] Conventional floppy Block diagram of a disk device [FIG. 10] Signal waveform diagram of a conventional device [Description of symbols] 12a Normal density magnetic medium 12b High density magnetic medium 13 Spindle motor 14 Write head 16 write circuit 16 erase circuit 17 delay circuit 18 preamplifier 19 low-pass filter 20 differential amplifier 21 comparator 22 time domain filter b write data signal c write current h write gate signal i read signal j read pulse signal -DDM, -LS, + LS switching signal

Claims (1)

(57) [Claims] It has a switching signal generating means, writing means, the reading means, the switching signal generating means generates a switching signal, the write
The write means for simultaneously changing the characteristics of the read means and the read means; the write means for changing the write current value to the write / read head in the magnetic head by the switch signal; and the write circuit by the switch signal. A delay circuit in which a delay time for a current is changed, and an erase circuit that changes an erase current value to an erase head in the magnetic head by the switching signal and is transmitted with a delay to the delay circuit. The read means includes: a low-pass filter that changes a cutoff frequency of a read signal from the magnetic head according to the switching signal; a differential amplifier circuit that changes a resonance frequency by the switching signal to differentiate an output of the low-pass filter; the differential amplification times by changing the time width of the pulse by the signal
A time domain filter for converting the output of the path into a pulse waveform. 2. It has a switching signal generating means, writing means, the reading means, the switching signal generating means generates a switching signal, the write
Simultaneously changing the characteristics of the reading means and the reading means
Are those which may, said writing means includes a write circuit for changing a write current to the write read head in the magnetic head by the switching signal, the erase current value into the erase head in the magnetic head by the switching signal An erasing circuit for changing the cutoff frequency of a read signal from the magnetic head in accordance with the switching signal; and a low-pass filter for changing a resonance frequency in accordance with the switching signal. a differential amplifier circuit for differentiating the output, the differential amplifier times by changing the time width of the pulse by the switching signal
A time domain filter for converting the output of the path into a pulse waveform. 3. A switching signal generating unit, a writing unit, and a reading unit; the switching signal generating unit generating a switching signal;
Means and at least one of the characteristics of the reading means are changed.
Are those that can, the write means, erasure by the switching signal and the write current can be changed value writing circuit to write the read head in the magnetic head, to the erasing head in the magnetic head by the switching signal An erasing circuit capable of changing a current value, wherein the reading means is capable of changing a cutoff frequency of a read signal from a magnetic head by the switching signal, and is capable of changing a resonance frequency by the switching signal. said a differential amplifier for differentiating the output of the low-pass filter, changeably said differentiating the duration of the pulse by the switching signal
A floppy disk drive, comprising: a time domain filter that converts the output of the amplifier circuit into a pulse waveform. 4. A switching signal generating unit, a writing unit, and a reading unit; the switching signal generating unit generating a switching signal;
Means and at least one of the characteristics of the reading means are changed.
It is intended that it is to said writing means, which has a write circuit capable of changing the write current value to the write and read heads in a magnetic head by the switching signal, said read means, by the switching signal A low-pass filter capable of changing a cutoff frequency of a read signal from a magnetic head, a differential amplifier circuit for differentiating an output of the low-pass filter so that a resonance frequency can be changed by the switching signal, and changing a pulse time width by the switching signal Differentiation possible above
A floppy disk drive, comprising: a time domain filter that converts the output of the amplifier circuit into a pulse waveform. 5. A switching signal generating unit, a writing unit, and a reading unit; the switching signal generating unit generating a switching signal;
Means and at least one of the characteristics of the reading means are changed.
It is intended that it is to said writing means, which has a write circuit capable of changing the write current value to the write and read heads in a magnetic head by the switching signal, said read means, by the switching signal A differential amplifier circuit for differentiating the output from the magnetic head so that the resonance frequency can be changed, and a time domain filter for making the output of the differential amplifier circuit a pulse waveform so that the pulse width can be changed by the switching signal. A floppy disk drive. 6. A switching signal generating unit, a writing unit, and a reading unit; the switching signal generating unit generating a switching signal;
Means and at least one of the characteristics of the reading means are changed.
It is intended that it is to said writing means, which has a write circuit capable of changing the write current value to the write and read heads in a magnetic head by the switching signal, said read means, by the switching signal A low-pass filter capable of changing a cut-off frequency of a read signal from the magnetic head, and a time-domain filter that changes the output of the differential amplifier circuit into a pulse waveform so that the pulse width can be changed by the switching signal. Floppy disk device.