JPH0410204A - Magnetic head circuit - Google Patents

Abstract

PURPOSE:To shorten recovery time from the end of write to effective read at a maximum by executing write and read by a magnetic disk device while sharing a single magnetic head. CONSTITUTION:A frequency divider circuit 31 is provided to generate a pseudo data pulse by dividing the frequency of a write clock, and a selector 30 is provided to select a data pulse shaping an input data pulse when a write/read signal instructs write. Then, a flip-flop circuit 13 is provided to switch the direction of a current to flow to a magnetic head 15 by the selected pulse, and detection circuits 33, 34 and 35 are provided to detect the switching of the write/read signal instruction from write to read. Further, write control circuits 35 and 37 are provided to execute control so that the selector 30 can select the pseudo data pulse and the current can flow to the magnetic head 15 until prescribed timing after the write/read signal instruction of read and the detection of the detection circuits 33, 34 and 35. Thus, the recovery time from the end of write to effective read can be shortened at a maximum.

Description

[Detailed Description of the Invention] [Summary] Regarding a magnetic head circuit that shares a single magnetic head for writing and reading in a magnetic disk device, etc., the recovery time from the end of writing until reading becomes valid is In order to achieve the shortest possible time, data is written by switching the direction of the current flowing through the coil of the magnetic head according to the input data pulse, and the voltage across the coil of the magnetic head is differentially amplified by automatic gain control. In a magnetic head circuit that reads data, there is a frequency divider circuit that divides the write clock to generate a pseudo data pulse, and a selector that selects a data pulse that is a shaped input data pulse when a write/read signal instructs writing. , a circuit that switches the direction of the current flowing through the magnetic head with a selected pulse; a detection circuit that detects that the write/read signal has switched from writing to a reading instruction; The magnetic head is configured to include a write control circuit that selects a pseudo data pulse with the selector after detection by the detection circuit and controls current to flow through the magnetic head until a predetermined timing is reached.

[Industrial application field]

The present invention relates to a magnetic head circuit, and more particularly to a magnetic head circuit that performs writing and reading by sharing a single magnetic head in a magnetic disk device or the like.

[Conventional technology]

FIG. 3 shows a configuration diagram of an example of a conventional magnetic head circuit.

In the same figure, at the time of writing, the switch SW is turned on according to the write/read signal shown in FIG. 4(A), and the data pulse shown in FIG. After being shaped by the small write clock in the flip-flop 12 as shown in FIG. 4(D), the frequency is divided in the flip-flop 13. The transistors Qa and Qb are alternately switched according to the Q and σ terminal outputs a and b of the flip-flop 13 shown in FIGS.
), (H) respectively flow, and information is recorded on the recording medium.

During reading, switch SW is turned off and transistor Q
The current from the constant current source 16 flowing through a and Qb is cut off, and the voltage induced in the coil of the magnetic head 15 by the magnetic field generated from the recording medium passes through the AGC differential amplifier and is output as a read signal.

[Problems to be Solved by the Invention] Now, looking at the voltages across the head, the voltages Ha and Hb across the head during writing are equal to the read current 1a.
, Ib, as shown in FIG. 4(I). The changes in Ha and Hb when switching from writing to reading are determined by the time constant determined by the inductance of coil L, resistance Rd, and stray capacitance from the voltage when SW is turned off, as shown in Figure 4 (I). Changes to Therefore, the read output induced by the magnetic field from the recording medium is combined with this voltage. The read output of a magnetic head is generally treated as a differential signal, and AGC is applied to keep the amplitude of the read output constant in order to absorb level fluctuations caused by unevenness of the medium. T when switching. In addition, during a period where there is a voltage difference as shown in FIG. 4(1), a DC imbalance state occurs, and the information recorded on the recording medium cannot be output correctly. Therefore, in such conventional circuits that do not control the timing of the switching signal with respect to the write data pulse, the time from the end of writing until the read output is normally output, that is, the recovery time, is the time required for switching from the last write data pulse. There was a problem in that the recovery time could not always be kept short because it changed depending on the timing with the signal.

The present invention has been made in view of the above points, and an object of the present invention is to provide a magnetic head circuit that minimizes the recovery time from the end of writing until the time when reading becomes effective.

[Means to solve the problem]

The magnetic head circuit of the present invention writes data by switching the direction of the current flowing through the coil of the magnetic head according to an input data pulse, and performs automatic gain control on the voltage across the coil of the magnetic head to differentially amplify the data. A magnetic head circuit that performs readout includes a frequency divider circuit that divides the frequency of the phytoclock to generate a pseudo data pulse, and a selector that selects a data pulse obtained by shaping the input data pulse when the write/read signal instructs interpolation. , a circuit that switches the direction of the current flowing through the magnetic head with a selected pulse, a detection circuit that detects when the write/read signal switches from writing to a read instruction, and a detection circuit that detects when the write/read signal indicates a read instruction. The write control circuit includes a write control circuit that selects a pseudo data pulse with a selector after detecting the pulse, and controls current to flow through the magnetic head until a predetermined timing is reached.

[Effect]

In the present invention, after the write/read signal switches from write to read instruction, the write control circuit extends the write period and writes pseudo data pulses until a predetermined timing is reached. The reading operation is switched to when the potential difference becomes zero, that is, when the DC unbalanced state does not occur. Therefore, the recovery time from the end of writing to the time when reading becomes valid is always the shortest.

(Example) FIG. 1 shows a configuration diagram of an embodiment of the circuit of the present invention.

In the figure, the same parts as in FIG. 3 are given the same reference numerals, and their explanations will be omitted.

In the same figure, the input data pulse shown in FIG. 2(B) supplied to the data input terminal of the flip-flop 12 is
A signal as shown in FIG. 3C obtained by shaping at the rising edge of the write clock shown as D> is supplied to the A terminal of the selector 30. The 172 frequency divider circuit 31 divides the write clock into 172
The frequency is divided and supplied to the B terminal of the selector 30 as a pseudo data pulse as shown in FIG. When writing (write), the input signal of the A terminal is output from the Y terminal, and when the write/read signal is at H level (read), the input signal of the B terminal is output from the Y terminal.

Furthermore, the flip-flop 33 latches the write/read signal supplied to the data input terminal at the falling edge of the write clock and generates the signal shown in FIG. 2 (H) and (1) from the Q and σ terminals, respectively.
) Output the signals shown respectively. The Q output of the flip-flop 33 and the σ output of the flip-flop 34 are connected to the NAND circuit 3.
5 to generate a signal shown in FIG. The data input terminal of the flip 70 tube 36 is grounded, and the flip flop 36 is preset at the falling edge of the output of the NAND circuit 35, and then inputs data at the rising edge of the Y terminal output signal of the selector 30, which is supplied to the clock input terminal CK. The signal shown in FIG. 2 (K) is latched and outputted from the σ terminal, and this signal is logically ANDed with the write/read signal and the Q output of the flip-flop 34 in the AND circuit 37, resulting in the signal shown in FIG. 2 (L). The rewrite (W/R) signal shown is supplied to the switch SW. The switch SW is turned on during the L level period of the read/write signal and turned off during the H level period.

The above flip-flops 33, 34 and NAND circuit 35
detects the rise of the write/read signal, and the flip-flop 36 keeps the read/write signal at L level, that is, writes, from the rise of the output of the NAND circuit 35, which is the rise detection signal of the write/read signal, until the output of the selector 30 rises. As an instruction. During the period T+ after the write/read signal rises until the read/write signal rises, the pseudo data pulse generated by the 172 frequency divider circuit 31 is supplied to the flip-flop 13. That is, the flip-flop 36 and the AND circuit 37 extend the write instruction period of the write/read signal and generate a dry signal.

At the time of writing, the output of the flip-flop 13 as shown in FIG.
With the signals a and b shown in M) and (N), the transistor Qa,
When Qb is switched, the current shown in Figure 2 (○>, (P)) flows through the coil of the magnetic head 15, and information is recorded.At this time, the voltage across the head is as shown in Figure 2 (Q). At the time t when the write/read signal rises, there is a potential difference V+ and the DC is unbalanced, but at the time t1 when the read/write signal rises, the potential difference is zero and the DC is balanced. This is the result of performing a write operation using pseudo data pulses to achieve DC balance.

In this way, after the write/read signal switches from write to read instruction, the write control circuit composed of the flip-flop 36 and the AND circuit 37 extends the write period and writes the pseudo data pulse until a predetermined timing. As a result, reading is started when the potential difference between both ends of the coil of the magnetic head becomes zero. For this reason, the recovery time from when writing ends to when read output becomes normal and reading becomes valid is up to 10-odd microseconds due to conventional DC imbalance.
Whereas the recovery time could sometimes extend to EC, the present invention reduces the recovery time to about several microseconds, making the recovery time always the shortest.

(Effects of the Invention) As described above, according to the magnetic head circuit of the present invention, it is possible to minimize the recovery time from the end of the field setting until the reading becomes effective, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the circuit of the present invention, and FIG.
FIG. 3 is a configuration diagram of an example of a conventional circuit, and FIG. 4 is a signal waveform diagram of various parts of the circuit shown in FIG. In the figure, 12.13, 33, 34.36 are 70 knobs, 15 is a magnetic head, 16 is a constant current source, 17 is an AGC differential amplifier, 31 is a 172 frequency divider circuit, 35 is a NAND circuit, and 37 is an AND circuit. Shows the circuit. v1 Applicant Fujitsu Co., Ltd. Agent Patent Attorney Tadahiko Ito

Claims (1)

[Claims] Data is written by switching the direction of the current flowing through the coil (L) of the magnetic head (15) according to the input data pulse, and also changes the voltage across the coil (L) of the magnetic head (15). In a magnetic head circuit that performs automatic gain control to differentially amplify and read data, there is a frequency divider circuit (31) that divides the write clock frequency to generate a pseudo data pulse, and a frequency divider circuit (31) that divides the write clock frequency and generates a pseudo data pulse, and when the write/read signal instructs writing. A selector (30
), a circuit (13) that switches the direction of the current flowing through the magnetic head with a selected pulse, and a detection circuit (33, 34, 35) that detects that the write/read signal has switched from writing to reading instructions. , After the write/read signal instructs reading, the selector (30) selects a pseudo data pulse after detection by the detection circuit (33, 34, 35), and current flows through the magnetic head until a predetermined timing is reached. 1. A magnetic head circuit comprising a write control circuit (36, 37) for controlling the magnetic head.